JP2020088964A - Energization control circuit unit for switching control element and on-vehicle electronic control device including the same - Google Patents

Abstract

To improve the switching efficiency of a switching element that intermittently controls an exciting current of an inductive load, and suppress the heat generation.SOLUTION: A switching control element 145 has a high-speed operating first switching element 145a and a highly conductive second switching element 145b connected in parallel, and includes a time difference control circuit 140A that generates a first gate voltage GT1 when a drive signal voltage GT0 is generated, and stops a second gate voltage GT2 and stops the first gate voltage GT1 stops after a first opening delay time Toff has elapsed when a second gate voltage GT2 is generated after a second closing delay time Ton has elapsed and the drive signal voltage GT0 is stopped, and the first switching element 145a shares switching transient loss and the second switching element 145b shares closed circuit conduction loss.SELECTED DRAWING: Figure 2

Description

The present application relates to an energization control circuit unit for an opening/closing control element that intermittently controls an exciting current of an inductive load, and an in-vehicle electronic control device using the same.

For example, in order to drive a fuel injection solenoid valve of an internal combustion engine at high speed, a high voltage boosted from an on-vehicle battery is instantaneously supplied to an electromagnetic coil for driving the solenoid valve, and then the on-vehicle battery voltage opens the valve for a predetermined period. In an in-vehicle engine control device that repeats the operation of holding control, in order to obtain the high voltage required to drive an electric load at a high voltage, the exciting current of the inductive element is frequently changed by a switching control element. It is equipped with a high-voltage capacitor that is intermittently controlled to be charged by an induced voltage when the exciting current is cut off.
In the case of fuel injection control, this high-voltage capacitor is boost-charged from an on-vehicle battery of DC12V system, and after being charged to, for example, DC75V by initial charging, it is reduced to DC70V each time fuel injection is performed. The intermittent operation is repeated ten times or more to restore DC75V again.
Therefore, the open/close control element of the inductive element needs to interrupt a large current of about 10 A in a cycle of, for example, several tens of microseconds, and it is important to reduce the power consumption and suppress the temperature rise.
The power consumption generated in the switching control element is classified into two types, one of which is a closed circuit conduction loss due to internal resistance when the circuit is closed, and the other is a high voltage applied. It is the switching transient loss due to the intermittent operation of the exciting current in the state.

Since this switching transient loss is inversely proportional to the current increase/decrease rate (slew rate), which is a characteristic of the switching element itself, as will be described later, using a switching element with a large current increase/decrease rate suppresses the switching transient loss. However, there is a problem that a switching element having a large current increase/decrease rate generally has a large closed circuit resistance and a large closed circuit conduction loss.
Further, since the induction energy generated by the inductive element is proportional to the square of the exciting current, it is extremely useful to increase the exciting current of the inductive element in order to recover the charging voltage of the high voltage capacitor within a certain period. Along with this, the closed circuit conduction loss of the switching control element increases. On the other hand, although the switching transient loss of the switching control element increases in proportion to the exciting current, if the exciting current is increased, the switching frequency of the switching control element can be suppressed.
However, if the switching frequency of the switching control element is increased with the same exciting current, the charging voltage of the high-voltage capacitor can be recovered in a short time, but the frequency of switching transient loss of the switching control element increases accordingly.
Therefore, the value of the exciting current and the switching frequency for minimizing this total loss must be determined in consideration of the internal resistance of the applied switching control element when the switching circuit is closed and the current increase/decrease rate during the switching transition period.

For example, according to the following Patent Document 1 "Apparatus and method for forcibly sharing switching loss of parallel transistors", transistors connected in parallel to supply a load (corresponding to a boosting inductive element in the present application) One of them takes the opening and closing transient loss by one of which is closed earlier and delays the opening, and the other is spared of the burden of the opening and closing transient loss by opening the latter by delaying closing and leading opening, and the shares are alternated to equalize the opportunity. It is intended to share the switching transient loss.
However, if there is a difference in the current increase/decrease rate of the transistor, the switching transient loss to be shared will be different, while in the period in which both are closed, the closing conduction loss will be shared at the same time. Therefore, it is impossible to evenly share the closed-circuit conduction loss due to the difference in the closed-circuit resistance.
However, this Patent Document 1 is for supplying a variable constant voltage to a load by PWM control of a transistor, and a surge voltage is prevented from being generated by a commutation diode when the transistor is opened, and a time difference is set. The alternating selector that performs the control is not specifically described.

JP, 06-090151, A

In the parallel transistor circuit according to Patent Document 1, the current increase/decrease rate of the transistor and the closed-circuit resistance have not been investigated. Therefore, each transistor has a common standard, and mutual characteristics differ within the range of product variations. Assumed to be.
In each of the transistors, switching transient loss and closed circuit energization loss occur, and the loss sharing ratio differs due to the characteristic variations, and it is not possible to perform control to equalize the heat generated by the transistors. .
Therefore, even if two transistors are used, the performance cannot be maximized.

The present application discloses a step-up circuit unit for charging a high-voltage capacitor by intermittently energizing an inductive element by an open/close control element, or intermittently controlling an inductive exciting current at a high frequency to change the energization duty so as to make it variable or constant. It is an object of the present invention to provide an energization control circuit unit for an opening/closing control element, which is applied to an in-vehicle electronic control device including a current control unit adapted to obtain an exciting current and which can save power and downsize the device. ..

An energization control circuit unit for the switching control element disclosed in the present application is connected in series to an inductive load fed from a DC power source, and performs a closing operation and an opening operation in response to a logic level of a drive signal voltage. In the energization control circuit unit for, the opening/closing control element is configured by a parallel circuit of a first opening/closing element and a second opening/closing element, and one opening/closing element, the first opening/closing element, opens/closes the other. The slew rate has a larger current increase/decrease rate than the second switching element, which is an element, and the other switching element has a high conductivity with a smaller internal resistance than the one switching element. Is distributed to the first gate voltage and the second gate voltage by the time difference control circuit, the first switching element performs the closing operation and the opening operation in response to the logic level of the first gate voltage, and the second switching element is The time difference control circuit is configured to perform the closing operation and the opening operation in response to the logic level of the second gate voltage. The time difference control circuit further includes a second time difference setting unit that generates a gate voltage and subsequently generates a second gate voltage for closing the second switching element with a predetermined second closing delay time. When the drive signal voltage stops, the second gate voltage is stopped first, and then the first gate voltage is stopped after a predetermined first open circuit delay time is provided.

According to the energization control circuit unit for the switching control element disclosed in the present application, the first switching element suitable for high-speed switching is provided as the switching control element that performs the intermittent control of the inductive load in response to the logic level of the drive signal voltage. , A second switching element having a small circuit resistance is connected in parallel, and the drive signal voltage is distributed to the first and second gate voltages by the time difference control circuit to open and close the first and second switching elements, respectively. Is configured to drive.
When the drive signal voltage is generated, the time difference control circuit delays the second gate voltage with respect to the first gate voltage, and when the drive signal voltage is stopped, the first gate voltage is delayed with respect to the second gate voltage. Is becoming

Therefore, switching transient loss is reduced by ending the generation of excessive loss in a transient period in which the exciting current of the inductive load is intermittently interrupted in a short time, and the closed-circuit resistance is reduced during energizing of the exciting current to reduce the conduction loss. There is an effect that the generation of heat can be suppressed, the intermittent control efficiency of the load current can be improved as a whole, and the heat generated by the switching control element can be suppressed to reduce the size and simplification of the heat dissipation structure.
Since the second switching element for boosting has an overwhelmingly small current increase/decrease rate compared to the first switching element for boosting, the second closed circuit delay time may be substantially close to zero. Therefore, at least the second switching element is not driven to be closed before the closing command of the first switching element.

1 is an overall circuit block diagram of an in-vehicle electronic control device according to Embodiment 1. FIG. It is a detailed circuit diagram of the electricity supply control circuit unit of the thing of FIG. 3 is a time chart of charging characteristics and inductive element current of the high voltage capacitor of FIG. 1. 3 is a time chart of a drive signal of the opening/closing control element in FIG. 2. 5 is a detailed time chart of a drive signal of the opening/closing control element in FIG. 4. It is a figure which shows the list of the power loss in the thing of FIG. 1, and the power loss in another aspect. 7 is an overall circuit block diagram of an in-vehicle electronic control device according to Embodiment 2. FIG. It is a detailed circuit diagram of the electricity supply control circuit unit of the thing of FIG. It is a figure which shows the list of the pulse train signals of the thing of FIG. 8 is a flowchart for explaining the operation of the arithmetic control circuit unit of FIG. 7. FIG. 3 is an overall circuit block diagram of an in-vehicle electronic control device that is a modification of the first embodiment. FIG. 7 is an overall circuit block diagram of a vehicle-mounted electronic control device that is a modification of the second embodiment.

Embodiment 1.
First, the configuration will be described in detail with reference to FIG. 1, which is an overall circuit block diagram of the vehicle-mounted electronic control device according to the first embodiment, and FIG. 2, which is a detailed circuit diagram of the energization control circuit unit of FIG. The energization control unit shown in FIG. 2 is also applied to an in-vehicle electronic control device which is an embodiment shown in FIG. 12 described later.
1, an in-vehicle electronic control device 100A includes a stabilized power supply 110 that generates a control voltage Vcc, an arithmetic control circuit unit 120A that includes a microprocessor (CPU) 123, and a booster circuit unit 130 that includes an energization control circuit unit 240A. The main component is an electric load drive circuit 150, which is an injector drive circuit, for example.
A DC power supply 101, which is a DC12V vehicle battery, is connected to the outside of the on-vehicle electronic control unit 100A via a load power switch 102 which is an output contact of a power relay energized by a power switch (not shown). Are connected to each other to supply the power supply voltage Vbb to the on-vehicle electronic control unit 100A.

Further, the input sensor 103 including various input sensors and a power switch is connected to the in-vehicle electronic control device 100A, and the output load 104 driven by the in-vehicle electronic control device 100A includes, for example, a plurality of electromagnetic waves. It includes a vehicle-mounted electric load 105 which is a fuel injection solenoid valve having a coil (INJ).
As an internal configuration of the in-vehicle electronic control device 100A, the booster circuit unit 130 includes a series circuit of an inductive element 131 supplied with a power supply voltage Vbb, a charging diode 132, and a high voltage capacitor 133, and a series circuit of the charging diode 132 and the high voltage capacitor 133. The open/close control element 145 is connected in parallel to the ground line connected to the negative terminal of the DC power supply 101, which is the vehicle-mounted battery, via the combined current detection resistor 135.
The open/close control element 145 is configured by a parallel circuit of a first open/close element 145a and a second open/close element 145b which are field effect transistors, and the first open/close element 145a is the second open/close element 145b. The second switching element 145b has a high conductivity and a large slew rate as compared with the first switching element 145b, and has a higher conductivity than the first switching element 145a, which has a smaller internal resistance when closed.

The time difference control circuit 140A included in the energization control circuit unit 240A, which will be described later with reference to FIG. 2, distributes the drive signal voltage GT0 generated by the drive signal output circuit 138 to distribute the first gate voltage GT1 and the second gate voltage GT2. Is generated, and this is a drive signal for each of the first switching element 145a and the second switching element 145b.
The drive signal output circuit 138 constitutes a drive signal generation circuit by a current determination circuit and a voltage determination circuit, and the current determination circuit is the voltage across the combined current detection resistor 135 connected in series to the downstream end of the switching control element 145. The value of the detection voltage Vs is compared with the current upper limit value Vref12 which is a comparison voltage proportional to the target upper limit current of the exciting current for the inductive element 131, and when the exciting current exceeding the target upper limit current is reached, the first drive inhibition is performed. A first comparator 136a for generating the signal GT01. Since the positive feedback resistor 136c is connected between the output terminal of the first comparator 136a and the positive side input terminal, the switching control element 145 opens and is charged by the induction voltage of the induction element 131. The first drive inhibition signal GT01 is released when the charging current for the high-voltage capacitor 133 is lower than the current lower limit value Vref11 (not shown).

Further, the voltage determination circuit determines that the monitoring voltage obtained by dividing the voltage between the positive terminal of the high voltage capacitor 133 and the ground by the voltage dividing resistors 134a and 134b exceeds the voltage upper limit Vref22 for the target monitoring voltage. The second comparator 137a for generating the second drive inhibition signal GT02.
In the second comparator 137a, a positive feedback resistor 137c is connected between the monitoring input terminal and the comparison output terminal, and after the second drive prohibition signal GT02 is generated, the charge charged in the high voltage capacitor 133 is changed to the on-vehicle electric power. By discharging the load 105, the monitor voltage becomes equal to or lower than a predetermined lower limit voltage value Vref21 (not shown), so that the second drive inhibition signal GT02 is released.
The drive signal output circuit 138 is adapted to generate the drive signal voltage GT0 in a logic state in which neither the first drive prohibition signal GT01 nor the second drive prohibition signal GT02 is generated.
The arithmetic control circuit unit 120A is a microprocessor including a non-volatile program memory (PMEM) and a data memory (DMEM), a memory (MEM) including a volatile RAM memory (RMEM), and a multi-channel AD converter (ADC). (CPU), the microprocessor (CPU) generates a fuel injection command INJi to the electric load drive circuit 150, which is an injector drive circuit, and the current upper limit value stored in the memory (MEM). The value of Vref12 can be transferred to the first register 136b in the booster circuit unit 130.

In this embodiment, the second register 137b that stores the voltage upper limit value Vref22 is set to a fixed value by the voltage dividing resistor for the control voltage Vcc.
Further, the electric load drive circuit 150 includes a pair of quick power feeding elements 152, a valve opening holding element 153, a commutation circuit element 155 provided for each of the odd-numbered cylinder group and the even-numbered cylinder group, and an energization selection element 151 provided for each cylinder. Is equipped with.
The rapid power feeding element 152 sequentially and rapidly drives the electromagnetic coil (INJ) of the fuel injection electromagnetic valve as the vehicle-mounted electric load 105 by the high voltage Vh which is the charging voltage of the high voltage capacitor 133, and the valve opening holding element 153 rapidly feeds power. During the valve opening period of the solenoid valve after opening the element 152, the valve opening holding operation is performed by the power supply voltage Vbb via the backflow prevention element 154.
The energization selection element 151 is closed circuit driven during the energization period of the electromagnetic coil (INJ) of the fuel injection solenoid valve as the vehicle-mounted electric load 105. When the energization selection element 151 is opened, a regenerative discharge diode (not shown) The high voltage capacitor 133 is regeneratively discharged through the high voltage capacitor 133.

In FIG. 2, a pair of first opening/closing elements connected in parallel to the opening/closing control element 145 to which the first gate voltage GT1 and the second gate voltage GT2 are applied by the time difference control circuit 140A which constitutes the energization control circuit unit 240A. An example in which, in addition to the element 145a and the second switching element 145b, a field effect parallel switching element 145bb having a small closed circuit resistance is added is indicated by a dotted line, and the parallel switching element 145bb also has a second gate voltage GT2. Is applied, and internal parasitic capacitors 146a, 146b, 146bb included in each switching element are shown.
Further, a second time difference setting capacitor 41b is additionally connected between the gate terminal and the source terminal of the second switching element 145b, if necessary, and the internal parasitic capacitor 146a of the first switching element 145a is required. Accordingly, the smoothing capacitor 48a and the smoothing resistor 49a are connected to form an input filter circuit.
However, the value of the current increase/decrease rate of the first switching element 145a, which decreases with the addition of this filter circuit, becomes larger than the current increase/decrease rate of the second switching element 145b and the parallel switching element 145bb side. ing.

The time difference control circuit 140A rapidly charges the first temporary difference setting capacitor 41a via the first quick closing diode 43a and the charging resistor 42 when the logic level of the drive signal voltage GT0 becomes the high level “H”. Then, the first gate for rapidly charging the internal parasitic capacitor 146a of the first switching element 145a via the first rapid closing diode 43a, the low resistance first rapid closing resistor 44a, and the waveform shaping element 46 which is a comparator. A voltage GT1 is generated to rapidly close the first switching element 145a, and the second switching element 145b or the second switching element 145b and the parallel switching element 145bb are connected to each other via the second delay closing resistance 45b. By charging the internal parasitic capacitors 146b and 146bb and the second time difference setting capacitor 41b, the second gate voltage GT2 rises with a delay, and the respective switching elements are delayed and closed.

When the logic level of the drive signal voltage GT0 becomes the low level “L”, the time difference control circuit 140A also causes the second quick opening diode 43b and the low resistance second quick opening resistor 44b to make the second Of the internal switching capacitors 146b and 146bb of the second switching element 145b and the parallel switching element 145bb and the second time difference setting capacitor 41b to rapidly discharge the second gate voltage GT2, The second switching element 145b or the second switching element 145b and the parallel switching element 145bb are rapidly opened, and the charge stored in the first temporary difference setting capacitor 41a is discharged slowly via the first delay opening resistance 45a, and the residual voltage thereof is generated. Becomes less than the comparison reference voltage 47 connected to the negative side input terminal of the waveform shaping element 46, the first gate voltage GT1 is rapidly attenuated by the comparison output of the waveform shaping element 46 to delay the first switching element 145a. It is designed to open rapidly from.

Regarding the in-vehicle electronic control device 100A according to the first embodiment configured as shown in FIGS. 1 and 2, FIG. 3 which is a time chart of charging characteristics and inductive element current of the high voltage capacitor of FIG. 1, and the switching control element in FIG. 4, which is a time chart of the drive signal of FIG. 4, and FIG. 5 which is a detailed time chart of the drive signal of the opening/closing control element in FIG. 4, the operation thereof will be described in detail. The time chart of the charging characteristics of the high-voltage capacitor and the inductive element current shown in FIG. 3 is also applied to the vehicle-mounted electronic control unit which is a modification of the first embodiment shown in FIG. 11 described later. is there. Further, the time chart of the drive signal of the switching control element shown in FIG. 4 is also applied to the energization control circuit unit of the second embodiment shown in FIG. 8 described later.
First, in FIG. 1, when a power switch (not shown) is closed, the load power switch 102, which is the output contact of the power relay, is closed, and the power supply voltage Vbb is applied to the vehicle-mounted electronic control unit 100A.
As a result, the stabilized power supply 110 generates a stabilized control voltage Vcc of DC5V, for example, and the microprocessor (CPU) constituting the arithmetic control circuit section 120A starts the control operation.
The microprocessor (CPU) drives the load on the output load 104 in response to the operating state of the input sensor 103 and the content of the control program stored in the non-volatile program memory (PGM) which is a part of the memory (MEM). A fuel injection command INJi is generated for a specific vehicle-mounted electric load 105 in the output load 104, which is a fuel injection electromagnetic valve, and an electric load drive circuit 150 that is an injector drive circuit is generated. Each electromagnetic coil (INJ) for each cylinder is driven via the booster circuit unit 130, and the booster circuit unit 130 operates to charge the high-voltage capacitor 133 at high voltage.

Next, FIG. 3A and FIG. 3B which are time charts of the charging characteristics and the inductive element current of the high voltage capacitor of FIG. 1 will be described.
In FIG. 3(A), the horizontal axis represents the time axis and the vertical axis represents the charging voltage of the high-voltage capacitor 133. For example, a period of 100 msec immediately after the power switch is closed (the time axis is compressed in the figure. ), the high voltage capacitor 133 is initially charged as shown by the dotted line and reaches the voltage lower limit value Vref21.
In the subsequent charging period, the charging voltage of the high voltage capacitor 133 rises and stabilizes at the voltage upper limit value Vref22.
Here, by rapidly supplying power to the electromagnetic coil (INJ) for fuel injection, the high voltage capacitor 133 is discharged, and the charging voltage does not drop below the voltage lower limit value Vref21 in one discharge. It has become.
However, once the voltage upper limit value Vref22 is reached, the fuel is injected a plurality of times (for example, the second time), and the residual charging voltage of the high-voltage capacitor 133 drops below the voltage lower limit value Vref21. GT0 occurs, and the charging operation for the high voltage capacitor 133 starts again.
The charge/discharge cycle T20 is T20=5 msec, for example, when the 4-cylinder 4-cycle engine is rotating at 6000 RPM.

In FIG. 3B, the upper part shows the waveform of the drive signal voltage GT0 generated by the drive signal output circuit 138, and the lower part shows the waveform of the exciting current flowing through the inductive element 131.
When the logic level of the drive signal voltage GT0 becomes the high level “H”, the switching control element 145 is closed to increase the exciting current, and when this reaches the current upper limit value Vref12 corresponding to the detection voltage Vs by the second current I2, The first drive inhibit signal GT01 is generated by the comparison output of the one comparator 136a.
As a result, the logic level of the drive signal voltage GT0, which is the output of the drive signal output circuit 138, changes to the low level “L”, the switching control element 145 is opened, and the exciting current flowing in the inductive element 131 is excited by the high voltage capacitor 133. To the combined current detection resistor 135, and as the charging current decreases, the output of the first comparator 136a changes its logic level to the low level "L" and the first drive inhibit signal GT01. Is to be released.
The period during which the switching control element 145 is open is shown as a cutoff time ΔT, and the charging current flowing through the combined current detection resistor 135 at this time is shown as a first current I1 and does not correspond to the detection voltage Vs. It is shown by the current lower limit value Vref11.

On the other hand, when the divided voltage of the high voltage capacitor 133 exceeds the voltage upper limit value Vref22, the logic of the second drive prohibition signal GT02 which is the output of the second comparator 137a is high until the divided voltage falls below the voltage lower limit value Vref21. The level becomes "H", the logic level of the drive signal voltage GT0 output from the drive signal output circuit 138 maintains the low level "L", and the exciting current decreases to zero.
However, when the charging voltage of the high-voltage capacitor 133 becomes equal to or lower than the voltage lower limit value Vref21, the second drive prohibition signal GT02 is stopped until the voltage becomes equal to or higher than the voltage upper limit value Vref22. In response to the output logic, the logic level of the drive signal voltage GT0 is alternately inverted so that the open/close control element 145 is intermittently driven, and the intermittent period is, for example, T10=10 to 25 μsec.

Here, assuming that the element resistance R of the inductive element 131, the inductance L, and the induction time constant τ=R/L, the following formula is established when Ton<<τ.
First, the closing time Ton of the switching control element 145 in which the exciting current of the inductive element 131 rises from the first current I1 to the second current I2 and the cutoff time ΔT until the exciting current decreases from the second current I2 to the first current I1 are: There is a relation of formulas (1a) (1b) (1c).
L×(I2-I1)/Ton=Vbb (1a)
L×(I2-I1)/ΔT=Vh-Vbb... (1b)
∴ΔT=Ton×Vbb/(Vh-Vbb) (1c)
However, Vh is the charging voltage of the high voltage capacitor 133, and Vbb is the power supply voltage.
For example, if Vbb=14V, Vh=75V and the current ratio k=I1/I2, then ΔT=0.23Ton, and the intermittent period T10 is expressed by the formula (2).
T10=Ton+ΔT=1.23Ton
=1.23L×I2(1-k)/Vbb (2)

As an example, if R=0.1Ω, L=25 μH, τ=L/R=250 μsec, I2=14 A, I1=6 A, Ton=14.3 μsec<<τ according to the formula (1a), and the formula (1b) ΔT=3.3 μsec, and T10=176 μsec according to the equation (2).
The current increase rate is (14-6)/14.3=0.56A/μsec, which is much slower than the slew rate (current increase/decrease rate A/μsec) in the switching control element 145. It has changed.

Next, FIGS. 4A to 4E, which are time charts of the drive signals of the opening/closing control element in FIG. 2, will be described.
In FIG. 4(A), the drive signal voltage GT0 is a signal voltage for intermittently controlling the switching control element 145 at a switching period T10 of 176 μsec, and when the logic level is high level “H”, the switching control element 145 is closed. However, when the logic level is the low level "L", the switching control element 145 is opened.
However, the drive signal voltage GT0 is distributed to the first gate voltage GT1 and the second gate voltage GT2 by the time difference control circuit 140A described above with reference to FIG. 2, and FIG. 4B shows the waveform of the first gate voltage GT1. FIG. 4D shows the waveform of the second gate voltage GT2.
In FIG. 4C, this figure shows an increase/decrease waveform of the first capacitor voltage Vc1 by the first temporary difference setting capacitor 41a, and when the drive signal voltage GT0 is generated, the first temporary difference is generated via the low resistance charging resistor 42. It is shown that the setting capacitor 41a is rapidly charged, the first gate delay time tdon is placed, the first gate voltage GT1 is generated, and the first switching element 145a is rapidly closed.
When the drive signal voltage GT0 is stopped, the charge stored in the first temporary difference setting capacitor 41a is slowly discharged through the first delay opening resistor 45a, and the first opening/closing element 145a is delayed opening after the first opening delay time Tdoff. Indicates that you will.

In FIG. 4(E), this figure shows an increase/decrease waveform of the second capacitor voltage Vc2 by the second time difference setting capacitor 41b, and when the drive signal voltage GT0 is generated, it passes through the high-resistance second delay closed resistor 45b. The second time difference setting capacitor 41b is slowly charged to generate the second gate voltage GT2 with the second closed circuit delay time Tdon, and the second switching element 145b or the second switching element 145b and the parallel switching element 145bb are connected. Indicates that the delay is closed.
Then, there is a relation of the second closed circuit delay time Tdon≧first closed circuit delay time tdon, and the second switching element 145b or the second switching element 145b and the parallel switching element 145bb are more than the first switching element 145a. It is designed to be closed late.
However, since the second switching element 145b and the parallel switching element 145bb have an overwhelmingly smaller rate of current increase/decrease than the first switching element, the second closed circuit delay time Tdon may be equal to the first closed circuit delay time tdon. It is a thing.
When the drive signal voltage GT0 is stopped, the internal parasitic capacitors 146b and 146bb and the second time difference setting capacitor 41b are rapidly discharged through the second quick opening diode 43b and the second quick opening resistor 44b, and the second opening delay time tdoff. It is shown that the second switching element 145b or the second switching element 145b and the parallel switching element 145bb are rapidly opened.

The first open circuit delay time Tdoff≧the second open circuit delay time tdoff, and the first switching element 145a is more than the second switching element 145b or the second switching element 145b and the parallel switching element 145bb. It is designed to open later.
If the second time difference setting capacitor 41b indicated by the dotted line is not provided, there is an error in the switching delay time due to the characteristic variations of the internal parasitic capacitors 146b and 146bb of the second switching element 145b and the parallel switching element 145bb. In this case, the single closing period of the first switching element 145a becomes long and the closing energization loss becomes large. Therefore, in order to obtain a stable opening/closing delay time, the second time difference setting capacitor 41b is provided. It is desirable to keep it.
If the second time difference setting capacitor 41b is provided, even if the second closing delay time Tdon and the second opening delay time tdoff of the second switching element 145b and the parallel switching element 145bb are set to the same time. Of course, the second quick opening diode 43b may be short-circuited and deleted, and the second delay closing resistor 45b may be cut off and deleted.

Next, FIGS. 5A to 5D, which are detailed time charts of the drive signals of the opening/closing control element in FIG. 4, will be described.
Note that although FIGS. 5A, 5B, and 5C correspond to FIGS. 4A, 4B, and 4D, FIG. 4) and the first closed circuit delay time tdon and the second open circuit delay time tdoff in FIG. 4D are omitted and are simply expressed.
In FIG. 5D, the first inter-element voltage 501a indicates the inter-element voltage during the closing operation of the first switching element 145a, and this inter-element voltage is the high voltage capacitor when the first gate voltage GT1 is generated. It is the first voltage Vh1 which is the current voltage of 133, and is attenuated to the first inter-element voltage Von1 based on the internal resistance of the first switching element 145a when the closing time t1 has elapsed.
Since the switching element voltage v1 is Vh1 at time t=0 and Von1≈0 at time t1, the formula (3a) is satisfied.
v1=Vh1×(1-t/t1)... (3a)
The second element-to-element voltage 501b is indicated by the second element-to-element voltage Von2 having a value smaller than the first element-to-element voltage Von1 after the circuit is closed.

Similarly, the switching element current 502 is i1=0 at time t=0 and becomes the first current I1 discharged from the inductive element 131 to the high-voltage capacitor 133 at time t1, so that the slew rate of the switching element is α When I=I1/t1, the formula (4a) is satisfied.
i1=I1×t/t1=αt (4a)
The inductive element current 503 is increasing/decreasing between the first current I1 and the second current I2, the first switching element 145a and the second switching element 145b are opened, and the current is zero. However, the current of the inductive element 131 continues to flow as the charging current to the high voltage capacitor 133.
The slew rate of the high-speed first switching element 145a is, for example, α1=200 A/μsec, whereas in the case of the low-speed second switching element 145b, for example, α2=10 A/μsec. Is becoming
Therefore, the transient loss energy Eon when the first switching element 145a is closed is an integrated value from time t=0 to time t=t1 in the equation (5a).
Eon=∫v1×i1 dt (t=0 to t1)
=Vh1×I1 ² /6α ··· (5a)
However, t1=I1/α.

Similarly, the first inter-element voltage 501a at the time when the first gate voltage GT1 is stopped is v2=Von1≈0 at the new time t=0, and v2=Vh2 at the new time t=T2, and the switching The element current 502 is i2=second current I2 at the new time t=0, and i2=0 at the new time t2, and thus (3b) to (5b) are established.
However, the second voltage Vh2 is the current voltage of the high voltage capacitor 133 associated with the current charging.
v2=Vh2×t/t2... (3b)
i2=I2(1-t/t2)... (4b)
Eoff=∫v2×i2 dt (t=0 to t2)
=Vh2×I2 ² /6α (5b)
However, t2=I2/α.
Therefore, the switching transient loss Poc generated in the switching control element 145 when the inductive element 131 is intermittently controlled in the intermittent cycle T10 and its exciting current is increased/decreased between the first current I1 and the second current I2 is calculated by the formula (6) ).
Poc=(Eon+Eoff)/T10
=Vh×(I1 ² +I2 ² )/(6α×T10) (6)
However, since the increment of the charging voltage by one charging is minute, Vh1≈Vh2, and the voltage fluctuation before and after the charging/discharging of the high-voltage capacitor 133 is, for example, DC70V to DC75V, which is small, so Vh1≈Vh2≈. It is Vh.

Next, in the closed period of the open/close control element 145, the closed circuit energization loss caused by the internal resistance of the open/close control element 145 when the open/close control element 145 is closed is calculated.
In FIG. 5D, the new time at which the first current I1 flowing from the first switching element 145a to the second switching element 145b when the second switching element 145b is closed and is flowing in the inductive element 131 is t= The exciting current i that increases to the second current I2 at time t=Ton is represented by the equation (7a).
i=I1+βt (7a)
However, the current increase rate β is as shown in the equation (7b).
β=(I2-I1)/Ton... (7b)
Therefore, the closed circuit energization loss Pon in the closed circuit time Ton period due to the internal resistance Rs of the switching control element 145 is calculated by the formula (8a) when the integration time is t=0 to Ton.
Pon=∫(I1+βt) ² ×Rsdt/Ton
^{= I2 2 [k + (1} -k) 2/3] Rs ··· (8a)
However, when k=I1/I2 and the closed circuit time Ton is replaced by the intermittent period T10, the formula (8a) is converted into the formula (8b).
^{Pon = I2 2 [k + (} 1-k) 2/3] Rs × (Ton / T10) ··· (8b)

When the exciting current attenuates from the second current I2 to the first current I1, this current is the charging current for the high voltage capacitor 133, and the energizing current of the switching control element 145 becomes zero.
Here, for example, if k=6/14=0.43, the formula (9) is obtained from the formula (8b) and the formula (2).
^{Pon = 0.54 × I2 2 × Rs} × (Ton / T10)
=0.44×I2 ² ×Rs... (9)
However, the internal resistance Ra of the first switching element 145a and the internal resistance Rb of the second switching element 145b, which are connected in parallel, are taken as the total of the closed circuit conduction loss Pa and Pb of each switching element when the total current is I2. The closed circuit energization loss P is expressed by the equations (10a) to (10c).
Pa=0.44×I2 ² ×Ra×[Rb/(Ra+Rb)] ² ... (10a)
Pb=0.44×I2 ² ×Rb×[Ra/(Ra+Rb)] ² ... (10b)
P=Pa+Pb=0.44×I2 ² ×Ra×Rb/(Ra+Rb) ··· (10c)

Next, FIG. 6, which is a diagram showing a list of the power loss in FIG. 1 and the power loss in other modes, will be described in detail. It should be noted that the table of the power loss shown in FIG. 6 and the power loss in other modes is also applied to the vehicle-mounted electronic control device shown in FIG. 11 to be described later, which is a modification of the first embodiment. is there.
In FIG. 6, the morphological classification in the leftmost column shows five types of morphology from the top to the bottom as follows.
The uppermost first form shows the form of FIG. 1 in which a high speed and high resistance first element and a low speed and low resistance second element are used in parallel, which has a large current increase/decrease rate and a large internal resistance when closed.
The second mode of the second stage is a case where only the first element having high speed and high resistance is used in parallel, the characteristics thereof are completely the same, and it is assumed that both operate uniformly without time difference control.
The third mode of the third stage is a case where only the second element having a low speed and low resistance is used in parallel, the characteristics thereof are completely the same, and it is assumed that the two elements operate equally without performing the time difference control.
The modification of the fourth step is the one shown in FIG. 2, in which the first element with high speed and high resistance is decelerated by the smoothing filter by the smoothing capacitor 48a and the smoothing resistor 49a to become the second element with low speed and low resistance. Are second elements of the same type connected in parallel.
However, the internal resistance is assumed to vary by ±13%.
In the reference form at the bottom, the difference between the current increase/decrease rate α and the internal resistance Rs of the high-speed type first element and the low-speed type second element is four times or more, and the internal resistance Rs of the first element is the induction element 131. Is larger than the resistance value of the inductive element 131, and the internal resistance Rs of the second element is smaller than the resistance value of the inductive element 131.

In these form categories, the current increase/decrease rate α and the switching transient loss Poc associated therewith are shown from the left column to the right column, followed by the internal resistance and the closed circuit conduction loss Pon associated therewith, and further the switching transient. The total value of loss and closed circuit conduction loss is listed.
Further, the shared current in the right column shows the shared current of the parallel switching device when the exciting current of the inductive element 131 increases and decreases from the first current I1=6A to the second current I2=14A. The ratio between the total value of the switching transient loss Poc and the total value of the closed circuit energization loss Pon is shown.
As is apparent from the diagram showing this list, in the first and fourth modifications of the uppermost stage shown in FIG. 1 or 2, the loss ratio Poc/Pon is relatively close to 1, and the second ratio In the third and third modes, the ratio fluctuates greatly, and the total value of the switching transient loss Poc and the closed circuit energization loss Pon is also a significantly large value. The switching transient loss Poc is obtained by the formula (6), and the closed circuit energization loss Pon is obtained by the formula (9). Further, V0=75V, I1=6A, I2=14A, and T10=176 μsec.
Therefore, it is apparent that the switching element with high speed and high resistance and the switching element with low speed and low resistance are used together to perform the staggered switching control, whereby the total loss can be significantly reduced and the efficiency of the boost control can be improved.

The first embodiment relates to an opening/closing control element 145 which is connected in series to an inductive element 131 which is an inductive load supplied from a DC power supply 101 and performs a closing operation and an opening operation in response to a logic level of a drive signal voltage GT0. In the energization control circuit unit 240A, the opening/closing control element 145 is configured by a parallel circuit of first and second opening/closing elements 145a and 145b, and one opening/closing element, the first opening/closing element 145a, is the other. The second switching element 145b which is the switching element has a large current increase/decrease rate, and the other switching element has a high conductivity with a smaller internal resistance than one switching element. The drive signal voltage GT0 is distributed to the first gate voltage GT1 and the second gate voltage GT2 by the time difference control circuit 140A, and the first switching element 145a responds to the logic level of the first gate voltage GT1 to perform the closing operation and the opening operation. The second switching element 145b is configured to perform the closing operation and the opening operation in response to the logic level of the second gate voltage GT2, and the time difference control circuit 140A generates the drive signal voltage GT0. First, a first gate voltage GT1 for closing the first switching element 145a is generated, and then a second gate voltage for closing the second switching element 145b with a predetermined second closing delay time Tdon. The time difference control circuit 140A further includes a second time difference setting unit that generates the voltage GT2. When the drive signal voltage GT0 stops, the time difference control circuit 140A first stops the second gate voltage GT2, and then the predetermined first opening delay time Tdoff. Is provided to stop the first gate voltage GT1.

The first switching element 145a, the second switching element 145b, and the parallel switching element 145bb that may be connected in parallel with the second switching element 145b are all field-effect transistors, each of which has a gate terminal. In addition to having the internal parasitic capacitors 146a, 146b, 146bb between the switch terminal and the source terminal, the parallel switching element 145bb, like the second switching element 145b, is highly conductive with a smaller internal resistance than the first switching element 145a. And the internal resistances thereof both have a positive temperature coefficient, so that the parallel switching element 145bb and the second switching element 145b are intermittently controlled by the common second gate voltage GT2. It has become.

As described above, in the first embodiment, the second switching element may be connected in parallel with the parallel switching element having the same internal resistance, and each of them has the positive temperature coefficient and the same first switching element. It is designed to be intermittently controlled by the two-gate voltage GT2.
Therefore, when performing intermittent control of a large current load, the heat generated by the closed circuit energization loss can be shared by multiple switching elements to efficiently dissipate heat, and due to variations in internal resistance, either load When the current becomes larger than the other, the temperature rise of one switching element becomes larger than the other, the internal resistance increases, and the self-correction of the tendency of a uniform current to flow acts, causing an excessive temperature difference. There is a feature that does not occur.
This also applies to the second embodiment.

Further, the current increase/decrease rate α1 during the opening/closing operation of the first switching element 145a is four times or more faster than the current increase/decrease rate α2 of the second switching element 145b and the parallel switching element 145bb. The internal resistance Rs2 of the second switching element 145b and the parallel switching element 145bb at the time of closing operation is lower than ¼ of the internal resistance Rs1 of the first switching element 145a.
As described above, in the first embodiment, the current increase/decrease rate and the internal resistance of the first switching element of high speed/high resistance, the second switching element of low speed/low resistance, and the parallel switching element are 4 times or more each other. There is a gap.
Therefore, while the first switching element absorbs all of the switching transient loss, the closed-circuit conduction loss at the time of closing is shared in inverse proportion to the internal resistance, so the effect of individual variation fluctuations is reduced and the There is a feature that the share of loss can be distributed reliably.
This also applies to the second embodiment.

In addition, the time difference control circuit 140A includes a first temporary difference setting circuit that serves as a first temporary difference setting unit and a second time difference setting circuit that serves as a second time difference setting unit, and the first temporary difference setting circuit uses the drive signal voltage GT0 to change the first temporary difference setting circuit. One temporary closing diode 43a and a first temporary difference setting capacitor 41a that is rapidly charged via a low resistance charging resistor 42, and a high resistance first delay opening circuit that slowly discharges the charge stored in the first temporary difference setting capacitor 41a. The first temporary difference setting circuit is configured by a resistor 45a and sets the first temporary difference setting circuit via the first quick closing diode 43a and the charging resistor 42 when the logic level of the drive signal voltage GT0 becomes the high level “H”. While the capacitor 41a is rapidly charged, the internal parasitic capacitor of the first switching element 145a is connected via the first rapid closing diode 43a, the low resistance first rapid closing resistor 44a, and the waveform shaping element 46 which is a comparator. By generating the first gate voltage GT1 for rapidly charging 146a, the first switching element 145a is rapidly closed, and the first temporary difference setting circuit also sets the logic level of the drive signal voltage GT0 to the low level “L”. At this time, the charge stored in the first temporary difference setting capacitor 41a is slowly discharged through the first delay open circuit resistor 45a, and the residual voltage is less than the comparison reference voltage 47 connected to the negative side input terminal of the waveform shaping element 46. Then, the first gate voltage GT1 is rapidly attenuated by the comparison output of the waveform shaping element 46, and the first switching element 145a is opened rapidly.

As described above, in the first embodiment, the first temporary difference setting capacitor on the side of the first switching element to which the first gate voltage GT1 is applied via the waveform shaping element responds to the logic level of the drive signal voltage GT0. Rapid charging by a low resistance charging resistor or slow discharging by a first delay open circuit resistance is performed, and the waveform shaping element compares the charging voltage of the drive signal voltage GT0 or the first temporary difference setting capacitor with the comparison reference voltage. One gate voltage GT1 is generated to perform the quick closing operation and the delay opening operation of the first switching element.
Therefore, the gate voltage at the time of the opening/closing operation of the first switching element is suddenly increased or delayed immediately by the presence or absence of the drive signal voltage GT0, and is rapidly decreased, thereby suppressing a decrease in the current increase/decrease rate of the first switching element and opening/closing the switching element. There is a feature that it is possible to suppress the occurrence of transient loss due to operation.

A smoothing capacitor 48a is connected to the gate terminal of the first switching element 145a, and a smoothing resistor 49a is connected between the smoothing capacitor 48a and the output terminal of the waveform shaping element 46 to form a filter circuit. The value of the current increase/decrease rate of the first switching element 145a, which decreases with the addition of the filter circuit, is larger than the current increase/decrease rate of the second switching element 145b and the parallel switching element 145bb side. .
As described above, in the first embodiment, the filter circuit including the smoothing capacitor and the smoothing resistor is provided between the gate terminal of the first switching element and the output terminal of the waveform shaping element that drives the first switching element to open and close. It is provided.
Therefore, while suppressing the noise generated by excessively rapidly opening and closing the first switching element, it is possible to perform the rapid switching operation of the first switching element and suppress the switching transient loss that occurs during the switching operation. There is a feature that can be done.

The second time difference setting circuit slowly charges the internal parasitic capacitors 146b and 146bb and a part or all of the second time difference setting capacitor 41b connected to the gate terminal of the second switching element 145b. The second time difference control circuit includes the second delay circuit resistor 45b, and the second time difference control circuit, when the logic level of the drive signal voltage GT0 becomes the high level “H”, the internal parasitic capacitor 146b via the second delay circuit resistor 45b. By charging 146bb and the second time difference setting capacitor 41b, the second gate voltage GT2 rises with a delay, and the second switching element 145b or the second switching element 145b and the parallel switching element 145bb are delayed and closed, The second time difference control circuit also internally operates via the second quick open circuit diode 43b and the low resistance second quick open resistor 44b when the logic level of the drive signal voltage GT0 becomes the low level “L”. By rapidly discharging the charge stored in the parasitic capacitors 146b and 146bb and the second time difference setting capacitor 41b to rapidly reduce the second gate voltage GT2, the second switching element 145b or the second switching element 145b and the parallel switching element are connected. 145bb is designed to be opened rapidly.

As described above, in the first embodiment, the internal parasitic capacitor or the second time difference setting capacitor on the side of the second switching element to which the second gate voltage GT2 is applied responds to the logic level of the drive signal voltage GT0 to generate the first Slow charging by the second delay closing resistance or quick discharge by the second quick opening resistance is performed to perform the delay closing operation or the quick opening operation.
Therefore, the delay closing time of the second switching element fluctuates due to variations in the electrostatic capacitance of its internal parasitic capacitor, but a second time difference setting capacitor is provided to increase the combined capacitance, and the second delay closing time is correspondingly increased. If the resistance value of the resistor is made small, a stable delay closed time can be obtained.

Further, the inductive load is supplied with the power supply voltage Vbb from the DC power supply 101 which is an on-vehicle battery, and the energization control circuit units 240A and 240B including the switching control element 145 perform on/off control of the exciting current, which is higher than the power supply voltage Vbb. An inductive element 131 that obtains a high high voltage Vh and supplies power to the in-vehicle electric load 105, and the booster circuit unit 130 including the inductive element 131 energizes and drives the inductive element 131 by the open/close control element 145. The high voltage capacitor 133 is charged by the induced voltage generated by the inductive element 131 via the charging diode 132 when the circuit 145 is opened. The booster circuit unit 130 supplies the drive signal voltage to the energization control circuit units 240A and 240B. The drive signal generation unit that generates GT0 is provided, and when the charging voltage of the high voltage capacitor 133 is equal to or lower than a predetermined voltage lower limit value Vref21, the drive signal generation unit exceeds the predetermined voltage upper limit value Vref22. The generation of the drive signal voltage GT0 is permitted during the period of, and the open/close control element 145 is closed-circuited with the generation of the drive signal voltage GT0, and the exciting current of the inductive element 131 exceeds the predetermined current upper limit value Vref12. Then, the drive signal output circuit 138 is provided to stop the generation of the drive signal voltage GT0 until the exciting current becomes equal to or lower than the predetermined current lower limit value Vref11 or the predetermined cutoff time ΔT elapses.

As described above, the in-vehicle electronic control device according to the first embodiment intermittently applies the power supply voltage Vbb to the inductive element by the open/close control element, and charges the high voltage capacitor by the inductive voltage generated when the open/close control element opens. The switching control element is provided with a booster circuit unit for obtaining the high voltage Vh, and the switching control element is configured by connecting in parallel a first switching element suitable for high-speed switching and a second switching element having a small internal resistance, and a drive signal generator. Is provided with a time difference control circuit that distributes the drive signal voltage GT0 generated by the first gate voltage GT1 that drives the first switching element to be closed, and the second gate voltage GT2 that drives the second switching element to be closed. Therefore, when the drive signal voltage GT0 is generated, the time difference control circuit delays the second gate voltage GT2 with respect to the first gate voltage GT1 and when the drive signal voltage GT0 is stopped, the first gate voltage GT1 is changed to the second gate voltage GT2. It is supposed to stop later than.

Therefore, the switching transient loss associated with charging a high-voltage capacitor that accumulates a large amount of electrostatic energy even when the capacitance is small is reduced by intermittently controlling a small inductive element that has a large excitation current and a small inductance. In addition, since the conduction loss due to the interruption of a large current is reduced, a small inductive element and a small high voltage capacitor can be used.
When the energization control circuit unit 240B shown in FIG. 8 is applied to the booster circuit unit 130 shown in FIG. 1 instead of the energization control circuit unit 240A shown in FIG. As described in detail in Section 1, the time difference control circuit 140B is supplied with the drive signal voltage GT0 from the drive signal output circuit 138 shown in FIG. The current increases from the first current I1 to the second current I2, and when the drive signal voltage GT0 is stopped, the exciting current decreases from the second current I2 to the first current I1, and the first voltage CMP1 in FIG. For example, a detection voltage corresponding to a current corresponding to 90% of the first current I1 may be set, and a second voltage CMP2 may be set to a detection voltage corresponding to a current corresponding to 90% of the second current I2.

Embodiment 2.
Next, FIG. 7 which is an overall circuit block diagram of the vehicle-mounted electronic control device according to the second embodiment, FIG. 8 which is a detailed circuit diagram of the energization control circuit unit of FIG. 7, and a list of pulse train signals of FIG. The configuration will be described in detail with reference to FIG. The energization control circuit unit shown in FIG. 8 is also applied to an in-vehicle electronic control device that is a modification of the first embodiment shown in FIG. 11 described later.
In FIG. 7, an in-vehicle electronic control device 100B includes a stabilized power supply 110 that generates a control voltage Vcc, an arithmetic control circuit unit 120B that includes a microprocessor CPU, an energization control circuit unit 240B that includes a time difference control circuit 140B, and an inductive property. A discharge control circuit 160 that limits the induced voltage generated when the loads 104a, 104b, and 104c cut off the energization is mainly configured.
A DC power supply 101, which is a DC12V vehicle battery, is connected to the outside of the on-vehicle electronic control unit 100B via a load power switch 102 which is an output contact of a power relay energized by a power switch (not shown). Are connected to each other to supply the power supply voltage Vbb to the in-vehicle electronic control device 100B.
The input sensor 103 including various input sensors and a power switch is connected to the vehicle-mounted electronic control device 100B, and the output load 104 driven by the vehicle-mounted electronic control device 100B is, for example, a linear solenoid as a part thereof. It includes certain inductive loads 104a-104c.

As the internal configuration of the on-vehicle electronic control device 100B, the downstream end of the inductive load 104a is connected to the switching control element 145 in the energization control circuit unit 240B via the combined current detection resistor 175, and the voltage across the combined current detection resistor 175 is connected. Is input to the microprocessor CPU as the current monitoring signal IN via the differential amplifier 176.
In addition, a discharge diode 169a is provided at a connection point between the switching control element 145 and the combined current detection resistor 175, and the discharge diode 169a is connected to the positive side line of the DC power supply 101 via the save capacitor 161 and the backflow prevention diode 162. Or is connected to the negative ground line of the DC power supply 101 via the save capacitor 161.
Further, a series circuit of a voltage limiting diode 163 and an overvoltage detection resistor 164 and a series circuit of a discharging resistor 165 and a discharging transistor 166 are connected in parallel to the evacuation capacitor 161, thereby forming a discharge control circuit 160, and the discharging control circuit 160 is constructed. In the control circuit 160, when the charging voltage of the saving capacitor 161 exceeds the operating voltage Vz of the voltage limiting diode 163, the discharging transistor 166 is closed-circuited to release the charging charge of the saving capacitor 161 and set the charging voltage to a predetermined value. It is limited to.

The arithmetic control circuit unit 120B includes a memory (MEM) 121 including a non-volatile program memory (PMEM) and a data memory (DMEM) and a volatile RAM memory (RMEM), and a multi-channel AD converter (ADC) 122. Is configured by a microprocessor (CPU) 123 which includes a drive signal voltage GT0a as a drive signal voltage GT0 which is a pulse train signal for variably controlling an exciting current for the inductive loads 104a to 104c. , GT0b, GT0c are generated from flag memories (FLGa, FLGb, FLGc) 124a, 124b, 124c.
Similarly, the plurality of inductive loads 104a to 104c are connected to the energization control circuit unit 240B, the differential amplifier 176, and the combined current detection resistor 175, respectively, and the microprocessor (CPU) 123 corresponds to each of the inductive loads 104a to 104c. The drive signal voltages GT0a to GT0c are generated.
However, the discharge control circuit 160 is shared by the inductive loads 104a to 104c, and only the discharge diodes 169a, 169b, 169c are individually connected.
That is, the negative terminals of the inductive loads 104a to 104c are connected to the common save capacitor 161 via the discharge diodes 169a to 169c, respectively.

On the other hand, the switching control element 145 is composed of a parallel circuit of first and second switching elements 145a and 145b, which are field effect transistors similar to those of FIG. 1, and the first switching element 145a is The second switching element 145b has a high conductivity, which has a larger slew rate than that of the second switching element 145b, and has a smaller electrical resistance than the first switching element 145a.
The switching current detection resistor 147a is connected to the source terminal of the first switching element 145a, and the voltage across the switching current detection resistor 147a is input to the time difference control circuit 140B as the first current detection voltage Vss.
As will be described later with reference to FIG. 8, when the first switching element 145a has a current mirror terminal, the switching current detection resistor 147aa can be connected to this terminal to obtain the first current detection voltage Vss. is there.

In FIG. 8, the opening/closing control element 145 to which the first gate voltage GT1 and the second gate voltage GT2 are applied by the time difference control circuit 140B included in the energization control circuit unit 240B has a pair of first and second control elements 145 as in the case of FIG. An example in which one switching element 145a and the second step-up switching element 145b for boosting are connected in parallel and a field effect type parallel switching element 145bb having a small internal resistance at the time of closing is added is indicated by a dotted line. The second gate voltage GT2 is also applied to the parallel switching element 145bb, and the internal parasitic capacitors 146a, 146b and 146bb included in each switching element are shown.
The energization control circuit unit 240B is used for controlling the current of the inductive load shown in FIG. 7, and additionally has switching current detection resistors 147a and 147aa added to the first switching element 145a in FIG. If the first current detection voltage Vss is obtained by using the first current detection voltage Vss, it can be used as a substitute unit of the energization control circuit unit 240A shown in FIG. 1 and can be used for boosting control. Will be described later.
When the drive signal voltage GT0 is of the second embodiment that generates a pulse train signal for performing variable constant current control, the drive signal voltage GT0 is smoothed via the smoothing resistor 171 and the smoothing capacitor 172. Then, the voltage is converted into an analog signal voltage proportional to the target current, and the reduced voltage CMP0 is obtained through the voltage dividing resistor 173. The voltage dividing ratio of the voltage dividing resistor 173 is 90%, for example. .

On the other hand, in the case of the boost control in the first embodiment shown in FIG. 1, the exciting current of the inductive load is at the logic level of the drive signal voltage GT0 until the exciting current increases from the first current I1 to the second current I2. Keeps "H", and when this logic level is inverted to "L", it decreases from the second current I2 to the first current I1, and the smoothing resistor 171, the smoothing capacitor 172, and the voltage dividing resistor 173 are unnecessary. Is.
The time difference control circuit 140B includes a first time difference setting circuit that serves as a first time difference setting unit and a second time difference setting circuit that serves as a second time difference setting unit. The first time difference setting circuit includes a first current comparison circuit 141a. The intermediate logical product element 144a, the temporary storage circuit 142, and the logical sum element 143a are included.
The first current comparison circuit 141a determines whether the value of the first current detection voltage Vss is equal to or higher than the deceleration voltage CMP0 in the second embodiment, or the first current I1 (FIG. 5(D )), the temporary storage circuit 142 is set to be driven via the intermediate logical product element 144a when the drive signal voltage GT0 is generated. .

Along with this, the OR element 143a generates the first gate voltage GT1 immediately after the drive signal voltage GT0 is generated, and the generation of the first gate voltage GT1 is continued while the temporary storage circuit 142 is generating the set signal. When the drive signal voltage GT0 is stopped, the first gate voltage GT1 is stopped with a first open circuit delay time Tdoff (see FIG. 4B) until the temporary storage circuit 142 is reset.
The second time difference setting circuit includes a second current comparison circuit 141b, an intermediate logical product element 144b, a temporary storage circuit 142, and a logical product element 143b.
The second current comparison circuit 141b determines whether the value of the first current detection voltage Vss is equal to or higher than the deceleration voltage CMP0 in the second embodiment or the second current I2 (FIG. 5(D )), the temporary storage circuit 142 is reset driven via the intermediate logical product element 144b.
Accordingly, the logical product element 143b has the second gate delay time Tdon (see FIG. 4D) after the drive signal voltage GT0 is generated until the temporary storage circuit 142 is set and driven. The voltage GT2 is generated, and the second gate voltage GT2 is immediately stopped when the drive signal voltage GT0 is stopped.

Note that the two switches shown in the signal input circuit of FIG. 8 are unnecessary, and the reduction voltage CMP0 is applied or the first voltage CMP1 and the second voltage CMP2 are applied depending on the application. It is displayed as a matter of convenience.
Next, a filter circuit including a smoothing capacitor 148a and a smoothing resistor 149a is provided at the gate terminal of the first switching element 145a so as to suppress noise generation due to a sharp switching operation of the first switching element 145a. It has become.
However, the value of the current increase/decrease rate of the first switching element 145a, which decreases with the addition of this filter circuit, becomes larger than the current increase/decrease rate of the second switching element 145b and the parallel switching element 145bb side. ing.
In addition, a stabilizing circuit including a stabilizing capacitor 148b and a stabilizing resistor 149b is provided at the gate terminal of the second switching element 145b, whereby the second switching element 145b or the second switching element 145b is provided. An excessive opening delay operation due to the internal parasitic capacitors 146b and 146bb of the parallel switching element 145bb is suppressed, and an appropriate opening and closing delay operation is performed.

In FIG. 9, the arithmetic control circuit unit 120B includes a non-volatile data memory, of which 25 units of memory, for example, N=24 bits as one unit, are used as a pulse train signal storage memory.
In the memory S corresponding to the memory number S (S=0 to 24), the logic of S memories in the memory of N=24 bits is “1”, and the logic of N−S memories is “0”. Has become.
The array of the logic "1" and the logic "0" in the memory S is distributed as much as possible in the N-bit memory, and for example, 12 logic "1" are followed by 12 logic ". In the case of arranging "0" and obtaining the energization duty of 50% by one intermittent operation of the switching control element 145, the logical "1" and the logical "0" are alternately arranged and the intermittent operation is performed 12 times. The same energization duty of 50% is obtained.
The arithmetic control circuit unit 120B further includes ring registers RRGa, RRGb, and RRGc each of which has a unit of 24 bits corresponding to the inductive loads 104a to 104c. The ring register has a memory corresponding to a required energization duty γ. The data of S is transferred, and the logic signal of this ring register is sequentially circularly moved by the clock signal CLK of a predetermined cycle, and the logic signal of the final stage is sequentially stored in the flag memories (FLGa, FLGb, FLGc) 124a, 124b, 124c. It is temporarily stored and is output as the drive signal voltages GT0a, GT0b, GT0c.

Hereinafter, the operation and operation of the in-vehicle electronic control device 100B according to the second embodiment configured as shown in FIGS. 7 to 9 will be described in detail.
When the energization control circuit unit 240B shown in FIG. 8 is applied to the in-vehicle electronic control device 100A according to the first embodiment shown in FIG. The time chart, the time chart of the drive signal of the open/close control element in FIG. 4, and the detailed time chart of the drive signal of the open/close control element in FIG. 5 are as described above in the first embodiment.
First, in FIG. 7, when a power switch (not shown) is closed, the load power switch 102, which is the output contact of the power relay, is closed, and the power supply voltage Vbb is applied to the vehicle-mounted electronic control unit 100B.

As a result, the stabilized power supply 110 generates a stabilized control voltage Vcc of DC5V, for example, and the microprocessor (CPU) 123 starts the control operation.
The microprocessor (CPU) 123 responds to the operating state of the input sensor 103 and the content of the control program stored in the non-volatile program memory (PGM) which is a part of the memory (MEM) 121, and responds to the output load 104. A load drive command signal is generated, and drive signal voltages GT0a to GT0c are generated for inductive loads 104a to 104c, which are specific electric loads in the output load 104, to supply a variable constant exciting current. It is like this.
Next, FIG. 10, which is a flowchart for explaining the operation of FIG. 7, will be described. Although the current control of the inductive load 104a will be described here, the same applies to the case of current control for the other inductive loads 104b and 104c.

In FIG. 10, step S1000 is an operation start step in which the microprocessor (CPU) 123 starts current control.
In a succeeding step S1001, it is determined whether or not the initial setting is completed by monitoring an initial setting flag (not shown). If the initial setting is completed, a “YES” determination is made and the process proceeds to step S1003a. This is a determination step of making a "NO" determination and proceeding to step S1002a.
Step S1002a is a step of reading and setting the target current I0. The target inductive load is, for example, a linear solenoid, and dither including a small ripple current is included in order to avoid static friction resistance acting on the drive mechanism. When performing current control, the dither amplitude current ΔI is also set.
The following step S1002b is a step in which the upper limit value and the lower limit value of the target current are set when the dither amplitude is set in step S1002a.
The following step S1002c is a step of estimating the current resistance value of the inductive load 104c by detecting the current value of the power supply voltage Vbb and the installation environment temperature of the inductive load 104c.

The following step S1002d is the energization duty γ0=I0×R/Vbb estimated from the target current, the current voltage and the current resistance, and the energization duty corresponding to the upper limit current setting value I2 and the lower limit current setting value I1 set in step S1002b. This is a step of calculating γ2·γ1 and selecting a memory having a number closest to the energization duty γ0 from the data memory of FIG. 9 and transferring the memory to the ring register RRGa to shift to step S1003a.
The process block S1002 constituted by the processes S1002a to S1002d serves as a means for setting the target energization duty γ, and according to the data table of FIG. 9, the energization duty can be increased or decreased only in 4.2% units. You can't do it.
However, the determination cycle Tc=T0×N (the product of the cycle T0 of the clock signal CLK and the number of bits N of the register) that goes around the ring register is a time constant that is the ratio between the resistance value of the inductive load 104c and the inductance L. It is set to an overwhelmingly smaller value than τ=L/R. For example, if the duty S/N=50 and the duty S/N=54.2 are alternately inverted, the intermediate duty is 52. 0.1% can be obtained, and if the duty S/N=50, 54.2, and 50 are combined and sequentially used alternately, an average duty of (50+54.2+50)/3=51.4 can be obtained.

Similarly, various intermediate duties can be obtained depending on the combination of different types of duty S/N and the degree of their application frequency.
Therefore, if the microprocessor (CPU) 123 performs the proportional/integral control according to the magnitude of the deviation between the target current and the detected current, and selects a value that is closest to the energization duty to be set, the result will be It is possible to perform highly accurate constant current control.
In step S1003a subsequent to step S1002d, it is determined whether or not the dither current is set in step S1002b, and if it is set, a “YES” determination is made and the process proceeds to step S1004, and if not set, “NO” is set. It is a determination step of performing the determination of “” and shifting to step S1003b.
In step S1003b, the energization duty γ0 set in step S1002d or the latest energization duty changed in the subsequent steps S1006a, S1006b, S1009a, and S1009b is maintained, and the latest state of transition to step S1007a is maintained. Is.
In step S1004, it is determined whether it is time to change the size of the dither amplitude, and if it is not the time to change, a "NO" determination is made, the process proceeds to step S1003b, and if it is the time to change, a "YES" determination is made periodically. This is a determination step of performing and shifting to step S1005.

In step S1005, it is determined whether it is a large current period or a small current period of the dither current, and if it is a large current period, a “YES” determination is made, the process proceeds to step S1005, and the energization duty γ2 is set. During the small current period, “NO” is determined and the process proceeds to step S1006a to set the energization duty γ1. During the large current period, “YES” is determined and the process proceeds to step S1006b and the energization duty γ1 is set. This is a determination step in which γ2 is set.
In step S1003b or step S1006a or step S1007a subsequent to step S1006b, in the step S1002a or step S1002b, the target current set value I0 or the upper limit current set value I2 or the lower limit current set value I1 and the current monitoring signal IN are set. It is determined whether or not there is a comparison deviation of the current current read by, and if the comparison deviation is within the allowable value range, a "NO" determination is made and the process proceeds to step S1007b to maintain the current-carrying duty as it is and to compare the comparison deviation. If there is, it is a determination step of making a “YES” determination and proceeding to step S1008.
In step S1008, if the current monitoring signal IN is larger than the set value, a “YES” determination is made and the process proceeds to step S1009a, and if it is smaller, a “NO” determination is made and the process proceeds to step S1009b to reduce the energization duty or This is a positive/negative determination step of the control error in which the amount is increased.
In operation end step S1010 following step S1007b or step S1009a or step S1009b, another control program is executed to return to step S1000 which is an operation start step within a predetermined time limit, and the subsequent steps are repeated. It is supposed to be done.

As is clear from the above description, the time difference control circuit according to the second embodiment has the same configuration as the time difference control circuit 140A shown in FIG. 2 in order to obtain the second closed circuit delay time Tdon and the first open circuit delay time Tdoff. A timer using a resistor and a capacitor is used, and the first current flowing to the first switching element 145a side like the time difference control circuit 140B shown in FIG. 8 is detected by the switching current detection resistors 147a and 147aa. Both of them are applicable to the boost control circuit shown in FIG. 1 or the current control circuit shown in FIG. 7.
However, in the case of the current control circuit of FIG. 7, there is a fundamental difference in the behavior of the switching elements 145a and 145b when the exciting current is rapidly increasing or rapidly decreasing, based on its operating principle.
First, when the time difference control circuit 140A of FIG. 2 is applied to the constant current control circuit of FIG. 7 to obtain a variable constant exciting current by the intermittent operation of the drive signal voltage GT0 (see FIG. 12), for example, a target is set. Regardless of whether the stable control state in which 90% to 110% of the current has already flowed close to the exciting current I0, or the transient state in which the exciting current sharply increases or decreases due to a large deviation from the target current I0. The switching operation of the switching control element 145 is controlled by a timer corresponding to the current increase/decrease rate α.

On the other hand, when the time difference control circuit 140B of FIG. 8 is applied to the constant current control circuit of FIG. 7 to obtain a variable constant exciting current by the intermittent operation of the drive signal voltage GT0, for example, the target exciting current I0 is approached. In the stable control state in which 90% to 110% of the current has already flowed, the exciting current is the first switching element 145a depending on the presence or absence of the deceleration voltage CMP0 which is the detection voltage corresponding to the current of about 90% of the target current I0. It is possible to determine whether or not the current is flowing to the first switching element 145a, or whether the exciting current flowing in the second switching element 145b is transferred to the first switching element 145a.
However, in a transient state in which the exciting current greatly deviates from the target current I0 and the exciting current rapidly increases, the deceleration voltage CMP0 serving as a comparison reference sharply increases, but the actual exciting current is the inductive load. The temporary storage circuit 142 is not set because it rises slowly due to the influence of the induction time constant, and therefore the transition from the first switching element 145a to the second switching element 145b is not performed.

Similarly, in a transient state in which the exciting current greatly deviates from the target current I0 and the exciting current sharply decreases, the deceleration voltage CMP0 serving as the comparison reference sharply decreases, but the actual exciting current is the inductive load. The temporary storage circuit 142 is not reset because it gradually decreases due to the influence of the induction time constant of 1., and the transition from the first switching element 145a to the second switching element 145b is not performed. Therefore, in the case of the time difference control circuit 140B, the second switching element 145b is not closed in the sudden increase/decrease state of the exciting current, and the intermittent operation of the exciting current is always performed only by the first switching element 145a. Will be seen.
As a result, the first switching element 145a shares the closed-circuit conduction loss in the sudden increase/decrease state of the exciting current and the switching transient loss in the constant current stable control state, and the second switching element 145b in the constant current stable control state. It is suitable for variable constant current control of an inductive load that does not increase switching transient loss at a relatively low voltage because it will share the closed-circuit conduction loss at.

The energization control circuit unit 240B is connected to the inductive element 131, which is an inductive load supplied from the DC power supply 101, in series and performs the closing operation and the opening operation in response to the logic level of the drive signal voltage GT0. Therefore, the switching control element 145 is configured by a parallel circuit of first and second switching elements 145a and 145b, and one switching element, the first switching element 145a, is the other switching element. The slew rate has a larger current increase/decrease rate than the second switching element 145b, and the other switching element has a high electrical conductivity with a smaller internal resistance than one switching element, and the drive signal voltage GT0 is The time difference control circuit 140B distributes the first gate voltage GT1 and the second gate voltage GT2, and the first switching element 145a performs the closing operation and the opening operation in response to the logic level of the first gate voltage GT1. The switching element 145b is configured to perform a closing operation and an opening operation in response to the logic level of the second gate voltage GT2, and when the drive signal voltage GT0 is generated, the time difference control circuit 140B is the first switching element. A second time difference for generating a first gate voltage GT1 for closing the circuit 145a, and subsequently generating a second gate voltage GT2 for closing the second switching element 145b with a predetermined second circuit closing delay time Tdon. When the drive signal voltage GT0 is stopped, the time difference control circuit 140A further includes the setting unit, first stops the second gate voltage GT2, and then stops the first gate voltage GT1 with a predetermined first open circuit delay time Tdoff. And a first temporary difference setting unit that does.

Further, the time difference control circuit 140B includes a first temporary difference setting circuit that serves as a first temporary difference setting unit and a second time difference setting circuit that serves as a second time difference setting unit, and the first switching element 145a is connected in series to its source terminal. A first current detection voltage Vss, which is the upstream end potential of the connected switching current detection resistor 147a or the switching current detection resistor 147aa connected to the current mirror terminal, is generated, and the first temporary difference setting circuit is the first current comparison circuit. 141a, the intermediate logical product element 144a, the temporary storage circuit 142, and the logical sum element 143a, the first current comparison circuit 141a determines that the value of the first current detection voltage Vss is inductive during the operation of the drive signal voltage GT0. By generating a voltage equal to or higher than the decrement voltage CMP0 or the predetermined first voltage CMP1 corresponding to a predetermined deceleration current that is close to the target current for the load, the temporary storage circuit via the intermediate logical product element 144a. 142 is set and driven.

The OR element 143a generates the first gate voltage GT1 immediately after the drive signal voltage GT0 is generated, and continues to generate the first gate voltage GT1 while the temporary storage circuit 142 is generating the set signal. When the drive signal voltage GT0 is stopped, the first gate voltage GT1 is stopped with a first open circuit delay time Tdoff until the temporary storage circuit 142 is reset, and the second time difference setting circuit intervenes with the second current comparison circuit 141b. The second current comparison circuit 141b is configured by the logical product element 144b, the temporary storage circuit 142, and the logical product element 143b. In the second current comparison circuit 141b, the value of the first current detection voltage Vss during the suspension of the drive signal voltage GT0 is the deceleration voltage CMP0 or the advance voltage By generating a voltage equal to or higher than the predetermined second voltage CMP2, the temporary storage circuit 142 is reset-driven via the intermediate logical product element 144b, and the logical product element 143b generates the drive signal voltage GT0. The second gate voltage GT2 is generated after the second closed circuit delay time Tdon until the temporary storage circuit 142 is set driven, and the second gate voltage GT2 is immediately stopped when the drive signal voltage GT0 is stopped. There is.

As described above, in the second embodiment, the first switching element includes the switching current detection resistor for generating the first current detection voltage Vss, and the time difference control circuit includes the drive signal voltage GT0 and the first switching element. It is provided with a comparison/determination circuit that determines whether or not the current of the second switching element has shifted to the side of the first switching element when the increase in the current of the element is determined, and when the drive signal voltage GT0 is input to the time difference control circuit. , The first gate voltage GT1 is generated immediately, but the second gate voltage GT2 is generated when the first current detection voltage Vss increases above a predetermined value, and the second gate voltage GT2 is generated when the drive signal voltage GT0 is stopped. GT2 is generated immediately, but the first gate voltage GT1 is stopped when the first current detection voltage Vss increases above a predetermined value and the current of the second switching element shifts to the first switching element side. It has become.

Therefore, the second switching element is prevented from generating the switching transient loss by performing the switching operation during the period when the first switching element is closed, and the first switching element is closed during the closing period. The closed circuit energization loss of the switching element can be reduced, the generated loss can be shared by each other, and the timing of generating and stopping the first gate voltage GT1 and the second gate voltage GT2 does not depend on the timer circuit, and The characteristic is that the one current detection voltage Vss and the reduction voltage CMP0 approaching the current detection voltage corresponding to the target load current or the first voltage CMP1 and the second voltage CMP2 can be compared to make an accurate and quick determination. is there.
In the embodiment shown by the solid line in FIG. 8 (the first voltage CMP1 and the second voltage CMP are not connected), the intermittent period of the drive signal voltage GT0 input to the time difference control circuit 140B is short, and the open/close control element is open. It is suitable for constant current control in which the increase/decrease in the load current due to one intermittent operation is extremely small.

Further, the intermittent period of the drive signal voltage GT0 input to the time difference control circuit 140B is larger than a predetermined intermittent period, and the load current is increased from the first current I1 to the second current I2 by one closing drive command. In the case where the load current is reduced from the second current I2 to the first current I1 by one subsequent open circuit command, the value of the first current detection voltage Vss of the first current comparison circuit 141a approaches the first current I1. Since the first storage voltage CMP1 is equal to or higher than the first voltage CMP1 and the drive signal voltage GT0 is generated, the temporary storage circuit 142 is set driven through the intermediate logical product element 144a, and the second current comparison circuit 141b is The value of the current detection voltage Vss is equal to or higher than the second voltage CMP2 when approaching the second current I2, and the drive signal voltage GT0 is stopped, so that the temporary storage circuit 142 is operated via the intermediate logical product element 144b. It is designed to be reset driven.

As described above, in the second embodiment, the first current comparison circuit uses the first voltage CMP1 approaching the first current I1, which is the lower limit current associated with one intermittent operation of the switching control element, as the comparison input. In the second current comparison circuit, the second voltage CMP2 approaching the second current I2 which is the upper limit current associated with one intermittent operation of the switching control element is used as a comparison input.
Therefore, this embodiment is suitable for application as an alternative means of the energization control circuit unit 240A in the booster circuit unit 130 shown in FIG. 1, and the drive signal voltage GT0 in this case is the drive signal output circuit in FIG. 138 is generated, and the reduced voltage CMP0 by the smoothing resistor 171, the smoothing capacitor 172, and the voltage dividing resistor 173 in FIG. 8 is removed without being used.

The time difference control circuit 140B includes a filter circuit including a smoothing resistor 149a connected to the output circuit of the logical sum element 143a and a smoothing capacitor 148a, and a stabilizing resistor 149b connected to the output circuit of the logical product element 143b. And a stabilizing capacitor 148b, and the filter circuit suppresses a sharp change in the first gate voltage GT1 and suppresses noise generation due to a sharp opening/closing operation of the first switching element 145a. On the other hand, the stabilizing circuit suppresses the fluctuation of the switching transient time due to the fluctuation fluctuation of the internal parasitic capacitors 146b and 146bb of the second switching element 145b or the parallel switching element 145bb, and controls the gate by the second gate voltage GT2. It is intended to stabilize the voltage increase/decrease characteristic.

As described above, in the second embodiment, the gate terminal of the first switching element and the gate terminals of the second switching element and the parallel switching element are provided with the filter circuit and the stabilizing circuit, respectively.
Therefore, while suppressing the noise generated by excessively rapidly opening and closing the first switching element, the rapid switching operation of the first switching element can be performed to suppress the transient loss that occurs during the switching operation. At the same time, the delay closing time of the second switching element fluctuates due to variations in the electrostatic capacitance of the internal parasitic capacitor, but a second time difference setting capacitor is provided to increase the combined capacitance, and the second delay closing By making the resistance value of the resistor small, it is possible to obtain a stable delay circuit closing time, thereby suppressing an increase in circuit closing loss of the first switching element.

Further, the inductive load is supplied with the power supply voltage Vbb from the DC power supply 101 which is an on-vehicle battery, and the energization control circuit units 240A and 240B including the opening/closing control element 145 perform on/off control of the exciting current, and the inductive load of the opening/closing control element 145. An electromagnetic coil that is an inductive load 104a to which a variable or constant exciting current is supplied according to the energization duty γ, and the electromagnetic coil that is the inductive load 104a stores the accumulated electromagnetic energy when the switching control element 145 is opened. The discharge diode 169a that discharges is connected in parallel, and the drive signal voltage GT0 input to the energization control circuit units 240A and 240B is a pulse train signal generated by the drive signal generator, and the pulse train signal is the determination cycle Tc. Energization duty γ=Ton/Tc, which is the ratio of the closed cycle time Ton=S×T0, which is the product of the number S of times the drive signal voltage GT0 is generated, and the one-time generation time T0, to the determination cycle Tc. The exciting current is controlled to be increased/decreased by increasing/decreasing the electric current. The drive signal generating unit responds to the target value of the exciting current for the electromagnetic coil which is the inductive load 104a and the current monitoring signal IN to change the energizing duty γ. It is the arithmetic and control circuit unit 120B that increases and decreases.

As described above, the on-vehicle electronic control device according to the second embodiment intermittently applies the power supply voltage Vbb to the electromagnetic coil that is the inductive load by the switching control element, and the inductive load is generated by the energization duty of the switching control element. Equipped with a drive signal generator that controls the excitation current to the electromagnetic coil to match the target current, and the switching control element is a parallel connection of the first switching element suitable for high-speed switching and the second switching element with low internal resistance. The first gate voltage GT1 for driving the first switching element to be closed and the second switching element for driving the second switching element to be closed by distributing the driving signal voltage GT0 generated by the driving signal generator. The time difference control circuit includes a time difference control circuit for generating the gate voltage GT2. When the drive signal voltage GT0 is generated, the second time difference control circuit delays the second gate voltage GT2 with respect to the first gate voltage GT1 and stops the drive signal voltage GT0. The first gate voltage GT1 is delayed more than the second gate voltage GT2.
Therefore, the switching operation frequency of the switching control element can be increased to improve the control accuracy of the exciting current with respect to the electromagnetic coil that is an inductive load.
When the energization control circuit unit 240A shown in FIG. 2 described in detail in FIG. 12 is applied instead of the energization control circuit unit 240B applied in FIG. 7 (see FIG. 8), the calculation of FIG. The drive signal voltage GT0a generated by the control circuit unit 120B may be directly applied as the drive signal voltage GT0 in FIG.

Further, the discharge diode 169a is connected to the positive side line of the DC power supply 101 via the save capacitor 161 and the backflow prevention diode 162, or is connected to the negative ground line of the DC power source 101 via the save capacitor 161. A series circuit of a voltage limiting diode 163 and an overvoltage detection resistor 164 and a series circuit of a discharging resistor 165 and a discharging transistor 166 are connected in parallel to the evacuation capacitor 161, thereby forming a discharge control circuit 160, and the discharge control circuit 160. When the charging voltage of the saving capacitor 161 exceeds the operating voltage Vz of the voltage limiting diode 163, the discharging transistor 166 is driven in a closed circuit to release the charging charge of the saving capacitor 161 and limit the charging voltage to a predetermined value. When the negative terminal of the save capacitor 161 is connected to the ground line, the operating voltage Vz of the voltage limiting diode 163 is a value larger than the maximum value of the power supply voltage Vbb.

As described above, the on-vehicle electronic control device according to the second embodiment includes the save capacitor charged by the exciting current flowing in the inductive load when the switching control element is opened, and the charge voltage of the save capacitor is The discharge control circuit limits the value to a predetermined value.
Therefore, when the exciting current flowing through the inductive load is larger than the target value, the exciting current can be rapidly attenuated by opening the control switching element to quickly restore the target value. There is a feature that high-precision current control can be performed.
Part of the electromagnetic energy stored in the inductive load is temporarily stored in the escape capacitor when the switching control element opens, and this is gradually consumed by the discharge resistance during the intermittent cycle of the switching control element. Therefore, the discharge resistor does not generate an instantaneous excessive loss, small circuit parts can be used, and if there is an inductive load that is simply interrupted without current control, The save capacitor and the discharge control circuit can be shared by these inductive loads to reduce the cost burden.

Further, the discharge resistor 165 can be eliminated by adding a constant current control function to the discharge transistor 166.
On the other hand, when the exciting current is rapidly attenuated, the switching transient loss of the switching control element increases, and the frequency of intermittent control can be increased, which in turn causes the frequency of switching transient loss to increase. The switching transient loss is characterized by being shared by the first switching element having a large current increase/decrease rate.

Further, the drive signal generation unit includes a plurality of ring registers S (S=1 to n) selected according to the value of the energization duty γ, and the ring register S makes one round with N clock signals and makes a determination cycle. It is composed of N-bit memories corresponding to Tc, and S memories of the N-bit memories are logic “1”, and NS memories are logic “0”, so that the energization duty is γ= The logic signal of each memory of the ring register S is sequentially read by the clock signal having the generation time T0 as a cycle, and this becomes the drive signal voltage GT0.

As described above, the in-vehicle electronic control device according to the second embodiment uses the N-bit ring register that can obtain the determination period Tc with N clock signals, and closes the logic "1" circuit arranged in the ring register. The drive signal voltage GT0 for the energization control circuit unit is generated in response to the command signal, and the energization duty γ=S/N of the switching control element corresponds to the number S of logic "1" in the ring register. Has been decided.
Therefore, when bits having a logic "1" are dispersedly arranged in the N-bit rolling transistor, it is possible to obtain a stable exciting current with little pulsation fluctuation.

For example, in a 100-bit register, 90 bits are logical "0" and 10 bits are logical "1". When these are centrally arranged, a continuous 90 clocks open command and a subsequent 10 clocks closed command. Then, the opening/closing control element performs the intermittent operation only once in 100 clocks, and the energization duty by this becomes γ=10/100.
On the other hand, even if the open command of 9 clocks and the close command of 1 clock are repeated 10 times, the same energization duty is obtained and the pulsation fluctuation of the exciting current is suppressed, but in this case, the intermittent operation is repeated 10 times within the same period. Since it is necessary to perform the operation, the frequency of occurrence of switching transient loss of the switching control element increases.
However, there is a characteristic that the switching transient loss is shared by the first switching element having a large current increase/decrease rate.

Next, with respect to FIG. 11 which is an overall circuit block diagram of the vehicle-mounted electronic control device which is a modification of the first embodiment, the configuration will be described in detail, focusing on the differences from FIG. In the vehicle-mounted electronic control device shown in FIG. 11, the energization control circuit unit shown in FIG. 7 is applied instead of the energization control circuit unit shown in FIG. 11, the in-vehicle electronic control device 100C includes a stabilizing power supply, a calculation control circuit unit, a booster circuit unit, and an electric load drive circuit that is an injector drive circuit, as in the in-vehicle electronic control device 100A in FIG. The circuit unit 130 is the same as that of FIG. 1 except that the energization control circuit unit 240A is changed to the energization control circuit unit 240B.
However, regarding the booster circuit unit 130, although the drive signal output circuit 138 and the combined current detection resistor 135 are shown in FIG. 11, the high voltage capacitor 133, the first comparator 136a, and the second comparator 137a in FIG. Illustration of these and related circuits is omitted.

The energization control circuit unit 240B applied in place of the energization control circuit unit 240A in FIG. 1 has the same internal configuration as that shown in FIG. 8, but the input signal circuit of the energization control circuit unit 240B is the same. Has been modified to fit for the injector drive circuit as follows.
The first difference is that the combined current detection resistor 135 is connected to the downstream side of the switching control element 145 in FIG. 11, whereas the combined current detection resistor 175 in FIG. 8 is connected to the switching control element 145 as shown in FIG. 7. Is connected to the upstream side of.
As a result, since the switching current detection resistor 147a in FIG. 11 is connected in series with the combined current detection resistor 135, the first current detection voltage Vss is the sum of the voltages across the switching current detection resistor 147a and the combined current detection resistor 135. Is becoming
The second difference is that the drive signal voltage GT0 in FIG. 8 is a pulse train signal for constant current control generated by the arithmetic control circuit unit 120B in FIG. 7, but is generated by the drive signal output circuit 138 in FIG. It is the drive signal voltage GT0 for boost control.

Therefore, the smoothing resistor 171, the smoothing capacitor 172, and the voltage dividing resistor 173 in FIG. 8 are omitted, and the first current comparing circuit 141a has the first voltage which is the divided voltage of the current lower limit value Vref11 described in FIG. CMP1 is input, and the second voltage CMP2, which is the divided voltage of the current upper limit value Vref12 described above with reference to FIG. 3, is input to the second current comparison circuit 141b.
In the time difference control circuit 140B in FIG. 11, the intermediate logical product element 144b can be omitted and the temporary storage circuit 142 can be directly reset by the output of the second current comparison circuit 141b.
The reason is that the second voltage CMP2>the first voltage CMP1. Therefore, when the temporary storage circuit 142 is set by the intermediate logical product element 144a, the second current comparison circuit 141b causes the temporary storage circuit 142 to be erroneously set. This is because it will not be reset.

The step-up control operation for the high-voltage capacitor 133 according to that of FIG. 11 is the same as that of FIG. 1, but in the case of FIG. 11, the process in which the element current in FIG. 3B rises from zero to the first current I1. Then, the first switching element 145a is not opened.

Next, FIG. 12, which is an overall circuit block diagram of the vehicle-mounted electronic control unit, which is a modification of the second embodiment, will be described in detail, focusing on differences from FIG. 7. In the vehicle-mounted electronic control device shown in FIG. 12, the power-supply control circuit unit shown in FIG. 2 is applied instead of the power-supply control circuit unit in the vehicle-mounted electronic control device shown in FIG. 7. 12, the in-vehicle electronic control device 100D includes a stabilized power supply 110, an arithmetic control circuit unit 120B, a discharge control circuit 160, a combined current detection resistor 175, and a differential amplifier 176, like the in-vehicle electronic control device 100B in FIG. ing.
However, the energization control circuit unit 240A applied in place of the energization control circuit unit 240B in FIG. 7 has the same internal configuration as that shown in FIG. 2, but the input signal circuit of the energization control circuit unit 240A is the same. Is changed to conform to the variable constant constant current control as follows.

The first difference is that the combined current detection resistor 135 is connected to the downstream side of the switching control element 145 in FIG. 2, whereas the combined current detection resistor 175 in FIG. 12 is connected to the upstream side of the switching control element 145. Has been done.
The second difference is that the drive signal voltage GT0 in FIG. 2 is generated in the drive signal output circuit 138 in the booster circuit unit 130 in FIG. 1, but is generated by the arithmetic control circuit unit 120B in FIG. It is the drive signal voltage GT0a.
As a result, the current control operation for the inductive loads 104a to 104c according to the one shown in FIG. 12 is similar to that shown in FIG.
However, while the time difference control circuit 140B in FIGS. 7 and 8 is of the transition current detection type, the time difference control circuit 140A in FIG. 12 is of the timer type, and therefore the first switching element 145a in the stable current control state. To the second switching element 145b, the margin delay time generated when the current is switched to the second switching element 145b tends to increase the closed-circuit energization loss generated in the first switching element 145a.

Although the present application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments are applicable to particular embodiments. However, the present invention is not limited to this, and can be applied to the embodiments alone or in various combinations.
Therefore, innumerable variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, it is assumed that at least one component is modified, added or omitted, and at least one component is extracted and combined with the components of other embodiments.

101 DC power supply, 131 inductive element (inductive load), 140A time difference control circuit, 145 switching control element, 145a first switching element, 145b second switching element, 240A, 240B energization control circuit unit

An energization control circuit unit for the switching control element disclosed in the present application is connected in series to an inductive load supplied from a DC power source, and performs a closing operation and an opening operation in response to a logic level of a drive signal voltage. In the energization control circuit unit for, the opening/closing control element is configured by a parallel circuit of a first opening/closing element and a second opening/closing element, and one opening/closing element, the first opening/closing element, opens/closes the other. The slew rate has a larger current increase/decrease rate than the second switching element, which is an element, and the other switching element has a high conductivity with a smaller internal resistance than the one switching element. Is distributed to the first gate voltage and the second gate voltage by the time difference control circuit, the first switching element performs the closing operation and the opening operation in response to the logic level of the first gate voltage, and the second switching element is The time difference control circuit is configured to perform the closing operation and the opening operation in response to the logic level of the second gate voltage, and when the drive signal voltage is generated, the first time difference control circuit first closes the first switching element. The time difference control circuit further includes a second time difference setting unit that generates a gate voltage and subsequently generates a second gate voltage for closing the second switching element with a predetermined second closing delay time. When the drive signal voltage stops, the second gate voltage is stopped first, and then the first gate voltage is stopped after a predetermined first open circuit delay time is provided. The first switching element, the second switching element, and the parallel switching element that may be connected in parallel with the second switching element are all field-effect transistors, and each has a gate terminal and a source. In addition to having an internal parasitic capacitor between the terminal and the parallel switching element, like the second switching element, the parallel switching element has a high conductivity with a smaller internal resistance than the first switching element, and also has an internal resistance. Have a positive temperature coefficient, and the parallel switching element and the second switching element are intermittently controlled by the common second gate voltage. Furthermore, the time difference control circuit includes a first time difference setting circuit that serves as a first time difference setting unit and a second time difference setting circuit that serves as a second time difference setting unit. A first temporary difference setting capacitor that is rapidly charged via a closing diode and a low resistance charging resistor, and a high resistance first delay open circuit resistance that slowly discharges the charge stored in the first temporary difference setting capacitor. When the logical level of the drive signal voltage becomes high level, the time difference setting circuit rapidly charges the first time difference setting capacitor via the first quick closing diode and the charging resistor, while The first gate voltage for rapidly charging the internal parasitic capacitor of the first switching element is generated through the diode, the low resistance first quick closing resistor, and the waveform shaping element that is the comparator, and the first gate voltage is generated. When the switching element is driven by the quick closing circuit, and the first temporary difference setting circuit also slows down the charge of the first temporary difference setting capacitor via the first delay open circuit resistance when the logic level of the drive signal voltage becomes low level. When the residual voltage is discharged and becomes less than the comparison reference voltage connected to the negative side input terminal of the waveform shaping element, the first gate voltage is rapidly attenuated by the comparison output of the waveform shaping element, and the first switching element is rapidly changed. It is opened.

Claims (13)

An energization control circuit unit for an opening/closing control element which is connected in series to an inductive load fed from a DC power source and performs a closing operation and an opening operation in response to a logic level of a drive signal voltage,
The opening/closing control element is configured by a parallel circuit of a first opening/closing element and a second opening/closing element, and the first opening/closing element that is one opening/closing element is the second opening/closing element that is the other opening/closing element. The slew rate has a large current increase/decrease rate as compared with the switching element, and the other switching element has a high electrical conductivity with a smaller internal resistance than the one switching element,
The drive signal voltage is distributed to a first gate voltage and a second gate voltage by a time difference control circuit, the first switching element performs a closing operation and an opening operation in response to the logic level of the first gate voltage, The second switching element is configured to perform a closing operation and an opening operation in response to a logic level of the second gate voltage,
When the drive signal voltage is generated, the time difference control circuit first generates a first gate voltage for closing the first switching element, and then a second closed circuit delay time that is set in advance. A second time difference setting unit that generates a second gate voltage for closing the second switching element,
When the drive signal voltage stops, the time difference control circuit further stops the second gate voltage first, and then stops the first gate voltage after a predetermined first open circuit delay time. An energization control circuit unit for the switching control element, which has a setting unit. The first switching element, the second switching element, and the parallel switching element that may be connected in parallel with the second switching element are all field-effect transistors, each of which has a gate terminal and a gate terminal. While having an internal parasitic capacitor between the source terminal and
Similar to the second switching element, the parallel switching element has a high conductivity with a smaller internal resistance than the first switching element, and both the internal resistances have a positive temperature coefficient. The energization control circuit unit for the switching control element according to claim 1, wherein the parallel switching element and the second switching element are intermittently controlled by the common second gate voltage. The current increase/decrease rate at the time of the opening/closing operation of the first opening/closing element is such that the high-speed operation is four times or more as high as the current increase/decrease rate of the second opening/closing element and the parallel opening/closing element.
The opening/closing according to claim 2, wherein the internal resistance of the second switching element and the parallel switching element at the time of the closing operation is 1/4 or less of the internal resistance of the first switching element. Energization control circuit unit for control element. The time difference control circuit includes a first time difference setting circuit that serves as the first time difference setting unit, and a second time difference setting circuit that serves as the second time difference setting unit,
The first temporary difference setting circuit looses the charge stored in the first temporary difference setting capacitor, which is rapidly charged by the drive signal voltage via the first quick-closing diode and the low-resistance charging resistor. It is composed of a high resistance first delay open circuit resistance that discharges quickly,
The first temporary difference setting circuit is configured to rapidly charge the first temporary difference setting capacitor via the first quick closing diode and the charging resistor when the logical level of the drive signal voltage becomes a high level. The first gate voltage for rapidly charging the internal parasitic capacitor of the first switching element via the first quick-closing diode, the low-resistance first quick-closing resistance, and the waveform shaping element that is a comparator. Is generated, the first switching element is rapidly closed circuit driven,
Also, the first temporary difference setting circuit, when the logical level of the drive signal voltage becomes a low level, the charge stored in the first temporary difference setting capacitor is slowly discharged through the first delay open circuit resistor, When the residual voltage becomes less than the comparison reference voltage connected to the negative side input terminal of the waveform shaping element, the first gate voltage is rapidly attenuated by the comparison output of the waveform shaping element to quickly open the first switching element. An energization control circuit unit for the switching control element according to claim 2 or 3. A smoothing capacitor is connected to the gate terminal of the first switching element, and a smoothing resistor is connected between the smoothing capacitor and the output terminal of the waveform shaping element to form a filter circuit. The value of the current increase/decrease rate of the first switching element, which decreases with the addition, is larger than the current increase/decrease rate of the second switching element and the parallel switching element. An energization control circuit unit for the opening/closing control element described in 1. The second time difference setting circuit, a part or all of the internal parasitic capacitor and the second time difference setting capacitor connected to the gate terminal of the second switching element, the internal parasitic capacitor, the second time difference setting capacitor With a second delay circuit resistance to slowly charge the
The second time difference setting circuit charges the internal parasitic capacitor and the second time difference setting capacitor via the second delay circuit resistance when the logical level of the drive signal voltage becomes a high level. The second gate voltage rises with a delay, the second switching element or the second switching element and the parallel switching element is delayed closed drive,
The second time difference setting circuit further includes, when the logical level of the drive signal voltage becomes a low level, the internal parasitic capacitor via the second quick opening diode and the low resistance second quick opening resistor. By rapidly discharging the charge charged in the second time difference setting capacitor and rapidly lowering the second gate voltage, the second switching element or the second switching element and the parallel switching element are rapidly opened. An energization control circuit unit for the switching control element according to claim 4 or 5. The time difference control circuit includes a first time difference setting circuit that serves as the first time difference setting unit, and a second time difference setting circuit that serves as the second time difference setting unit,
The first switching element generates a first current detection voltage, which is an upstream end potential of a switching current detection resistor connected in series to its source terminal or a switching current detection resistor connected to a current mirror terminal,
The first temporary difference setting circuit is composed of a first current comparison circuit, an intermediate logical product element, a temporary storage circuit, and a logical sum element,
The first current comparison circuit, the value of the first current detection voltage during the operation of the drive signal voltage, the decrement voltage corresponding to a predetermined deceleration current approaching the target current for the inductive load, or in advance By generating a voltage equal to or higher than a predetermined first voltage, the set drive of the temporary storage circuit via the intermediate logical product element,
The OR element generates the first gate voltage as soon as the drive signal voltage is generated, and continues the generation of the first gate voltage while the temporary storage circuit is generating the set signal. When the signal voltage is stopped, the first gate voltage is stopped with the first open circuit delay time until the temporary storage circuit is reset,
The second time difference setting circuit is composed of a second current comparison circuit, an intermediate AND element, the temporary storage circuit and an AND element,
The second current comparison circuit, the value of the first current detection voltage during the stop of the drive signal voltage, by generating a voltage of the reduction voltage or a predetermined second voltage or more, Reset driving the temporary storage circuit via an intermediate logical product element,
The AND element generates the second gate voltage after the second closed circuit delay time until the temporary storage circuit is set driven after the drive signal voltage is generated, and the drive signal voltage is The energization control circuit unit for the switching control element according to claim 2 or 3, wherein the second gate voltage is stopped immediately when stopped. The intermittent period of the drive signal voltage input to the time difference control circuit is larger than a predetermined intermittent period, and the load current rises from the first current to the second current by one closing drive command, and the subsequent one time. In which the load current is reduced from the second current to the first current by the open command of
The first current comparison circuit is configured such that the value of the first current detection voltage is equal to or higher than the first voltage when the first current detection voltage approaches the first current, and the drive signal voltage is generated. The temporary storage circuit is set driven through a product element,
The second current comparison circuit is configured such that the value of the first current detection voltage is equal to or higher than the second voltage when approaching the second current, and the drive signal voltage is stopped. The energization control circuit unit for the opening/closing control element according to claim 7, wherein the temporary storage circuit is reset-driven via a product element. The time difference control circuit includes a filter circuit including a smoothing resistor connected to the output circuit of the logical sum element and a smoothing capacitor, and a stabilizing resistor and a stabilizing capacitor connected to the output circuit of the logical product element. Equipped with a stabilization circuit by
Whereas the filter circuit suppresses the abrupt change of the first gate voltage and suppresses the noise generation due to the abrupt switching operation of the first switching element,
The stabilizing circuit suppresses variation of switching transient time due to variation variation of internal parasitic capacitors of the second switching element or the parallel switching element, and stabilizes the increase/decrease characteristic of the gate voltage by the second gate voltage. An energization control circuit unit for the opening/closing control element according to claim 7 or 8, which is for use. The inductive load is supplied with a power supply voltage from the DC power supply which is an on-vehicle battery, and the energization control circuit unit including the opening/closing control element performs on/off control of an exciting current, and a high voltage higher than the power supply voltage. And an inductive element for supplying electric power to an in-vehicle electric load,
A booster circuit unit including the inductive element is a high voltage charged by the inductive voltage generated by the inductive element via a charging diode when the inductive element is energized by the open/close control element to drive the inductive element. Equipped with a capacitor,
The booster circuit unit includes a drive signal generator that generates the drive signal voltage for the energization control circuit unit,
When the charging voltage of the high-voltage capacitor is equal to or lower than a predetermined voltage lower limit value, the drive signal generator generates the drive signal voltage in a period until the charging voltage exceeds a predetermined voltage upper limit value. While permitting, when the switching control element is closed-circuit driven with the generation of the drive signal voltage, and the exciting current of the inductive element exceeds a predetermined current upper limit value, the exciting current is a predetermined current. The switching control element according to claim 6 or 7, further comprising: a drive signal output circuit that stops the generation of the drive signal voltage until it becomes equal to or less than a lower limit value or a predetermined cutoff time elapses. An in-vehicle electronic control device equipped with an energization control circuit unit. The inductive load is supplied with a power supply voltage from the DC power supply which is an on-vehicle battery, and the energization control circuit unit including the opening/closing control element performs on/off control of an exciting current, and the energization duty γ of the opening/closing control element is used. An electromagnetic coil supplied with a variable or constant exciting current,
The electromagnetic coil is connected in parallel with a discharge diode that releases accumulated electromagnetic energy when the switching control element is opened.
The drive signal voltage input to the energization control circuit unit is a pulse train signal generated by a drive signal generator,
The pulse train signal has a ratio of the closed cycle time Ton=S×T0, which is the product of the number S of times of generation of the drive signal voltage generated in the determination cycle Tc, and one generation time T0, and the determination cycle Tc. The exciting current is controlled to be increased or decreased by increasing or decreasing a certain energization duty γ=Ton/Tc,
The opening/closing according to claim 6 or 7, wherein the drive signal generator is an arithmetic and control circuit that adjusts the energization duty γ to increase or decrease in response to a target value of an exciting current for the electromagnetic coil and a current monitoring signal. An in-vehicle electronic control device including an energization control circuit unit for a control element. The discharge diode is connected to the positive side line of the DC power source via a save capacitor and a backflow prevention diode, or connected to the negative side ground line of the DC power source via the save capacitor,
A series circuit of a voltage limiting diode and an overvoltage detection resistor, and a series circuit of a discharge resistor and a discharge transistor are connected in parallel to the save capacitor to form a discharge control circuit,
The discharge control circuit is configured to drive the discharge transistor in a closed circuit when the charging voltage of the save capacitor exceeds the operating voltage of the voltage limiting diode, and discharges the charge stored in the save capacitor. Is limited to the specified value,
The switching control according to claim 11, wherein when the negative side terminal of the save capacitor is connected to the negative side ground line, the operating voltage of the voltage limiting diode is larger than the maximum value of the power supply voltage. An in-vehicle electronic control device including an energization control circuit unit for an element. The drive signal generator includes a plurality of ring registers selected according to the value of the energization duty γ,
The ring register is configured by an N-bit memory corresponding to the determination cycle Tc by making a cycle with N clock signals, and S memories of the N-bit memory become logic "1", and N- Since the S memories have the logic “0”, the energization duty becomes γ=S/N,
The logic signal of each memory of the ring register is sequentially read by the clock signal having the generation time as a cycle to be the drive signal voltage. An in-vehicle electronic control device equipped with an energization control circuit unit.

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