JP2020088274A - Semiconductor unit, electronic device, and semiconductor unit manufacturing method - Google Patents

Semiconductor unit, electronic device, and semiconductor unit manufacturing method Download PDF

Info

Publication number
JP2020088274A
JP2020088274A JP2018223718A JP2018223718A JP2020088274A JP 2020088274 A JP2020088274 A JP 2020088274A JP 2018223718 A JP2018223718 A JP 2018223718A JP 2018223718 A JP2018223718 A JP 2018223718A JP 2020088274 A JP2020088274 A JP 2020088274A
Authority
JP
Japan
Prior art keywords
wiring board
insulating member
semiconductor element
connection portion
solder connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2018223718A
Other languages
Japanese (ja)
Inventor
渉 横田
Wataru Yokota
渉 横田
昌志 磯田
Masashi Isoda
昌志 磯田
晃治 中山
Koji Nakayama
晃治 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP2018223718A priority Critical patent/JP2020088274A/en
Publication of JP2020088274A publication Critical patent/JP2020088274A/en
Withdrawn legal-status Critical Current

Links

Images

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

To provide a semiconductor unit that can improve the stress absorption performance of a solder connection portion, an electronic device, and a semiconductor unit manufacturing method.SOLUTION: An insulating member 4 is arranged between a wiring board 2 and a semiconductor element 3, and a solder connection portion 51 passing through a through hole 41 of the insulating member 4 constitutes an electric connecting portion 5. Since the solder connection portion 51 passes through the through hole 41 of the insulating member 4, a molten solder metal is held by the through hole 41 in a soldering process and is unlikely to hang down due to its own weight. Therefore, by a Z-direction dimension of the insulating member 4 is appropriately set, and therefore, the Z-direction dimension of the solder connection portion 51 can be increased and the stress absorption performance can be improved.SELECTED DRAWING: Figure 1

Description

本発明は、半導体ユニット、電子機器および半導体ユニット製造方法に関する。 The present invention relates to a semiconductor unit, an electronic device and a semiconductor unit manufacturing method.

一般に、半導体素子が配線板に実装された半導体ユニットとして、半導体素子の電極と配線板の電極とがはんだ付けされることで電気的に接続されたものが知られている。このような半導体ユニットでは、配線板の線膨張係数と半導体素子の線膨張係数とが異なることがあり、高温下に配置されたり使用により温度上昇したりした場合に、線膨張係数の差によって、はんだ金属に応力が加わることがある。 In general, a semiconductor unit in which a semiconductor element is mounted on a wiring board is known in which electrodes of the semiconductor element and electrodes of the wiring board are electrically connected by soldering. In such a semiconductor unit, the linear expansion coefficient of the wiring board and the linear expansion coefficient of the semiconductor element may be different, and when they are placed under high temperature or the temperature rises due to use, due to the difference in linear expansion coefficient, Stress may be applied to the solder metal.

そこで、線膨張係数の差によって生じる応力を吸収するために、基板(配線板)から金属配線(電極)を突出させ、この金属配線の先端にはんだボールを設けた接続構造が提案されている(例えば特許文献1参照)。特許文献1に記載された接続構造では、金属配線が変形することにより、線膨張係数の差によって生じる応力を吸収可能となっている。 Therefore, in order to absorb the stress caused by the difference in linear expansion coefficient, a connection structure has been proposed in which a metal wiring (electrode) is projected from a substrate (wiring board) and a solder ball is provided at the tip of this metal wiring ( For example, see Patent Document 1). In the connection structure described in Patent Document 1, the deformation of the metal wiring makes it possible to absorb the stress caused by the difference in linear expansion coefficient.

しかしながら、特許文献1に記載されたように金属配線を変形させる構成では、線膨張係数の差が大きくなった場合に応力を吸収しきれない場合があり、応力吸収性能をさらに向上させることが望まれていた。そこで、配線板と半導体素子との対向方向においてはんだ接続部の寸法を大きくするといった対応が考えられる。しかしながら、対向方向と鉛直方向とを略一致させてはんだ付けする場合、はんだ接続部の対向方向寸法は、はんだ金属の自重と、はんだ金属と電極との間の表面張力と、の関係によって上限が決まってしまう。従って、はんだ接続部の対向方向寸法を大きくすることで応力吸収性能を向上させることは困難であった。 However, in the configuration in which the metal wiring is deformed as described in Patent Document 1, the stress may not be completely absorbed when the difference in linear expansion coefficient becomes large, and it is desired to further improve the stress absorption performance. It was rare. Therefore, it is conceivable to increase the size of the solder connection portion in the direction in which the wiring board and the semiconductor element face each other. However, when soldering while making the facing direction and the vertical direction substantially coincident with each other, the facing direction dimension of the solder connection part has an upper limit due to the relationship between the weight of the solder metal and the surface tension between the solder metal and the electrode. It will be decided. Therefore, it is difficult to improve the stress absorption performance by increasing the size of the solder connection portion in the facing direction.

本発明の目的は、はんだ接続部の応力吸収性能を向上させることができる半導体ユニット、電子機器および半導体ユニット製造方法を提供することである。 An object of the present invention is to provide a semiconductor unit, an electronic device, and a semiconductor unit manufacturing method capable of improving the stress absorption performance of a solder joint.

請求項1に係る発明は、配線板と、前記配線板に重なるように配置される半導体素子と、前記配線板の電極と前記半導体素子の電極とを接続する電気接続部と、を備えた半導体ユニットであって、前記配線板と前記半導体素子との間に配置される絶縁性部材をさらに備え、前記絶縁性部材には、前記配線板と前記半導体素子との対向方向に沿って延在する複数の貫通孔が形成され、前記電気接続部は、前記複数の貫通孔のそれぞれを通過するはんだ接続部を有して構成されていることを特徴とする半導体ユニット
である。
The invention according to claim 1 includes a wiring board, a semiconductor element arranged so as to overlap with the wiring board, and an electrical connecting portion that connects an electrode of the wiring board and an electrode of the semiconductor element. The unit further includes an insulating member arranged between the wiring board and the semiconductor element, and the insulating member extends along a facing direction of the wiring board and the semiconductor element. In the semiconductor unit, a plurality of through holes are formed, and the electrical connection portion is configured to have a solder connection portion that passes through each of the plurality of through holes.

本発明の半導体ユニットによれば、はんだ接続部が絶縁性部材の貫通孔を通過していることで、はんだ付けの工程において、溶融したはんだ金属が貫通孔によって保持され、自重によって垂れ下がりにくい。従って、絶縁性部材の対向方向寸法を適宜に設定することにより、はんだ接続部の対向方向寸法を大きくすることができ、応力吸収性能を向上させることができる。 According to the semiconductor unit of the present invention, since the solder connection portion passes through the through hole of the insulating member, the molten solder metal is held by the through hole during the soldering process and is unlikely to sag due to its own weight. Therefore, by appropriately setting the facing dimension of the insulating member, the facing dimension of the solder connection portion can be increased, and the stress absorption performance can be improved.

本発明の第1実施形態に係る半導体ユニットを示す断面図である。It is a sectional view showing a semiconductor unit concerning a 1st embodiment of the present invention. 前記半導体ユニットの配線板の上面を示す平面図である。It is a top view which shows the upper surface of the wiring board of the said semiconductor unit. 前記半導体ユニットの半導体素子の下面を示す平面図である。It is a top view showing the lower surface of the semiconductor element of the semiconductor unit. 前記配線板の電極と、前記半導体ユニットにおける絶縁性部材の線膨張係数と、の関係を示すグラフである。6 is a graph showing a relationship between an electrode of the wiring board and a linear expansion coefficient of an insulating member in the semiconductor unit. 本発明の第2実施形態に係る半導体ユニットを示す断面図である。It is sectional drawing which shows the semiconductor unit which concerns on 2nd Embodiment of this invention. 本発明の実施例1〜11の条件を示すグラフである。It is a graph which shows the conditions of Examples 1-11 of the present invention.

以下、本発明の各実施形態を図面に基づいて説明する。尚、第2実施形態においては、第1実施形態で説明する構成部材と同じ構成部材及び同様な機能を有する構成部材には、第1実施形態と同じ符号を付すとともに説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the second embodiment, the same components as those described in the first embodiment and components having the same function are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted.

[第1実施形態]
本実施形態の半導体ユニット1Aは、図1に示すように、配線板2と、半導体素子3と、絶縁性部材4と、電気接続部5と、を備える。以下では、配線板2の面内に沿うとともに互いに略直交する2方向をX方向およびY方向とし、配線板2の板厚方向(面直方向)をZ方向とする。また、特に記載がない限り、Z方向は鉛直方向と略一致しているものとする。
[First Embodiment]
As shown in FIG. 1, the semiconductor unit 1A of the present embodiment includes a wiring board 2, a semiconductor element 3, an insulating member 4, and an electrical connection portion 5. In the following, the two directions along the surface of wiring board 2 and substantially orthogonal to each other will be referred to as the X direction and the Y direction, and the plate thickness direction (perpendicular direction) of wiring board 2 will be the Z direction. In addition, the Z direction is substantially the same as the vertical direction unless otherwise specified.

配線板2は、半導体素子3が実装される実装基板であって、図2に示すように、上面21側に複数の電極22が設けられている。また、配線板2は、例えば板厚1mm程度のガラスエポキシを基材として構成されている。尚、図1には1つの半導体素子3のみが示されているが、配線板2には複数の半導体素子が実装されてもよい。 The wiring board 2 is a mounting substrate on which the semiconductor element 3 is mounted, and has a plurality of electrodes 22 provided on the upper surface 21 side as shown in FIG. The wiring board 2 is made of, for example, glass epoxy having a thickness of about 1 mm as a base material. Although only one semiconductor element 3 is shown in FIG. 1, a plurality of semiconductor elements may be mounted on the wiring board 2.

半導体素子3は、全体がXY平面に沿って延びる板状に形成され、Z方向を対向方向として配線板2の上面21側に重なるように配置される。半導体素子3は、例えば、ガラスエポキシを基材とする再配線層31と、再配線層31の上面側(即ち配線板2とは反対側)にダイボンディングされたシリコン製のチップ32と、チップ32を上面側から覆うエポキシ製の保護層33と、を有する。 The entire semiconductor element 3 is formed in a plate shape extending along the XY plane, and is arranged so as to overlap with the upper surface 21 side of the wiring board 2 with the Z direction as the opposite direction. The semiconductor element 3 includes, for example, a rewiring layer 31 made of glass epoxy as a base material, a silicon chip 32 die-bonded to an upper surface side of the rewiring layer 31 (that is, a side opposite to the wiring board 2), and a chip. And a protective layer 33 made of epoxy that covers 32 from the upper surface side.

半導体素子3には、図3に示すように、再配線層31の下面311側に複数の電極34が設けられている。半導体素子3における複数の電極34は、配線板2の複数の電極22のそれぞれに対応して配置されており、具体的には、Z方向において対向するように配置されている。尚、半導体素子は、下面側に電極が設けられたものに限定されず、その側面から電極が突出したものであってもよい。 In the semiconductor element 3, as shown in FIG. 3, a plurality of electrodes 34 are provided on the lower surface 311 side of the redistribution layer 31. The plurality of electrodes 34 of the semiconductor element 3 are arranged corresponding to the plurality of electrodes 22 of the wiring board 2, and specifically, are arranged so as to face each other in the Z direction. The semiconductor element is not limited to the one having the electrode provided on the lower surface side, and may have the electrode protruding from the side surface thereof.

配線板2の電極22および半導体素子3の電極34は、いずれも円形となっており、対応する電極22、34同士の直径が同程度となっている。配線板2の電極22および半導体素子3の電極34は、XY平面において中心部Oから遠くに位置するものほど直径が大きい。各々の電極22、34は、中心部Oから自身の中心に向かって延びる方向が変形方向となる。即ち、電極22、34の変形方向寸法は直径に等しい。 The electrode 22 of the wiring board 2 and the electrode 34 of the semiconductor element 3 are both circular, and the diameters of the corresponding electrodes 22 and 34 are approximately the same. The electrode 22 of the wiring board 2 and the electrode 34 of the semiconductor element 3 have a larger diameter as they are located farther from the central portion O in the XY plane. The direction in which each of the electrodes 22 and 34 extends from the central portion O toward its center is the deformation direction. That is, the dimension of the electrodes 22, 34 in the deformation direction is equal to the diameter.

このとき、電極22、34の直径は、中心部Oから遠ざかるにしたがって3段階以上で大きくなっていることが好ましい。また、隣り合う電極22、34同士は所定の間隔を空けて配置されている。従って、中心部Oに近い領域ほど電極22、34の密度が高くなっている。 At this time, it is preferable that the diameters of the electrodes 22 and 34 increase in three or more steps as the distance from the central portion O increases. Further, the adjacent electrodes 22 and 34 are arranged with a predetermined space therebetween. Therefore, the density of the electrodes 22 and 34 is higher in the region closer to the central portion O.

尚、中心部Oは、半導体素子3が熱変形する際の中心となる位置(変形基準位置)であって、例えば、半導体素子3が円板状である場合にはその円の中心とすればよく、長方形状である場合には対角線の交点とすればよく、他の形状である場合には重心とすればよい。 The central portion O is a position (deformation reference position) that becomes a center when the semiconductor element 3 is thermally deformed, and, for example, when the semiconductor element 3 has a disk shape, it may be a center of the circle. Well, in the case of a rectangular shape, it may be the intersection of diagonal lines, and in the case of other shapes, it may be the center of gravity.

絶縁性部材4は、全体がXY平面に沿って延びる板状に形成され、Z方向において配線板2と半導体素子3との間に挟まれるように配置される。絶縁性部材4には、Z方向に沿って延在する複数の貫通孔41が形成されている。貫通孔41の数は、配線板2の電極22および半導体素子3の電極34の数と同数である。 The insulating member 4 is formed into a plate shape that extends along the XY plane, and is arranged so as to be sandwiched between the wiring board 2 and the semiconductor element 3 in the Z direction. The insulating member 4 is provided with a plurality of through holes 41 extending along the Z direction. The number of through holes 41 is the same as the number of electrodes 22 of wiring board 2 and electrodes 34 of semiconductor element 3.

また、複数の貫通孔41の位置は、配線板2の複数の電極22および半導体素子3の電極34のそれぞれに対応している。貫通孔41は例えば円筒状に形成されているものとする。複数の貫通孔41の直径は互いに等しいものとするが、電極22、34と同様に、XY平面において中心部Oから遠くに位置するものほど直径が大きくなっていてもよい。 The positions of the through holes 41 correspond to the electrodes 22 of the wiring board 2 and the electrodes 34 of the semiconductor element 3, respectively. The through hole 41 is assumed to be formed in a cylindrical shape, for example. Although the diameters of the plurality of through holes 41 are equal to each other, the diameter may be increased as the electrodes 22 and 34 are located farther from the central portion O in the XY plane.

尚、絶縁性部材4は、配線板2および半導体素子3のいずれに対しても直接には固定されていないものとするが、配線板2または半導体素子3に対して固定されてもよい。 The insulating member 4 is not directly fixed to the wiring board 2 or the semiconductor element 3, but may be fixed to the wiring board 2 or the semiconductor element 3.

電気接続部5は、配線板2の電極22と半導体素子3の電極34とを電気的に接続するためのものであって、複数のはんだ接続部51によって構成されている。はんだ接続部51は、複数の貫通孔41のそれぞれを通過するように構成されている。即ち、はんだ金属を溶融させて貫通孔41に充填することによりはんだ接続部51が構成され、はんだ接続部51は円柱状となっている。 The electrical connection portion 5 is for electrically connecting the electrode 22 of the wiring board 2 and the electrode 34 of the semiconductor element 3 and is composed of a plurality of solder connection portions 51. The solder connection portion 51 is configured to pass through each of the plurality of through holes 41. That is, the solder connection portion 51 is formed by melting the solder metal and filling the through hole 41, and the solder connection portion 51 has a cylindrical shape.

尚、はんだ金属の貫通孔41への充填方法は任意であり、例えば棒状のはんだ金属を予め貫通孔41に挿通しておくとともにはんだ金属を溶融させてもよいし、溶融したはんだ金属を貫通孔41内に供給してもよい。 The method of filling the through hole 41 with the solder metal is arbitrary. For example, the rod-shaped solder metal may be inserted into the through hole 41 in advance and the solder metal may be melted. It may be supplied in 41.

さらに、互いに対応する配線板2の電極22およびはんだ接続部51について、絶縁性部材4の線膨張係数をα1とし、配線板2の線膨張係数をα2とし、はんだ接続部51の接合温度をTとし、基準室温をTrとし、XY平面における中心部Oとはんだ接続部51との間の距離をr1とし、XY平面における中心部Oと電極22との間の距離をr2とした際に、電極22の直径D1が式(1)を満足する。 Further, regarding the electrode 22 and the solder connection portion 51 of the wiring board 2 which correspond to each other, the linear expansion coefficient of the insulating member 4 is α1, the linear expansion coefficient of the wiring board 2 is α2, and the joining temperature of the solder connection portion 51 is T When the reference room temperature is Tr, the distance between the center portion O on the XY plane and the solder connection portion 51 is r1, and the distance between the center portion O on the XY plane and the electrode 22 is r2, The diameter D1 of 22 satisfies the formula (1).

Figure 2020088274
Figure 2020088274

即ち、はんだ金属を溶融させる際に、絶縁性部材4および配線板2が接合温度Tまで加熱されると仮定すると、はんだ接続部51と電極22とは、線膨張係数α1、α2、および、中心部Oと間の距離r1、r2に応じて位置ずれする。このとき、直径D1が上記式(1)を満足することにより、はんだ接続部51と電極22とがXY平面内で重なりを有し、これらを電気的に接続することができる。尚、距離r1と距離r2とは互いに等しくてもよい。 That is, assuming that the insulating member 4 and the wiring board 2 are heated to the bonding temperature T when the solder metal is melted, the solder connection portion 51 and the electrode 22 have the linear expansion coefficients α1, α2, and the center. The position is displaced according to the distances r1 and r2 between the section O and the section O. At this time, when the diameter D1 satisfies the above formula (1), the solder connection portion 51 and the electrode 22 have an overlap in the XY plane, and these can be electrically connected. The distance r1 and the distance r2 may be equal to each other.

さらに、互いに対応する半導体素子3の電極34およびはんだ接続部51について、半導体素子3の線膨張係数をα3とし、XY平面における中心部Oと電極34との間の距離をr3とした際に、電極34の直径D2が式(2)を満足する。 Further, regarding the electrode 34 and the solder connection portion 51 of the semiconductor element 3 which correspond to each other, when the linear expansion coefficient of the semiconductor element 3 is α3 and the distance between the central portion O and the electrode 34 in the XY plane is r3, The diameter D2 of the electrode 34 satisfies the equation (2).

Figure 2020088274
Figure 2020088274

即ち、はんだ金属を溶融させる際に、絶縁性部材4および半導体素子3が接合温度Tまで加熱されると仮定すると、はんだ接続部51と電極34とは、線膨張係数α1、α3、および、中心部Oとの間の距離r1、r3に応じて位置ずれする。このとき、直径D2が上記式(2)を満足することにより、はんだ接続部51と電極34とがXY平面内で重なりを有し、これらを電気的に接続することができる。尚、距離r1と距離r3とは互いに等しくてもよい。 That is, assuming that the insulating member 4 and the semiconductor element 3 are heated to the bonding temperature T when the solder metal is melted, the solder connection portion 51 and the electrode 34 have the linear expansion coefficients α1, α3, and the center. The position is displaced according to the distances r1 and r3 between the section O and the section O. At this time, if the diameter D2 satisfies the above formula (2), the solder connection portion 51 and the electrode 34 have an overlap in the XY plane, and these can be electrically connected. The distance r1 and the distance r3 may be equal to each other.

はんだ接続部51の接合温度Tは、はんだ接続部51を構成するはんだ金属の融点に応じて適宜に設定され、例えば、融点の1.05倍や、融点よりも5K高い温度であればよい。また、基準室温Trは、はんだ接続作業が実施される室内の想定温度であればよく、例えば20℃であればよい。 The joining temperature T of the solder connecting portion 51 is appropriately set according to the melting point of the solder metal forming the solder connecting portion 51, and may be 1.05 times the melting point or 5 K higher than the melting point, for example. The reference room temperature Tr may be an assumed temperature in the room where the solder connection work is performed, and may be 20° C., for example.

図4に、式(1)を等式とした場合の絶縁性部材4の線膨張係数をα1と、電極22の直径D1との関係の一例を示す。例えば電極22の直径D1を1mm以下に設定した場合、線膨張係数α1は、130ppm/K以下となる。従って、この条件においては、線膨張係数α1が130ppm/K以下であることが好ましい。 FIG. 4 shows an example of the relationship between the linear expansion coefficient α1 of the insulating member 4 and the diameter D1 of the electrode 22 when the equation (1) is made equal. For example, when the diameter D1 of the electrode 22 is set to 1 mm or less, the linear expansion coefficient α1 is 130 ppm/K or less. Therefore, under this condition, the linear expansion coefficient α1 is preferably 130 ppm/K or less.

ここで、絶縁性部材4の具体的な特性について説明する。絶縁性部材4の線膨張係数は、300ppm/K以下であることが好ましく、上記のように130ppm/K以下であることがより好ましい。また、絶縁性部材4の弾性率は、30Mpa以下であることが好ましい。これらの特性を満たす材質としては、フッ素ゴムやシリコーンが例示される。 Here, specific characteristics of the insulating member 4 will be described. The linear expansion coefficient of the insulating member 4 is preferably 300 ppm/K or less, and more preferably 130 ppm/K or less as described above. The elastic modulus of the insulating member 4 is preferably 30 Mpa or less. Examples of materials that satisfy these characteristics include fluororubber and silicone.

半導体ユニット1Aは、例えばヘッドアップディスプレイ装置等の車載用の電子機器に搭載されたり、熱源を有する電子機器に搭載されたりする。電子機器の使用状態や外部環境によっては、半導体ユニット1Aの温度が上昇する。 The semiconductor unit 1A is mounted in, for example, a vehicle-mounted electronic device such as a head-up display device, or mounted in an electronic device having a heat source. The temperature of the semiconductor unit 1A rises depending on the usage state of the electronic device and the external environment.

このとき、配線板2の線膨張係数α2と半導体素子3の線膨張係数α3との差によって電極22と電極34とが位置ずれしようとする。即ち、はんだ接続部51にせん断応力が加わり、はんだ接続部51がZ方向に対して傾斜するように変形することで応力が吸収される。絶縁性部材4ははんだ接続部51よりも弾性率が低く変形容易に構成されており、はんだ接続部51の変形を阻害しないようになっている。 At this time, the electrode 22 and the electrode 34 tend to be displaced due to the difference between the linear expansion coefficient α2 of the wiring board 2 and the linear expansion coefficient α3 of the semiconductor element 3. That is, shear stress is applied to the solder connection portion 51, and the solder connection portion 51 is deformed so as to be inclined with respect to the Z direction, whereby the stress is absorbed. The insulating member 4 has a lower elastic modulus than the solder connection portion 51 and is configured to be easily deformed, so that the deformation of the solder connection portion 51 is not hindered.

はんだ接続部51が変形する際のせん断ひずみ量は、はんだ接続部51のXY平面内の寸法と、Z方向寸法と、の比率によって決まり、はんだ接続部51のZ方向寸法を大きくするほど、せん断ひずみ量を低減することができる。 The amount of shear strain when the solder connecting portion 51 is deformed is determined by the ratio of the dimension in the XY plane of the solder connecting portion 51 and the dimension in the Z direction, and the larger the Z direction dimension of the solder connecting portion 51, the greater the shearing force. The amount of strain can be reduced.

このような本実施形態によれば、以下のような効果がある。即ち、はんだ接続部51が絶縁性部材4の貫通孔41を通過していることで、はんだ付けの工程において、溶融したはんだ金属が貫通孔41によって保持され、自重によって垂れ下がりにくい。従って、絶縁性部材4のZ方向寸法を適宜に設定することにより、はんだ接続部51のZ方向寸法を大きくすることができ、応力吸収性能を向上させることができる。 According to this embodiment as described above, the following effects can be obtained. That is, since the solder connection portion 51 passes through the through hole 41 of the insulating member 4, the molten solder metal is held by the through hole 41 during the soldering process and is unlikely to hang down due to its own weight. Therefore, by appropriately setting the Z-direction dimension of the insulating member 4, the Z-direction dimension of the solder connection portion 51 can be increased and the stress absorption performance can be improved.

また、はんだ接続部51が絶縁性部材4の貫通孔41を通過していることで、はんだ接続部51の形状の設定自由度が高く、強度を向上させやすい。さらに、絶縁性部材4を設けたり、はんだ接続部51の形状を適宜に設定したりすることにより、配線板2と半導体素子3との相対振動の共振周波数を適宜に設定することができる。即ち、半導体ユニット1Aに対して外部から加わる衝撃の周波数(予測値)と、相対振動の共振周波数と、をずらすことができる。 Further, since the solder connection portion 51 passes through the through hole 41 of the insulating member 4, the degree of freedom in setting the shape of the solder connection portion 51 is high, and the strength can be easily improved. Furthermore, by providing the insulating member 4 and appropriately setting the shape of the solder connection portion 51, the resonance frequency of relative vibration between the wiring board 2 and the semiconductor element 3 can be appropriately set. That is, the frequency (predicted value) of the impact applied to the semiconductor unit 1A from the outside and the resonance frequency of the relative vibration can be shifted.

さらに、絶縁性部材4がはんだ接続部51よりも弾性率が低いことで、はんだ接続部51に応力を吸収させやすくすることができる。 Furthermore, since the insulating member 4 has a lower elastic modulus than the solder connection portion 51, the solder connection portion 51 can easily absorb stress.

また、電極22、34が、XY平面において中心部Oから遠くに位置するものほど直径が大きいことで、はんだ金属を溶融させる際に電極22、34同士の位置ずれが生じやすい領域において、はんだ接続部51と電極22、34とを接続しやすくすることができる。さらに、電極22、34同士の位置ずれが生じにくい領域においては電極22、34を小径とし、電極22、34の密度を向上させることができる。 In addition, since the electrodes 22 and 34 are located farther from the central portion O in the XY plane, the diameter is larger, so that when the solder metal is melted, displacement of the electrodes 22 and 34 is likely to occur. The part 51 and the electrodes 22 and 34 can be easily connected. Further, in the region where the positional displacement between the electrodes 22 and 34 is unlikely to occur, the electrodes 22 and 34 can have a small diameter to improve the density of the electrodes 22 and 34.

また、絶縁性部材4の線膨張係数を300ppm/K以下とすれば、はんだ金属を溶融させる際に電極22、34同士の位置ずれを生じにくくし、電極22、34同士を小径として電極密度を向上させることができる。さらに、絶縁性部材4の線膨張係数を130ppm/K以下とすれば、はんだ金属を溶融させる際に電極22、34同士の位置ずれをより生じにくくし、電極22、34同士を小径として電極密度を向上させることができる。 Further, when the linear expansion coefficient of the insulating member 4 is set to 300 ppm/K or less, the electrodes 22 and 34 are less likely to be misaligned when the solder metal is melted, and the electrodes 22 and 34 have a small diameter to reduce the electrode density. Can be improved. Furthermore, if the linear expansion coefficient of the insulating member 4 is set to 130 ppm/K or less, the positional displacement between the electrodes 22 and 34 is less likely to occur when the solder metal is melted, and the electrodes 22 and 34 are reduced in diameter to reduce the electrode density. Can be improved.

また、絶縁性部材4の弾性率を30Mpa以下とすれば、はんだ接続部51が変形する際に絶縁性部材4が抵抗となりにくく、はんだ接続部51を長寿命化することができる。さらに、絶縁性部材4の線膨張係数を300ppm/K以下とし、且つ、弾性率を30Mpa以下とすれば、はんだ接続部51をより長寿命化することができる。 Further, if the elastic modulus of the insulating member 4 is 30 MPa or less, the insulating member 4 is unlikely to become a resistance when the solder connecting portion 51 is deformed, and the solder connecting portion 51 can have a long life. Furthermore, if the coefficient of linear expansion of the insulating member 4 is 300 ppm/K or less and the elastic modulus is 30 MPa or less, the life of the solder connection part 51 can be further extended.

[第2実施形態]
本実施形態の半導体ユニット1Bは、図5に示すように、配線板2と、半導体素子3と、絶縁性部材4と、電気接続部5と、連結部6と、を備える。即ち、本実施形態の半導体ユニット1Bは、第1実施形態の半導体ユニット1Aに連結部6が追加されたものである。
[Second Embodiment]
As shown in FIG. 5, the semiconductor unit 1B of the present embodiment includes a wiring board 2, a semiconductor element 3, an insulating member 4, an electrical connecting portion 5, and a connecting portion 6. That is, the semiconductor unit 1B of the present embodiment is obtained by adding the connecting portion 6 to the semiconductor unit 1A of the first embodiment.

連結部6は、絶縁物によって、Z方向に沿って延びる柱状に形成され、配線板2と半導体素子3とを連結し、これにより、配線板2と半導体素子3とがXY平面内で相対移動不能となる。尚、連結部6は円柱状であってもよいし角柱状であってもよい。絶縁性部材4は連結部6を貫通しており、これにより、絶縁性部材4は、配線板2および半導体素子3に対して固定され、XY平面内で相対移動不能となる。 The connecting portion 6 is formed of an insulating material in a columnar shape extending in the Z direction, and connects the wiring board 2 and the semiconductor element 3 to each other, whereby the wiring board 2 and the semiconductor element 3 relatively move in the XY plane. It becomes impossible. The connecting portion 6 may have a cylindrical shape or a prismatic shape. The insulating member 4 penetrates the connecting portion 6, whereby the insulating member 4 is fixed to the wiring board 2 and the semiconductor element 3 and cannot move relative to each other in the XY plane.

本実施形態では、連結部6が設けられていることにより、配線板2、半導体素子3および絶縁性部材4が熱変形する際の中心(変形基準位置)は、連結部6が設けられた位置となる。このとき、連結部6の中心を変形基準位置としてもよいし、連結部6の外周部を変形基準位置としてもよい。 In the present embodiment, since the connecting portion 6 is provided, the center (deformation reference position) when the wiring board 2, the semiconductor element 3, and the insulating member 4 are thermally deformed is the position where the connecting portion 6 is provided. Becomes At this time, the center of the connecting portion 6 may be the deformation reference position, or the outer peripheral portion of the connecting portion 6 may be the deformation reference position.

このような本実施形態によれば、前記第1実施形態の効果に加え、以下のような効果がある。即ち、配線板2と半導体素子3とがXY平面内で移動不能に連結されていることで、はんだ金属を溶融させるプロセス中に、外的要因(熱風や振動、各部材間の摩擦係数の差異等)によって配線板2に対して半導体素子3全体が位置ずれすることを抑制することができる。 According to this embodiment as described above, the following effects are obtained in addition to the effects of the first embodiment. That is, since the wiring board 2 and the semiconductor element 3 are immovably connected to each other in the XY plane, external factors (hot air, vibration, difference in friction coefficient between members, etc.) are generated during the process of melting the solder metal. Etc., it is possible to suppress the positional displacement of the entire semiconductor element 3 with respect to the wiring board 2.

また、絶縁性部材4が配線板2および半導体素子3に対してXY平面内で移動不能となっていることで、上記外的要因によって配線板2および半導体素子3に対して絶縁性部材4全体が位置ずれすることを抑制することができる。 Further, since the insulating member 4 is immovable in the XY plane with respect to the wiring board 2 and the semiconductor element 3, the insulating member 4 as a whole is prevented from the wiring board 2 and the semiconductor element 3 due to the external factors. Can be suppressed from being displaced.

なお、本発明は、前記実施形態に限定されるものではなく、本発明の目的が達成できる他の構成等を含み、以下に示すような変形等も本発明に含まれる。 The present invention is not limited to the above-described embodiment, but includes other configurations and the like that can achieve the object of the present invention, and the following modifications and the like are also included in the present invention.

例えば、前記第1実施形態では、絶縁性部材4がはんだ接続部51よりも弾性率が低いであるものとしたが、絶縁性部材4は、はんだ接続部51が応力を吸収するために変形することを許容する程度の弾性率を有していればよい。 For example, in the first embodiment, the insulating member 4 has a lower elastic modulus than the solder connecting portion 51, but the insulating member 4 deforms because the solder connecting portion 51 absorbs stress. What is necessary is just to have an elastic modulus that allows the above.

また、前記第1実施形態では、電極22、34が円状であり、中心部Oから遠くに位置するものほど直径が大きいものとしたが、配線板および半導体素子の電極を矩形状等の他の形状とするとともに、中心部Oから遠くに位置するものほど変形方向の寸法を大きくしてもよい。このとき、変形方向とは、中心部Oと各々の電極とを結ぶ方向である。 In addition, in the first embodiment, the electrodes 22 and 34 are circular, and the diameter of the electrodes located farther from the central portion O is larger. However, the electrodes of the wiring board and the semiconductor element are rectangular or the like. In addition to the above shape, the size in the deformation direction may be increased as the distance from the central portion O increases. At this time, the deformation direction is a direction connecting the central portion O and each electrode.

また、前記第1実施形態では、中心部Oから遠くに位置する電極22、34ほど直径が大きく、且つ、電極22、34の直径D1、D2が式(1)、(2)を満足するものとしたが、配線板および半導体素子の電極の直径(変形方向寸法)は適宜に設定されればよい。例えば、はんだ金属を溶融する際に各部材がどの程度温度上昇するのかを予め測定しておき、式(1)、(2)の溶融温度Tに代えて各部材の温度を用いてもよい。また、必要な電極数が少ない場合や要求される電極密度が低い場合、複数の電極の直径(変形方向寸法)を互いに等しくしてもよい。 In the first embodiment, the electrodes 22 and 34 located farther from the central portion O have a larger diameter, and the diameters D1 and D2 of the electrodes 22 and 34 satisfy the expressions (1) and (2). However, the diameters (dimensions in the deformation direction) of the wiring board and the electrodes of the semiconductor element may be set appropriately. For example, it is possible to measure in advance how much the temperature of each member rises when the solder metal is melted, and use the temperature of each member instead of the melting temperature T in the formulas (1) and (2). In addition, when the required number of electrodes is small or the required electrode density is low, the diameters (dimensions in the deformation direction) of the plurality of electrodes may be equal to each other.

また、前記第1実施形態では、絶縁性部材4の線膨張係数が300ppm/K以下であることが好ましく、弾性率が30Mpa以下であることが好ましいとしたが、絶縁性部材4の各特性は、配線板2、半導体素子3および接続部51の材質や形状、特性等に応じて適宜に設定されればよい。 Further, in the first embodiment, the linear expansion coefficient of the insulating member 4 is preferably 300 ppm/K or less, and the elastic modulus is preferably 30 MPa or less, but each characteristic of the insulating member 4 is The wiring board 2, the semiconductor element 3, and the connecting portion 51 may be appropriately set according to their materials, shapes, characteristics, and the like.

また、前記第2実施形態では、絶縁性部材4が連結部6を貫通することにより、絶縁性部材4が配線板2および半導体素子3に対してXY平面内で移動不能となっているものとしたが、連結部は、絶縁性部材4の外側において配線板2と半導体素子3とを連結するものであってもよい。また、絶縁性部材4を囲むように複数の連結部を配置することにより、絶縁性部材4を配線板2および半導体素子3に対してXY平面内で移動不能としてもよい。 Further, in the second embodiment, since the insulating member 4 penetrates the connecting portion 6, the insulating member 4 is immovable in the XY plane with respect to the wiring board 2 and the semiconductor element 3. However, the connecting portion may connect the wiring board 2 and the semiconductor element 3 outside the insulating member 4. Further, by disposing a plurality of connecting portions so as to surround the insulating member 4, the insulating member 4 may be immovable with respect to the wiring board 2 and the semiconductor element 3 in the XY plane.

その他、本発明を実施するための最良の構成、方法などは、以上の記載で開示されているが、本発明は、これに限定されるものではない。すなわち、本発明は、主に特定の実施形態に関して特に図示され、且つ、説明されているが、本発明の技術的思想および目的の範囲から逸脱することなく、以上述べた実施形態に対し、当業者が様々な変形を加えることができるものである。 Besides, the best configuration, method, and the like for carrying out the present invention have been disclosed in the above description, but the present invention is not limited thereto. That is, the present invention is mainly illustrated and described mainly with respect to specific embodiments, but is not limited to the embodiments described above without departing from the technical idea and the scope of the object of the present invention. Those skilled in the art can make various modifications.

従って、上記に開示した形状、材質などを限定した記載は、本発明の理解を容易にするために例示的に記載したものであり、本発明を限定するものではない。それらの形状、材質などの限定の一部、もしくは全部の限定を外した部材の名称での記載は、本発明に含まれるものである。 Therefore, the description of limiting the shape, the material, and the like disclosed above is given as an example for facilitating the understanding of the present invention, and does not limit the present invention. The description of the members whose names exclude some or all of the limitations of their shapes and materials are included in the present invention.

以下、本発明の実施例について説明する。 Examples of the present invention will be described below.

前記第1実施形態の半導体ユニット1Aにおいて、絶縁性部材4の弾性率を1、10、30、100MPaのいずれかに設定するとともに、線膨張係数を30、100、300ppm/Kのいずれかに設定し、これらを実施例1〜11とした。各実施例の特性は表1および図6に示す通りである。 In the semiconductor unit 1A of the first embodiment, the elastic modulus of the insulating member 4 is set to any one of 1, 10, 30, 100 MPa, and the linear expansion coefficient is set to any one of 30, 100, 300 ppm/K. However, these were made into Examples 1-11. The characteristics of each example are shown in Table 1 and FIG.

Figure 2020088274
Figure 2020088274

上記の実施例1〜11について、温度上昇と温度低下とを繰り返し、はんだ接続部51を繰り返し変形させた際の耐久性をシミュレーションにより評価した。尚、温度は100℃〜―40℃の間で変化させた。はんだ接続部51が破断に至るまでの温度上昇と温度低下のサイクル数(破断サイクル)を表1に示す。 With respect to the above Examples 1 to 11, the temperature rise and the temperature decrease were repeated, and the durability when the solder connection portion 51 was repeatedly deformed was evaluated by simulation. The temperature was changed between 100°C and -40°C. Table 1 shows the number of cycles of temperature increase and temperature decrease until the solder connection part 51 breaks (breaking cycle).

実施例1〜8において、破断サイクルが2000回以上となり、特に良好な結果が得られた。即ち、線膨張係数300ppm/K以下かつ弾性率10MPaの条件と、線膨張係数100ppm/K以下かつ弾性率30MPaの条件と、において特に良好な結果が得られた(図6において破線で囲まれた領域)。また、実施例9〜11においても、破断サイクルが300回以上となり、良好な結果が得られた。 In Examples 1 to 8, the break cycle was 2000 times or more, and particularly good results were obtained. That is, particularly good results were obtained under the conditions of a linear expansion coefficient of 300 ppm/K or less and an elastic modulus of 10 MPa and a condition of a linear expansion coefficient of 100 ppm/K or less and an elastic modulus of 30 MPa (enclosed by a broken line in FIG. 6). region). Further, also in Examples 9 to 11, the break cycle was 300 times or more, and good results were obtained.

1A、1B 半導体ユニット
2 配線板
22 電極
3 半導体素子
34 電極
4 絶縁性部材
41 貫通孔
5 電気接続部
51 はんだ接続部
6 連結部
O 中心部(変形基準位置)
1A, 1B Semiconductor unit 2 Wiring board 22 Electrode 3 Semiconductor element 34 Electrode 4 Insulating member 41 Through hole 5 Electrical connection part 51 Solder connection part 6 Connection part O Center part (deformation reference position)

特開2001−127111号公報JP, 2001-127111, A

Claims (11)

配線板と、前記配線板に重なるように配置される半導体素子と、前記配線板の電極と前記半導体素子の電極とを接続する電気接続部と、を備えた半導体ユニットであって、
前記配線板と前記半導体素子との間に配置される絶縁性部材をさらに備え、
前記絶縁性部材には、前記配線板と前記半導体素子との対向方向に沿って延在する複数の貫通孔が形成され、
前記電気接続部は、前記複数の貫通孔のそれぞれを通過するはんだ接続部を有して構成されていることを特徴とする半導体ユニット。
A semiconductor unit comprising a wiring board, a semiconductor element arranged so as to overlap the wiring board, and an electrical connecting portion connecting an electrode of the wiring board and an electrode of the semiconductor element,
Further comprising an insulating member arranged between the wiring board and the semiconductor element,
The insulating member is formed with a plurality of through holes extending along the facing direction of the wiring board and the semiconductor element,
The semiconductor unit, wherein the electrical connection portion is configured to have a solder connection portion that passes through each of the plurality of through holes.
前記絶縁性部材は、前記はんだ接続部よりも弾性率が低いことを特徴とする請求項1に記載の半導体ユニット。 The semiconductor unit according to claim 1, wherein the insulating member has a lower elastic modulus than the solder connection portion. 前記配線板の電極および前記半導体素子の電極は、面内における所定位置を変形基準位置として、当該変形基準位置から遠くに位置するものほど、前記変形基準位置から延びる変形方向の寸法が大きいことを特徴とする請求項1又は2に記載の半導体ユニット。 With respect to the electrodes of the wiring board and the electrodes of the semiconductor element, with respect to a predetermined reference position in the plane as a deformation reference position, the farther from the deformation reference position, the larger the dimension in the deformation direction extending from the deformation reference position is. The semiconductor unit according to claim 1 or 2, which is characterized. 互いに対応する前記配線板の電極および前記はんだ接続部について、前記絶縁性部材の線膨張係数をα1とし、前記配線板の線膨張係数をα2とし、当該はんだ接続部の接合温度をTとし、基準室温をTrとし、前記変形基準位置と当該はんだ接続部との間の面内距離をr1とし、前記変形基準位置と当該電極との間の面内距離をr2とした際に、当該電極の前記変形方向の寸法D1が、式(1)を満足することを特徴とする請求項3に記載の半導体ユニット。
Figure 2020088274
Regarding the electrodes and the solder connection portions of the wiring board that correspond to each other, the linear expansion coefficient of the insulating member is α1, the linear expansion coefficient of the wiring board is α2, the joining temperature of the solder connection portion is T, and the reference When the room temperature is Tr, the in-plane distance between the deformation reference position and the solder connection portion is r1, and the in-plane distance between the deformation reference position and the electrode is r2, the electrode The semiconductor unit according to claim 3, wherein the dimension D1 in the deformation direction satisfies Expression (1).
Figure 2020088274
互いに対応する前記半導体素子の電極および前記はんだ接続部について、前記絶縁性部材の線膨張係数をα1とし、前記半導体素子の線膨張係数をα3とし、当該はんだ接続部の接合温度をTとし、基準室温をTrとし、前記変形基準位置と当該はんだ接続部との間の面内距離をr1とし、前記変形基準位置と当該電極との間の面内距離をr3とした際に、当該電極の前記変形方向の寸法D2が、式(1)を満足することを特徴とする請求項3に記載の半導体ユニット。
Figure 2020088274
Regarding the electrodes and the solder connection portions of the semiconductor element corresponding to each other, the linear expansion coefficient of the insulating member is α1, the linear expansion coefficient of the semiconductor element is α3, the joining temperature of the solder connection portion is T, and the reference When the room temperature is Tr, the in-plane distance between the deformation reference position and the solder connection portion is r1, and the in-plane distance between the deformation reference position and the electrode is r3, the electrode of the electrode is The semiconductor unit according to claim 3, wherein the dimension D2 in the deformation direction satisfies the expression (1).
Figure 2020088274
前記配線板と前記半導体素子とを連結する連結部をさらに備えることを特徴とする請求項1〜5のいずれか1項に記載の半導体ユニット。 The semiconductor unit according to claim 1, further comprising a connecting portion that connects the wiring board and the semiconductor element. 前記連結部が前記絶縁性部材に挿通されることにより、前記絶縁性部材が前記配線板および前記半導体素子に対して固定されることを特徴とする請求項6に記載の半導体ユニット。 The semiconductor unit according to claim 6, wherein the insulating member is fixed to the wiring board and the semiconductor element by inserting the connecting portion into the insulating member. 前記絶縁性部材の線膨張係数が300ppm/K以下であることを特徴とする請求項1〜7のいずれか1項に記載の半導体ユニット。 The linear expansion coefficient of the said insulating member is 300 ppm/K or less, The semiconductor unit of any one of Claims 1-7 characterized by the above-mentioned. 前記絶縁性部材の弾性率が30Mpa以下であることを特徴とする請求項1〜8のいずれか1項に記載の半導体ユニット。 The elastic unit of the said insulating member is 30 Mpa or less, The semiconductor unit of any one of Claims 1-8 characterized by the above-mentioned. 請求項1〜9のいずれか1項に記載の半導体ユニットを備えたことを特徴とする電子機器。 An electronic device comprising the semiconductor unit according to claim 1. 配線板と、前記配線板に重なるように配置される半導体素子と、前記配線板の電極と前記半導体素子の電極とを接続する電気接続部と、を備えた半導体ユニットを製造する半導体ユニット製造方法であって、
前記配線板と前記半導体素子との間に、これらの対向方向に沿って延在する複数の貫通孔が形成された絶縁性部材を配置し、
はんだ金属を溶融することにより、前記複数の貫通孔のそれぞれを通過するはんだ接続部を形成し、複数の当該はんだ接続部によって前記電気接続部を構成することを特徴とする半導体ユニット製造方法。
Semiconductor unit manufacturing method for manufacturing a semiconductor unit including a wiring board, a semiconductor element arranged so as to overlap with the wiring board, and an electrical connecting portion connecting an electrode of the wiring board and an electrode of the semiconductor element And
Between the wiring board and the semiconductor element, an insulating member having a plurality of through holes extending along the facing direction thereof is arranged,
A method of manufacturing a semiconductor unit, comprising: melting a solder metal to form a solder connection portion that passes through each of the plurality of through holes, and configuring the electrical connection portion by the plurality of solder connection portions.
JP2018223718A 2018-11-29 2018-11-29 Semiconductor unit, electronic device, and semiconductor unit manufacturing method Withdrawn JP2020088274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018223718A JP2020088274A (en) 2018-11-29 2018-11-29 Semiconductor unit, electronic device, and semiconductor unit manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018223718A JP2020088274A (en) 2018-11-29 2018-11-29 Semiconductor unit, electronic device, and semiconductor unit manufacturing method

Publications (1)

Publication Number Publication Date
JP2020088274A true JP2020088274A (en) 2020-06-04

Family

ID=70908880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018223718A Withdrawn JP2020088274A (en) 2018-11-29 2018-11-29 Semiconductor unit, electronic device, and semiconductor unit manufacturing method

Country Status (1)

Country Link
JP (1) JP2020088274A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529390A (en) * 1991-07-19 1993-02-05 Fujitsu Ltd Manufacture of multichip module
JPH1197481A (en) * 1997-09-17 1999-04-09 Fujitsu Ltd Method for mounting semiconductor element and element mounting sheet using the same
JP2001298124A (en) * 2001-04-09 2001-10-26 Hitachi Ltd Bga-type semiconductor device and substrate for packaging the same
JP2005012022A (en) * 2003-06-19 2005-01-13 Ricoh Co Ltd Flip chip packaging body and method for packaging flip chip
JP2007149930A (en) * 2005-11-28 2007-06-14 Renesas Technology Corp Electronic apparatus and manufacturing method thereof
WO2015198836A1 (en) * 2014-06-27 2015-12-30 ソニー株式会社 Semiconductor device and manufacturing method therefor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529390A (en) * 1991-07-19 1993-02-05 Fujitsu Ltd Manufacture of multichip module
JPH1197481A (en) * 1997-09-17 1999-04-09 Fujitsu Ltd Method for mounting semiconductor element and element mounting sheet using the same
JP2001298124A (en) * 2001-04-09 2001-10-26 Hitachi Ltd Bga-type semiconductor device and substrate for packaging the same
JP2005012022A (en) * 2003-06-19 2005-01-13 Ricoh Co Ltd Flip chip packaging body and method for packaging flip chip
JP2007149930A (en) * 2005-11-28 2007-06-14 Renesas Technology Corp Electronic apparatus and manufacturing method thereof
WO2015198836A1 (en) * 2014-06-27 2015-12-30 ソニー株式会社 Semiconductor device and manufacturing method therefor

Similar Documents

Publication Publication Date Title
JP6354831B2 (en) Semiconductor device, method for assembling semiconductor device, component for semiconductor device, and unit module
US7804170B2 (en) Semiconductor device and method of designing the same
JP4710735B2 (en) Manufacturing method of electronic device
US7038313B2 (en) Semiconductor device and method of manufacturing the same
JP2009295959A (en) Semiconductor device, and method for manufacturing thereof
JP6937845B2 (en) Semiconductor device
JP7280789B2 (en) power module
JP5950684B2 (en) Semiconductor device
JP6200759B2 (en) Semiconductor device and manufacturing method thereof
CN108028227A (en) The method of surface mount device and this device of attachment
JP2020088274A (en) Semiconductor unit, electronic device, and semiconductor unit manufacturing method
CN117855153A (en) Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
JP2014120592A (en) Power module
JP5585518B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2014209614A (en) Heat radiator for electronic component
JP3215254B2 (en) High power semiconductor devices
JP5127617B2 (en) Semiconductor device
JP2007250772A (en) Electronic control apparatus
KR102081200B1 (en) Heat radiating structure and method for constructing heat radiating system
JP7495902B2 (en) Semiconductor Package
JP5777175B2 (en) Electronic circuit board and its assembly method
JP7207476B2 (en) Electronic components with metal caps
JP2011071550A (en) Electronic apparatus
WO2014045711A1 (en) Semiconductor module
JP5181369B2 (en) Electronic circuit board and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210819

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220714

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220802

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220921

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230110

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20230308