JP2020080454A - Photoelectric conversion device, photoelectric conversion system, mobile body, and signal processing device - Google Patents

Abstract

To make it possible to reduce noise.SOLUTION: The photoelectric conversion device includes: a plurality of photoelectric conversion elements; and a plurality of analog-digital converters arranged corresponding to the photoelectric conversion elements. Each of the analog-digital converters includes: a comparator for receiving a signal based on charges generated in the photoelectric conversion element; a first switch connecting an input node and an output node of the comparator; and an offset control circuit for changing a voltage of the input node of the comparator using a capacitive element after the first switch is controlled from on to off. The analog-digital converters include a first analog-digital converter and a second analog-digital converter. The capacitance element of the offset control circuit of the first analog-digital converter has a first capacitance value. The capacitive element of the offset control circuit of the second analog-digital converter has a second capacitance value different from the first capacitance value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a photoelectric conversion device, a camera, a moving body, and a signal processing device.

  In recent years, a photoelectric conversion device equipped with a plurality of analog-digital converters (AD converters) is known. Patent Document 1 discloses an imaging device including a plurality of photoelectric conversion elements arranged in a matrix and an AD converter arranged corresponding to each column.

  Patent Document 1 discloses that a predetermined voltage (offset) is applied to an input terminal of the comparison unit after the comparison unit of the AD converter is reset. Further, different offsets are applied to the plurality of AD converters arranged corresponding to the plurality of columns. As a result, when signals of similar levels are input from a plurality of columns, the comparison processing of a plurality of AD converters does not end at the same time, and power concentration is reduced.

JP, 2014-033363, A

  The imaging device described in Patent Document 1 includes a plurality of wirings for supplying offsets having different voltage values to a plurality of AD converters. Since the number of wirings provided in the imaging device increases, the distance between adjacent wirings tends to be short. As a result, noise such as crosstalk may occur.

  In view of the above problems, it is an object of the present invention to reduce noise in a photoelectric conversion device.

  A photoelectric conversion device according to one embodiment includes a plurality of photoelectric conversion elements and a plurality of analog-digital converters arranged corresponding to the plurality of photoelectric conversion elements, and each of the plurality of analog-digital converters. Is a comparator that receives a signal based on the charge generated in the photoelectric conversion element, a first switch that connects an input node and an output node of the comparator, and the first switch is controlled from on to off. And an offset control circuit that changes the voltage of the input node of the comparator by using a capacitive element, the plurality of analog-digital converters including a first analog-digital converter and a second analog-digital converter. An analog-digital converter, wherein the capacitance element of the offset control circuit of the first analog-digital converter has a first capacitance value, and the capacitance element of the offset control circuit of the second analog-digital converter The capacitance element has a second capacitance value different from the first capacitance value.

Equipped with multiple analog-digital converters,
A signal processing apparatus according to another embodiment includes a plurality of analog-digital converters, each of the plurality of analog-digital converters connecting a comparator that receives an analog signal and an input node and an output node of the comparator. And a offset control circuit for changing the voltage of the input node of the comparator by using a capacitive element after the first switch is controlled from on to off. The analog-to-digital converter includes a first analog-to-digital converter and a second analog-to-digital converter, and the capacitance element of the offset control circuit of the first analog-to-digital converter has a first capacitance value. And the capacitance element of the offset control circuit of the second analog-digital converter has a second capacitance value different from the first capacitance value.

  According to the present invention, noise can be reduced.

The figure which shows the structure of a photoelectric conversion apparatus typically. (A) The equivalent circuit diagram which shows the structure of the AD converter of a photoelectric conversion apparatus. (B) A timing chart for explaining the operation of the photoelectric conversion device. (A) The equivalent circuit diagram which shows the structure of the AD converter of a photoelectric conversion apparatus. (B) A timing chart for explaining the operation of the photoelectric conversion device. (A) The equivalent circuit diagram which shows the structure of the AD converter of a photoelectric conversion apparatus. (B) A timing chart for explaining the operation of the photoelectric conversion device. 7A and 7B are timing charts for explaining the operation of the photoelectric conversion device. The figure which shows the structure of a photoelectric conversion apparatus typically. The figure which shows the structure of a photoelectric conversion apparatus typically. 7A and 7B are timing charts for explaining the operation of the photoelectric conversion device. The block diagram of the Example of a photoelectric conversion system. The block diagram of the Example of a mobile body.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The invention is not limited to only the examples described below. A modified example in which a part of the configuration of the embodiment described below is modified without departing from the spirit of the invention is also an embodiment of the invention. Further, an example in which a part of the configuration of any of the following embodiments is added to another example or replaced with a part of the configuration of another example is also an example of the present invention.

  FIG. 1 is a diagram schematically showing the configuration of the photoelectric conversion device of this embodiment. The plurality of photoelectric conversion elements 100 are arranged in a matrix to form a photoelectric conversion element array 101. The photoelectric conversion element array 101 is connected to a vertical scanning circuit 102 that controls in the row direction. The vertical signal line 103 arranged in each column of the photoelectric conversion element array 101 is connected to the corresponding comparator 106. Note that one comparator 106 may be arranged for each photoelectric conversion element 100.

  The comparator 106 has two input nodes. A signal based on the charge generated in the photoelectric conversion element 100 is input to one input node of the comparator 106 via the vertical signal line 103. Further, the ramp reference signal generated by the ramp generation circuit 104 is input to another input node of the comparator 106. The offset control circuit 105 is connected to at least one of the two input nodes of the comparator 106. The offset control circuit 105 changes the voltage of the input node of the comparator 106 by a predetermined amount after the auto-zero operation (reset operation) is performed in the comparator 106. A change in the voltage of the input node of the comparator 106 is also referred to as an offset being added.

  The comparator 106 compares the signal of the vertical signal line 103 and the ramp reference signal RAMP with each other. The comparator 106 supplies the latch pulse signal to the latch 108 at the timing when the magnitude relation between the two is reversed. Upon receiving the latch pulse signal, the latch 108 captures the count signal generated by the counter 107. Through the above operation, AD conversion is performed on the signal based on the charges generated in the photoelectric conversion element 100. That is, the comparator 106 constitutes an analog-digital converter (hereinafter, AD converter). In this embodiment, the plurality of photoelectric conversion elements 100 are arranged in a plurality of columns. A plurality of AD converters are arranged corresponding to the plurality of columns.

  The horizontal scanning circuit 109 sequentially reads the digital values stored in the latch 108 and outputs a digital video signal.

  FIG. 2A is a configuration example showing the comparator 106 and the offset control circuit 105 of the AD converter corresponding to one column. Unless otherwise specified, each of the plurality of AD converters has the configuration shown in FIG.

  The two input nodes inn and inp of the comparator 106 are connected to one vertical line Vsig and one ramp signal line VRMP via capacitive elements C1 and C2, respectively. Further, the switch for the auto-zero operation is controlled by the control signal φ1. The auto-zero operation is an operation of short-circuiting the input node and the output node of the comparator 106, and the auto-zero operation is executed by turning on the switch controlled by the control signal φ1. Since the operating point at which the output of the comparator 106 is inverted is determined by the auto-zero operation, the auto-zero operation may be referred to as the reset operation or the initialization operation of the comparator 106.

  The offset control circuit 105 includes two switches and one capacitive element C3. The capacitive element C3 is a variable capacitance. The plurality of AD converters are divided into a plurality of groups, and different capacitance values can be set among the plurality of groups. The same capacitance value is set for one group of AD converters. A switch controlled by the control signal φ1 and a switch controlled by the control signal φ2 are connected to the first terminal of the capacitive element C3. The switch controlled by the control signal φ1 is connected to the power supply, and the switch controlled by the control signal φ2 is connected to the input node inp of the comparator 106. The second terminal of the capacitive element C3 is grounded.

  FIG. 2B is a timing chart for explaining the operations of the comparator 106 and the offset control circuit 105 of FIG. 2A. VRMP represents the potential of the ramp signal line VRMP (signal value of the ramp reference signal), and the control signals φ1 and φ2 are pulses for controlling the switches, respectively. In the figure, when each control signal is at a high level (hereinafter, hi), the corresponding switch is on (conductive state), and when each control signal is at a low level (hereinafter, lo), the corresponding switch is off (non-conductive state). ).

  While the control signal φ1 is high, VRMP is set to a predetermined level, and the capacitors 106 and C2 perform the auto-zero operation of the comparator 106. The input and output of the comparator 106 are short-circuited, and the input node inp of the comparator 106 becomes a predetermined voltage different from the power supply level. At the same time, the power supply level is held in the capacitive element C3. In the subsequent period, the control signal φ1 is set to lo and then the control signal φ2 is set to hi. As a result, part of the charges set in the capacitive element C3 moves to the capacitive element C2. In other words, the power supply level voltage held in the capacitive element C3 and the voltage held in the input node inp of the comparator 106 are weighted averaged according to the combined capacitance of the capacitive elements C2 and C3. As a result, the voltage of the input node inp of the comparator 106 changes by a predetermined change amount Vshift. This change amount Vshift depends on the ratio of the capacitance values of the capacitive element C2 and the capacitive element C3. For example, if the capacitance value of the capacitive element C3 is different between the first column and the second column, the change amount Vshift can be different. The change amount Vshift is also called an offset amount.

  After this, the control signal φ2 is set to lo, and VRMP ramp-down is started. AD conversion is performed by measuring the time from the start of the ramp-down until the magnitude relationship between the input signals Vsig and VRMP is inverted.

  As described above, in the present embodiment, after the switch connecting the input node and the output node of the comparator 106 is controlled from on to off, the offset control circuit 105 uses the capacitive element C3 to input the comparator 106. Changing the voltage of the node. At this time, for example, the capacitance value of the capacitance element C3 of the offset control circuit 105 of the first column is different from the capacitance value of the capacitance element C3 of the offset control circuit 105 of the second column. Therefore, in the two columns, the voltage at the input node of the comparator 106 changes with different amounts of change (offset amounts).

  With such a configuration, it is possible to reduce the possibility that the comparison processing of a plurality of AD converters will end at the same time. As a result, it is possible to reduce noise while reducing the number of wirings.

  In the above example, the capacitive element C3 is a variable capacitance. However, the capacitive element C3 may have a fixed capacitance value. Even in this case, the two capacitive elements C3 included in different groups have different capacitance values.

  FIG. 3A shows another configuration example of the comparator 106 and the offset control circuit 105 of the photoelectric conversion device. The configuration of the offset control circuit 105 is different from that of the first embodiment. The configuration of the photoelectric conversion device is the same as that of the first embodiment except the configuration of the offset control circuit 105. Therefore, in the present embodiment, only parts different from the first embodiment will be described, and description of the same parts as the first embodiment will be omitted.

  The capacitance value of the capacitive element C3 of this embodiment is variable. Three switches are connected to the capacitive element C3. The first terminal of the capacitive element C3 is connected to the input node of the comparator 106 via the switch controlled by the control signal φ3. The second terminal of the capacitive element C3 is connected to the ground node via the switch controlled by the control signal φ1. Further, the second terminal of the capacitive element C3 is connected to the power supply via the switch controlled by the control signal φ2.

  The operations of the comparator 106 and the offset control circuit 105 of FIG. 3A will be described with reference to FIG. As in FIG. 2B, VRMP indicates the potential of the ramp signal line, and the control signal φ1, the control signal φ2, and the control signal φ3 are pulses for controlling the corresponding switches. The switch is turned on by hi.

  The control signal φ3 is added to the case of FIG. 2B, and the control signal φ3 is hi during the period of the auto-zero operation and the period of the offset giving operation. As in the case of FIG. 2B, the control signal φ1 and the control signal φ2 are controlled. The control signal φ3 becomes lo after the auto-zero operation and the offset giving operation are completed.

  By this operation, first, the auto-zero operation is performed in the state where the first terminal of the capacitive element C3 is connected to the input node inp of the comparator 106. At this time, the second terminal of the capacitive element C3 is grounded. Next, the auto-zero operation ends, and then the power supply level voltage is supplied to the second terminal of the capacitive element C3. The change in the voltage of the second terminal of the capacitive element C3 changes the voltage of the input node inp of the comparator 106 according to the capacitance value of the capacitive element C3. As a result, the voltage of the input node inp of the comparator 106 is controlled in the same manner as in FIG. For example, the capacitance value of the capacitive element C3 of the offset control circuit 105 in the first column is different from the capacitance value of the capacitive element C3 of the offset control circuit 105 in the second column. Therefore, in the two columns, the voltage at the input node of the comparator 106 changes with different amounts of change (offset amounts).

  Thus, in this embodiment, after the switch connecting the input node and the output node of the comparator 106 is controlled from on to off, the offset control circuit 105 uses the capacitive element C3 to input the comparator 106. Changing the node voltage. At this time, for example, the capacitance value of the capacitance element C3 of the offset control circuit 105 of the first column is different from the capacitance value of the capacitance element C3 of the offset control circuit 105 of the second column. Therefore, in the two columns, the voltage at the input node of the comparator 106 changes with different amounts of change (offset amounts).

  With such a configuration, it is possible to reduce the possibility that the comparison processing of a plurality of AD converters will end at the same time. As a result, it is possible to reduce noise while reducing the number of wirings.

  In the above example, the capacitive element C3 is a variable capacitance. However, the capacitive element C3 may have a fixed capacitance value. Even in this case, the two capacitive elements C3 included in different groups have different capacitance values.

  FIG. 4A shows another configuration example of the comparator 106 and the offset control circuit 105 of the photoelectric conversion device. The configuration of the offset control circuit 105 is different from that of the first embodiment. Moreover, the configuration of the capacitive element C2 connected to the input node inp of the comparator 106 is different. Except for these, the configuration of the photoelectric conversion device is the same as that of the first embodiment. Therefore, in the present embodiment, only parts different from the first embodiment will be described, and description of the same parts as the first embodiment will be omitted.

  In FIG. 4A, both the capacitive element C2 and the capacitive element C3 are variable capacitors. The capacitance element C2 and the capacitance element C3 are connected in parallel between the input node inp of the comparator 106 and the ramp signal line VRMP by the switch controlled by the control signal φ2. Specifically, the first terminal of the capacitive element C2 and the first terminal of the capacitive element C3 are both connected to the input node inp of the comparator 106. A switch controlled by the control signal φ2 is connected between the second terminal of the capacitive element C2 and the second terminal of the capacitive element C3. The switch short-circuits the second terminal of the capacitive element C2 and the second terminal of the capacitive element C3 according to the control signal φ2. Further, the second terminal of the capacitive element C3 is connected to the power supply via the switch controlled by the control signal φ1.

  Similar to the first embodiment, the capacitance value of the capacitive element C3 of the offset control circuit 105 of the first column is different from the capacitance value of the capacitive element C3 of the offset control circuit 105 of the second column. In the present embodiment, the capacitance value of the capacitive element C3 in the first column is larger than the capacitance value of the capacitive element C3 in the second column. On the other hand, the capacitance value of the capacitive element C2 in the first column is smaller than the capacitance value of the capacitive element C2 in the second column.

With such a configuration, when the signal value of the ramp reference signal changes, the voltage change at the input node inp of the comparator 106 in the first column and the voltage change at the input node inp of the comparator 106 in the second column. Change is almost the same. As a result, the symmetry of the inputs of the two comparators is improved. Further, the sum of the capacitance value of the capacitive element C3 and the capacitance value of the capacitive element C2 in the AD converter of the first column is equal to It is preferably equal to the sum of the capacitance value of the capacitance element C3 and the capacitance value of the capacitance element C2 in the AD converter. When this condition is satisfied, the symmetry of the inputs of the two comparators 106 is further improved.

  The operation of the comparator 106 and the offset control circuit 105 of FIG. 4A will be described with reference to FIG. As in FIG. 2B, VRMP indicates the potential of the ramp signal line, and the control signals φ1 and φ2 are pulses for controlling the corresponding switches. The switch is turned on by hi.

  Driving of the control signal φ2 is different from that in the case of FIG. First, after the control signal φ1 becomes lo, the control signal φ2 becomes hi. Therefore, after the auto-zero operation of the comparator 106 is completed, the switch controlled by the control signal φ2 is controlled from off to on. The voltage of the second terminal of the capacitive element C3 changes from the power supply level to a level according to the initial value of the ramp reference signal VRMP. Along with this, the voltage of the input node inp of the comparator 106 changes. As described above, the capacitance value of the capacitive element C3 of the offset control circuit 105 of the first column is different from the capacitance value of the capacitive element C3 of the offset control circuit 105 of the second column. Therefore, in the two columns, the voltage at the input node inp of the comparator 106 changes with different amounts of change (offset amounts).

  Next, while the signal value of the ramp reference signal VRMP is changing, that is, during the AD conversion period, the control signal φ2 is maintained at hi. Therefore, while the signal value of the lamp reference signal VRMP is changing, the switch controlled by the control signal φ2 is kept on. The ramp reference signal VRMP is transmitted to the input node inp of the comparator 106 via the combined capacitance of the capacitive element C2 and the capacitive element C3. As described above, the capacitance value of the capacitive element C3 in the first column is larger than the capacitance value of the capacitive element C3 in the second column, while the capacitance value of the capacitive element C2 in the first column is Is smaller than the capacitance value of the capacitive element C2. Therefore, the symmetry of the ramp reference signal VRMP input to the comparator 106 is improved between the first column and the second column.

  As described above, in the present embodiment, after the switch connecting the input node and the output node of the comparator 106 is controlled from on to off, the offset control circuit 105 uses the capacitive element C3. The voltage of the input node of is changed. At this time, for example, the capacitance value of the capacitance element C3 of the offset control circuit 105 of the first column is different from the capacitance value of the capacitance element C3 of the offset control circuit 105 of the second column. Therefore, in the two columns, the voltage at the input node of the comparator 106 changes with different amounts of change (offset amounts).

  With such a configuration, it is possible to reduce the possibility that the comparison processing of a plurality of AD converters will end at the same time. As a result, it is possible to reduce noise while reducing the number of wirings.

  In the above example, the capacitive element C2 and the capacitive element C3 are variable capacitors. However, both the capacitance element C2 and the capacitance element C3 may have a fixed capacitance value. Even in this case, the two capacitive elements C3 included in different groups have different capacitance values.

  The present embodiment is a modification of the operation of the photoelectric conversion devices of Embodiments 1 to 3. Therefore, the configuration of the photoelectric conversion device is the same as that described in the first to third embodiments.

  In this embodiment, in the slope type AD converter, the conversion gain is changed by changing the slope of the ramp reference signal VRMP. FIG. 5 is a diagram illustrating an example of changing the analog gain of the ramp reference signal VRMP. As shown in FIG. 5A, in the low gain setting, the slope of the ramp down is relatively steep. On the other hand, as shown in FIG. 5B, in the high gain setting, the slope of the ramp down is relatively gentle.

  At this time, it is desirable that the offset amount Vshift applied to the input node inp of the comparator 106 by the offset control circuit 105 be changed according to the conversion gain of the AD converter. In this example, the offset amount Vshift is set in inverse proportion to the gain. At the same time, it is desirable to change the difference between the offset amount of the first row and the offset amount of the second row by changing the gain setting. With such a configuration, the processing time including AD conversion can be made substantially constant regardless of the gain setting.

  FIG. 6 is a diagram schematically showing the configuration of the photoelectric conversion device of this embodiment. The photoelectric conversion device of the present embodiment is different from the photoelectric conversion devices of the first to fourth embodiments shown in FIG. 1 in that two comparators 106 are arranged for each one of the vertical signal lines 103. In FIG. 6, circuits subsequent to the input capacitive elements C1 and C2 of the comparator 106 and the latch 108 are omitted. Below, the part different from Examples 1 to 4 will be mainly described.

  In this embodiment, two comparators 106, that is, two AD converters are connected to one vertical signal line 103. With this configuration, one input analog signal can be processed by two AD converters in parallel. Therefore, two digital signals can be obtained in a short time. Random noise can be reduced by adding or averaging two digital signals.

  Each of the two AD converters connected to one vertical signal line 103 includes an offset control circuit 105. Here, the two AD converters connected to one vertical signal line 103 are referred to as a first AD converter and a second AD converter for convenience. The offset control circuit 105 of the first AD converter and the offset control circuit 105 of the second AD converter provide the comparator 106 with offsets of different change amounts (offset amounts).

  By setting different offset amounts for the first AD converter and the second AD converter, the AD conversion timing can be dispersed. As a result, it is possible to obtain the effect of further reducing noise. Although an example in which two comparators 106 are connected to one vertical signal line 103 has been described here, three or more comparators may be connected to one vertical signal line 103.

  In the fourth embodiment, it is preferable that the difference between the offset amount in the AD converter in the first column and the offset amount in the AD converter in the second column be changed by the conversion gain. However, in the case of this embodiment using a plurality of AD converters, there is a trade-off between AD conversion time and noise reduction. Particularly, when the gain is low, the noise reduction amount may be small even if the offset amount difference between the first AD converter and the second AD converter is increased. Therefore, in the first AD converter and the second AD converter, the offset amount may not be inversely proportional to the gain setting.

  FIG. 7 is a diagram schematically showing the configuration of the photoelectric conversion device of this example. FIG. 7 shows one row of the photoelectric conversion elements 100 in the photoelectric conversion element array 101. For convenience, the four photoelectric conversion elements 100 in FIG. 7 will be referred to by adding symbols p1 to p4 in order from the top.

  In this embodiment, two vertical signal lines 103 are arranged for one column of the photoelectric conversion element array 101. For convenience, the two vertical signal lines 103 are labeled with symbols V1 and V2. The vertical signal line V1 is connected to the photoelectric conversion elements p1 and p3. The vertical signal line V2 is connected to the photoelectric conversion elements p2 and p4.

  Two comparators 106, that is, two AD converters (first AD converter AD1 and second AD converter AD2) are arranged for one column of the photoelectric conversion element array 101.

  The vertical signal line V1 and the vertical signal line V2 are selectively connected to the first AD converter AD1 and the second AD converter AD2 via a multiplexer 110 (hereinafter, MUX 110), respectively. The two MUXs 110 are controlled by the selection signal S1 and the selection signal S2, respectively.

  With the above-described configuration, the photoelectric conversion apparatus according to the present embodiment is configured to read the signals of the plurality of photoelectric conversion elements 100 at high speed, process one input signal with two AD converters, and add the obtained digital signals. Alternatively, it is possible to set a mode for reading a low-noise signal by averaging.

  The operation of the photoelectric conversion device of this embodiment will be described with reference to FIG. FIG. 8A is a diagram for explaining the operation in the mode for reading signals at high speed.

  In this mode, the selection signal S1 and the selection signal S2 are always hi. In the first period, the drive signal H1 and the drive signal H2 are simultaneously set to hi. As a result, the photoelectric conversion elements p1 and p2 become active. At this time, the signal from the photoelectric conversion element p1 is AD-converted by the first AD converter AD1. The signal from the photoelectric conversion element p2 is AD-converted by the second AD converter AD2. These operations are shown by period p1 ADC and period p2 ADC in FIG. 8A, respectively.

  In the subsequent second period, the drive signal H3 and the drive signal H4 are simultaneously set to hi. As a result, the photoelectric conversion elements p3 and p4 become active. The signal from the photoelectric conversion element p3 is AD-converted by the first AD converter AD1. The signal from the photoelectric conversion element p4 is AD-converted by the second AD converter AD2. These operations are shown by period p3 ADC and period p4 ADC in FIG. 8A, respectively.

  FIG. 8B is a diagram for explaining the operation in the mode for reading a signal with low noise.

  The driving signals H1 to H4 become hi in order from the first period to the fourth period. Therefore, the photoelectric conversion elements p1 to p4 are activated one by one. During the period when the drive signal H1 is hi, the selection signal S1 is hi and the selection signal S2 is lo. Therefore, the signal from the photoelectric conversion element p1 is input to both the first AD converter AD1 and the second AD converter AD2. Therefore, two digital signals can be obtained in a short time. Each is AD converted.

  Next, while the drive signal H2 is hi, the selection signal S1 is lo and the selection signal S2 is hi. Therefore, the signal from the photoelectric conversion element p2 is input to both the first AD converter AD1 and the second AD converter AD2. Therefore, two digital signals can be obtained in a short time. Each is AD converted.

  In the subsequent third period and fourth period, operations similar to those in the first period and the second period are performed, respectively. As a result, two digital signals are obtained from the signal from the photoelectric conversion element p3. Further, two digital signals are obtained from the signal from the photoelectric conversion element p4.

  In at least one of the above two modes, the offset control circuit 105 gives different offset amounts to the first AD converter AD1 and the second AD converter AD2. With this configuration, it is possible to obtain an image signal with high accuracy and low noise.

  An example of the photoelectric conversion system will be described. Examples of photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, camera heads, copying machines, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. FIG. 9 shows a block diagram of a camera as an example of the photoelectric conversion system.

  In FIG. 9, reference numeral 1001 denotes a barrier for protecting the lens. A lens 1002 forms an optical image of a subject on the image pickup apparatus 1004. Reference numeral 1003 is a diaphragm for changing the amount of light passing through the lens 1002. The photoelectric conversion device described in each of the above-described embodiments is used as the image pickup device 1004.

  A signal processing unit 1007 obtains an image signal by performing processing such as correction and data compression on the pixel signal output from the image pickup apparatus 1004. Further, in FIG. 9, reference numeral 1008 denotes a timing generation section that outputs various timing signals to the image pickup apparatus 1004 and the signal processing section 1007, and 1009 denotes an overall control section that controls the entire camera. Reference numeral 1010 is a frame memory unit for temporarily storing image data. Reference numeral 1011 is an interface unit for recording or reading on a recording medium. Reference numeral 1012 denotes a removable recording medium such as a semiconductor memory for recording or reading the imaged data. Reference numeral 1013 is an interface unit for communicating with an external computer or the like.

  Note that the camera system may include at least the imaging device 1004 and the lens 1002 that focuses the light from the subject on the imaging device 1004.

  As described above, in the embodiment of the photoelectric conversion system, the photoelectric conversion device of each of the above-described embodiments is used as the imaging device 1004. With such a configuration, noise can be reduced in the camera system.

  An example of the moving body will be described. The moving body of this embodiment is an automobile equipped with a vehicle-mounted camera. FIG. 10A schematically shows the appearance and main internal structure of the automobile 2100. The automobile 2100 includes an image pickup device 2102, an image pickup system integrated circuit (ASIC: Application Specific Integrated Circuit) 2103, an alarm device 2112, and a main controller 2113.

  As the imaging device 2102, any of the photoelectric conversion devices described in the above embodiments is used. The alarm device 2112 warns the driver when a signal indicating an abnormality is received from the imaging system, the vehicle sensor, the control unit, or the like. The main control unit 2113 comprehensively controls the operations of the imaging system, the vehicle sensor, the control unit, and the like. The automobile 2100 does not have to include the main control unit 2113. In this case, the imaging system, the vehicle sensor, and the control unit each have a communication interface, and each transmits and receives a control signal via the communication network (for example, CAN standard).

  FIG. 10B is a block diagram showing the system configuration of the automobile 2100. The automobile 2100 includes a first imaging device 2102 and a second imaging device 2102. That is, the vehicle-mounted camera of this embodiment is a stereo camera. A subject image is formed on the imaging device 2102 by the optical unit 2114. The pixel signal output from the imaging device 2102 is processed by the image preprocessing unit 2115, and then transmitted to the imaging system integrated circuit 2103. The image preprocessing unit 2115 performs processing such as SN calculation and addition of synchronization signals.

  The imaging system integrated circuit 2103 includes an image processing unit 2104, a memory 2105, an optical distance measuring unit 2106, a parallax calculation unit 2107, an object recognition unit 2108, an abnormality detection unit 2109, and an external interface (I/F) unit 2116. . The image processing unit 2104 processes the pixel signal to generate an image signal. The image processing unit 2104 also corrects an image signal and complements an abnormal pixel. The memory 2105 temporarily holds the image signal. Further, the memory 2105 may store the position of the abnormal pixel of the known imaging device 2102. The optical distance measuring unit 2106 focuses or measures the distance of the subject using the image signal. The parallax calculation unit 2107 performs subject matching (stereo matching) of parallax images. The object recognition unit 2108 analyzes the image signal and recognizes a subject such as a car, a person, a sign, or a road. The abnormality detection unit 2109 detects a failure or malfunction of the imaging device 2102. When detecting an abnormality or malfunction, the abnormality detection unit 2109 sends a signal indicating that an abnormality has been detected to the main control unit 2113. The external I/F unit 2116 mediates exchange of information between each unit of the imaging system integrated circuit 2103 and the main control unit 2113 or various control units.

  The automobile 2100 includes a vehicle information acquisition unit 2110 and a driving support unit 2111. The vehicle information acquisition unit 2110 includes vehicle sensors such as a speed/acceleration sensor, an angular velocity sensor, a steering angle sensor, a distance measuring radar, and a pressure sensor.

  The driving support unit 2111 includes a collision determination unit. The collision determination unit determines whether there is a possibility of collision with an object, based on the information from the optical distance measuring unit 2106, the parallax calculation unit 2107, and the object recognition unit 2108. The optical distance measuring unit 2106 and the parallax calculation unit 2107 are an example of a distance information acquisition unit that acquires distance information to an object. That is, the distance information is information regarding the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit may determine the possibility of collision using any of these pieces of distance information. The distance information acquisition means may be realized by specially designed hardware or a software module.

  Although the example in which the driving support unit 2111 controls the automobile 2100 so as not to collide with another object has been described, it is possible to control the vehicle 2100 to automatically drive the vehicle so that the vehicle does not stick out of the lane. Is also applicable.

  The automobile 2100 further includes a drive unit used for traveling such as an airbag, an accelerator, a brake, a steering, a transmission and the like. The vehicle 2100 also includes those control units. The control unit controls the corresponding drive unit based on the control signal of the main control unit 2113.

  As described above, the photoelectric conversion device according to any one of the above-described embodiments is used for the imaging device 2102 in the embodiment of the automobile. With such a configuration, noise can be reduced.

100 photoelectric conversion element 105 offset control circuit 106 comparator C1 capacitance element C2 capacitance element C3 capacitance element

Claims (16)

A plurality of photoelectric conversion elements,
A plurality of analog-digital converters arranged corresponding to the plurality of photoelectric conversion elements,
Each of the plurality of analog-digital converters,
A comparator for receiving a signal based on the charge generated in the photoelectric conversion element,
A first switch connecting an input node and an output node of the comparator;
An offset control circuit that changes the voltage of the input node of the comparator using a capacitive element after the first switch is controlled from on to off;
The plurality of analog-digital converters include a first analog-digital converter and a second analog-digital converter,
The capacitance element of the offset control circuit of the first analog-digital converter has a first capacitance value;
The capacitance element of the offset control circuit of the second analog-digital converter has a second capacitance value different from the first capacitance value,
A photoelectric conversion device characterized by the above. The amount of change in voltage by the offset control circuit in the first analog-digital conversion is different from the amount of change in voltage by the offset control circuit in the first analog-digital conversion.
The photoelectric conversion device according to claim 1, wherein: The offset control unit includes a second switch connecting a first terminal of the capacitive element and the input node of the comparator,
From the state in which the first switch is on and the second switch is off, the first switch is controlled from on to off, and then the second switch is controlled from off to on. The
The photoelectric conversion device according to claim 1 or 2, characterized in that. The offset control circuit includes a third switch that connects the first terminal of the capacitive element and a power supply,
The third switch is controlled by the same control signal as the first switch,
The photoelectric conversion device according to claim 3, wherein The offset control circuit includes a fourth switch that connects the second terminal of the capacitive element and a power supply, and a fifth switch that connects the second terminal of the capacitive element and a ground node. ,
The fifth switch is controlled by the same control signal as the first switch,
The photoelectric conversion device according to claim 3, wherein The analog-digital converter has a first terminal connected to the input node of the comparator, and a second terminal receiving a reference signal to be compared with a signal based on the charge generated in the photoelectric conversion element. Including a second capacitive element,
A first terminal of the capacitive element included in the offset control circuit is connected to the input node of the comparator,
The offset control circuit includes a second switch connecting the second terminal of the capacitive element and the second terminal of the second capacitive element.
The photoelectric conversion device according to claim 1 or 2, characterized in that. The capacitance value of the capacitance element of the first analog-digital converter is larger than the capacitance value of the capacitance element of the second analog-digital converter,
A capacitance value of the second capacitance element of the first analog-digital converter is smaller than a capacitance value of the second capacitance element of the second analog-digital converter,
The photoelectric conversion device according to claim 6, wherein. The sum of the capacitance value of the capacitance element and the capacitance value of the second capacitance element in the first analog-digital converter is the capacitance value of the capacitance element in the second analog-digital converter and the second capacitance value of the second capacitance element. Equal to the sum of the capacitance values of the capacitive elements of
The photoelectric conversion device according to claim 6 or 7, characterized in that. From the state in which the first switch is on and the second switch is off, the first switch is controlled from on to off, and then the second switch is controlled from off to on. The
The photoelectric conversion device according to claim 6, wherein the photoelectric conversion device is a photoelectric conversion device. The second switch is kept on while the signal value of the reference signal is changing,
The photoelectric conversion device according to claim 9, wherein The first capacitance value of the capacitive element of the first analog-digital converter is variable,
The second capacitance value of the capacitance element of the second analog-digital converter is variable,
The photoelectric conversion device according to any one of claims 1 to 10, characterized in that. The first capacitance value and the second capacitance value change according to the conversion gain of the first analog-digital converter and the conversion gain of the second analog-digital converter,
The photoelectric conversion device according to claim 11, wherein: The plurality of photoelectric conversion elements are arranged in a plurality of rows,
Multiple signal lines are arranged corresponding to multiple columns,
The first analog-digital converter and the second analog-digital converter are connected to one of the plurality of signal lines,
The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is a photoelectric conversion device. A photoelectric conversion device according to any one of claims 1 to 13,
A signal processing device that processes a signal from the photoelectric conversion device,
A photoelectric conversion system characterized in that Is a mobile,
The photoelectric conversion system according to claim 14,
And a control unit that controls the moving body based on an image signal acquired by the photoelectric conversion system,
A moving body characterized by the above. Equipped with multiple analog-digital converters,
Each of the plurality of analog-digital converters,
A comparator that receives an analog signal,
A first switch connecting an input node and an output node of the comparator;
An offset control circuit that changes the voltage of the input node of the comparator using a capacitive element after the first switch is controlled from on to off;
The plurality of analog-digital converters include a first analog-digital converter and a second analog-digital converter,
The capacitance element of the offset control circuit of the first analog-digital converter has a first capacitance value;
The capacitance element of the offset control circuit of the second analog-digital converter has a second capacitance value different from the first capacitance value,
A signal processing device characterized by the above.

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