JP2020062565A - Game machine - Google Patents

Abstract

To provide a game machine, if a communication interruption occurs between a main control circuit and a sub control circuit, allowing a confirmation of occurrence of the error, the occurrence date and time, and the content.SOLUTION: A sub control circuit includes a sub CPU achieving: display processing means for performing processing to display an image in a liquid crystal display device (a liquid crystal display area 23); and communication interruption determination means for determining that a communication interruption state occurs if a state occurs where command data has not been received for a predetermined time or longer. If a communication interruption state occurs, the communication interruption determination means has a function to store a code indicating the communication interruption and the time and date of a built-in RTC in an error information history storage area of a sub RAM. The display processing means has a function to display in the liquid crystal display device the code indicating the communication interruption and the time and date when the code was stored that are stored in the error information history storage area.SELECTED DRAWING: Figure 49

Description

  The present invention relates to a gaming machine such as a pachi-slot.

  Conventionally, a gaming machine called a so-called pachi-slot is known. In such a gaming machine, a plurality of reels having a plurality of symbols arranged on their respective surfaces, game medals, coins, etc. (hereinafter referred to as "medals, etc.") are inserted, and the start lever is operated by the player. It is detected that the start switch requesting the start of rotation of the plurality of reels and the stop button provided corresponding to each of the plurality of reels are pressed by the player, and the corresponding reel is rotated. And a stop switch that outputs a signal requesting the stop of the.

  Further, such a gaming machine is provided corresponding to each of the plurality of reels, and stepping motors for transmitting respective driving forces to the respective reels, and stepping based on signals output by the start switch and the stop switch A reel control unit that controls the operation of the motor to rotate and stop each reel.

  With this configuration, when the gaming machine detects that the start lever has been operated, it performs a lottery based on a random number value, and the result of this lottery (hereinafter referred to as “internal winning combination”) and the stop button have been operated. The rotation of the reel is stopped on the basis of the timing at which is detected.

  In recent years, as a game machine of this type, after a big bonus (hereinafter, referred to as “BB”) in which a game that gives a relatively large profit to a player can be performed a predetermined number of times, a replay related to a replay is determined as an internal winning combination. It is known that a gaming state with a high probability of being operated (hereinafter, referred to as "high RT") is activated (for example, refer to Patent Document 1).

  Further, in this gaming machine, when a predetermined condition is satisfied while the BB is operating or a gaming state in which the replay probability is low is operating, in addition to the above-mentioned high RT, a specific internal winning combination relating to the payout of medals. An assist time (hereinafter referred to as "AT") for notifying (hereinafter referred to as "small winning combination") is activated. The state in which both the high RT and the AT are activated is called ART.

  According to the gaming machine, during the operation of ART, the probability of losing the winning combination is lower than that in the normal gaming state, and the probability of winning the small winning combination is high, so that the medals to be paid out are increased. be able to. Therefore, it is possible to attract the interest of the player and enhance the playability thereof.

  Further, in recent years, by internally winning a predetermined small winning combination (for example, cherry) during a general game, a predetermined number of games are generated with a predetermined probability of a special game state advantageous to the player (hereinafter referred to as a chance zone). , A gaming machine that internally wins a predetermined small winning combination in the chance zone to add a chance zone of a predetermined number of games with a predetermined probability (for example, see Patent Document 2), or a predetermined small winning combination (for example, replay) There is known a gaming machine that shifts to a high RT state by continuously winning an internal prize over a plurality of games. According to the gaming machine, the player's interest is sustained by appropriately extending the number of continuous games in the chance zone that is advantageous to the player and expecting the ART state to operate by shifting to a high RT. You can

  On the other hand, the CPU of the main control circuit performs the important processing of the gaming machine, such as the control of the rotating reels of the gaming machine, the internal winning combination processing, the winning determination processing, the medal payout processing, etc. It is executed according to a program stored in advance in the ROM.

  The internal winning combination is determined based on the random number and the internal lottery table, and the rotation of each reel is stopped based on the determined internal winning combination and the timing at which the reel stop operation is detected. At this time, the extracted random number value is stored in the random number value storage area of the RAM, and the internal winning combination is determined in the internal lottery process based on the stored random number value.

  Further, the sub-control circuit performs various processes such as determination and execution of effect data based on various commands output from the main control circuit such as a start command. Therefore, the sub-control circuit also has a RAM, and in the RAM, various information obtained by the processing of the CPU of the main control circuit, such as the extracted random number value, game state, internal winning combination, and the number of payouts. , Bonus carry-over status, information specifying a set value, various counters, flags, etc. are stored.

JP, 2009-5978, A JP, 2004-236763, A JP, 2001-58021, A JP, 2011-11035, A

  For example, it is rare that an unauthorized device is attached to the information path that connects the main control circuit that manages the entire gaming machine and the sub control circuit that manages the production surface, etc. There is an act of sending a command indicating the winning number of the winning combination and the number of payouts more advantageous than the actual number to the sub control circuit.

  In addition, there is a goto action in which only the command of the winning combination is continuously sent from the information path to the sub control circuit as if the communication was from the main control circuit.

  When the game is started and lottery is performed by the main control circuit and the winning combination is determined, a command is sent to the sub control circuit and the medal is paid out according to the winning combination by the sub control circuit. . In the conventional gaming machine, the sub-control circuit does not evaluate whether or not the internal winning combination process, the winning determination process, and the medal payout process commands are received from the main control circuit. Further, in the conventional gaming machine, when a communication error, a communication interruption (communication interruption), and a cancellation of the communication interruption occur between the main control circuit and the sub-control circuit, after that, the date and content of the occurrence and cancellation of the error, etc. Could not be confirmed.

  The present invention has been made in view of the above-described circumstances, and when a communication disconnection occurs between the main control circuit and the sub control circuit, it is possible to check the occurrence of an error, the date and time of occurrence, and the content. An object is to provide a game machine.

  Therefore, in the gaming machine according to the present invention, the main body, the front door that is openably and closably attached to the main body, and the front door is switched to a locked state or an unlocked state with the front door and the main body closed. Lock mechanism, a display device that displays an image, a first control unit that performs a first control, and a second control that is connected to the display device and the first control unit to perform a second control. An error information history storage for storing error information relating to the error detected by the error detection unit, the second control unit including a control unit and an error detection unit that detects that an error has occurred. Error information for sequentially storing error information related to the error in the error information history storage area based on storage means including an area and detection of the occurrence of the error by the error detection means Recording means, error information history display means for displaying the error information history stored in the error information history storage area on the display device, and an RTC capable of timing elapsed time and providing timed time information. Having the lock mechanism, it is possible to switch the locked state to the unlocked state by rotating the inserted door key in a predetermined direction, and the lock mechanism sets the door key in the predetermined direction. The second control unit is rotatable in the opposite direction, and the second control unit causes the display device to display the error information history when the state in which the door key is rotated in the direction opposite to the predetermined direction is maintained for a certain time or more. Is displayed, and the error information history displayed on the display device is based on the character string information indicating the error detected by the error detecting unit and the detection of the error. And serial RTC-provided time information is intended to be displayed side by side on the horizontal axis.

According to this configuration, when an error occurs, the error information detected by the error detecting means is stored in the error information history storage area. Then, by rotating the door key in a direction opposite to the direction in which the lock mechanism is unlocked, the error information history display means can display the time information by the RTC on the display device.
Thus, when an error occurs, it is possible to confirm the occurrence of the error, the date and time of occurrence, and the content after that.

  Further, in the gaming machine according to the present invention, the error information history displayed on the display device is time information displayed below the time information displayed above the vertical direction of the displayed time information. Is the older time information. With this configuration, it is possible for the watcher of the gaming machine to easily recognize and grasp the time history of the error information.

Further, the gaming machine according to the present invention, a plurality of reels on which a plurality of symbols are displayed, a symbol display means for displaying a part of the plurality of symbols displayed on the reels, and a game start operation by the player. Starting operation detecting means for detecting, based on the detection of the starting operation by the starting operation detecting means, the symbol changing means for changing the symbol by rotating the reel, and the detection of the starting operation by the starting operation detecting means. Based on the internal winning combination determining means for determining an internal winning combination with a predetermined probability, a stop operation detecting means provided corresponding to the plurality of reels, and detecting a stop operation for stopping each reel, Based on the internal winning combination determined by the internal winning combination determining means and the stop operation detected by the stop operation detecting means, stop control means for stopping the variable display of the symbols, A command transmitting means for transmitting a command according to the progress of the technique, a command receiving means for receiving the command transmitted by the command transmitting means, and a determination internal based on the command related to the start operation received by the command receiving means. The winning combination acquiring means for acquiring the winning combination, the stop position is acquired from the stop start position and the number of sliding frames of the symbol included in the command data regarding the stop operation received by the command receiving means, and the acquired stop is acquired. If the winning combination for obtaining the determination winning combination according to the position and the determination winning combination can be obtained, it is determined whether or not the internal winning combination for determination and the winning combination for determination match. The winning determination means and the determination processing means for performing a process based on the determination result of the winning determination means.
According to this, it becomes possible for the sub control circuit to judge whether or not the received command is valid.
Further, by comparing the winning combination with the internal winning combination, it is possible to determine whether or not the reel stop command is incorrect.
The gaming machine of the present invention, when the payout means for paying out the game medium based on the combination of the symbols stopped by the stop control means, and the command received by the command receiving means is a command relating to the payout of the game medium, Obtaining the determination payout number based on the combination of the symbols, further comprising a payout determination means for determining whether or not the payout number included in the command relating to the payout and the determination payout number, The determination processing means may perform the processing based on the determination result of the payout determination means.

  In this case, it is possible to determine whether or not the payout command is illegal by comparing the judgment payout number with the payout number included in the received payout command.

  The gaming machine of the present invention further comprises storage means for storing the arrangement of the plurality of symbols and the combination of the symbols, and the winning combination obtaining means is based on the command received by the command receiving means and the combination of the symbols. The internal winning combination for determination may be acquired, and the winning combination acquiring means may be configured to acquire the winning combination for determination based on the command received by the command receiving means and the arrangement of the symbols. .

  According to this, based on the arrangement of the symbols, it is possible to accurately determine whether or not the received command is valid.

  According to the present invention, it is possible to provide a gaming machine capable of confirming the occurrence of an error, the date and time of occurrence, and the content thereof when a communication disconnection occurs between the main control circuit and the sub control circuit.

It is an external view of the gaming machine in the present embodiment. It is a diagram showing a symbol display area and a winning line of the gaming machine in the present embodiment. It is a figure which shows the symbol arrangement table of the game machine in this Embodiment. It is a figure which shows the front upper part of the game machine in this Embodiment. (A) is a diagram showing a left decorative panel and a left infrared sensor of the gaming machine in the present embodiment. (B) is a diagram showing a left infrared sensor of the gaming machine in the present embodiment. It is a figure which shows the structure of the main control circuit of the game machine in this Embodiment. It is a figure which shows the structure of the sub-control circuit of the game machine in this Embodiment. It is a figure which shows the area | region image in the sub ROM of the sub control circuit in this Embodiment. It is a figure which shows the area | region image in the sub RAM of the sub control circuit in this Embodiment. It is a figure which shows the area image in the backup RAM of the sub-control circuit in this Embodiment. It is a figure which shows an example of the structure of the error information history storage area in the sub RAM of the sub control circuit in this Embodiment. FIG. 7 is a diagram showing an example of the content of data stored in an error information history storage area in the sub RAM of the sub control circuit in the present embodiment. FIG. 6 is an explanatory diagram showing a communication log collecting ring buffer area in the sub RAM of the sub control circuit in the present embodiment. FIG. 7 is an explanatory diagram showing a communication error storage area in the sub RAM of the sub control circuit in the present embodiment. It is a figure which shows the example of a transition of the game state of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table determination table of the gaming machine in this Embodiment. It is a figure which shows the example of the internal lottery table of the game machine in this Embodiment. It is a diagram showing an example of an internal lottery table for the RB1 game state of the gaming machine in the present embodiment. It is a figure which shows the example of the internal lottery table for RB2 game states of the gaming machine in this Embodiment. It is a figure which shows the example of the RT transition table of the game machine in this Embodiment. It is a diagram showing an example of a bonus internal winning combination determination table of the gaming machine in the present embodiment. It is a diagram showing an example of a small winning combination / replay internal winning combination determination table of the gaming machine in the present embodiment. It is a figure which shows the example of the symbol combination table of the game machine in this Embodiment. It is a figure showing an example of a bonus operation time table of a game machine in this embodiment. It is a figure which shows the example of the attraction-in priority table A of the game machine in this Embodiment. It is a figure which shows the example of the attraction-in priority table B of the game machine in this Embodiment. It is a figure which shows the example of the stop table of the game machine in this Embodiment. It is a figure which shows the example of the internal winning combination storage area of the game machine in this Embodiment. It is a figure which shows the example of the display combination storage area of the game machine in this Embodiment. It is a figure showing an example of a carryover combination storing area of a game machine of this embodiment. It is a figure which shows the example of the game state flag storage area of the game machine of this Embodiment. It is a figure which shows the example of storage of the symbol storage area A of the game machine in this Embodiment. It is a diagram showing a storage example of the symbol storage area B of the gaming machine in the present embodiment. It is a figure which shows the flowchart of the reset interruption processing by the main CPU performed by the main control circuit in this Embodiment. FIG. 9 is a diagram showing a flowchart of bonus operation monitoring processing performed by the main control circuit in the present embodiment. It is a figure which shows the flowchart of the internal lottery process performed in the main control circuit in this Embodiment. It is a figure which shows the flowchart of the internal lottery process performed in the main control circuit in this Embodiment. FIG. 6 is a diagram showing a flow chart of reel stop control processing performed by a main control circuit in the present embodiment. FIG. 7 is a diagram showing a flowchart of a display combination search process performed by the main control circuit in the present embodiment. It is a figure which shows the flowchart of RT control processing performed in the main control circuit in this Embodiment. It is a figure showing a flow chart of bonus end check processing performed with a main control circuit in this embodiment. It is a figure showing a flow chart of bonus operation check processing performed with a main control circuit in this embodiment. FIG. 7 is a diagram showing a flowchart of communication data storage processing performed by the main CPU of the main control circuit in the embodiment of the present invention. It is a figure which shows the flowchart of the interruption process (1.1173 ms) by the main CPU performed by the main control circuit in this Embodiment. It is a figure which shows the flowchart of the communication data transmission process performed by the main CPU of the main control circuit in embodiment of this invention. FIG. 6 is a diagram showing a flowchart of a non-operation command set process in the communication data transmission process performed by the main CPU of the main control circuit in the embodiment of the present invention. It is a schematic diagram showing the whole management system of a game machine in this embodiment. It is the schematic which shows the menu screen of the game machine in this Embodiment. It is the schematic which shows the error information history screen of the game machine in the form of this execution. It is an explanatory view showing the contents of information of a two-dimensional code used in the gaming machine management system in the present embodiment. It is explanatory drawing which shows the code number, classification, and parameter of the received command used for the game machine in this Embodiment. It is explanatory drawing which shows the recording image of the information of the secondary element code when a COM error generate | occur | produces in the game machine in this Embodiment, (a) is an accidental occurrence during a normal game, (b) ) Shows the case where the setting is changed due to the goto action, and (c) shows the case where the lever continuous transmission is performed. FIG. 16 is a diagram showing an example of notifying a liquid crystal display area of a RAM destruction in the game machine according to the present embodiment when the RAM is destroyed. FIG. 16 is a diagram showing an example of notifying a liquid crystal display area of an abnormality in communication from the main control circuit to the sub control circuit in the game machine according to the present embodiment. FIG. 7 is a diagram showing a flowchart for explaining processing when the sub CPU of the sub control circuit in the present embodiment is turned on. It is a figure which shows the flowchart of the power interruption interruption processing of the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the mother task which performs various task starting requests performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the error monitoring task performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board communication reception interruption process by the sub CPU performed by the sub control circuit in this Embodiment. It is a diagram showing a flow chart of effect registration processing performed in the sub-control circuit in the present embodiment. It is a diagram showing a flow chart of effect content determination processing performed in the sub-control circuit in the present embodiment. It is a diagram showing a flow chart of effect content determination processing performed in the sub-control circuit in the present embodiment. It is a figure which shows the flowchart of the fraud determination processing at the time of the reel stop command reception performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the fraud determination processing at the time of receiving the display command performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the fraud determination processing at the time of the payout command reception performed by the sub-control circuit in this Embodiment. FIG. 7 is a diagram showing a flowchart of fraudulent occurrence time processing performed by the sub control circuit according to the present embodiment. It is a figure which shows the example of the symbol arrangement table for a sub CPU fraud determination performed by the sub control circuit in this Embodiment. It is a figure which shows the example of the symbol combination table for a sub CPU fraud determination performed by the sub control circuit in this Embodiment. It is a figure which shows the detailed flowchart of the sub CPU main board communication task performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board communication reception data log saving process performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the main board communication reception data log temporary area storage process performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the main board communication error history data storage process performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the main board reception command check process performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the COM error check process performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of RTC control task performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the backup creation process performed by the sub CPU of the sub control circuit in this Embodiment. It is a perspective view showing appearance of a game machine in other embodiments of the present invention. It is a front view which shows the schematic structure of the game board of the game machine in other embodiment of this invention. It is a block diagram showing a configuration of a main control circuit and a sub-control circuit of the gaming machine in another embodiment of the present invention.

[Pachislot machine configuration]
The gaming machine of the present invention will be specifically described below with reference to the drawings. In the following embodiments, the gaming machine of the present invention is a gaming machine provided with three rotating reels for variable display of symbols, and is given to a player in addition to coins, medals, tokens, or the like. An explanation will be given by using a so-called pachi-slot gaming machine, which is a gaming machine that can be played using a gaming value such as a card.

  Further, in the following embodiments, a pachi-slot gaming machine will be described as an example, but the gaming machine of the present invention is not limited, and may be a pachinko machine or slot machine. An example of a pachinko gaming machine will be described later separately.

  First, with reference to FIG. 1, an overview of the pachi-slot gaming machine according to the present embodiment will be described. Note that FIG. 1 is a perspective view of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 1, the gaming machine 1 includes a housing 1a that houses reels 3L, 3C, 3R, a main control circuit 60 (see FIG. 6) described later, and the like. The housing 1a includes a front door 1b that can be opened and closed. Further, the gaming machine 1 includes a lock mechanism that switches the front door 1b to the locked state or the unlocked state with the front door 1b closed. The lock mechanism is operated by inserting the door key 2 into the door key hole 1c and rotating the door key 2.

  Symbol display areas 4L, 4C, 4R as substantially vertical surfaces and a liquid crystal display area 23 are formed on the front surface of the central portion of the front door 1b. Inside the front of the central portion of the cabinet 1a, three reels 3L, 3C, and 3R are rotatably provided in a horizontal row. On each of the three reels 3L, 3C, and 3R, a symbol row composed of a plurality of types of symbols is drawn on the outer peripheral surface of each reel.

  The symbols on the reels 3L, 3C, 3R can be seen through the symbol display areas 4L, 4C, 4R. Further, each reel 3L, 3C, 3R is controlled by a main control circuit 60 (see FIG. 6) described later so as to rotate at a constant speed (for example, 80 rotations / minute), and in the symbol display areas 4L, 4C, 4R. The symbols drawn on the displayed reels 3L, 3C, and 3R fluctuate as the reels rotate.

  Below the liquid crystal display area 23, a substantially horizontal pedestal portion 10 is formed. On the left side of the pedestal portion 10, for betting credited medals by a push button operation, and a C / P button 14 for switching between credit (Credit) and payout (Pay) of medals that a player has won in a game. The maximum BET button 13 is provided.

  The payout mode or the credit mode is switched by the player's operation on the C / P button 14. In the credit mode, when a winning is achieved, the payout number of medals corresponding to the winning is credited.

  Further, in the payout mode, when the winning is achieved, the number of medals corresponding to the winning is paid out from the medal payout opening 15 in the lower front part, and the medals paid out from the medal payout exit 15 are sent to the medal receiving portion 16. It is stored.

  In addition, the winning means that the combination of the symbols relating to the small winning combination stops on the activated line. The small winning combination is a winning combination in which medals are paid out.

  Further, by the player's operation on the maximum BET button 13, among the credited medals, the maximum number of medals that can be inserted at that time is inserted. By operating the maximum BET button 13, a pay line to be described later is activated.

  A medal slot 22 is provided on the right side of the base 10. The pay line, which will be described later, is activated according to the medals inserted into the medal insertion slot 22.

  A selection button 24 and a decision button 25 are provided on the left of the medal insertion slot 22. The player can input the menu screen and the like displayed in the liquid crystal display area 23 by using the select button 24 and the enter button 25.

  Speakers 21L and 21R are provided on the left and right above the medal receiving portion 16. The speakers 21L and 21R output game sounds such as effect sounds and notification sounds according to the game situation.

  A start lever 6 is provided to the left of the front surface of the pedestal portion 10. The start lever 6 rotates the reels 3L, 3C, 3R in response to a player's start operation, and starts changing the symbols displayed in the symbol display areas 4L, 4C, 4R.

  At the center of the front surface of the pedestal portion 10, on the right side of the start lever 6, three stop buttons 7L for stopping the rotation of the three reels 3L, 3C, 3R by the player's pressing operation (stop operation). , 7C, 7R are provided.

  Here, the stop of the rotation of the reel first performed when the rotation of the three reels 3L, 3C, 3R is performed is referred to as the first stop, and the rotation of the two reels is performed after the first stop. The second stop of the rotation of the reel that is performed when the reel is being performed is performed after the second stop, and is performed last when the remaining one reel is being rotated. The stop of the rotation of the reel is called the third stop.

  A stop operation for the player to make a first stop is referred to as a first stop operation. Similarly, a stop operation for the player to make a second stop is called a second stop operation, and a stop operation for making a third stop is called a third stop operation.

  A light-transmissive upper panel 101 is provided above the front door 1b, and an upper panel LED (Light Emitting Diode) (not shown) is provided inside the upper panel 101. Note that another light-emitting body may be used instead of the LED. The upper panel 101 emits light according to the contents of the effect described later.

  The liquid crystal display area 23 is arranged on the front side of the reels 3L, 3C, 3R when viewed from the front side, displays an image, and is drawn on the reels 3L, 3C, 3R in the symbol display areas 4L, 4C, 4R. The displayed pattern is transparently displayed. The transmittance in the symbol display areas 4L, 4C, 4R can be changed.

  The liquid crystal display area 23 displays the number of stored (credited) medals or the number of paid-out medals when a winning is achieved. In addition, the liquid crystal display area 23 displays a frame image having a predetermined shape so as to surround the symbol display areas 4L, 4C, and 4R, and a predetermined image according to effect contents described later.

  A lower panel 102 is provided below the liquid crystal display area 23 and above the pedestal portion 10, and an LED for the lower panel 102 (although another light emitting body may be used instead of the LED is provided inside the lower panel 102. Good) is provided. The lower panel 102 emits light according to the contents of the effect described later.

  A light-transmitting waist panel 103 is provided below the pedestal portion 10, and an LED for the waist panel 103 (another light-emitting body may be used instead of the LED) is provided inside the waist panel 103. There is. The waist panel 103 emits light according to the effect contents described later.

  One symbol is displayed in each of the upper, middle, and lower regions in each of the vertically long rectangular symbol display regions 4L, 4C, and 4R, and each symbol display region 4L, 4C, and 4R is on the peripheral surface of the corresponding reel. Three of the arranged symbols are displayed. That is, the symbol display areas 4L, 4C, 4R have a function as a so-called display window.

  Next, the winning line will be described with reference to FIG. In the symbol display areas 4L, 4C, and 4R, five winning lines (center line 8c, bottom line 8d, cross) connecting any of the upper, middle, and lower rows in the above-described symbol display areas 4L, 4C, and 4R. An up line 8a, a cross down line 8e, and an RB middle special line 8f) are provided.

  The gaming machine 1, when the rotation of the reels 3L, 3C, 3R is stopped, determines the establishment / non-establishment of the winning combination based on the combination of the symbols displayed on the activated pay line. Hereinafter, the activated winning line will be referred to as an activated line, and the activated winning line will not be referred to as an ineffective line.

  As shown in FIG. 2, the center line 8c is a line connecting the left / middle tier region D, the middle / middle tier region E, and the right / middle tier region F, respectively. The bottom line 8d is a line formed by connecting the left / lower stage region G, the middle / lower stage region H, and the right / lower stage region I, respectively.

  The cross-up line 8a is a line formed by connecting the left / lower tier region G, the middle / middle tier region E, and the right / upper tier region C, respectively. The cross-down line 8e is a line connecting the left / upper region A, the middle / middle region E, and the right / lower region I, respectively. The RB middle special line 8f is a line formed by connecting the left / middle area D, the middle / lower area H, and the right / upper area C, respectively.

  In the present embodiment, in the BB game state (RB game state), only the RB special line 8f becomes an effective line by inserting two medals. On the other hand, in the gaming states other than the BB gaming state (RB gaming state), four winning lines of the center line 8c, the bottom line 8d, the cross-up line 8a, and the cross-down line 8e become effective lines by inserting three medals. Become.

  The BB1 gaming state to the BB4 gaming state may be collectively referred to as the BB gaming state. Also, the RB1 gaming state to the RB2 gaming state may be collectively referred to as the RB gaming state.

  Next, the symbol array arranged on the reels 3L, 3C, 3R will be described with reference to the symbol arrangement table shown in FIG. FIG. 3 is a diagram showing an arrangement of symbols drawn on the outer peripheral surfaces of the reels 3L, 3C, 3R of the gaming machine 1 according to the present embodiment.

  On the outer peripheral surface of the reels 3L, 3C, 3R, a symbol row in which 21 symbols of a plurality of types are arranged is drawn. Specifically, a design row composed of red 7 design, don 1 design, don 2 design, BAR design, wave design, bell 1 design, bell 2 design, cherry 1 design, cherry 2 design, replay design is drawn. ing.

  The symbol arrangement table is stored in the main ROM 32 of the main control circuit 60 described later. As shown in FIG. 3, in the symbol arrangement table, in order to associate the rotational positions of the reels 3L, 3C, 3R with the symbols drawn on the reel outer peripheral surface, every 1/21 revolutions of the reels 3L, 3C, 3R. The symbol positions from "0" to "20" that are sequentially assigned to are defined.

  Next, with reference to FIG. 4, the upper portion of the gaming machine will be described. Note that FIG. 4 is a diagram showing an upper front part of the gaming machine 1.

  As shown in FIG. 4, a display panel unit 110 is provided at the center of the upper part of the liquid crystal display area 23, and a left selection panel 151L and a right selection panel 151R are provided on the left and right of the display panel unit 110.

  A left decoration panel 121L and a right decoration panel 121R are provided on the upper left and right sides of the display panel unit 110.

  The display panel unit 110 has a plurality of display panels having high light transmittance and excellent light guiding properties, and a plurality of LEDs.

  As shown in FIG. 5A, a left infrared sensor 120L is provided inside the left decorative panel 121L. Although not shown, a right infrared sensor 120R is also provided inside the right decoration panel 121R.

  The infrared sensors 120L and 120R are so-called reflective infrared sensors and can detect whether an object (for example, a player's hand) is present or approaching in the direction in which the infrared beam is output.

  As shown in FIG. 5B, the left infrared sensor 120L outputs an infrared beam in the direction of the arrow AR and receives the reflected infrared beam, whereby the player's hand or the like approaches the left selection panel 151L. Detect that. Similarly, the right infrared sensor 120R detects whether the player's hand or the like is approaching the vicinity of the right selection panel 151R.

  It should be noted that the infrared sensors 120L and 120R do not always operate, but operate when a specific effect is executed.

  Further, although the reflection type infrared sensor is adopted in the present embodiment, it is also possible to adopt another sensor capable of detecting that the player's hand or the like approaches near the left selection panel 151L and the right selection panel 151R. May be The left selection panel 151L and the right selection panel 151R themselves may be so-called touch sensors.

[Circuit configuration of game machines]
Next, with reference to FIG. 6, a circuit configuration of the gaming machine 1 including a main control circuit 60, a sub control circuit 70, a peripheral device electrically connected to the main control circuit 60 or the sub control circuit 70, and the like will be described. Note that FIG. 6 is a diagram showing a circuit configuration of the gaming machine 1.

  The main control circuit 60 controls the progress of a series of games such as determination of internal winning combination and reel rotation control. The main control circuit 60 has a microcomputer 30 arranged on a circuit board as a main component, and a circuit for random number sampling is added thereto. The microcomputer 30 is composed of a main CPU 31, a main ROM 32 and a main RAM 33.

  The main CPU 31 has a command transmitting means. The command transmitting means is adapted to transmit a command to the sub control circuit 70.

  A clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37 are connected to the main CPU 31.

  The main CPU 31 determines an internal winning combination based on the random number value and the internal lottery table, and stops the rotation of the reels 3L, 3C, 3R based on the internal winning combination and the timing at which the stop operation is detected.

  The main CPU 31 determines whether or not a winning combination has been established, based on the combination of the symbols displayed in the symbol display areas 4L, 4C, 4R when the rotation of the reels 3L, 3C, 3R is stopped. If the winning combination has been established, the player is provided with a profit such as paying out a medal in accordance with the winning combination.

  The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The random number generator 36 generates a random number in the range of “0” to “65535”. The sampling circuit 37 extracts (samples) one random number value from the random numbers generated by the random number generator 36.

  In the gaming machine 1, the extracted random number value is stored in the random number value storage area of the main RAM 33 described later. Then, the internal winning combination is determined in the internal lottery process based on the random number value stored in the random number storage area of the main RAM 33 for each game.

  The random number sampling means may be configured to execute the random number sampling within the microcomputer 30, that is, on the operation program of the main CPU 31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The main ROM 32 of the microcomputer 30 stores programs related to the processing of the main CPU 31, various tables, and the like.

  Various information obtained by the processing of the main CPU 31 is set in the main RAM 33. For example, information specifying the extracted random number value, game state, internal winning combination, payout number, bonus carryover status, set value, etc., various counters and flags are set. Part of this information is transmitted to the sub control circuit 70 by the above-mentioned command.

  Examples of main peripheral devices whose operations are controlled by control signals from the microcomputer 30 include a hopper 40 and stepping motors 49L, 49C, 49R. Signals are exchanged between these actuators and the main CPU 31 via the I / O port 38.

  Further, each circuit for receiving a control signal output from the main CPU 31 and controlling the operation of each of the above-described peripheral devices is connected to the output unit of the microcomputer 30. As each circuit, there are a motor drive circuit 39 and a hopper drive circuit 41.

  The hopper drive circuit 41 drives and controls the hopper 40. As a result, the medals stored in the hopper 40 are paid out.

  The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R. As a result, the reels 3L, 3C, 3R are rotated and stopped.

  Further, the input unit of the microcomputer 30 is connected to each switch and each circuit for generating an input signal that triggers the output of the control signal to each of the above-mentioned circuits and each peripheral device. As each switch and each circuit, a start switch 6S, stop switches 7LS, 7CS, 7RS, maximum BET switch 13S, C / P switch 14S, setting key switch 20S, medal sensor 22S, reset switch 23S, reel position detection circuit 50, There is a payout completion signal circuit 51. The stop switches 7LS, 7CS, 7RS are collectively referred to as the stop switch 7S. Signals are input between these circuits and the main CPU 31 via the I / O port 38.

  The start switch 6S detects a player's start operation on the start lever 6 and outputs a start signal for instructing the start of a game to the microcomputer 30.

  The stop switches 7LS, 7CS, 7RS detect the stop operation of the player on the stop buttons 7L, 7C, 7R, respectively, and stop the rotation of the reels 3L, 3C, 3R corresponding to the detected stop buttons 7L, 7C, 7R. A stop signal to instruct is output to the microcomputer 30.

  The maximum BET switch 13S detects a player's insertion operation (pressing operation) on the maximum BET button 13 and outputs a signal for instructing insertion of medals from credited medals to the microcomputer 30.

  The C / P switch 14S detects a player's switching operation on the C / P button 14 and outputs a signal for switching between the credit mode and the payout mode to the microcomputer 30. When the credit mode is switched to the payout mode, a signal for instructing the payout of medals credited to the gaming machine 1 is output to the microcomputer 30.

  The setting key switch 20S detects that the setting key for operating the set value of the gaming machine 1 has been operated, and outputs the detection signal to the microcomputer 30.

  The medal sensor 22S detects a medal inserted into the medal insertion slot 22 by a player's insertion operation, and outputs a signal indicating that the medal has been inserted to the microcomputer 30.

  The reset switch 23S functions as a state release command input means for inputting a state release command, and outputs a signal for releasing a selector error of a selector (not shown) installed inside the gaming machine or a hopper error of the hopper 40. To do. The selector error is an error regarding the inserted medal passage time, the inserted medal passage check, and the inserted medal reverse, and the hopper error is an error regarding a hopper jam, a hopper empty, and an auxiliary storage full.

  The reel position detection circuit 50 detects the pulse signal from the reel rotation sensor and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 51 indicates that the payout of medals is completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the designated number. Generate a signal to indicate.

  The sub control circuit 70 performs various processes such as determination and execution of effect data based on various commands output from the main control circuit 60 such as a start command described later. The sub control circuit 70 does not input commands, information, etc. to the main control circuit 60, and one-way communication is performed from the main control circuit 60 to the sub control circuit 70.

  Main peripheral devices whose operations are controlled by control signals from the sub-control circuit 70 include a liquid crystal display device 5 as a display unit for displaying an image in the liquid crystal display area 23, speakers 21L and 21R, and various operation panels 101 to. 103, a display panel unit 110, and infrared sensors 120L and 120R.

  The sub control circuit 70 determines an image displayed on the liquid crystal display device 5 based on the determined effect data, displays the image, determines and outputs a light emission pattern of the various operation panels 101 to 103 and the display panel unit 110, an infrared sensor. The determination of the operation timing of 120L and 120R, the determination of the effect sound and the effect sound output from the speakers 21L and 21R, and the output control are performed.

  The details of the configuration of the sub control circuit 70 according to the present embodiment will be described later.

  In the gaming machine 1, when a player operates the start lever 6 to output a signal for starting a game from the start switch 6S, a control signal is output to the motor drive circuit 39, and the stepping motor is operated. Rotation of the reels 3L, 3C, 3R is started by drive control of 49L, 49C, 49R (for example, excitation of each phase).

  At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set in a predetermined area of the main RAM 33 as a pulse counter.

  In the gaming machine 1, when the "16" pulse is output, the reels 3L, 3C, 3R move by one symbol. The number of symbols moved is counted, and the count value is set in a predetermined area of the main RAM 33 as a symbol counter. That is, each time the pulse counter counts "16" pulses, the symbol counter is updated by "1".

  The symbol at the symbol position indicated by the symbol counter value (see FIG. 3) corresponds to the symbol located on the center line 8c. For example, when the symbol counter of the left reel 3L is "0", the red 7 at the symbol position "0" of the symbol arrangement table shown in FIG. 3 is located on the center line 8c.

  Further, a reel index is obtained from the reels 3L, 3C, and 3R for each rotation, and is output to the main CPU 31 via the reel position detection circuit 50. By the output of the reel index, the pulse counter and the symbol counter set in the main RAM 33 are cleared to "0".

  In this way, the symbol position within the range of one rotation is specified for each reel 3L, 3C, 3R. The distance by which each symbol moves by one symbol due to the rotation of the reel is called one frame. That is, moving the symbol by one frame corresponds to updating the symbol counter by "1".

  A symbol arrangement table (FIG. 3) is stored in the main ROM 32 in order to associate the rotational positions of the reels 3L, 3C, and 3R with the symbols drawn on the reel outer peripheral surface. This symbol arrangement table has a code number from "0" to "20", which is sequentially given at a constant rotation pitch of each reel 3L, 3C, 3R with reference to the position where the aforementioned reel index is output. , And a symbol code for identifying the type of symbol provided corresponding to each code number.

  When the start signal is output from the start switch 6S, the random number generator 36 and the sampling circuit 37 extract the random number value. In the gaming machine 1, when the random number value is extracted, it is stored in the random number value storage area of the main RAM 33. Then, the internal winning combination is determined based on the random number value stored in the random number storage area.

  When the stop signals are output from the stop switches 7LS, 7CS, 7RS by the stop operation after the reels 3L, 3C, 3R reach the constant speed rotation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R to stop the rotation of the reels 3L, 3C, 3R.

  The gaming machine 1 pulls in the symbols relating to the establishment of the internal winning combination by the maximum number of sliding symbols, that is, by pulling four symbols from the time when the stop operation is performed, and stops the rotation of the reel 3. Specifically, after the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the gaming machine 1 determines whether or not there is a symbol relating to the establishment of the internal winning combination within 4 frames, When there is a symbol relating to the establishment of the internal winning combination within 4 frames, the number of sliding symbols is determined so that the symbol is stopped and displayed on the activated line, and the corresponding reel is stopped.

  Further, when a plurality of winning combinations are determined as the internal winning combination, the gaming machine 1 is related to the internal winning combination having a higher priority when there are a plurality of symbols relating to the establishment of the internal winning combination within 4 frames. The number of sliding symbols is determined so that the symbol is stopped and displayed on the activated line.

  Basically, the first priority (the highest priority) is a combination of symbols relating to replay, and the second priority is a combination of symbols relating to a small winning combination. Next, the third priority is a combination of symbols related to the bonus.

  Further, when the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the symbol position corresponding to the symbol counter of the corresponding reel 3, that is, the symbol position at which the rotation of the reel 3 starts to be stopped is referred to as "stop start position". The symbol position in which the determined number of sliding symbols (numerical value range “0” to “4”) is added to the stop start position, that is, the symbol position at which the rotation of the reel 3 is stopped is referred to as the “scheduled stop position”. The number of sliding pieces is the amount of rotation of the reel 3 from when the stop operation is detected by the stop switches 7LS, 7CS, 7RS until the rotation of the corresponding reel 3 is stopped, and in the gaming machine 1, the maximum number of sliding pieces is " 4 ”.

  When the rotation of all the reels 3L, 3C, 3R is stopped, the search process of the display combination, that is, the process of determining the establishment / non-establishment of the combination is performed based on the combination of the symbols displayed on the activated line. The display combination is searched based on a later-described symbol combination table stored in the main ROM 32. In this symbol combination table, combinations of symbols relating to display combinations and corresponding payouts are set.

  When it is determined by the search of the display combination that the winning combination of symbols has been displayed, a control signal is output to the hopper drive circuit 41, and the hopper 40 is driven to pay out medals.

  At this time, the medal detection unit 40S counts the number of medals paid out from the hopper 40, and when the counted value reaches the designated number, the payout completion signal circuit 51 outputs a signal indicating the completion of the medal payout. . As a result, a control signal is output to the hopper drive circuit 41 and the drive of the hopper 40 is stopped.

  When the credit mode is switched by the C / P switch 14S, if it is determined that the winning symbol combination is displayed, the payout amount according to the winning symbol combination is displayed in the main RAM 33. Add to credit counter.

  Further, the number of paid-out medals is transmitted to the sub-control circuit 70, and based on this, the number of paid-out medals and the updated number of credits are displayed in the liquid crystal display area 23. Here, the payout of medals or the credits performed when a combination of symbols relating to winning is displayed may be simply referred to as “payout”.

  Next, the circuit configuration of the sub control circuit 70 will be described with reference to FIG. Note that FIG. 7 is a diagram showing a circuit configuration of the sub control circuit 70 of the gaming machine 1.

  The sub-control circuit 70 performs control for effecting a game using video, sound, light, and the like. The sub control circuit 70 determines effect data and performs various effect processes based on various commands transmitted from the main control circuit 60 and input information from the selection switch 24S and the decision switch 25S.

  The selection switch 24S detects the operation of the player with respect to the selection button 24, and moves, for example, a display (for example, an icon) indicating which item among the items to be selected displayed on the menu screen or the like is in the selected state. To output to the sub CPU 71.

  Further, the decision switch 25S detects the player's operation of the decision button 25, and outputs, for example, a signal indicating that the player has selected an item in the selected state to the sub CPU 71. In other words, the player can select an item by pressing the select button 24 until the desired item is selected on the menu screen or the like and then pressing the enter button 25.

  The sub control circuit 70 includes a sub CPU 71 as a processing unit, a sub ROM 72 that functions as a processing information storage unit, a DRAM 73-1 (also referred to as “sub RAM 73-1”) that functions as a control information storage unit, an SRAM 73-2, and a GPU 74. It has a VRAM 75 and a digital amplifier 78.

  The sub CPU 71 performs display control of the liquid crystal display device 5, output control of the speakers 21L and 21R, various operation panels 101 to 103, light emission control of the display panel unit 110, and the like based on a program stored in the sub ROM 72. Specifically, the sub CPU 71 receives various commands and the like from the main control circuit 60 and stores various information included in the commands in the sub RAM 73-1.

  As will be described in detail later, the sub CPU 71 has a communication error detection means 71a, a procedure detection means 71b, a data destruction detection means 71c, an error information registration means 71d, a received data log storage means 71e, and an error information history display means. 71f, two-dimensional code conversion means 71g, and communication disconnection detection means 71h.

  Further, a SRAM 73-2 (also referred to as “backup RAM 73-2”) described later is connected to the sub CPU 71. The backup RAM 73-2 backs up the data copied to the sub RAM 73-1 when the power is turned on.

  A door opening / closing switch 29S is connected to the sub CPU 71. The door opening / closing switch 29S is a sensor for monitoring opening / closing of the front door 1b of the gaming machine 1, detects a state in which the front door 1b is opened, and causes the sub CPU 71 to display, for example, "the door is opened. It outputs a signal that gives the warning "Open." The door open / close switch 29S functions as a door open state detecting means.

  All the information in the main control circuit 60 is transmitted by the command, and the sub control circuit 70 can judge the state of the main control circuit 60 one by one. The sub CPU 71 executes the program while referring to the game state information, the internal winning combination information, and the like stored in the DRAM 73-1 to display the liquid crystal display device 5, the speakers 21L and 21R, and various operation panels 101 to 103, and display. The content of the effect to be performed by the effect device such as the panel unit 110 is determined.

  In addition, the sub CPU 71 controls the liquid crystal display device 5 via the GPU 74 based on the determined effect data, and outputs sounds from the speakers 21L and 21R, and various operation panels 101 to 103 and the display panel unit 110. Control the light emission.

  The upper panel 101, the waist panel 102, and the lower panel 103 are each actually provided with a plurality of LEDs, which are controlled by input / output processing of individually provided ports (not shown). Therefore, the light emission can be individually controlled by each port.

  The sub CPU 71 also executes a random number acquisition program stored in the sub ROM 72 to acquire a random number value used when determining effect data and the like. However, when the random number generator and the sampling circuit are provided in the sub control circuit 70 as in the main control circuit 60, the processing is not necessary.

  As shown in FIG. 8, the sub ROM 72 has an OS area 72a for storing an operating system, a sub control program storage area 72b for storing a program executed by the sub CPU 71, a game data initialization setting data area 72c, and a staff operation. An initial setting data area 72d, various program table areas 72e for storing various tables, a program management data area 72f, an image data (still image / moving image) area 72g, a sound data area 72h, and an accessory moving data area. 72i and.

  The sub-control program storage area 72b is based on the device driver, the inter-board communication process for controlling the communication with the main control circuit 60, the effect registration process for determining the effect contents, and various LED data based on the registered LED data. An LED control task for controlling light output by the operation panels 101 to 103 and the display panel unit 110, a voice control task for controlling sound output by the speakers 21L and 21R based on registered sound data, registered. A drawing control task or the like for controlling display of an image by the liquid crystal display device 5 based on the animation data is stored.

  The various program table area 72e stores an effect lottery table, an error code table of the sub control circuit shown in FIG. 12, and the like. In addition to that, the various program table areas 72e have a symbol arrangement table for sub CPU fraud determination shown in FIG. 67 and a sub table shown in FIG. 68 for sub CPU fraud determination to be described later regarding whether or not the winning combination is correct. A symbol combination table for CPU fraud determination is stored. The symbol arrangement table for sub CPU fraud determination and the symbol combination table for sub CPU fraud determination are stored in the main ROM 32 of the main control circuit 60, respectively, and shown in FIG. 3 and FIG. It is a table created based on the symbol combination table.

  The program management data area 72f stores a magic code, a program version and the like. The image data (still image / moving image) area 72g stores animation data such as character object data. The sound data area 72h stores sound data such as BGM and sound effects. Further, the accessory moving data area 72i stores, for example, LED control data for performing a lighting pattern of light or the like.

  As shown in FIG. 9, the sub RAM 73-1 includes a game data area 73a-1 as a game data storage area, a game data sum value area 73b-1, a work area 73c-1, and a staff operation setting data area 73g. -1, a staff operation setting data sum value area 73h-1, an error information history storage area 73d-1, a communication log collecting ring buffer area 73e-1, and a communication error saving buffer area 73f-1. There is. The staff operation setting data registered in the staff operation setting data area 73g-1 is data in which the setting items on the menu screen are stored.

  The game data area 73a-1 is adapted to store the data stored in the sub RAM 73-1 among the information including the game data regarding the progress of the game. The game data sum value area 73b-1 is adapted to store a checksum sum value of the game data stored in the game data area 73a-1. The work area 73c-1 stores data in various processes.

  The game data area 73a-1 and the work area 73c-1 are used as temporary work storage means when the sub CPU 71 executes each program. Further, the game data area 73a-1 is, for example, a command transmitted from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters, and any of 4 bytes to 8 bytes. Information such as a magic code and various flags is stored.

  The error information history storage area 73d-1 is adapted to store error codes (see FIG. 12) indicating all error information detected by the communication error detecting means 71a, the procedure detecting means 71b, the data destruction detecting means 71c and the like. ing. In the error information history storage area 73d-1, the error information history is created by sequentially storing the error codes.

  In the error information history storage area 73d-1, the error detected by the communication error detecting means 71a is stored as a COM error, and the error detected by the procedure detecting means 71b is stored as a procedure abnormal error. Further, the error detected by the data destruction detecting means 71c is stored as a data destruction error.

  Further, in the error information history storage area 73d-1, when the communication disconnection detecting means 71h of the sub CPU 71 detects the disconnection of the communication from the main control circuit 60 to the sub control circuit 70, "communication disconnection notification". If an error code (COM DCN ALM) is stored together with the date and time of occurrence, and the "communication interruption notification" is released, the release time is stored in the error code (COM DCN ALM) stored when the error occurred. .

  As shown in FIG. 10, the backup RAM 73-2 includes a backup data 1 area 73a-2, a backup data 1 sum value area 73b-2, and a backup data 2 area 73c- which is a mirroring of the backup data 1 area 73a-2. 2, a backup data 2 sum value area 73d-2, a staff backup data area 73e-2, an error information history storage area 73f-2, and a staff backup data sum value area 73g-2.

  In this embodiment, the backup data 1 area 73a-2 and the backup data 2 area 73c-2 are configured as a single backup RAM 73-2. In this specification, “mirroring” is used to mean copying data, and is not limited to the meaning of copying data to another storage.

  The backup data 1 area 73a-2 and the backup data 2 area 73c-2 each have an arbitrary magic code of 4 bytes to 8 bytes.

  As shown in FIG. 11, the error information history storage area 73d-1 of the sub RAM 73-1 includes an error code (ERROR CODE in the figure), an error occurrence time ("occurrence" in the figure), and an error release time ( In the figure, 128 sets can be stored, with “release”) as one set.

  The error code is 1-byte data. The communication between the main control circuit 60 and the sub control circuit 70 and the content of the error code relating to the sub control circuit 70 are as shown in FIG. Power failure error before operation (error code "WDR PRE" in the figure), power failure error after the first lever operation after turning on the power (error code "WDR POST" in the figure), communication error (in the figure) , “COM error”), procedure error (“procedure error” in the figure), data destruction error (“sum error” in the figure), communication disconnection error between the main control circuit 60 and the sub control circuit 70 ("Communication interruption notification" in the figure) and other errors are included.

  In the error information history storage area 73d-1, the error occurrence time and the error release time are both the 2-byte data year, 1-byte data month, 1-byte data day, 1-byte data hour, 1-byte data minute It is made up of 1-byte data seconds.

  As shown in FIG. 13, the communication log collection ring buffer area 73e-1 stores an appropriate number of data groups each consisting of a data set of 256 commands and parameters and one corresponding buffer index, which are stored in the ring. It works as a buffer.

  As shown in FIG. 14, the communication error storage buffer area 73f-1 stores 1024 data groups each including a data set of 256 commands and parameters and one corresponding buffer index. Further, the communication error storage buffer area 73f-1 is provided with one buffer selection index indicating which of the 1024 buffer indexes is selected.

  Further, in the communication log collection ring buffer area 73e-1 shown in FIG. 13 and the communication error storage buffer area 73f-1 shown in FIG. 14, the command consists of one character data and the parameter consists of two character data. .

  Further, as shown in FIG. 7, the sub CPU 71 has a communication error detecting means 71a, a procedure detecting means 71b, a data destruction detecting means 71c, an error information registering means 71d, a received data log saving means 71e, and error information. The history display means 71f, the two-dimensional code conversion means 71g, and the communication disconnection detection means 71h are provided.

  The communication error detecting means 71a detects that a communication error has occurred between the main control circuit 60 and the sub control circuit 70 by executing a COM error check process shown in FIG. .

  The procedure detection means 71b detects the progress of the game in a procedure different from the normal game procedure, that is, an abnormal procedure, by executing a main board reception command check process shown in FIG. 73 described later. ing.

  The data destruction detection means 71c executes the sum check processing of the sub control game data storage area in the sub CPU main board communication task shown in FIG. 69, which will be described later, so that the game data area 73a-1 of the sub RAM 73-1 (FIG. So that it is possible to detect the data destruction of the command received from the main control circuit 60, the effect data information, the game status information, the internal winning combination information, the display combination information, the various counters and the various flags. It has become.

  The error information registration means 71d stores the error code of the detected error in the error information history storage area 73d-1 of the sub RAM 73-1 when the occurrence of the error is detected by each error detection means. ing.

  Specifically, when the communication error detection means 71a detects the occurrence of a communication error, the error information registration means 71d stores the COM error error code (COM ERR ALM) in the error information history storage area 73d-1. It is supposed to do.

  The error information registration unit 71d stores the error code of the procedure abnormality (for example, BLS123PE) in the error information history storage area 73d-1 when the occurrence of the procedure abnormality error is detected by the procedure detection unit 71b. There is.

  The error information registration means 71d stores the error code (MEM ERR ALM) of the sum abnormality in the error information history storage area 73d-1 when the occurrence of the sum abnormality error is detected by the data destruction detection means 71c. ing.

  In addition, when the communication disconnection detecting unit 71h detects the disconnection of the communication from the main control circuit 60 to the sub control circuit 70, the error information registration unit 71d displays the communication disconnection in the error information history storage area 73d-1. The error code (COM DCN ALM) for notification is stored.

  Further, in the error information history storage area 73d-1, the error information history is created by sequentially storing the error code.

  The reception data log storage means 71e collects information about the reception log (hereinafter, also referred to as communication log) by executing the main board communication reception data log storage processing shown in FIG. 70 described later, and is shown in FIG. 71 described later. By executing the main board communication reception data log temporary area storage processing, only one communication log is temporarily stored in the communication log collection ring buffer area 73e-1.

  Further, the reception data log storage means 71e executes the main board communication error history data storage processing shown in FIG. 72, which will be described later, and saves the communication error when the communication error detection means 71a detects the occurrence of the communication error. Up to 1024 communication logs related to communication errors (hereinafter referred to as communication error logs) are stored in the buffer area 73f-1.

  When a predetermined operation is performed on the door key 2 and a predetermined signal is received from the door key switch 2S, the error information history display means 71f causes the liquid crystal display device 5 to display the error information history stored in the error information history storage area 73d-1. It is supposed to be displayed.

  The two-dimensional code conversion means 71g manages the communication error log and the destination of the communication error relating to the communication error stored in the communication error storage buffer area 73f-1 when the communication error detection means 71a detects the occurrence of the communication error. The domain of the server 500 is converted into the two-dimensional code 300 as transmission information and transmitted to the error information history display means 71f.

  Then, as shown in FIG. 49, when the "COM error alarm" item 23b is selected in the liquid crystal display area 23 in which the error information history is displayed, the error information history display means 71f selects the "COM error alarm" item. The two-dimensional code 300 corresponding to the communication error is displayed on the right side of 23b.

  Here, as shown in FIG. 50, the transmission information included in the two-dimensional code 300 created by the two-dimensional code conversion unit 71g is 192 bytes. The transmission information has a general-purpose configuration so that not only the game machine 1 of the model described in the present embodiment but also the error information recorded by the game machine of another model can be transmitted. Alternatively, the transmission information may include the game record of the player. The items included in the transmission information will be described below.

  In the 0th byte to the 28th byte of the transmission information, the domain of the data management server 500 and data indicating a request to the data management server 500 are set. A case-specific code for identifying the gaming machine 1 is set in the 29th to 39th bytes of the transmission information.

  The 40th to 61st bytes of the transmission information are reserved areas. The time when the transmission information is generated is set in the 62nd to 67th bytes of the transmission information. A model code indicating the type of the gaming machine 1 is set in the 68th to 71st bytes of the transmission information.

  The classification number is set in the 72nd to 73rd bytes of the transmission information. Here, both the 72nd byte and the 73rd byte are set to 3FH.

  The error type is set in the 74th to 75th bytes of the transmission information. Error information is set in the 76th to 188th bytes of the transmission information. A checksum is set from the 189th byte to the 191st byte of the transmission information.

  The error information set from the 76th byte to the 188th byte of the transmission information has a command type consisting of one character (6 bits). If the command type is accompanied by a parameter, the command type of one character is followed by a parameter consisting of two characters (12 bits). FIG. 51 shows an example of command types and parameters.

  The communication disconnection detecting means 71h detects that the communication from the main control circuit 60 to the sub control circuit 70 is cut off. It is assumed that the communication interruption is detected when the interval between the commands transmitted from the main control circuit 60 to the sub control circuit 70 is a fixed time, for example, 30 ms or more.

  When the occurrence of a communication error is detected by the communication error detection means 71a, the error information registration means 71d stores the error code of the communication error in the error information history storage area 73d-1 of the sub RAM 73-1. Then, the reception data log saving means 71e saves the communication log in the communication log collecting ring buffer area 73e-1 and saves the communication error log in the communication error saving buffer area 73f-1.

  When an error other than a communication error is detected by the procedure detecting means 71b other than the communication error detecting means 71a, the data destruction detecting means 71c, or any other error detecting means, the error information registering means 71d causes an error error. The code is stored in the error information history storage area 73d-1 of the sub RAM 73-1. Then, the reception data log saving means 71e saves the communication log in the communication log collecting ring buffer area 73e-1, but does not save the communication log in the communication error saving buffer area 73f-1.

  Then, when the staff member performs a predetermined operation on the door key 2, the error information history display means 71f displays the error information history stored in the error information history storage area 73d-1 on the liquid crystal display device 5. In this case, when the "COM ERR ALM" item 23b is selected in the liquid crystal display area 23 as shown in FIG. 49, the error information history display means 71f displays the communication to the right of the "COM ERR ALM" item 23b. The two-dimensional code 300 corresponding to the error is displayed.

  In this embodiment, in order to display the error information history shown in FIG. 49 on the liquid crystal display device 5, two types of operation methods, that is, a normal operation by a staff member and a simple operation are adopted.

  In the normal operation, the clerk rotates the door key 2 to the right to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and the liquid crystal display area 23 is shown in FIG. The menu screen is displayed. Then, the staff operates the operation key to select the "error information history" item 23a, whereby the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23.

  On the other hand, in the simple operation, the clerk rotates the door key 2 counterclockwise and holds the state for a certain time, for example, 5 seconds or more, so that the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23. ing.

  Further, the sub CPU 71 has a built-in RTC 70a that is a circuit dedicated to timing. An external RTC 70c is connected to the sub CPU 71 for backing up the built-in RTC 70a. A battery 70b is connected to the external RTC 70c and the SRAM 73-2. The built-in RTC 70a and the external RTC 70c are processed by the RTC control task shown in FIG.

  The GPU 74 performs processing for displaying an image on the liquid crystal display device 5, based on an image display command or the like received from the sub CPU 71. Data necessary for the processing performed by the GPU 74 is expanded in the VRAM 75 at the time of startup. The GPU 74 sequentially superimposes the image data expanded in the VRAM 75 from the background image located at the rear to the image located at the front to generate image data, and supplies the image data to the liquid crystal display device 5.

  As a result, an image corresponding to the effect data determined by the sub CPU 71 is displayed on the liquid crystal display area 23 by the liquid crystal display device 5.

  The VRAM 75 has two frame buffers, a write image data area and a display image data area, the write image data area stores image data in which the GPU 74 generated a display image, and the display image data area is The image data to be displayed on the liquid crystal display device 5 is stored.

  The GPU 74 causes the liquid crystal display device 5 to sequentially display the image data by alternately switching these frame buffers (that is, switching banks).

  The digital amplifier 78 amplifies the digital-format sound data selected by the sub CPU 71 based on the effect data, based on the volume adjusted by a volume adjusting knob (not shown) provided in the gaming machine 1, and outputs the analog format. To the speaker 21L, 21R. As a result, a sound corresponding to the effect data determined by the sub CPU 71 is output from the speakers 21L and 21R.

[Game state]
Next, with reference to FIG. 15, the transition of the game state will be described. The main game states managed by the main control circuit 60 include a general game state, an RT1 game state, an RT2 game state, an RT3 game state, an RT4 game state, and a BB game state (general term of BB1 game state to BB4 game state). Further, although not shown, there is an SB gaming state in which only one game coexists with other gaming states, an RB1 gaming state that operates in the BB1 gaming state to the BB3 gaming state, and an RB2 gaming state that operates in the BB4 gaming state.

  First, in the normal game state, the SB spilled eyes (SB spilled eye 1 to SB spilled eye 12) are displayed on the activated line, thereby transitioning to the RT1 game state. Then, in the RT1 game state, the 1st stage rip 1 is displayed on the activated line, thereby transitioning to the RT2 game state. Next, in the RT2 game state, the raising two-stage lip (raising two-stage lip 1, raising two-stage lip 2) and the second raising (raising second 1 to raising 2 third 3) are displayed on the activated line, so that RT3 Transition to the gaming state.

  In addition, in the RT2 gaming state or the RT3 gaming state, the SB spilled eyes (SB spilled eyes 1 to SB spilled eyes 12) are displayed on the activated line, thereby transitioning to the RT1 gaming state. In the RT1 gaming state to the RT3 gaming state, the push-order bell failure (push-order bell failure 1-push-order bell failure 4) is displayed on the activated line, thereby transitioning to the normal game state.

  In the general gaming state, the RT1 gaming state to the RT3 gaming state, BB (BB1 to BB4) is determined as an internal winning combination, so that the state transits to the RT4 gaming state. In the RT4 gaming state, the BB (BB1 to BB4) is displayed, so that the BB gaming state is entered. When a predetermined number (270 or 60) of medals are paid out in the BB game state, the game state shifts to the normal game state.

  Next, the internal lottery table determination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. Note that FIG. 16 is a diagram showing an example of an internal lottery table determination table of the gaming machine 1 in the present embodiment.

  In the internal lottery table determination table, the internal lottery table used to determine the internal winning combination in the internal lottery process described later and the number of lottery in correspondence with the game state (on / off of each gaming state flag described later). Is specified. Thereby, for example, when only the SB gaming state flag and the RT1 gaming state flag are “1 (on)”, the “SB internal RT1 gaming state internal lottery table” is selected as the lottery number. “49” is selected.

  Next, the internal lottery table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 17 is a diagram in which examples of the internal lottery table for the general gaming state, the RT1 gaming state internal lottery table to the RT4 gaming state internal lottery table of the gaming machine 1 in the present embodiment are summarized.

  FIG. 18 is a diagram showing an example of the RB1 gaming state internal lottery table of the gaming machine 1 in the present embodiment.

  FIG. 19 is a diagram showing an example of the RB2 gaming state internal lottery table of the gaming machine 1 in the present embodiment. The internal lottery table for SB general gaming state, the internal lottery table for SB RT1 gaming state to the internal lottery table for SB RT4 gaming state, the lottery value corresponding to the winning number "1" in FIG. 17 is "1000", respectively. The difference is not "" but "1001", so the illustration is omitted.

  The internal lottery table is a table used when performing an internal lottery, that is, when determining an internal winning combination in an internal lottery process described later. In the internal lottery table, a lottery value and a data pointer are defined for each winning number. The lottery value is a numerical value used to determine the data pointer. There are two types of data pointers, a small win / replay data pointer and a bonus data pointer, which correspond to one or more internal winning combinations.

  The abbreviated name of the internal winning combination corresponding to the data pointer is shown in the right column of the winning number in the internal lottery table shown in FIGS. Further, on the right side of each internal lottery table shown in FIG. 18 and FIG. 19, the symbols that can be stopped and displayed on the line connecting the upper stage, the line connecting the middle stage, or the line connecting the lower stage of each reel corresponding to the data pointer. It shows a stop form.

  For example, in the RB1 gaming state, when "25" is determined as the small win / replay data pointer, the stop operation is performed at a timing at which the don symbols can be stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C. When done, the don symbol is stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C, but the stop operation is performed at a timing at which the don symbol can be stopped and displayed on the lower stage of the right reel 3R. Even in the case, the don symbol is not stopped and displayed on the lower stage of the right reel 3R.

  On the other hand, when "28" is determined as the small win / replay data pointer, the stop operation is performed at a timing when the don symbol can be stopped and displayed on the lower stage of the left reel 3L, the lower stage of the middle reel 3C, and the lower stage of the right reel 3R. By this, the don symbol is stopped and displayed on the line connecting the lower stages of the reels.

  In the stop form of the symbols aligned on the pay line in FIG. 18, “tempai miss” means that the stop operation is performed at a timing at which the don symbols can be stopped displayed on the corresponding line, "Don symbol-Don symbol-Don symbol" means a stop type that is not stopped and displayed on the line connecting the upper stage, the line connecting the middle stage, and the line connecting the lower stage of each reel.

  On the other hand, "Tempai per" means that the stop operation is performed on the corresponding line at a timing at which the don symbol can be stopped and displayed, so that the "don symbol-don symbol-don symbol" line connecting the upper stages of each reel. , A stop type that is displayed as a stop on the line connecting the middle row or the line connecting the lower rows.

  Next, a method of determining the data pointer using the lottery value, that is, an internal lottery method will be described. In the internal lottery, first, a random number value is extracted from a predetermined range of numerical values “0 to 65535”, and the lottery value corresponding to each lottery number is sequentially subtracted from the extracted random number value, and counting is performed. It is performed by determining whether or not it is. The digitizing is performed when the numerical value to be subtracted is smaller, in other words, when the result of the subtraction is negative.

  For example, when the internal lottery table for the general gaming state is determined to be the internal lottery table, when the extracted random number value is "1500", the main CPU 31 first corresponds to the winning number "1" from "1500". The lottery value "1000" to be subtracted is subtracted. The subtraction result is "1500-1000 = 500", which is positive.

  Next, the main CPU 31 subtracts the lottery value “2100” corresponding to the winning number “2” from the value “500” after the subtraction. The subtraction result is "500-2100 = -1600", which is negative. Therefore, the main CPU 31 determines the winning number "2" as the internal winning combination, that is, "13" as the small / replay data pointer and "0" as the bonus data pointer.

  According to this internal lottery method, the larger the numerical value defined as the lottery value, the higher the possibility that the data pointer of the corresponding lottery number is determined. The winning probability of each winning number is "the lottery value corresponding to each winning number / the number of all random number values that may be extracted (" 65536 ").

  Note that various types of lottery performed using lottery values to be described later are the same as when determining the data pointer. That is, in the various lottery tables, lottery values are defined in association with items (for example, winning numbers) that may be selected by lottery. Hereinafter, various lottery methods based on the lottery value are the same as the internal lottery method, and therefore description thereof will be omitted.

  Next, the RT transition table will be described with reference to FIG. The RT transition table is a table used when updating the game state flag in the RT control process described later. As shown in FIG. 20, the RT transition table defines the display combination and the control contents for the game state flag corresponding thereto.

  Specifically, when the combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the activated line, all the game state flags are turned off. That is, the general game state is activated. Further, when the combination of symbols relating to any of SB spilled eyes 1 to SB spilled eyes 12 is stopped and displayed on the activated line, the RT1 gaming state flag is turned on. Further, when the combination of symbols relating to the 1st stage rise 1 is stopped and displayed on the activated line, the RT2 game state flag is turned on. In addition, when the combination of the symbols related to the raising 2 stage lip 1, the raising 2 stage lip 2 and the raising 2nd stage 1st to the raising 2nd stage 3 is stopped and displayed on the activated line, the RT3 gaming state flag is turned on. To do.

  In addition, push order bell failure 1-push order bell failure 4, SB spilled eye 1-SB spilled eye 12, Raise 1 step Lip 1, Raise 2 step Lip 1, Raise 2 step Lip 2, Raise 2 eye 1 Raise 2 eye 3 is a case where a predetermined winning combination is determined as an internal winning combination, and when the stop operation is performed according to a predetermined stop operation sequence, the operation is stopped in a stop operation order different from the predetermined stop operation order. This is a display combination that may be stopped and displayed on the activated line when an operation is performed or when a stop operation is not performed at an appropriate timing, and details will be described later.

  Next, with reference to FIG. 21 and FIG. 22, a bonus internal winning combination determination table and a small combination / replay internal winning combination determination table stored in the main ROM 32 of the main control circuit 60 will be described. 21. FIG. 21 is a diagram showing an example of a bonus internal winning combination determination table of the gaming machine 1 in the present embodiment. Further, FIG. 22 is a diagram showing an example of a small winning combination / replay internal winning combination determining table of the gaming machine 1 in the present embodiment. Hereinafter, the bonus internal winning combination determination table and the small winning / replay internal winning combination determination table are collectively referred to as an internal winning combination determination table.

  The internal winning combination determination table is a table used when determining an internal winning combination based on a data pointer in an internal lottery process described later. The internal winning combination determination table defines each winning combination determined as an internal winning combination corresponding to the data pointer. Each winning combination corresponds to each bit stored in an internal winning combination storing area described later. Therefore, which combination is an internal winning combination can be identified by which bit in the internal winning combination storing area is "1".

  The internal winning combination determination table for bonus shown in FIG. 21 defines internal winning combinations corresponding to the bonus data pointers "1" to "5". When "5" is determined as the bonus data pointer, the combination of symbols relating to SB is stopped and displayed on the activated line depending on whether or not the stop operation is performed in a predetermined stop order, or , The combination of symbols relating to any one of SB spilled eye 1 to SB spilled eye 12 is stopped and displayed on the activated line.

  In the small winning / replaying internal winning combination determination table shown in FIG. 22, the internal winning combinations corresponding to the small winning / replaying data pointers "1" to "31" are defined. For example, when "1" is determined as the small win / replay data pointer, the normal lip 1 and the up 1-step lip 1 are the internal winning combinations.

  When "2" is determined as the small win / replay data pointer, a first stop operation is performed on the left reel 3L, a second stop operation is performed on the middle reel 3C, and a second stop operation is performed on the right reel 3R. Only when 3 stop operations are performed, the combination of symbols related to the 1st stage lift 1 is stopped and displayed on the activated line. On the other hand, when the stop operation is performed in a stop operation sequence other than this, the combination of the symbols relating to the normal lip 1 is stopped and displayed on the activated line.

  Also for the small role / replay data pointers "3" to "6", the stop operation sequence in which the combination of the symbols related to the 1st stage rip 1 is stopped and displayed on the activated line is predetermined, and this stop operation sequence is set. When the stop operation is performed in a stop operation sequence other than, the combination of the symbols relating to the normal lip 1 is stopped and displayed on the activated line.

  Further, when "7" is determined as the small win / replay data pointer, only when the first stop operation is performed on the left reel 3L, the raising 2-step lip 1, the raising 2-step lip 2, The combination of symbols relating to one of the raised second 1, raised 2 and 3 raised 2 is stopped and displayed on the activated line.

  In addition, when the raising 2nd 1, raising 2nd 2 and raising 2nd 3 are stopped and displayed on the activated line, at the same time, the normal lip 1 or the raised 1st stage lip 1 is stopped and displayed on the activated line. On the other hand, when the stop operation is performed in a stop operation sequence other than this, the combination of the symbols relating to the normal lip 1 is stopped and displayed on the activated line.

  Also for the small role / replay data pointers "8" to "11", the combination of symbols relating to the raising 2-step lip 1, the raising 2-step lip 2, raising the second 1, raising the second 2 and raising the second 3 is effective. The stop operation order to be stopped and displayed on the line is predetermined, and when the stop operation is performed in a stop operation order other than this stop operation order, the combination of the symbols relating to the normal lip 1 is normally displayed on the effective line. It is displayed as a stop.

  When "12" is determined as the small win / replay data pointer, the symbols relating to the bell are stopped and displayed in the middle stage of the middle reel 3C regardless of the stop operation order.

  When "13" is determined as the small win / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the third stop is performed on the right reel 3R. Only when the operation is performed, the symbols related to the bell are stopped and displayed in the middle stage of the middle reel 3C.

  On the other hand, when the stop operation is performed in a stop operation sequence other than this, a combination of symbols relating to one of the push-order bell failure 1 to the push-order bell failure 4 is stopped and displayed on the activated line. When the symbol relating to the bell is stopped and displayed in the middle stage of the middle reel 3C, "Bell 1 symbol (Bell 2 symbol) -Bell 1 symbol-" is displayed on any of the center line 8c, cross-up line 8a, and cross-down line 8e. "Bell 1 design" is stopped and displayed.

  Further, when the combination of symbols relating to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the activated line, the lower row of the left reel 3L, the lower row of the middle reel 3C, and the lower row of the right reel 3R are displayed. , "Bell 1 design (Bell 2 design) -Bell 1 design-Bell 1 design" are stopped and displayed.

  Also for the small role / replay data pointers "14" to "17", the stop operation sequence in which the symbols related to the bell are stopped and displayed in the middle stage of the middle reel 3C is predetermined, and the stop operation other than this stop operation sequence is performed. When the stop operation is performed in order, the combination of symbols relating to one of the push-order bell failure 1 to the push-order bell failure 4 is stopped and displayed on the activated line.

  In the internal lottery table, when a small role / replay pointer whose abbreviated name suggests a stop operation sequence (press sequence) for reels is determined, the suggested press sequence is the so-called correct press sequence. By performing the stop operation in the order of pressing, the reels 3 are stopped so that the player has an advantage.

  For example, when the small win / replay pointer “2” (abbreviation “left middle right bell”) is determined, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, Only when the third stop operation is performed on the right reel 3R, the symbols relating to the bell are stopped and displayed in the middle stage of the middle reel 3C (payout number: 4 sheets x 3 lines = 12 sheets), and other pushing order In the case of, the symbols related to the bell are stopped and displayed on the lower stage of the middle reel 3C (payout number: 4 x 1 line = 4). The small role / replay pointers whose abbreviations indicate the stop operation order (press order) for the reels are "2" to "11" and "13" to "17".

  Next, the symbol combination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. Note that FIG. 23 is a diagram showing an example of a symbol combination table of the gaming machine 1 in the present embodiment.

  In the symbol combination table, a combination of symbols relating to the privilege display displayed on the activated line, or a combination of symbols relating to the transition of the gaming state, and data indicating the display combination corresponding to the symbol combination and the storage area type , And the number of payouts are specified. The data indicating the display combination is any one of display combination storage area 1 to display combination storage area 7 (display combination storage area 1 to display combination storage area 7 are collectively referred to as display combination storage area), each of which is composed of 1 byte described later. Is the data stored in. Further, in which display combination storage area the data is stored is defined by the storage area type.

  In the symbol combination table, as a display combination, BB1 to BB4, SB, normal lip 1, raising 1 step lip 1, raising 2 step lip 1, raising 2 step lip 2, control lip 1 to control lip 3, bell, ice 1 , Cherry 1 to cherry 12, control combination 1 to control combination 3, BB middle combination 1 to BB middle combination 5, up 2nd 1 up 2nd 3, push order bell failure 1 push order bell failure 4, SB Spilled eyes 1 to SB spilled eyes 12 are defined.

  For example, the normal lip 1 is established by displaying "replay symbol-replay symbol-replay symbol" on the activated line. Replay is performed in the next game by the establishment of any of various replays (normal rip 1, raising 1-stage rep 1, raising 2nd-stage rep 1, raising 2nd-stage rep 2, control rep 1 to control rep 3) Be seen. That is, the same number of medals as the number of inserted coins in the game in which any of the various replays is established is automatically inserted in the next game without being based on the insertion operation by the player.

  This allows the player to play the next game without consuming medals. Here, the payout of tokens and the re-playing described above are examples of giving a game value. The bell is established by displaying "ANY symbol-Bell 1 symbol-ANY symbol" on the activated line. In addition, "ANY" represents that any design may be used.

  Next, with reference to FIG. 24, the bonus operation time table stored in the main ROM 32 of the main control circuit 60 will be described. Note that FIG. 24 is a diagram showing an example of a bonus operation time table of the gaming machine 1 in the present embodiment.

  The bonus operation time table is a table used when setting conditions for ending the BB gaming state and the RB gaming state. In the bonus operation table, the ending conditions relating to the BB1 gaming state to the BB4 gaming state, the RB1 gaming state, and the RB2 gaming state are defined. Specifically, in the bonus operation table, "270" is defined as the value of the bonus end number counter as the end condition of the BB1 game state to the BB3 game state.

  Further, as the ending condition of the BB4 gaming state, "60" is defined as the value of the bonus ending number counter. In the BB1 gaming state to the BB3 gaming state, the RB1 gaming state operates, and in the BB4 gaming state, the RB2 gaming state operates. Further, in the bonus operation table, "12" and "8" are defined for the values of the number of possible games and the number of possible winnings, respectively, as conditions for ending the RB1 gaming state and the RB2 gaming state.

  Next, the attraction priority table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. Note that FIG. 25 is a diagram showing an example of the attraction-in priority table A of the gaming machine 1 in the present embodiment, and FIG. 26 shows an example of the attraction-in priority table B of the gaming machine 1 in the present embodiment. It is a figure. Hereinafter, the attraction-in priority table A and the attraction-in priority table B are collectively referred to as attraction-in priority table.

  When a plurality of winning combinations are determined as internal winning combinations, the winning priority table indicates that when a plurality of winning combinations can be drawn on the activated line, the symbols relating to any winning combination are given priority on the activated line. It specifies whether to stop. As described above, basically, the replay, the small combination (the larger the number of payouts, the higher the priority. In the case of JAC1 (7 in BB), this is the priority) and the bonus order. Has become.

  However, in the present embodiment, there are a plurality of types of replays, and the priority order of each replay differs depending on the conditions, so the attraction priority table A and attraction priority table B are provided for each condition.

  The pull-in priority table A is a table used in normal times (including during BB) and in a so-called push-order correct answer, and the priority order of each replay is an increase 2-step rep 1, an increase 2-step rep 2> an increase 1-step rep 1 > Normal Lip 1> Control Lip 1-Control Lip 3

  On the other hand, the pull-in priority table B is a table used when a so-called push-order incorrect answer is given, and the priority order of each replay is normal rip 1> raise 2 stage rep 1, raise 2 stage rep 2, raise 1 stage rip 1> control The order is Lip 1-Control Lip 3.

  Although not shown, when two or more winning combinations related to the transition of the RT gaming state are simultaneously displaying combinations, which one is to be prioritized is predetermined. In the present embodiment, in order of higher priority, the raising 2 stage lip 1, the raising 2 stage lip 2, the raising 2nd 1−the raising 2nd 3> the raising 1st stage lip 1> SB spilling eye 1−SB spilling Eye 12> push order bell failure 1-push order bell failure 4

  Next, the stop table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. Note that FIG. 27 is a diagram showing an example of a stop table for a case where the small win / replay data pointer “15” is won and the middle reel is first stopped. In the stop table, line data and stop data corresponding to the symbol positions “0” to “20” are defined. The symbol position is a symbol position located in the middle stage of the symbol display area when a stop operation is detected, and is a symbol position where the rotation of the reel is started to stop.

  Although not shown, the main ROM 32 of the main control circuit 60 stores a small win / replay data pointer and a plurality of stop tables according to the player's stop operation sequence. For example, when "5" is determined as the bonus data pointer, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. Only in the case of performing, the stop table in which the number of sliding frames is defined such that none of the SB spilled eyes 1 to SB spilled eyes 12 is stopped and displayed on the activated line is selected.

  On the other hand, when the stop operation is performed in a stop operation order other than this stop operation order, when the stop operation is performed on each reel at a timing when the combination of symbols relating to SB is not stop-displayed, the SB spill 1 ~ The stop table in which the number of sliding symbols is defined is selected so that the combination of symbols relating to any of the SB spilled eyes 12 is stopped and displayed on the activated line.

  Next, with reference to FIG. 28 to FIG. 30, the internal winning combination storing area, the display combination storing area and the carryover combination storing area assigned to the main RAM 33 of the main control circuit 60 will be described. Note that FIG. 28 is a diagram showing an example of an internal winning combination storing area of the gaming machine 1 in the present embodiment. Further, FIG. 29 is a diagram showing an example of a display combination storing area of the gaming machine 1 in the present embodiment. Further, FIG. 30 is a diagram showing an example of a carryover combination storing area of the gaming machine 1 in the present embodiment.

  As shown in FIG. 28, the internal winning combination storing area is made up of an internal winning combination storing area 1 to an internal winning combination storing area 5. The internal winning combination storing area 1 to the internal winning combination storing area 5 are 8-bit data areas allocated on the main RAM 33 and store internal winning combination information. Each internal winning combination storing area indicates which combination is an internal winning combination by storing data of "0" or "1" in the area of bits "0" to "7".

  As shown in FIG. 29, the display combination storing area is composed of a display combination storing area 1 to a display combination storing area 7. The display combination storing area 1 to the display combination storing area 7 are 8-bit data areas allocated on the main RAM 33 and store display combination information. Each display combination storing area indicates which combination is a display combination by storing data of "0" or "1" in the area of bits "0" to "7".

  As shown in FIG. 30, the internal carryover combination storage area is an 8-bit data area allocated on the main RAM 33 and stores internal carryover combination information. The carryover combination storage area indicates which combination is a carryover combination by storing data of "0" or "1" in the areas of bits "0" to "3".

  Next, with reference to FIG. 31, a game state flag storage area assigned to the main RAM 33 of the main control circuit 60 will be described. 31. FIG. 31 is a diagram showing an example of the game state flag storage area of the gaming machine 1 in the present embodiment.

  As shown in FIG. 31, the game state flag storage area includes a game state flag storage area 1 and a game state flag storage area 2. The gaming status flag storage area is an 8-bit data area allocated on the main RAM 33, and indicates whether each gaming status flag is on or off. Further, when all the data in each area of the game state flag storage area is "0", it indicates that the game state is the normal game state.

  Next, the symbol storage area in the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. 32 and 33. 32 is a diagram showing a storage example of the symbol storage area A (in the non-RB) of the gaming machine 1 in the present embodiment (when the symbol position data of each reel is "0"). FIG. 33 is a storage example of the symbol storage area B (in RB) of the gaming machine 1 in the present embodiment (when the symbol position data of each reel is “9”, “8”, “9” from the left reel). ) Is a figure which shows.

  The symbol storage area is an area for storing the corresponding symbol code in the symbol display areas 4L, 4C, and 4R forming each activated line, and is provided for each activated line. For example, when the gaming state is a gaming state other than the RB gaming state, it corresponds to the middle row of the left symbol display area 4L, the middle row of the middle symbol display area 4C, and the middle row of the right symbol display area 4R that configure the center line 8c. Stores the design code.

  Such a symbol storage area is also provided for other effective lines (cross-down line 8e, bottom line 8d, cross-up line 8a). When the gaming state is the RB gaming state, the effective line is only one line (special line 8f in RB), and the special line 8f in RB is formed in the symbol storage area corresponding to the special line in RB 8f. A symbol code corresponding to each of the middle row of the left symbol display area 4L, the lower row of the middle symbol display area 4C, and the upper row of the right symbol display area 4R is stored.

  The symbol storage area shown in FIG. 32 shows the symbol storage area when the symbol code is stored when the symbol position data of each reel is “0”. The case where the symbol position data is "0" means that the symbol position "0" of each reel 3L, 3C, 3R (7 symbols red on the left reel 3L, 7 symbols red on the middle reel 3C, red symbol on the right reel 3R). 7 symbols) are displayed in the middle of the left symbol display area 4L, the middle of the middle symbol display area 4C, and the middle of the right symbol display area 4R, respectively.

  Therefore, in this case, in the symbol storage area corresponding to the upper row of the left symbol display area 4L, the symbol of the symbol position "1" (wave pattern), in the symbol storage area corresponding to the lower row of the left symbol display area 4L, the symbol position of " The symbol code indicating the symbol “20” (replay symbol) will be stored. The symbol storage area corresponding to the upper portion of the middle symbol display area 4C has a symbol position "1" (replay symbol), and the symbol storage area corresponding to the lower portion of the middle symbol display area 4C has a symbol position of "20". A design code indicating the design (cherry 1 design) will be stored.

  Furthermore, in the symbol storage area corresponding to the upper part of the right symbol display area 4R, the symbol at the symbol position "1" (cherry 1 symbol), and in the symbol storage area corresponding to the lower row of the right symbol display region 4R, the symbol position "20" The symbol code indicating the symbol (bell 1 symbol) will be stored.

[Control operation of main control circuit]
Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS.

  First, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described with reference to FIG. 34. FIG. 34 is a diagram showing a flowchart of the reset interrupt process performed by the main CPU 31 in the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt when the power is turned on and a voltage is applied to the reset terminal, and the reset interrupt processing stored in the main ROM 32 is sequentially performed based on the occurrence of the interrupt. Is configured to do.

  First, the main CPU 31 clears the designated storage area (step S1). Specifically, the main CPU 31 clears the designated storage area of the main RAM 33 at the end of the previous game. More specifically, the main CPU 31 erases data in the writable area in the main RAM 33 used in the previous game, writes parameters necessary for the current game in the writable area in the main RAM 33, and in the current game. Specifies the start address for the sequence program.

  Next, the main CPU 31 executes a bonus operation monitoring process (step S2).

  Next, the main CPU 31 performs medal acceptance / start check processing (step S3). In the medal acceptance / start check process, the inserted number counter is updated by checking the medal sensor 22S and the maximum BET switch 13S, and the input check of the start switch 6S is performed. The main CPU 31 activates the pay line through the medal acceptance / start check process.

  Next, the main CPU 31 performs a process of extracting a random number value and storing it in the random number value storage area (step S4). Specifically, the main CPU 31 extracts a random number value from the range of “0” to “65535” by the random number generator 36 and the sampling circuit 37, and stores the extracted random number value in the random number storage area of the main RAM 33.

  Next, the main CPU 31 performs an internal lottery process (step S5). Specifically, the main CPU 31 refers to the internal lottery table determination table (see FIG. 16), the internal lottery table (see FIGS. 17 to 19), and the internal winning combination determination table (see FIGS. 21 and 22) described above. Determine the internal winning combination.

  Next, the main CPU 31 transmits start command data to the sub control circuit 70 (step S6). The start command includes information such as game status information, internal winning combination information (small winning combination / replay data pointer, bonus data pointer and internal winning combination storing area), and carryover status information indicating whether or not the bonus is carried over. It is included.

  As a specific process, the main CPU 31, for example, sets parameters such as a flag and a counter, sets a start command, and performs a communication data storage process described later to store communication data to be transmitted in a communication data storage area. You are supposed to register at. The following command data is also transmitted to the sub control circuit 70 in the same manner.

  Next, the main CPU 31 requests the start of rotation of all reels (step S7). When the rotation start of all reels is requested, the rotation start processing and the acceleration control processing of the reels 3L, 3C, 3R are performed.

  Next, the main CPU 31 waits for a constant speed for reel rotation (step S8).

  Next, the main CPU 31 executes reel stop control processing (step S9). In this reel stop control process, the main CPU 31 stops the rotation of each reel 3L, 3C, 3R based on the stop signal or the like transmitted from the stop switches 7LS, 7CS, 7RS by the player's stop operation.

  Next, the main CPU 31 performs a display combination search process (step S10). In this display combination search process, the main CPU 31 determines the display combination and the payout number based on the combination of the symbols displayed on the activated line as a result of stopping the rotation of all the reels 3L, 3C, 3R.

  Next, the main CPU 31 performs RT control processing (step S11).

  Next, the main CPU 31 transmits the display command data (step S12). The display command includes information such as display combination information indicating a display combination and payout amount information indicating a payout amount.

  As a specific process, the main CPU 31, for example, sets the RT operation combination display flag in P1 and sets the winning number counter in P2. Then, the main CPU 31 sets a display command and performs a communication data storage process described later to register the communication data to be transmitted in the communication data storage area.

  Next, the main CPU 31 performs medal payout processing (step S13). Specifically, in the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 to pay out medals based on the payout number, and in the credit mode, the main CPU 31 based on the payout number. The credit counter set in the RAM 33 is updated.

  Next, it is determined whether or not the bonus operation is in progress (step S14). Specifically, it is determined whether or not it is in the BB1 gaming state to the BB4 gaming state or the SB gaming state. At this time, when the main CPU 31 determines that the bonus operation is being performed, the main CPU 31 performs a bonus end check process (step S15), and proceeds to the process of step S16. On the other hand, when the main CPU 31 determines that the bonus operation is not being performed or after the processing of step S15 is completed, then the main CPU 31 performs the bonus operation check processing (step S16).

  In this way, the main CPU 31 executes the processing from step S1 to step S16 as the processing in one game (one game), and when the processing in step S16 ends, the processing in step S1 is executed to execute the processing in the next game. Move to.

  Next, the bonus operation monitoring process will be described with reference to FIG. Note that FIG. 35 is a diagram showing a flowchart of bonus operation monitoring processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not it is in the BB game state (step S31). At this time, when the main CPU 31 determines that it is in the BB gaming state, it shifts to the processing of step S32. On the other hand, when the main CPU 31 determines that it is not in the BB gaming state, it ends the bonus operation monitoring process.

  When determining in the BB game state in the process of step S31, the main CPU 31 then determines whether or not it is in the RB game state (step S32). At this time, when the main CPU 31 determines that it is in the RB game state, it ends the bonus operation monitoring process.

  On the other hand, when the main CPU 31 determines that it is not in the RB game state, it performs the RB operation time process according to the BB type based on the bonus operation time table (see FIG. 24) (step S33), and performs the bonus operation monitoring process. To finish. Specifically, in the BB1 gaming state to the BB3 gaming state, the RB1 gaming state is activated, and in the BB4 gaming state, the RB2 gaming state is activated.

  Next, the internal lottery process will be described with reference to FIGS. 36 and 37. 36 and 37 are flowcharts of the internal lottery process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 refers to the internal lottery table determination table (see FIG. 16) and determines the type of the internal lottery table and the lottery number based on the game state flag (step S61). Next, the main CPU 31 acquires a random number value from the random number value storage area and sets it as a determination random number value (step S62). Next, the main CPU 31 sets "1" as the initial value of the winning number (step S63).

  Next, the main CPU 31 refers to the internal lottery table and acquires the lottery value based on the winning number (step S64). Next, the main CPU 31 subtracts the lottery value from the determination random number value, and sets the subtraction result as the determination random number value (step S65). Specifically, the main CPU 31 subtracts the lottery value acquired in the process of step S64 from the determination random number value stored in the determination random value storage area, and updates the determination random value storage area with the subtraction result. .

  Next, the main CPU 31 determines whether or not a digit has been carried out in the subtraction processing in step S65, that is, whether or not the subtraction result has a negative value (step S66). At this time, when the main CPU 31 determines that the carry has been carried out, the main CPU 31 acquires the small win / replay data pointer and the bonus data pointer based on the winning number (step S70), and proceeds to the processing of step S71.

  On the other hand, when the main CPU 31 determines that the carry has not been carried out, it then subtracts "1" from the lottery number and adds "1" to the winning number (step S67). Next, the main CPU 31 determines whether or not the number of lotteries is “0” (step S68).

  When the main CPU 31 determines in the process of step S68 that the number of lotteries is “0”, it determines the small win / replay data pointer and the bonus data pointer to be “0” (step S69), and in step S71. Move to processing. On the other hand, when the main CPU 31 determines that the number of lotteries is not “0”, the main CPU 31 proceeds to the process of step S64. After that, the main CPU 31 repeats the processing from step S64 to step S68 until the number of lottery becomes “0” or a digit is taken.

  After finishing the process of step S69 or step S70, the main CPU 31 then refers to the small winning combination / replay internal winning combination determination table (see FIG. 22), and based on the small winning / replay data pointer, the internal winning is determined. The winning combination is acquired (step S71). Next, the main CPU 31 updates the internal winning combination storing area according to the internal winning combination (step S72).

  Next, the main CPU 31 determines whether or not the carryover combination storing area is "00000000" (step S73). At this time, when the main CPU 31 determines that the carryover combination storing area is not “00000000”, the main CPU 31 proceeds to the process of step S80. On the other hand, when the main CPU 31 determines that the internal carryover combination storing area is “00000000”, it refers to the bonus internal winning combination determination table (FIG. 21) and acquires the internal winning combination based on the bonus data pointer ( Step S74).

  Next, the main CPU 31 determines whether SB is an internal winning combination (step S75). At this time, when the main CPU 31 determines that SB is an internal winning combination, the main CPU 31 updates the internal winning combination storing area according to SB (step S76), and shifts to the processing of step S80. On the other hand, when determining that SB is not the internal winning combination, the main CPU 31 determines whether BB is the internal winning combination (step S77).

  When determining in the process of step S77 that the BB is not the internal winning combination, the main CPU 31 proceeds to the process of step S80. On the other hand, when determining that BB is the internal winning combination, the main CPU 31 updates the carryover combination storing area according to BB (step S78), turns on the RT4 gaming state flag (step S79), and the process of step S80. Move to.

  When the main CPU 31 determines in the processing of step S73 that the internal carryover combination storage area is not “00000000”, in the processing of step S77, it determines that BB is not the internal winning combination, the processing of steps S76 and S79. After finishing, the logical sum of the internal carryover combination storing area and the internal winning combination storing area 1 is calculated, and the result is stored in the internal winning combination storing area 1 (step S80).

  The main CPU 31 performs the lottery for the internal winning combination by repeatedly executing the processes of steps S64 to S68 in the internal lottery process. Specifically, the main CPU 31 sequentially subtracts the lottery value from the extracted random number value to obtain a small win / replay data pointer and a bonus data pointer corresponding to the winning number when the digit was carried out. The internal winning combination is determined based on the determined data pointers and the internal winning combination determination table.

  Next, the reel stop control processing will be described with reference to FIG. 38. FIG. 38 is a diagram showing a flowchart of reel stop control processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 sets "3" to the stop button non-operation counter (step S101), and then acquires the stop table corresponding to the internal winning combination (step S102).

  Next, the main CPU 31 determines whether or not a valid stop button has been pressed (step S103). An effective stop button is a stop button that has not been stopped. At this time, when determining that the valid stop button has been pressed, the main CPU 31 shifts to the processing of step S104.

  On the other hand, when determining that the valid stop button is not pressed, the main CPU 31 executes the process of step S103 again. That is, the main CPU 31 repeats the process of step S103 until the stop operation corresponding to the valid stop button is detected.

  When determining in the process of step S103 that a valid stop button is pressed, the main CPU 31 invalidates the operation of the corresponding stop button (step S104). Next, the stop table is reselected according to the operation stop button (stop order) (step S105).

  Next, the main CPU 31 sets "5" as the number of checks (step S106). Next, the main CPU 31 refers to the attraction-in priority table (see FIGS. 25 and 26), and based on the internal winning combination, within the range of the number of checks from the symbol position corresponding to the symbol counter, the symbol with the highest priority. The position is searched (step S107).

  Next, the main CPU 31 determines the number of sliding symbols based on the stop table, the symbol position corresponding to the symbol counter, and the result of the search, and sets the scheduled stop position (step S108). Next, the main CPU 31 transmits a reel stop command (step S109). The reel stop command includes information such as stop reel type information indicating which reel has stopped, stop start position information indicating a stop start position, and sliding frame number information indicating a sliding frame number.

  Next, the main CPU 31 refers to the symbol arrangement table (see FIG. 3), acquires the symbol code based on the stop reel, the planned stop position, and the game state, and stores it in the symbol storage area (step S110).

  Finally, the main CPU 31 determines whether or not there is a stop button for which the operation is valid (step S111). At this time, when determining that there is no stop button for which the operation is valid, the main CPU 31 ends the reel stop control process. On the other hand, when the main CPU 31 determines that there is a stop button for which the operation is valid, the main CPU 31 proceeds to the process of step S103. After that, the main CPU 31 repeats the processing from step S103 to step S111 until it is determined that there is no stop button for which the operation is valid.

  Next, the display combination search process will be described with reference to FIG. Note that FIG. 39 is a diagram showing a flowchart of the display combination search process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 clears the display combination storing area (step S121).

  Next, the main CPU 31 specifies the start address of the symbol storage area (step S122). Specifically, the main CPU 31 designates the address corresponding to the center line 8c as the start address when the gaming state is a gaming state other than the RB gaming state, and the RB when the gaming state is the RB gaming state. The address corresponding to the medium special line 8f is designated as the start address.

  Next, the main CPU 31 specifies the start address of the symbol combination table (see FIG. 23) (step S123). Specifically, the main CPU 31 specifies the address corresponding to BB1 as the start address.

  Next, the main CPU 31 compares the symbol combination defined in the symbol combination table with the symbol combination stored in the symbol storage area (step S124).

  Next, the main CPU 31 determines whether or not the combination of the symbols defined in the symbol combination table and the combination of the symbols stored in the symbol storage area match as a result of the comparison in the process of step S124 ( Step S125). At this time, when the main CPU 31 determines that the symbol combination defined in the symbol combination table does not match the symbol combination stored in the symbol storage area, the main CPU 31 proceeds to the process of step S129, while When it is determined that they match, data indicating the storage area type and the display combination is acquired from the symbol combination table (step S126).

  Next, the main CPU 31 stores the logical sum of the display combination storing area corresponding to the acquired storage area type and the acquired data indicating the display combination in the display combination storing area (step S127).

  Next, the main CPU 31 acquires the payout number from the symbol combination table and adds it to the payout number counter (step S128).

  When the main CPU 31 determines in the process of step S125 that the symbol combination defined in the symbol combination table does not match the symbol combination stored in the symbol storage area, or ends the process of step S128. Then, the address corresponding to the next winning combination in the symbol combination table is designated (step S129).

  Next, the main CPU 31 determines whether the end code is stored in the address designated in the process of step S129 (step S130). At this time, when the main CPU 31 determines that the end code is not stored, the main CPU 31 proceeds to the process of step S124. On the other hand, when the main CPU 31 determines that the end code is stored, it then determines whether or not all valid lines have been searched, that is, whether or not the steps S124 to S130 have been performed on all valid lines. It is determined (step S131).

  When the main CPU determines in the processing of step S131 that all effective lines have been searched, it ends the display combination search processing. On the other hand, when the main CPU determines that it has not searched for all valid lines, it then specifies the address corresponding to the next valid line in the symbol storage area (step S132), and proceeds to the process of step S123.

  Next, the RT control processing will be described with reference to FIG. Note that FIG. 40 is a diagram showing a flowchart of the RT control processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not it is in the BB carryover (RT4 gaming state) (step S161). At this time, when the main CPU 31 determines that the BB is being carried over, it ends the RT control processing. On the other hand, when the main CPU 31 determines that the BB is not being carried over, the main CPU 31 determines whether or not the BB is being carried over (step S162). Specifically, it is determined whether or not any BB game state flag is ON.

  When the main CPU 31 determines in the process of step S162 that the BB is in progress, the main CPU 31 ends the RT control process. On the other hand, when the main CPU 31 determines that it is not in BB, it refers to the RT transition table (see FIG. 20), and updates the gaming state flag based on the display combination if necessary (step S163). ), The RT control process is terminated.

  Next, the bonus end check processing will be described with reference to FIG. Note that FIG. 41 is a diagram showing a flowchart of bonus end check processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not it is in BB (step S141). At this time, when the main CPU 31 determines that it is not in BB, it turns off the SB game state flag (step S142) and ends the bonus end check process. On the other hand, when determining that the BB is in progress, the main CPU 31 determines whether or not the value of the bonus end number counter is "0" (step S143).

  When determining that the value of the bonus end number counter is "0", the main CPU 31 executes a bonus end time process (step S144). Specifically, the BB game state flag and the RB game state flag that are on are turned off. Next, the main CPU 31 transmits a bonus end command (step S145), and ends the bonus end check process.

  On the other hand, when the main CPU 31 determines that the value of the bonus end number counter is not "0", it subtracts "1" from the value of the number-of-games possible counter (step S146), and the display combination is the small combination. It is determined (step S147). At this time, when the main CPU 31 determines that the display combination is not the small combination, the main CPU 31 proceeds to the process of step S149. On the other hand, when determining that the display combination is a small combination, the main CPU 31 subtracts "1" from the value of the possible winning number counter (step S148), and proceeds to the processing of step S149.

  Next, the main CPU 31 determines whether or not the value of the prize winning number counter or the game possible number counter is "0" (step S149). At this time, when the main CPU 31 determines that neither the value of the possible winning number counter nor the value of the possible playing number counter is “0”, the bonus end checking process is ended. On the other hand, when the main CPU 31 determines that the value of the possible winning number counter or the value of the possible playing number counter is “0”, then the main CPU 31 performs the RB end time process (step S150) to end the bonus end check process. . In the processing at the end of RB, processing such as turning off the RB gaming state flag that is on is performed.

  Next, the bonus operation check process will be described with reference to FIG. Note that FIG. 42 is a diagram showing a flowchart of bonus operation check processing performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether the display combination is BB (any one of BB1 to BB4) (step S171). At this time, when the main CPU 31 determines that the display combination is not BB, the main CPU 31 proceeds to the process of step S174. On the other hand, when the main CPU 31 determines that the display combination is BB, the main CPU 31 performs bonus operation time processing (step S172).

  In this bonus operation time process, the bonus operation time table (FIG. 24) is referred to and the game state flag is turned on and the bonus end number counter is set to a value in accordance with the game state to be operated. Next, the main CPU 31 turns off the RT4 gaming state flag, clears the carryover combination storing area (step S173), transmits a bonus start command (step S176), and ends the bonus operation check processing. The bonus start command includes information indicating the type of bonus to be started.

  When determining that the display combination is not BB in the processing of step S171, the main CPU 31 then determines whether the display combination is SB (step S174). At this time, when the main CPU 31 determines that the display combination is not SB, the process proceeds to step S177. On the other hand, when determining that the display combination is SB, the main CPU 31 executes bonus operation time processing (step S175). In this bonus operation time process, the SB game state flag is turned on with reference to the bonus operation time table (FIG. 24). Next, the main CPU 31 transmits a bonus start command (step S176) and ends the bonus operation check process.

  When determining that the display combination is not SB in the process of step S174, the main CPU 31 then determines whether the display combination is replay (step S177). At this time, when it is determined that the display combination is not replay, the main CPU 31 ends the bonus operation check process. On the other hand, when the main CPU 31 determines that the display combination is replay, the main CPU 31 copies the value of the insertion number counter to the automatic insertion number counter (step S178), and ends the bonus operation check process. When the value is set in the automatic insertion number counter, in the process of step S3 in the next game, the number of medals corresponding to the value is automatically inserted (the medals of the player are not reduced).

  Next, the communication data storage processing will be described with reference to FIG. Note that FIG. 43 is a diagram showing a flowchart of communication data storage processing performed by the main control circuit 60 of the present embodiment. Further, the illustrated P1 to P5 data indicate parameters of each command.

  The main CPU 31 stores the transmission command in the 0th byte of the communication temporary storage area (step S1291). The main CPU 31 stores the P1 data in the first byte of the communication temporary storage area assigned to the main RAM 33 (step S1292). The main CPU 31 stores the P2 data in the second byte of the communication temporary storage area (step S1293). The main CPU 31 stores the P3 data in the third byte of the communication temporary storage area (step S1294). The main CPU 31 stores the P4 data in the fourth byte of the communication temporary storage area (step S1295). The main CPU 31 stores the P5 data in the fifth byte of the communication temporary storage area (step S1296). The main CPU 31 stores the game state flag in the sixth byte of the communication temporary storage area (step S1297).

  Then, the main sum value calculating means 31b of the main CPU 31 calculates the data of the 0th byte to the 6th byte of the communication temporary storage area by exclusive OR to create BCC data which is the main sum value (step S1299). ).

  The main CPU 31 stores the BCC data in the seventh byte of the communication temporary storage area (step S1300).

  Next, the main CPU 31 obtains the storage destination address of the communication data storage area from the communication data storage setting information (step S1301). Here, the main CPU 31 determines whether or not there is a free space in the communication data storage area (step S1302). When the main CPU 31 determines that there is no free space in the communication data storage area, the communication data storage processing ends.

  When the main CPU 31 determines that the communication data storage area has a space, the data stored in the communication temporary storage area is stored in the communication data storage area (step S1303). Further, the main CPU 31 updates the communication data storage setting information (step S1304) and ends the communication data storage processing.

  Next, with reference to FIG. 44, an interrupt process under the control of the main CPU 31 will be described. Note that FIG. 44 is a diagram showing a flowchart of the interrupt processing under the control of the main CPU 31 performed by the main control circuit 60 of the present embodiment. Further, the interrupt process under the control of the main CPU 31 is an interrupt process that occurs every predetermined period (1.1173 milliseconds in this embodiment).

  First, the main CPU 31 interrupts the program being executed before calling the interrupt processing under the control of the main CPU 31, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the main RAM 33. (Step S181). This is because when the interrupt processing under the control of the main CPU 31 is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the interrupted time. Is.

  Next, the main CPU 31 performs an input port check process (step S182). Specifically, the main CPU 31 checks the signal from each switch such as the maximum BET switch 13S.

  Next, the main CPU 31 performs reel control processing (step S183). Specifically, the main CPU 31 starts the rotation of the reels 3L, 3C, 3R when there is a reel rotation start request in the reset interrupt process (see FIG. 34), and rotates the reels at a constant speed. Take control. Further, when the scheduled stop position is determined by the number of sliding symbols being determined in the reel stop control process (see FIG. 38), the main CPU 31 indicates that the value of the symbol counter of the corresponding reel indicates the scheduled stop position. When the value is the same as the value, control is performed to stop the reel. For example, when the value indicating the planned stop position is “4”, the main CPU 31 performs control for stopping the corresponding reel when the value of the symbol counter becomes “4”.

  Next, the main CPU 31 performs a communication data transmission process described later (step S184). Further, the main CPU 31 performs a lamp drive control process (step S185). Next, the main CPU 31 refers to the value saved in the main RAM 33 in the process of step S181 and restores the register (step S186). When this process ends, the interrupt process under the control of the main CPU is ended, and the program interrupted due to the occurrence of the interrupt process under the control of the main CPU is continuously executed.

  Next, the communication data transmission process will be described with reference to FIG. Note that FIG. 45 is a diagram showing a flowchart of communication data transmission processing performed by the main control circuit 60 of the present embodiment. This communication data transmission process is mainly executed as a command transmission unit of the main CPU 31.

  First, the main CPU 31 sets the address of the current communication data storage area based on the communication data storage setting information (step S1341). Then, the main CPU 31 determines whether or not the communication data (transmission data) to be transmitted to the sub control circuit 70 is stored in the set address of the communication data storage area (step S1342).

  When the main CPU 31 determines that the transmission data is not stored at the address set in the communication data storage area, it sets a no-operation command (step S1343) and performs the communication data storage processing described above (step S1344). .

  After completion of the communication data storage processing here, or when the main CPU 31 determines that the transmission data is stored at the address set in the communication data storage area, the main CPU 31 transmits the data of the main control circuit 60. It is determined whether there is an available port (step S1345). When the main CPU 31 determines that the transmission port of the main control circuit 60 is empty, it ends the communication data transmission process.

  When the main CPU 31 determines that the transmission port of the main control circuit 60 has a free space, it sets the number of data for one packet (8 in this embodiment) (step S1346). Then, the main CPU 31 sets the head number of the packet transmission data setting output port (step S1347). Further, the main CPU 31 sets the data in the communication data storage area in the output port (step S1348).

  The main CPU 31 updates the address of the communication data storage area by adding 1 (step S1349). Next, the main CPU 31 updates the output port number by adding 1 (step S1350). Further, the main CPU 31 subtracts 1 from the data number counter (step S1351).

  Next, the main CPU 31 determines whether or not the data number counter is 0 (step S1352). When the main CPU 31 determines that the data number counter is not 0, it determines that the communication data storage area still has data that has not been set in the output port, and again outputs the data in the communication data storage area to the output port. (Step 1348).

  When the main CPU 31 determines that the data number counter is 0, it determines that one packet of data is stored in the output port, and sets a transmission start request in the communication register port (step S1353). As a result, one packet of data is transmitted.

  Then, the main CPU 31 sets the transmitted data in the communication data storage area (step S1354). Further, the main CPU 31 updates the communication data storage setting information, sets the address of the next communication data storage area (step S1355), and ends the communication data transmission process.

  Next, the non-operation command set process (step S1343) in the communication data transmission process of FIG. 45 will be described with reference to FIG. FIG. 46 is a diagram showing a flowchart of the no-operation command set process performed by the main control circuit 60 of the present embodiment.

  The no-operation command set process targets an input from the I / O port 38 of the main control circuit 60. First, the main CPU 31 sets a no-operation command as a communication parameter (step S401), and then sets input port data relating to port input information input via the I / O port 38 as a communication parameter (step S402). ). The input port data to be set is input to the I / O port 38 from the stop switch 7S, the start switch 6S, the medal sensor 22S, the reset switch 23S, the maximum BET switch 13S, the C / P switch 14S, the setting key switch 20S and the like. The data. After step S402, the main CPU 31 ends the no-operation command setting process.

[Game machine management system]
Next, an error information history transmission system using the gaming machine 1 of the present embodiment will be described with reference to FIG. The error information history transmission system is a system that stores various errors that have occurred in the gaming machine 1 as error information, transmits a history of error information to a remote server by using a mobile terminal, and analyzes the cause of the error. .

  As shown in FIG. 47, the error information history transmission system includes a gaming machine 1, a mobile communication terminal with a camera (hereinafter, referred to as “mobile terminal”) 400 as a mobile terminal carried by an attendant, and a data management server as a server. 500 and an analyzing PC 600 as an analyzing unit. Note that, in the example of FIG. 47, one mobile terminal 400 is shown for convenience of description, but in reality, a large number of mobile terminals 400 can access the data management server 500.

  The data management server 500 manages not only error information but also information about game records. The mobile terminal 400 and the data management server 500 can exchange data with each other via the network NW, for example, using TCP / IP as a communication protocol. The network NW is constructed by, for example, the Internet, a dedicated communication line (for example, CATV (Community Antenna Television) line), a mobile communication network (including a base station), a gateway, and the like. The gaming machine 1 is not connected to the network NW.

  Note that the mobile terminal 400, the data management server 500, and the analysis PC 600 each include a control unit, a storage unit, a display unit, a communication unit, etc., although they are not shown. In addition, the data management server 500 and the analysis PC 600 are preferably installed in an area 700 separated from the installation location of the gaming machine 1, such as a maker of the gaming machine 1 or a system management company.

  The sub CPU 71 of the gaming machine 1 displays the two-dimensional code 300 in the liquid crystal display area 23 so that the clerk (the mobile terminal 400) can access the data management server 500 when the service is provided by the error information history transmission system. Specifically, as shown in FIG. 49, a staff member displays the error information history in the liquid crystal display area 23, and selects a predetermined item such as a COM error alarm (COM ERR ALM) 23b which is a communication error alarm, for example. Thus, the two-dimensional code 300 is displayed.

  The control unit of the mobile terminal 400 reads the displayed two-dimensional code 300 with the camera 401 of the mobile terminal 400, analyzes the two-dimensional code 300 with the dedicated software of the mobile terminal 400, and analyzes the domain in the code and the communication error log, Information is acquired, the data management server 500 is accessed according to the domain included in the two-dimensional code 300, and the information included in the two-dimensional code 300 is transmitted as output transmission data.

  On the other hand, the control unit of the data management server 500 stores the communication error information included in the received transmission data in the storage unit.

  Further, the control unit of the data management server 500 stores the communication error information included in the output transmission data in an error information database DB (database) not shown and transmits the communication error information to the analysis PC 600. In addition, the control unit of the data management server 500 generates display data (for example, a Web page) that allows the mobile terminal 400 to display the error content indicated by the received communication error information, etc. And reply (indicated by the dashed-dotted line in the figure). Then, the control unit of the mobile terminal 400 causes the display unit to display the screen 402 indicating the error content and the like based on the received display data. The clerk can confirm the error content and the like from the screen 402.

  Further, the analysis PC 600 that receives the communication error information analyzes the cause of the communication error based on the communication error information and various information accumulated in the error information database DB. The cause of the communication error analyzed by the analyzing PC 600 is the improvement of the program or structure of the gaming machine 1 or the installation of the gaming machine 1 at the manufacturer of the gaming machine 1 in which the analyzing PC 600 is installed, a system management company, or the like. It will be used as appropriate, such as improving management in the designated halls.

  Next, the gaming machine 1 when the staff member uses the error information history transmission service will be described. The sub CPU 71 of the gaming machine 1 employs two types of operation methods, that is, a normal operation by a staff member and a simple operation in order to display the error information history shown in FIG. 49 on the liquid crystal display device 5. When performing a normal operation, the clerk rotates the door key 2 to the right to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and the liquid crystal display area 23 is displayed. The menu screen shown in FIG. 48 is displayed.

  Then, the staff member operates the operation key to select the "error information history" item 23a, whereby the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23. On the other hand, when performing a simple operation, the clerk rotates the door key 2 counterclockwise at the time of error occurrence or non-game and holds the state for a certain period of time, for example, 5 seconds or more. As a result, the error information history screen shown in FIG. 49 is displayed in the liquid crystal display area 23.

  When the sub CPU 71 detects an operation of selecting the "error information history" item 23a by the staff using the selection button 24 and the enter button 25, the sub CPU 71 displays the error information history in the liquid crystal display area 23 as shown in FIG. . Further, when the sub CPU 71 detects an operation for the staff to select the “COM error alarm” item 23b using the selection button 24 and the enter button 25, the sub CPU 71 generates transmission information based on the error information history, and FIG. As shown, the two-dimensional code 300 based on the transmission information is displayed on the right side of the "COM error alarm" item 23b.

  Further, the sub CPU 71 does not display the COM error alarm at the time when the communication error occurs once, and only when the communication error occurs again within 30 minutes after the first communication error occurs, the COM error alarm is generated. Is displayed. Therefore, the sub CPU 71 has a COM error timer for measuring the interval at which a communication error occurs. The COM error timer measures based on the timing of the built-in RTC 70a or the timing provided by the function provided by the OS.

  Further, in this embodiment, the sub CPU 71 creates the two-dimensional code 300 only when a communication error occurs. For this reason, if a communication error occurs accidentally during a normal game, for example, the data put as error information on the two-dimensional code 300 is transmitted during normal processing as shown in FIG. 52 (a). An error occurs, and normal processing is executed immediately after that. Here, the numerical values in FIG. 52 indicate the number of characters of data, 1-character data indicates a command type, and 2-character data indicates a parameter for the immediately preceding command.

  In addition, when the communication error is caused by the goto act and the setting is changed in the gaming machine 1, the data put on the two-dimensional code 300 as the error information is the communication error as shown in FIG. 52 (b). The setting will be changed immediately after the occurrence. Furthermore, when a communication error occurs and continuous transmission is performed by operating the lever, the data included as error information in the two-dimensional code 300 is in the command type immediately after the communication error occurs, as shown in FIG. 52 (c). A certain lever operation and a winning combination that is a parameter are continuous.

  In FIG. 53, when the data destruction detection means 71c detects that the data in the sub RAM 73-1 of the sub control circuit 70 has been destroyed, the sub control circuit 70 causes the liquid crystal display area 23 of the gaming machine 1 to be almost entirely covered. , An example of notifying that the game cannot be continued because a RAM abnormality occurs in the RAM data is shown.

  For example, when a part or all of the data received from the main control circuit 60, the effect data information, the game state information, the internal winning combination information, the display combination information, the various counters, and the information about the information such as the various flags are erased, In the portion excluding the symbol display areas 4L, 4C, and 4R of the liquid crystal display area 23 of the gaming machine 1, a message "RAM data error, the game cannot continue. Please change the setting." By making such notification, it can be expected to suppress goto actions.

  Further, in FIG. 54, when a communication error occurs between the main control circuit 60 and the sub control circuit 70, the sub control circuit 70 causes a communication abnormality on almost the entire liquid crystal display area 23 of the gaming machine 1. Therefore, an example of notifying that the game cannot be continued is shown.

  For example, when the communication error detecting means 71a of the sub control circuit 70 detects a COM error, when the procedure detecting means 71b detects a procedure error, or when the communication disconnection detecting means 71h causes the main control circuit 60 to change to the sub control circuit 70. When it is detected that the communication to the is cut off, the notification of the occurrence of the communication abnormality is performed. As a result, it can be expected that the goto action is suppressed as in the case where the data in the sub RAM 73-1 of the sub control circuit 70 is destroyed.

[Sub CPU]
Next, the power-on process (power interruption determination processing unit) of the sub CPU 71 will be described with reference to FIG. FIG. 55 is a flowchart of the power-on process of the sub CPU 71.

  The power-on process of the sub CPU 71 is an initialization process in the OS. When the power of the sub CPU 71 is turned on, the sub CPU initialization process is performed to initialize the CPU and internal devices and peripheral ICs. It is executed (step S910).

  Next, the sub CPU 71 executes a mother task activation request process described later based on FIG. 57 for various task activation requests (step S911). Then, the sub CPU 71 executes the sub RAM management process (step S912) to confirm that the backup data in the backup RAM 73-2 is normal.

  Next, the sub CPU 71 reads the power interruption determination flags written in predetermined areas of the backup data 1 area 73a-2 and the backup data 2 area 73c-2 of the backup RAM 73-2, and the power interruption determination flag is set to 1 It is determined whether or not (step S913).

  When the sub CPU 71 determines in step S913 that the power failure determination flag is 1, it determines that an abnormal power failure has occurred before the first operation of the start lever 6 after the power is turned on, and the error information registration means. By 71d, the error code (WDR PRE) indicating the power failure is registered in the error information history storage area 73d-1 of the sub RAM 73-1 (step S914).

  On the other hand, when determining in step S913 that the power failure determination flag is not 1, the sub CPU 71 determines whether the power failure determination flag is 2 (step S915).

  When it is determined in step S915 that the power failure determination flag is 2, the sub CPU 71 determines that abnormal power failure has occurred after the operation of the start lever 6, and the error information registration unit 71d determines that power failure has occurred. The error code (WDR POST) shown is registered in the error information history storage area 73d-1 of the sub RAM 73-1 (step S916).

  The sub CPU 71 registers the error code (WDR PRE) indicating the power failure abnormality (step S914), then determines in step S915 that the power failure determination flag is not 2, or the error code indicating the power failure abnormality. After (WDR POST) is registered (step S916), the power interruption determination flag is set to 1 (step S917), and the power-on process of the sub CPU is terminated.

  Further, a power failure detection circuit is provided in the sub control circuit 70 (not shown). When the power failure detection circuit detects a voltage drop, for example, a voltage drop to 4.5V, it outputs a power failure detection signal. The sub CPU 71 executes the power interruption interrupt process (power interruption determination processing unit) of the sub CPU shown in FIG. 56 in response to an interrupt input from the external interrupt port (NMI).

  In the power interruption interruption process of the sub CPU, the sub CPU 71 sets the power interruption determination flags written in predetermined areas of the backup data 1 area 73a-2 and the backup data 2 area 73c-2 of the backup RAM 73-2 to 0. Set (step S950). For this reason, if the power failure determination flag is 0 at the time of power activation, the power is not normally registered and no error is registered.

  Therefore, in comparison with the power interruption interruption process of the sub CPU 71 shown in FIG. 56, the power interruption process of the sub CPU 71 shown in FIG. Can be detected as Goto actions include, for example, disconnecting the output line of the power failure detection circuit or supplying power to the power failure detection circuit even if the power is turned off so that the detection signal is not output. .

  Further, in the power interruption interruption process of the sub CPU of FIG. 56, after the power interruption determination flag is set to 0 (step S950), the backup creation process shown in FIG. 76 is executed (step S951).

  Note that, unlike the main control, the sub CPU 71 does not calculate the sum value in the power interruption interruption process of the sub CPU. The calculation of the sum value by the sub CPU 71 is performed each time the valid command is received, the effect mode is changed, or the like.

  The mother task request process shown in FIG. 57 is a process of requesting the OS to activate a task required for the function of the gaming machine 1. First, the sub CPU 71 requests activation of the effect registration process (step S1001). Next, as a subtask activation request, an accessory control task activation request (step S1002), a lamp control task activation request (step S1003), a sound control task activation request (step S1004), a main board communication task activation request (step S1005), An animation task activation request (step S1006), an RTC control task activation request (step S1007), and then an error monitoring task activation request are issued.

  The error monitoring task of the sub CPU 71 will be described with reference to FIG. FIG. 58 is a flowchart of the error monitoring task of the sub CPU 71. The error monitoring task is executed by an error monitoring unit (not shown) of the sub CPU 71.

  The sub CPU 71 sets a cycle of 2 ms as the processing cycle of the error monitoring task (step S1101), and first determines whether or not COM ERR ALM is occurring (step S1102).

  When determining in step S1102 that COM ERR ALM is not occurring, the sub CPU 71 subsequently determines whether a sequence error has occurred (step S1103). The sequence error is an error due to an abnormal procedure related to communication other than the COM error.

  When the sub CPU 71 determines in step S1103 that a sequence error has occurred or in step S1102 that COM ERR ALM is occurring, it determines whether or not the door is open ( Step S1104). The door here is the front door 1b of the gaming machine 1, and the open state of the door is determined by the input state of the door opening / closing switch 29S input to the port of the sub control circuit 70.

  When determining in step S1104 that the door is open, the sub CPU 71 determines whether the reset switch 23S is on (step S1105).

  The signal of the reset switch 23S is port input data of the main control circuit 60, and is input to the sub control circuit 70 via the I / O 38 as a parameter of the non-operation command. Whether or not the received command of the sub control circuit 70 is a non-operation command is determined in a sub CPU main board communication task of FIG. 69 described later (step S818). If the command is determined to be a no-operation command in that step, the parameter of that command is registered in the work area 73c-1 (step S819).

  Next, when the sub CPU 71 determines in step S1105 that the reset switch 23S is on, it registers the cancellation of the error that is occurring (step S1106). The error released here is a communication error between the main control circuit 60 and the sub control circuit 70. This cancellation is registered in the error information history storage area 73d-1 of the sub RAM 73-1. As described above, the error being canceled is generated by inputting the door opening / closing switch 29S input to the port of the sub control circuit 70 and inputting a no-operation command input via the I / O 38 of the main control circuit 60. Since both of them are indispensable, they cannot be executed only by the command from the main control circuit 60.

  By the processing from step S1102 to step S1106 described above, the communication abnormality notification can be canceled when the door is opened and the reset switch is further turned on.

  Next, the sub CPU 71 determines whether or not there is data in the reception data registration queue (step S1107). Even if there is data in the reception data registration queue, the data is not extracted from the registration queue.

  When it is determined in step S1107 that there is no data in the reception data registration queue, the sub CPU 71 updates the communication disconnection counter by 1 (step S1108), and subsequently, when the communication disconnection counter is 15 (30 ms) or more, the communication disconnection notification is issued. It is determined whether or not has occurred (step S1109). The detection of the communication interruption is performed by the communication interruption detecting means 71h.

  When the sub CPU 71 determines in step S1109 that the communication disconnection counter is 15 (30 ms) or more and the communication disconnection notification does not occur, the sub CPU 71 registers the occurrence of the communication disconnection notification as error information (step S1110). Specifically, the error information registration means 71d registers an error code (COM DCN ALM) in the error information history storage area 73d-1 of the sub RAM 73-1.

  When the sub CPU 71 registers the error information in step S1110, or when it determines in step S1109 that "the communication interruption counter is 15 (30 ms) or more and the communication interruption notification has not occurred", the sub CPU 71 waits for a cycle of 2 ms. After performing (step S1114), the process returns to step S1102.

  On the other hand, when it is determined in step S1107 that there is data in the reception data registration queue, the sub CPU 71 subsequently determines whether a communication cutoff notification is occurring (step S1111).

  When the sub CPU 71 determines in step S1111 that the communication cutoff notification is occurring, the communication cutoff notification cancellation is registered in the error information (step S1112). Specifically, the error information registration means 71d registers the communication block notification cancellation as error information in the error information history storage area 73d-1 of the sub RAM 73-1.

  The sub CPU 71 clears the communication disconnection counter (step S1113) after performing the processing of step S1112 or when determining in step S1111 that the communication disconnection notification is not occurring (step S1114). After that, the process is returned to step S1102.

  Next, the operation of the above-described error information history transmission system will be described with reference to the flowcharts shown in FIGS. First, the main board communication reception interrupt processing in the sub control circuit 70 will be described with reference to FIG. 59. FIG. 59 is a diagram showing a flowchart of the main board communication reception interrupt processing in the sub control circuit 70 of the present embodiment. The program of the main board communication reception interrupt process in the sub control circuit 70 is executed by the sub CPU 71 as an interrupt process when transmission data is transmitted from the main control circuit 60 to the sub control circuit 70.

  The sub CPU 71 acquires the reception data from the reception data register (step S800). The sub CPU 71 also acquires the reception status data from the reception status register (step S801). Further, the sub CPU 71 registers the received data and the reception status data related to the received data in each queue buffer (step S802), and ends the main board communication reception interrupt process.

  The sub CPU 71 processes the 1-byte received data by executing the main board communication reception interrupt process of steps S800 to S802 described above once. In the present embodiment, one command consists of 8 bytes of data. Therefore, the sub CPU 71 completes the processing of one command by executing the serial data communication by continuously performing steps S800 to S802 eight times.

[Production registration processing]
Next, with reference to the flowchart shown in FIG. 60, the operation relating to the game of the sub control circuit 70 will be described.

  The effect registration processing performed by the sub CPU will be described with reference to FIG. 60. Note that FIG. 60 is a diagram showing a flowchart of the effect registration process of the present embodiment.

  First, the sub CPU 71 sets a cycle of 4 ms for effect registration processing (step S310). Next, the sub CPU 71 takes out the message from the message queue (step S311). Next, the sub CPU 71 determines whether or not there is a message in the message queue (step S312). At this time, when the sub CPU 71 determines that there is no message in the message queue, the sub CPU 71 proceeds to the process of step S317.

  On the other hand, when it is determined in step S312 that there is a message in the message queue, the sub CPU 71 determines whether or not a communication cutoff notification is being generated (step S313). The communication cutoff notification is performed when the communication cutoff detecting means 71h of the sub CPU 71 detects that the communication from the main control circuit 60 to the sub control circuit 70 is cut off. In the notification state, as shown in FIG. A communication error is displayed on almost the entire liquid crystal display area 23, and no presentation is performed.

  When the sub CPU 71 determines in step S313 that the communication cutoff notification is not occurring, it copies the game information from the message (step S314), and then performs effect content determination processing (step S315). In the effect content determination processing, as will be described in detail with reference to FIG. 61, the effect content according to various commands transmitted from the main CPU 31 is determined and is specified by the received command, for example, according to the game state or the operation state. Performance data is registered in the sub RAM 73-1.

  Subsequently, the sub CPU 71 performs a backup creation process of creating backup data from the sub RAM 73-1 to the SRAM 73-2 (step S316).

  Next, when the sub CPU 71 determines in step S312 that there is no message in the message queue, determines in step S313 that a communication cutoff notification is occurring, or executes the backup creation process in step S316, The animation data is registered (step S317). Specifically, the sub CPU 71 registers animation data based on the effect data registered in the effect content determination process. As a result, an image is displayed on the liquid crystal display device 5. That is, the sub CPU 71 transmits an image display command to the GPU 74 based on the effect data determined in the effect content determination process.

  The GPU 74 selects appropriate image data from the image data expanded in the VRAM 75 based on the received image display command, determines the display position and size of the image data, and stores the image data in the VRAM 75. Stored in one of the stored frame buffers.

  The GPU 74 performs a bank switching process for switching the display image data area and the write image data area in the frame buffer area at predetermined intervals (1/30 seconds). In the bank switching process, the GPU 74 outputs the image data written in the write image data area to the liquid crystal display device 5, replaces the display image data area with the write image data area, and displays the image data to be displayed next. Write.

  Next, the sub CPU 71 registers sound data (step S318). Specifically, the sub CPU 71 registers sound data based on the effect data registered in the effect content determination process. As a result, sound is output from the speakers 21L and 21R.

  Next, the sub CPU 71 registers LED data (step S319). Specifically, the sub CPU 71 registers the LED data based on the effect data registered in the effect content determination process. As a result, the various operation panels 101 to 103 and the display panel unit 110 are turned on or off. When this processing ends, the sub CPU 71 waits for a cycle of 4 ms (step S320) and returns to the processing of step S311.

  Next, with reference to FIG. 61, the effect content determination process in the flowchart of the effect registration process performed by the sub CPU shown in FIG. 60 will be described. Note that FIG. 61 is a diagram showing a flowchart of the effect contents determination process.

  First, the sub CPU 71 determines whether or not a start command has been received (step S350). When the sub CPU 71 determines that the start command is received, the sub CPU 71 acquires the determination internal winning combination from the storage area in which the reception data of the sub CPU 71 is stored and the symbol combination table for fraud determination, and the work of the sub RAM 73-1. The data is stored in the area 73c-1 (step S351).

  Next, the sub CPU 71 performs a start command reception process (step S352), and performs various processes such as determination and execution of effect data. Subsequently, the sub CPU 71 registers the effect data for start (step S353), and then determines the backup data 1 area 73a-2 of the backup RAM 73-2 and the backup in order to determine the power failure abnormality after the game starts. 2 is set as a power failure determination flag in a predetermined area of the data 2 area 73c-2 (step S354), and the effect content determination processing is ended.

  When determining in the process of step S350 that the start command has not been received, the sub CPU 71 then determines whether a reel stop command has been received (step S355).

  In the process of step S355, when the sub CPU 71 determines that the reel stop command is received, the sub CPU 71 performs the process at the time of receiving the reel stop command (step S356), and outputs the effect data at the time of stop according to the type of the operation stop button and the like. The registration is performed (step S357), subsequently the reel stop command reception injustice determination process shown in FIG. 63 is executed (step S358), and the effect content determination process is ended.

  When determining in the process of step S355 that the reel stop command has not been received, the sub CPU 71 then determines whether or not a display command has been received (step S359). When the sub CPU 71 determines that the display command has been received, the sub CPU 71 performs the display command reception process (step S360), and subsequently, the sub CPU 71 executes the display command reception injustice determination process (step S361) to produce an effect. The content determination process ends.

  When determining in the process of step S359 that the sub-command has not been received, the sub CPU 71 then determines whether or not a BET command has been received (step S362). At this time, when the sub CPU 71 determines that the BET command is received, the sub CPU 71 registers the effect data at the time of BET according to the number of inserted coins and the like (step S363), and ends the effect content determination process.

  When determining in the process of step S362 that the BET command has not been received, the sub CPU 71 determines whether or not a payout command has been received (step S364). At this time, when the sub CPU 71 determines that the payout command is received, the sub CPU 71 executes the payout command reception injustice determination process shown in FIG. 65 (step S365), and ends the effect content determination process.

  When determining in the process of step S364 that the payout command has not been received, the sub CPU 71 then determines whether or not a bonus start command has been received (step S366). When determining that the bonus start command has been received, the sub CPU 71 registers the bonus start effect data (step S367), and ends the effect content determination process.

  When determining in the process of step S366 that the bonus start command has not been received, the sub CPU 71 then determines whether or not a bonus end command has been received (step S368). At this time, if the sub CPU 71 determines that the bonus end command has not been received, the sub CPU 71 ends the effect content determination process. On the other hand, when the sub CPU 71 determines that the bonus end command is received, the sub CPU 71 performs a bonus end command reception process (step S369), registers bonus end effect data (step S370), and effects content determination process. finish.

  Next, the fraud determination process at the time of receiving the reel stop command of the sub CPU 71 will be described with reference to FIG. 63. FIG. 63 is a flow chart of fraud determination processing upon receipt of a reel stop command by the sub CPU 71.

  First, the sub CPU 71 acquires the stop reel number from the stop reel type included in the reception data of the reel stop command from the main CPU 31, and also acquires the stop position of the reel from the stop start position and the number of sliding frames. Then, further, the symbol data is acquired from the symbol arrangement table for sub CPU fraud determination shown in FIG. 67, which is stored in the various program table areas 72e of the sub ROM 72 (step S411).

  Next, the sub CPU 71 determines whether it is during the third stop, that is, when all reels are stopped (step S412), and when it is not the third stop, returns the process to the effect content determination process. On the other hand, when the sub CPU 71 determines in step S412 that the time is the third stop time, the sub winning combination for determination is selected from the symbol combination table for sub CPU fraud determination shown in FIG. 68 stored in the various program table areas 72e of the sub ROM 72. The winning combination (winning number) is acquired (step S413).

  Subsequently, the sub CPU 71 determines whether or not there is a winning combination for determination (step S414). If there is no winning combination for determination, that is, if the winning combination is missing or missed, fraud does not occur, and the reel is stopped. When the command is received, the fraud determination process ends.

  When determining in step S414 that there is a determination winning combination, the sub CPU 71 subsequently determines whether the determination internal winning combination and the determination winning combination match (step S415), and the determination internal winning combination. If it is determined that the winning combination does not match the determination winning combination, the fraud-occurrence process shown in FIG. 66 described later is executed (step S416).

  When it is determined in step S415 that the determination internal winning combination and the determination winning combination are the same, the sub CPU 71 ends the reel stop command reception injustice determination process because no injustice has occurred.

  Next, with reference to FIG. 64, the display command reception fraud determination process of the sub CPU 71 will be described. FIG. 64 is a flowchart of the fraud determination process at the time of receiving the display command by the sub CPU 71.

  First, the sub CPU 71, the display combination information (display combination storage area of the main RAM 33) included in the received data from the main CPU 31 and the symbol combination of the symbol combination table for the sub CPU fraud determination stored in the sub ROM 72, The determination display combination (winning number) is acquired from (step S421).

  Next, the sub CPU 71 collates the symbol data (symbol data only for the center) saved by the third stop of the reel (at the time of all stop) with the symbol combination in the sub CPU fraud determination symbol combination table, The winning combination for determination (winning number) is acquired (step S422).

  Next, the sub CPU 71 determines whether or not there is a determination display combination (step S423). When it is determined that there is no determination display combination, the sub CPU 71 is missing or missed, and no fraud has occurred. When the command is received, the fraud determination process ends.

  When determining in step S423 that there is a display combination for determination, the sub CPU 71 determines whether the internal winning combination for determination acquired and stored in step S352 matches the display combination for determination acquired in step S421. Yes (step S424).

  When determining in step S424 that the internal winning combination for determination and the display combination for determination match, the sub CPU 71 subsequently matches the winning combination for determination acquired in step S422 with the display combination for determination acquired in step S421. It is determined whether or not to do it (step S425).

  When it is determined in step S425 that the winning combination for determination matches the display combination for determination, the sub CPU 71 determines that no injustice has occurred, and thus ends the injustice determination process when receiving the display command.

  On the other hand, when the sub CPU 71 determines in step S424 that the determination internal winning combination and the determination display combination do not match, or determines in step S425 that the determination winning combination and the determination display combination do not match. The injustice occurrence process shown in FIG. 66 described later is executed (step S426), and the injustice determination process at the time of receiving the display command ends.

  Next, the payout command reception fraud determination process of the sub CPU 71 will be described with reference to FIG. FIG. 65 is a flowchart of the payout command reception fraud determination process by the sub CPU 71.

  The sub CPU 71 first acquires the payout number from the received data from the main CPU 31 (step S431), and determines whether or not there is a payout number (step S432).

  Next, in step S432, when the payout number is 0, the sub CPU 71 determines that the injustice has not been made, and ends the payout command reception injustice determination process.

  When it is determined in step S432 that there is a payout number, the sub CPU 71 determines from the determination display combination (winning number) acquired in step S421 and the fraud determination symbol combination table stored in the sub ROM 72. The payout number is acquired (step S433). In the sub CPU fraud determination symbol combination table shown in FIG. 68, “2 coins inserted” and “3 coins inserted” in the payout number column are inserted coins at the time of BET, and 2 coins are inserted during BB, and others. In the case of, it will be 3 pieces.

  Subsequently, the sub CPU 71 determines whether or not the determination payout number matches the payout number of the received data from the main CPU 31 (step S434).

  When it is determined in step S434 that the determination payout number matches the payout number of the received data, the sub CPU 71 determines that no fraud has occurred, and ends the payout command reception fraud determination process. On the other hand, when the sub CPU 71 determines in step S434 that the judgment payout number does not match the payout number of the received data, it executes the fraud occurrence process shown in FIG. 66 (step S435) to receive the payout command. When the fraud determination process ends.

  Next, the fraud occurrence process of the sub CPU 71 will be described with reference to FIG. FIG. 66 is a flowchart of the fraud-occurrence process (determination process) by the sub CPU 71.

  The sub CPU 71 first clears the counters for the number of navigation games and the number of navigation sets (step S441). This clears the ART winning information. Next, the error information registration means 71d of the sub CPU 71 regards the sequence error occurrence as error information of “procedure abnormality (other)” and stores the error code (BLS) in the error information history storage area 73d-1 of the work area of the sub RAM 73-1. 123PE) is registered (step S442). Accordingly, as a serious error, as shown in FIG. 54, the fact that the game cannot be continued due to a communication error is reported on almost the entire liquid crystal display area 23, and the reset switch 23S is turned on with the front door 1b opened. The error is reset so that it cannot be reset without operation.

  67 shows a symbol arrangement table for sub CPU fraud determination, and FIG. 68 shows a symbol combination table for sub CPU fraud determination. These tables are tables created for the sub CPU 71 on the basis of the symbol arrangement table shown in FIG. 3 and the symbol combination table shown in FIG. 23, which are stored in the main ROM 32 of the main control circuit 60, respectively. It is stored in various program table areas 72e of the ROM 72.

[Main board communication processing]
Next, the main board communication processing of the sub CPU 71 will be described with reference to FIG. 69. FIG. 69 is a diagram showing a flowchart of the main board communication processing of the sub CPU 71 of the present embodiment.

  In response to the scheduling function of the OS, the sub CPU 71 sets a cycle so that the main board communication processing program of the sub CPU 71 is executed at a cycle of 2 ms (step S808). As a result, this task is repeated at a cycle of 2 ms including the processing time. Therefore, the sub CPU 71 waits for a cycle of 2 ms (step S809) and waits for the remaining time of 2 ms when the flowchart is repeated.

  The cycle of this task processing is not limited to 2 ms, and may be executed in the range of 2 ms to 4 ms. Further, the main board communication processing program of the sub CPU 71 is not limited to the program executed at every predetermined time, and when the predetermined condition is satisfied irrespective of the time interval without setting the cycle and waiting for the cycle. It may be executed.

  Next, the sub CPU 71 acquires the reception data from the queue in which the reception data is registered in step S802 (step S810). The sub CPU 71 determines whether or not there is received data in the queue (step S811). When the sub CPU 71 determines that there is no received data in the queue, the sub CPU 71 acquires the received data from the queue again (step S810).

  When the sub CPU 71 determines that there is received data in the queue, it determines whether or not a physical layer error has occurred in the received data (step S812). If the sub CPU 71 determines that no physical layer error has occurred in the received data, it checks the numerical range of the received command and acquires it (step S813). In the present embodiment, the numerical range of the received command is 01H to 10H, as shown in FIG. Then, the sub CPU 71 determines whether the numerical value of the received command is within the proper range (step S814).

  When the sub CPU 71 determines that the numerical value of the command is within the proper range, the BCC check process is performed on the received data (step S815). Here, since one command is composed of 8-byte data, the sub CPU 71 sequentially XORs the data of the first byte to the seventh byte of each command, and presets the result as a correct result. The check processing is performed by comparing with the data of the 8th byte.

  Then, the sub CPU 71 determines whether or not the result of the BCC check process is normal (step S816). When the sub CPU 71 determines that the result of the BCC check processing is normal, the type of command is extracted (step S817).

  Next, the sub CPU 71 determines whether or not the extracted command is a no-operation command (step S818). When the sub CPU 71 determines that the extracted command is a non-operation command, it saves the main board input port data in the work area 73c-1.

  The main board input port data is data included in the parameter data of the no-operation command, and is data sent to the sub control circuit 70 via the I / O port 38 of the main control circuit 60.

  After storing the main board input port data (step S819), the sub CPU 71 returns to the process of waiting for a cycle of 2 ms (step S809), and acquires the data from the reception data registration queue again (step S810).

  On the other hand, when the sub CPU 71 determines in step S818 that the extracted command is not the non-operation command, it executes the reception data log saving process described later (step S820). Further, the sub CPU 71 executes a main board reception command check process described later (step S821).

  Then, the sub CPU 71 determines whether or not the command received this time is different from the command received last time (immediately before) (step S822). When the sub CPU 71 determines that the command received this time is not different from the command received immediately before, that is, the command is the same, the sub CPU 71 waits for a period of 2 ms (step S809) and acquires the received data from the queue again (step S809). S810).

  When the sub CPU 71 determines in step S822 that the command received this time is different from the command received immediately before, the sub CPU 71 registers the command received this time in the message queue (step S823). Then, the sub CPU 71 performs a sum check on the sub control game data sum value area 73b-1 (step S824).

  Further, the sub CPU 71 determines whether or not the game data is normal as a result of the sum check (step S825). When determining that the game data is normal, the sub CPU 71 waits for a cycle of 2 ms (step S809), and acquires the received data from the queue again (step S810).

  When the sub CPU 71 determines in step S825 that the game data is abnormal, the error information registration unit 71d registers the occurrence of the data destruction error in the error information history storage area 73d-1 (step S826). Then, the sub CPU 71 waits for a cycle of 2 ms (step S809) and acquires the reception data from the queue again (step S810).

  Further, when the sub CPU 71 determines in step S812 that a physical layer error has occurred in the received data, or in step S814 that the command is not within the proper range, or in step S816, the result of the BCC check process is normal. If it is determined that it is not, it is determined that a communication error has occurred, and the COM error check processing described later is executed (step S827). Then, the sub CPU 71 waits for a cycle of 2 ms (step S809) and acquires the reception data from the queue again (step S810).

  Next, the main board communication reception data log storage processing will be described with reference to FIG. 70. FIG. 70 is a diagram showing a flowchart of the main board communication reception data log storage processing performed by the sub control circuit 70 of the present embodiment. This main board communication reception data log storage processing is mainly executed by the reception data log storage means 71e of the sub CPU 71.

  When the main board communication reception data log storage processing is executed, the sub CPU 71 executes main board communication reception data log temporary area storage processing described later (step S830). The main board communication reception data log temporary area storage processing uses the communication log collection ring buffer area 73e-1 shown in FIG. 13, and is processing for storing all communication logs regardless of whether or not an error has occurred. ing.

  Subsequently, the sub CPU 71 executes a main board communication error history data storage process described later (step S831). The main board communication error history data saving process uses the communication error saving buffer area shown in FIG. 14 and is a process for saving a related communication log when a communication error occurs. After that, the sub CPU 71 ends the main board communication reception data log storage processing.

  Next, the main board communication reception data log temporary area storage processing of step S830 will be described with reference to FIG. 71. FIG. 71 is a diagram showing a flowchart of the main board communication reception data log temporary area saving process performed by the sub control circuit 70 of the present embodiment.

  When the main board communication reception data log temporary area saving process is executed, the sub CPU 71 acquires the communication log data buffer index of the communication log collecting ring buffer area 73e-1 (step S840). The number of buffers here is set appropriately.

  Then, the sub CPU 71 calculates the communication log data buffer storage position of the communication log collection ring buffer area 73e-1 (step S841). Here, the sub CPU 71 calculates the storage position in the communication log collection ring buffer area 73e-1 from the value of the buffer index.

  Further, the sub CPU 71 stores the received data in the communication log collection ring buffer area 73e-1 (step S842). In the present embodiment, as shown in FIG. 13, a maximum of 256 sets of numerical values in which a command and a parameter corresponding to each command are consecutive are stored. Then, the sub CPU 71 updates the communication log data buffer index (step S843). Here, the sub CPU 71 adds 1 to the buffer index that stores the received data.

  Then, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S844). When the sub CPU 71 determines that the value of the buffer index is the upper limit value, the sub CPU 71 returns the communication log data buffer index to the beginning (step S845) and causes this buffer to function as a ring buffer. After that, the sub CPU 71 ends the main board communication reception data log temporary area storage processing. If the sub CPU 71 determines that the value of the buffer index is not the upper limit value, the sub CPU 71 ends the main board communication reception data log temporary area saving process as it is.

  Next, the main board communication error history data storage processing in step S831 will be described with reference to FIG. Note that FIG. 72 is a diagram showing a flowchart of the main board communication error history data storage processing performed by the sub control circuit 70 of the present embodiment.

  When the main board communication error history data saving process is executed, the sub CPU 71 acquires the save buffer selection index of the communication error save buffer area 73f-1 (step S850). Then, the sub CPU 71 selects a communication error save buffer based on the save buffer selection index (step S851).

  Here, the sub CPU 71 determines whether or not a communication error (COM error) has occurred (step S852). When the sub CPU 71 determines that a COM error has occurred, the reception data log saving means 71e saves the communication log related to the communication error in the communication error saving buffer area 73f-1 selected in step S851 (step). S853). Then, the sub CPU 71 updates the selected buffer index (step S854). After that, the sub CPU 71 ends the main board communication error history data storage processing.

  If the sub CPU 71 determines in step S852 that no COM error has occurred, the sub CPU 71 acquires the selected buffer index (step S855). Then, the sub CPU 71 determines whether or not the reception data is being collected (step S856). When the sub CPU 71 determines that the received data is not being collected, the sub CPU 71 ends the main board communication error history data storage processing.

  When determining in step S856 that the reception data is being collected, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S857). In the present embodiment, the value of the buffer index is 0 to 255, and the upper limit value is 255. When the sub CPU 71 determines that the value of the buffer index is not the upper limit value, it stores the received data in the communication error storage buffer selected in step S851 (step S858). Then, the sub CPU 71 updates the selected buffer index (step S859). After that, the sub CPU 71 ends the main board communication error history data storage processing.

  When the sub CPU 71 determines in step S857 that the value of the buffer index is the upper limit value, the sub CPU 71 acquires the save buffer selection index (step S860). Then, the sub CPU 71 determines whether or not the value of the save buffer selection index is the upper limit value (step S861). In this embodiment, the upper limit value of the save buffer selection index is 1024.

  When determining in step S861 that the value of the save buffer selection index is not the upper limit value, the sub CPU 71 updates the save buffer selection index (step S862). Here, the sub CPU 71 adds one to the save buffer selection index. After that, the sub CPU 71 ends the main board communication error history data storage processing. When the sub CPU 71 determines that the value of the buffer selection index is the upper limit value, the sub CPU 71 ends the main board communication error history data storage processing.

  Next, the main board reception command check processing in step S821 will be described with reference to FIG. Note that FIG. 73 is a diagram showing a flowchart of the main board reception command check processing performed by the sub control circuit 70 of the present embodiment.

  When the main board reception command check processing is executed, the sub CPU 71 acquires reception data (step S870). Then, the sub CPU 71 sets the received command check table (step S871). Further, the sub CPU 71 acquires the previous (immediately before) received data (step S872).

  Then, the sub CPU 71 sets a command check counter (step S873). Further, the sub CPU 71 acquires confirmation data from the reception protocol confirmation data table (step S874). That is, here, the table of the received command and the previously received command shown in FIG. 51 is acquired.

  Next, the sub CPU 71 checks the table of the received command and the previously received command acquired in step S874 to determine whether the received commands are in the normal order (step S875). For example, when the received command shown in 03H of Data is “BET”, if the previous received command is demo display, BET, payout end, bonus start or error, it is determined that the procedure is in a normal order.

  When the sub CPU 71 determines in step S875 that the received commands are in the normal order, the sub CPU 71 ends the received command check process.

  When the sub CPU 71 determines in step S875 that the received commands are not in the normal order, for example, when the received command shown in 07H of Data in the table shown in FIG. 51 is “display”, the previous received command is In the case of the second stop instead of the all-time trunk stop state, it is determined that the procedure is not performed in a normal game, and the received command check table is updated (step S876). Then, the sub CPU 71 subtracts the command check counter (step S877).

  Subsequent to step S877, the sub CPU 71 determines whether or not the command check is completed (step S878). Here, the sub CPU 71 is configured to determine that the command check has ended because the command check counter has become equal to or less than a threshold value such as 0, for example.

  When the sub CPU 71 determines in step S878 that the command check is not completed, the sub CPU 71 again acquires confirmation data from the reception protocol confirmation data table (step S874).

  When the sub CPU 71 determines in step S878 that the command check is completed, the error information registration unit 71d registers the occurrence of the abnormal procedure error (sequence error) in the error information history storage area 73d (step S879). After that, the sub CPU 71 ends the received command check processing.

  Next, the COM error check processing of step S827 will be described with reference to FIG. Note that FIG. 74 is a diagram showing a flowchart of the COM error check processing performed by the sub control circuit 70 of the present embodiment.

  When the COM error check process is executed, the sub CPU 71 executes a received data log saving process (step S880). The procedure of this reception data log storage processing is as shown in the flowchart of the main board communication reception data log storage processing shown in FIG. In this case, in step S852 of the main board communication error history data storage processing shown in FIG. 72, it is determined that a COM error has occurred, and the reception data log storage unit 71e indicates a communication error in the communication error storage buffer area 73f-1. The related communication log is saved (step S853).

  Then, the sub CPU 71 determines whether or not the COM error timer is counting (step S881). When determining that the COM error timer is counting, the sub CPU 71 determines whether the COM error timer is within 30 minutes (step S882).

  When the sub CPU 71 determines in step S882 that the COM error timer is within 30 minutes, the error information registration unit 71d registers the occurrence of the communication error (COM error) in the error information history storage area 73d-1 (step S883). Then, the sub CPU 71 sets the count stop of the COM error timer (step S884), and ends the COM error check process.

  If the sub CPU 71 determines in step S881 that the COM error timer is not counting, or in step S882 that the COM error timer is not within 30 minutes, it sets the count start of the COM error timer ( In step S885), the COM error check process ends.

  As described above, the gaming machine management system of this embodiment obtains error information from the two-dimensional code 300 received by the data management server 500, and analyzes the cause of the error based on the error information. It is equipped with a PC 600.

  Therefore, it is possible to analyze and specify the cause of the error from the error information by using the separately-installed analysis PC 600, instead of merely specifying the content of the communication error in the gaming machine 1 as in the conventional case. The cause of the obtained error can be utilized for subsequent improvement of the gaming machine 1.

  Further, in the gaming machine 1 of the present embodiment, the communication error information regarding the communication error is converted into the two-dimensional code 300 only when the occurrence of the communication error is detected by the sub CPU 71. The control can be simplified as compared with the case of creating.

  Further, in the gaming machine 1 of the present embodiment, the error information history can be displayed on the liquid crystal display device 5 by operating the door key 2, so that the clerk can read the error information history without operating the setting key of the gaming machine 1. You can check it. Therefore, the clerk can display the error information history of the gaming machine 1 even during business hours, so that the cause of the error can be more effectively identified.

  Moreover, in the gaming machine 1 of the present embodiment, the clerk rotates the door key 2 counterclockwise and holds the state for a certain period of time to display the error information history. Therefore, a staff member who holds the door key 2 can easily display the error information history, and normally, the staff member who holds the door key 2 is more than the staff member who holds the setting key, which improves convenience. be able to.

  In addition, in the gaming machine 1 of the present embodiment, when the occurrence of a communication error is detected, the sub CPU 71 uses the occurrence of a communication error, its occurrence time, and its cancellation time as error information in the sub RAM 73. -1 is sequentially stored.

  Further, the sub CPU 71 creates an error information history from the stored error information, and displays the error information history on the liquid crystal display device 5 when an information disclosure request is made by operating the door key 2.

  Therefore, it is possible to confirm the illegal release of the communication error notification in the gaming machine 1 and to confirm the generation time and the release time of the communication error notification later.

  In addition, in the gaming machine 1 of the present embodiment, the sub CPU 71 performs such a procedure when the procedure detection unit 71b detects that the game has progressed in a procedure that cannot occur in a normal game, that is, an abnormal procedure. The occurrence of such an abnormal procedure and the procedure missed in the normal procedure are sequentially stored in the sub RAM 73-1 as error information.

  Further, the sub CPU 71 creates an error information history from the stored error information, and displays the error information history on the liquid crystal display device 5 when an information disclosure request is made by operating the door key 2.

  For example, FIG. 49 shows an example of the error information history in the liquid crystal display area 23. For example, No. In the error content “BLS123PE” shown in FIG. 6, normally, after the procedure of “B” indicating the insertion of a medal or the like, the procedure of “L” and “S” indicating the rotation start of the reel by the operation of the lever, the reel 1 The game ends after the procedure of "1" indicating the stop of "1", the procedure of "2" indicating the stop of reel 2, the procedure of "3" indicating the stop of reel 3, and the procedure of "P" for payment.

  However, there, the number "1" is circled to indicate that the procedure for stopping reel 1 has been missed. Therefore, as compared to the case where an abnormal procedure occurs and the screen simply returns to the demo screen as in the past, there are procedures that cannot occur in normal games, missed procedures, the number of occurrences, the presence or absence of continuous occurrence, etc. Since it becomes possible to confirm, the occurrence of goto can be one of the judgment factors. It should be noted that the omitted procedure can be clearly represented by distinguishing it by the color of the character itself, making the typeface different, or thickening the line of the character, in addition to enclosing it in a circle.

  Further, in the gaming machine 1 of the present embodiment, when the data destruction detection means 71c detects the data destruction of the sub RAM 73-1, the sub CPU 71 uses the sub RAM 73-1 as error information indicating that the data destruction has occurred. Are sequentially stored (step S826). Further, when the information disclosure request is made by operating the door key 2, the sub CPU 71 reads the error information history from the error information history storage area 73d-1 and displays it on the liquid crystal display device 5.

  Therefore, according to the gaming machine 1, it is possible to detect the data destruction of the sub RAM 73-1 during the game. Therefore, by immediately issuing an error notification for the data destruction, the occurrence of goto can be suppressed.

  As the error notification, for example, when the data in the sub RAM 73-1 of the sub control circuit 70 is destroyed, a fatal error is displayed on almost the entire liquid crystal display area 23 of the gaming machine 1 as shown in FIG. , Indicates that the game cannot be continued because an abnormality has occurred in the RAM data. As a result, it is possible to suppress the RAM destruction act due to the goto act. Such notification is canceled by changing the setting such as power-off.

  Moreover, as another example of the error information history shown in FIG. "WDR POST" and "WDR PRE" are shown in 2 and 4, respectively. “WDR PRE” indicates the power failure abnormality error before the first lever operation after the power is turned on, and “WDR POST” indicates the power failure abnormality error after the first lever operation after the power is turned on. As a result, it is possible to confirm that there was an electric power interruption different from the normal electric power interruption processing, and it is possible to confirm the goto action.

  Further, in the above-described gaming machine of the present embodiment, the case where the gaming machine 1 is a pachi-slot machine has been described. However, the gaming machine according to the present invention is not limited to this, and can be applied to, for example, a pachinko machine having a variable display device of symbols as described later.

  Further, in the above-described gaming machine of the present embodiment, the two-dimensional code 300 has been described as including only communication error history data. However, the gaming machine according to the present invention is not limited to this, and may include, for example, an error information history or a game record of the player.

  As described above, in the gaming machine of the present embodiment, when the communication error, the communication interruption and the cancellation of the communication interruption occur between the main control circuit 60 and the sub control circuit 70, or the sub control circuit 70 is disconnected from the power. When the error occurs, the time information of the occurrence of the error and the release time of the communication interruption are stored together with the error code, so that the date and time of the occurrence and the release of the error etc. can be confirmed later, and the game of pachi-slot etc. Useful for the machine.

  In the flowchart of the mother task shown in FIG. 57, when the OS issues a main board communication task activation request in response to the main board communication task activation request (step S1005), the main board communication task is shown in FIG. 69 as described above. It is executed according to the flowchart.

  The RTC control task is executed according to the flow chat shown in FIG. First, the sub CPU 71 sets a cycle of 100 ms as time management of the OS (step S1011). Next, the sub CPU 71 reads the date and time from the external RTC 70c (step S1012), and sets the read date and time of the external RTC 70c as the initial value of the built-in RTC 70a (step S1013).

  Next, the sub CPU 71 reads the status information from the external RTC 70c (step S1014), determines whether or not the status information could be read normally (step S1015), and if the status information is read normally, the power supply is turned on. It is determined whether there is an abnormality (step S1016). If there is no power supply abnormality, it is determined whether there is an oscillation abnormality (step S1017). If there is no oscillation abnormality, a reset signal is detected. Whether or not the reset signal is detected (step S1018), the date and time is read from the external RTC 70c (step S1019).

  When reading this date and time, the sub CPU 71 determines whether or not there is an abnormality in the date and time range (step S1020). For example, if the value of year, month, day or time exceeds two digits, it is determined that the date and time range is abnormal. When the sub CPU 71 determines that the date and time range is abnormal, the error code (RTC TIM) is set as the RTC time abnormality and the error information history storage area 73d-1 of the sub RAM 73-1 is determined as shown in the table of FIG. (Step S1021).

  On the other hand, when the sub CPU 71 determines in step S1015 that the status information cannot be normally read from the external RTC 70c, the error code (RTC communication line error) is displayed in the error information history storage area 73d-1. The DSC) is registered (step S1021).

  When the sub CPU 71 determines in step S1016 that the external RTC 70c has an abnormality in the power supply, it registers an error code (RTC POWER) in the error information history storage area 73d-1 as the RTC voltage drop (step S1016). S1021).

  When it is determined in step S1017 that the external RTC 70c has an oscillation abnormality, the sub CPU 71 registers an error code (RTC CLK) in the error information history storage area 73d-1 as an oscillation stop detection (step S1021). ).

  If the sub CPU 71 determines in step S1018 that a reset signal has been detected, the sub CPU 71 registers an error code (RTC RESET) in the error information history storage area 73d-1 as reset detection (step S1021).

  When the error code corresponding to the error type of the external RTC 70c is registered as error information in step S1021 as described above, the sub CPU 71 initializes the external RTC 70c and sets the current date and time of the internal RTC 70a in the external RTC 70c. Yes (step S1022).

  In this way, when the external RTC 70c is initialized and the current date and time of the built-in RTC 70a is set in the external RTC 70c, or when it is determined in step S1020 that the date and time range read from the external RTC 70c is normal in step S1019 In step S1023, the sub CPU 71 determines whether or not the date and time setting of the external RTC 70c has been changed from the staff operation screen (step S1023), and if it has been changed, the date and time data of the built-in RTC 70a is externally attached. The RTC 70c is set (step S1024).

  When the date / time data of the built-in RTC 70a is set to the external RTC 70c in step S1024, or when it is determined that the date / time setting of the external RTC 70c is not changed in step S1023, the sub CPU 71 waits for a cycle of 100 ms. Then, the status information is read again from the external RTC 70c (step S1025) (step S1014).

  Next, the backup creation processing will be described with reference to FIG. FIG. 76 is a flowchart of the backup creation process. By this processing, even if the data is destroyed, the correct value can be saved as a backup. As described above, this backup creation processing is also executed in the power interruption interruption processing of the sub CPU shown in FIG.

  First, the sub CPU 71 creates a sum value of the game data area 73a-1 and stores the created sum value in the game data sum value area 73b-1 (step S1051). Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 1 area 73a-2, and stores the sum value stored in step S1051 in the backup data 1 sum value area 73b-2 (step S1052).

  Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 2 area 73c-2 as the mirroring of the backup data 1 area 73a-2, and the sum value stored in step S1051 is used as the backup data 2 sum value area. 73d-2 is stored (step S1053).

  Next, the sub CPU 71 creates a sum value of the staff operation setting data area 73g-1 and stores the created sum value in the staff operation setting data sum value area 73h-1 (step S1054).

  Next, the sub CPU 71 copies the staff operation setting data area 73g-1 to the staff backup data area 73e-2, and stores the sum value stored in step S1054 in the staff backup data sum value area 73g-2 (step S1055). ). This completes the backup creation process.

[Structure of pachinko machine]
The present invention is not limited to a pachi-slot, but can be applied to a pachinko gaming machine. The pachinko game machine will be described below.

  As shown in FIGS. 77, 78 and 79, the pachinko machine 1010 includes a glass door 1011, a wooden frame 1012, a base door 1013, a game board 1014, a plate unit 1020, a liquid crystal display device 1032 for displaying an image, and a game ball. It includes a launching device 1130 for launching, a payout unit, a substrate unit, and the like, which are not shown.

  The glass door 1011 is attached to the base door 1013 so as to be openable and closable by a rotating shaft. An opening 1011a is formed in the center of the glass door 1011 and a transparent protective glass 1019 is arranged in the opening 1011a.

  The plate unit 1020 is a unit body in which the upper plate 1021 and the lower plate 1022 are integrated, and is arranged below the glass door 1011 in the base door 1013. The upper plate 1021 and the lower plate 1022 are formed with payout openings 1021a and 1022a for renting out game balls and paying out game balls (prize balls). When a predetermined payout condition is satisfied, a game is played. The balls are discharged, and in particular, the upper plate 1021 stores game balls to be shot in a game area 1015 described later.

  The launching device 1130 is provided in the lower right portion of the base door 1013, and includes a launching handle 1026 that can be operated by the player, and a panel body 1027 that fits in the lower right portion of the dish unit 1020. The firing handle 1026 is provided on the front side of the panel body 1027. A drive device for launching a game ball is provided on the back side of the panel body 1027. By operating the firing handle 1026, the player can shoot a game ball and proceed with the game.

  The game board 1014 is arranged in front of the base door 1013 so as to be located behind the protective glass 1019. A liquid crystal display device 1032 and the like are arranged behind the game board 1014. A payout unit and a board unit are disposed behind the base door 1013. Below the lower plate 1022, a speaker for presentation (not shown) is arranged.

  The game board 1014 is entirely made of various resins (transparent members) such as a transparent plate-shaped acrylic resin, polycarbonate resin, methacrylic resin and the like. Further, the game board 1014 has a game area 1015 on the front surface side thereof, in which the shot game balls can roll down. A plurality of game nails 1017 are driven into the game area 1015. An LED unit 1053 is provided on the lower left of the game board 1014.

  The liquid crystal display device 1032 is arranged behind (on the back side of) the game board 1014. The liquid crystal display device 1032 has a display area 1032a capable of displaying an image related to a game. In the display area 1032a, various images such as an identification pattern for effect, an effect image, and a decorative image for decoration are displayed.

  The firing handle 1026 is rotatable, and a firing solenoid (not shown) serving as a drive device is provided on the back side of the firing handle 1026. Further, a touch sensor (not shown) is provided on the peripheral portion of the firing handle 1026. Inside the firing handle 1026, a firing volume that changes the resistance value according to the rotation amount of the firing handle 1026 and changes the power supplied to the firing solenoid (not shown) is provided.

  When the player touches a touch sensor (not shown), it is detected that the player holds the firing handle 1026. When the firing handle 1026 is gripped by the player and rotated clockwise, the resistance value of the firing volume (not shown) changes according to the rotation angle, and corresponds to the resistance value at this time. Power is supplied to a firing solenoid (not shown). As a result, the game balls stored in the upper plate 1021 are sequentially shot to the game area 1015, and the game is advanced. When a firing stop button (not shown) is pressed, the firing of the game ball is stopped even when the firing handle 1026 is held and rotated.

  At the lower left of the game board 1014, members forming the general winning openings 1056a, 1056b, 1056c are arranged, and the portion of this member facing the LED unit 1053 is transparent. Therefore, the LED unit 1053 can be visually recognized from the lower left of the game board 1014. In the LED unit 1053, the special symbol display device shown in FIG. 79, the normal symbol display device 1033, the first special symbol hold display LEDs 1034a, 1034b, the second special symbol hold display LEDs 1034c, 1034d, the normal symbol hold display LEDs 1050a, 1050b, etc. Is provided.

  The special symbol display device is composed of 16 LEDs. These 16 LEDs are divided into two groups of 8 LEDs, one of which performs a variable display upon the start winning of the first starting opening 1023, and the other group of which is The variable display is performed in response to the start winning in the second start opening 1044. For convenience of the following description, one LED group is referred to as a first special symbol display device 1035a (see FIG. 79), and the other LED group is referred to as a second special symbol display device 1035b (see FIG. 79).

  The LEDs of the first and second special symbol display devices 1035a and 1035b perform variable display of special symbols by repeating lighting and extinguishing in group units by the establishment of a variable display start condition of a predetermined special symbol. Then, when the special symbol is in a specific stop display mode, the game state is shifted from the normal game state to the hit game state (special game state) which is a state advantageous to the player. When this hit game state is entered, as will be described later, the shutter 1040 is controlled to the open state, and the game ball can be received in the special winning opening 1039.

  The normal symbol display device 1033 is variably displayed as a normal symbol by alternately lighting and extinguishing the two display lamps alternately, and the normal electric auditors product 1048 is opened by the stop mode.

  The normal symbol hold display LEDs 1050a and 1050b display the number of executions of the variable display of the normal symbols which are held by turning on, off or blinking (so-called "holding number", "holding number regarding normal symbol").

  The first special symbol hold display LEDs 1034a, 1034b and the second special symbol hold display LEDs 1034c, 1034d are the number of executions of the variable display of the special symbols held by turning on, off, or blinking (so-called, "holding number", "special symbol"). "Reserved number of items") is displayed.

  In the display area of the liquid crystal display device 1032, effect images associated with the special symbols displayed on the first special symbol display device 1035a and the second special symbol display device 1035b are displayed.

  As shown in FIG. 78, on the game board 1014, two guide rails 1030 (1030a and 1030b), a stage 1055, a first starting opening 1023, a second starting opening 1044, a passage gate 1054, a shutter 1040, a special winning opening. 1039, general winning a prize mouths 1056a, 1056b, 1056c, 1056d, an ordinary electric accessory 1048 and the like are provided.

  The stage 1055 is provided on the upper part of the game board 1014, and the guide rail 1030 is provided so as to surround the game area 1015.

  The guide rail 1030 includes an outer rail 1030a and an inner rail 1030b. The launched game ball is guided by the guide rail 1030 to move to the upper part of the game board 1014, and while changing its traveling direction due to the collision with the plurality of game nails (not shown) and the stage 1055 described above. It flows downward toward the game board 1014. Specifically, the system that flows down the left side of the stage 1055 (so-called left-handed) and the firing handle 1026 are rotated to the right side, the game ball is driven into the right side of the stage 1055, and the right side of the stage 1055 flows down. There is a system (so-called right-handed).

  The first starting port 1023 is provided below the center of the game board 1014. The passage gate 1054 is provided on the upper right side of the stage 1055, and the second starting port 1044 is provided below the passage gate 1054. The ordinary electric accessory 1048 is provided in the second starting port 1044.

  In addition, the ordinary electric accessory 1048 includes a tongue-shaped member 1048a that projects and retracts in the front-back direction with respect to the game board surface. The normal electric accessory 1048 allows winning of the game ball into the second starting opening 1044 when the tongue-shaped member 1048a is projected, and disables winning of the game ball into the second starting opening 1044 when retracting. The ordinary electric accessory 1048 may be one in which a pair of blade members is opened and closed (so-called electric tulip).

  Also, when hitting to the right, the game ball 1017 is configured so that the game ball cannot enter the first starting opening 1023 from the right side of the stage 1055.

  Further, when the game ball passes through the passage gate 1054 during the variable display of the normal symbol, the display mode of the normal symbol hold display LEDs 1050a, 1050b is switched until the normal symbol in the variable display is stopped and displayed. Execution (start) of variable display of normal symbols based on passage of game balls to the passage gate 1054 is suspended. After that, when the normal symbol that has been variably displayed is stopped and displayed, the variable display of the suspended normal symbol is started.

  When a specific symbol is stopped and displayed as a normal symbol on the normal symbol display device 1033, an effect image that makes the player understand that the normal symbol lottery is won is displayed in the display area of the liquid crystal display device 1032. You may do it.

  Further, the shutter 1040 is arranged immediately below the first starting port 1023, and opens and closes the special winning opening 1039. An outlet 1057 is formed at the lowest portion of the game area 1015 directly below the shutter 1040. The general winning openings 1056a, 1056b, 1056c are provided on the lower left side of the game area 1015. A general winning opening 1056d is provided on the lower right side of the game area 1015.

  Further, a winning area is provided in the first starting opening 1023 described above, and the first starting winning opening switch 1116 (see FIG. 79) is provided in this winning area. A winning area is provided in the second starting opening 1044, and a second starting winning opening switch 1117 (see FIG. 79) is provided in this winning area. When the game ball is detected by the first start winning opening switch 1116, the variable display of the special symbol by the first special symbol display device 1035a is started.

  In addition, when the game ball enters the first starting port 1023 during the variable display of the special symbol, the game ball enters the first starting port 1023 until the special symbol during the variable display is stopped and displayed. Execution (start) of variable display of special symbols based on is suspended. After that, when the special symbols that have been variably displayed are stopped and displayed, the variable display of the special symbols that have been held is started. In the following description, the special symbol that is variably displayed on the first special symbol display device 1035a based on the entry of the game ball into the first starting opening 1023 is referred to as a first special symbol.

  Moreover, when the game ball is detected by the second start winning opening switch 1117, the variable display of the special symbol by the second special symbol display device 1035b is started. Moreover, when the game ball enters the second starting port 1044 during the variable display of the special symbol, the game ball enters the second starting port 1044 until the special symbol in the variable display is stopped and displayed. Execution (start) of variable display of special symbols based on is suspended. After that, when the special symbols that have been variably displayed are stopped and displayed, the variable display of the special symbols that have been held is started. In the following description, the special symbol that is variably displayed on the second special symbol display device 1035b based on the entry of the game ball into the second starting opening 1044 is referred to as a second special symbol.

  Here, the first special symbol display device 1035a and the second special symbol display device 1035b, the special symbol does not change at the same time. In addition, the variable display of the special symbol is performed with priority given to the start winning in the second start opening 1044.

  In addition, the number of suspensions of the variable display of the special symbol due to the ball entering the first starting opening 1023 and the second starting opening 1044 is limited to four times, respectively. Therefore, it is possible to hold a maximum of eight times.

  In addition, as another condition (variable display start of a predetermined special symbol), the special symbol is stopped and displayed. That is, the variable display of the special symbol is started each time the variable display start condition of the predetermined special symbol is satisfied.

  In the first special symbol display device 1035a and the second special symbol display device 1035b, the special symbol becomes a specific stop display mode, and when the gaming state is shifted to the jackpot gaming state, the shutter 1040 is opened. Driven. As a result, the special winning opening 1039 is in an open state (first state) in which it is easy to receive a game ball.

  On the other hand, in the special winning opening 1039 provided on the back side (rear side) of the shutter 1040, there is an area (not shown) having a count switch 1104 (see FIG. 79), and a predetermined number of game balls (for example, the area) The shutter 1040 is driven to the open state until the number of the shutters passes (7 pieces) or a predetermined time (for example, about 0.1 seconds or about 30 seconds) elapses. Then, in the open state, when a condition of winning a predetermined number of game balls into the special winning opening 1039 or elapse of a predetermined time is satisfied, the shutter 1040 is driven to be closed. As a result, the special winning opening 1039 is in a closed state in which it is difficult to receive the game ball (second state).

  A game in which the special winning opening 1039 is in a state where it is easy to receive a game ball in a certain time is called a round game. Therefore, the shutter 1040 is opened during round games and closed between round games. The round game is counted as the number of rounds such as "1" round and "2" round. For example, the first round game may be called the first round and the second round game may be called the second round. In this example, the shutter 1040 may be opened and closed a plurality of times in one round to keep the shutter open for a certain period of time.

  Subsequently, the shutter 1040 driven from the open state to the closed state (second state) is driven to the open state again. In other words, when the round game is finished, it is possible to continue to the next round game. The game from the first round game to the end of the (final) round game that cannot proceed to the next round game is called special game or jackpot game. In this example, all jackpots are 15 rounds.

  In addition, when a game ball wins the above-mentioned first starting opening 1023, second starting opening 1044, general winning openings 1056a to 1056d, and big winning opening 1039, the number preset according to the type of each winning opening. The game ball of is paid out to the upper plate 1021 or the lower plate 1022.

  Further, in this example, after the jackpot game is over, the winning probability of the ordinary symbol lottery becomes a high probability state, and the special electric game 1048 may shift to a time saving state in which the reserved balls of the special symbol game are easily accumulated due to the support. . Here, in the time saving state, passing the game ball through the passage gate 1054 is a condition for executing the normal symbol lottery, and therefore the game proceeds while right-handing.

  Also, when a big hit occurs in the right-handed state, it is possible to make a winning in the special winning opening 1039 by continuing the right-handed as it is. Further, when the support by the ordinary electric accessory 1048 cannot be received, the game is advanced while left-handed.

  Also, as shown in FIG. 77, effect buttons 1080a, 1080b, 1080c are provided on the front surface of the upper plate 1021, and those effects are produced during a mini game such as a push-button game, card flipping, or Sugoroku. By pressing the button, the effect display content on the liquid crystal display device 1032 can be changed.

  In addition, in the pachinko machine 1010, the liquid crystal display device is described as an example of the rendering means, but the invention is not limited to this, and a plasma display, a rear projection display, a CRT display, a lamp, a speaker, a movable accessory, or the like is used as the rendering means. Good.

  Next, with reference to FIG. 79, an electrical configuration of the pachinko machine 1010 will be described.

  As shown in FIG. 79, the pachinko machine 1010 is mainly composed of a main control circuit 1060 for controlling a game and a sub-control circuit 1200 for controlling an effect according to the progress of the game.

  The main control circuit 1060 includes a main CPU 1066, a main ROM 1068 (read-only memory), and a main RAM 1070 (readable / writable memory).

  A main ROM 1068, a main RAM 1070, etc. are connected to the main CPU 1066, and have a function of executing various processes according to a program stored in the main ROM 1068.

  The main ROM 1068 stores a program for controlling the operation of the pachinko machine 1010 by the main CPU 1066, a program for causing the main CPU 1066 to execute main processing, and various tables.

  The main RAM 1070 has a function of storing various flags and variable values as a temporary storage area of the main CPU 1066. The temporary storage area of the main CPU 1066 is not limited to the main RAM 1070, and other readable / writable storage medium may be used.

  The main control circuit 1060 also includes an initial reset circuit 1064 that generates a reset signal when the power is turned on, an I / O port 1071, and a command output port 1072. The initial reset circuit 1064 is connected to the main CPU 1066. The I / O port 1071 sends input signals from various devices to the main CPU 1066 and outputs signals from the main CPU 1066 to various devices.

  The command output port 1072 is for transmitting a command from the main CPU 1066 to the sub control circuit 1200. The main control circuit 1060 also includes a backup capacitor 1074. The backup capacitor 1074 is used to hold various data stored in the main RAM 1070, for example, by rapidly supplying power to the main RAM 1070 when power is cut off.

  Various devices are connected to the main control circuit 1060. For example, in the main control circuit 1060, the first special symbol display device 1035a and the second special symbol display device 1035b, the first special symbol hold display LEDs 1034a, 1034b and the second special symbol hold display LEDs 1034c, 1034d, the normal symbol display device 1033. , The normal symbol hold display LEDs 1050a, 1050b, the tongue-shaped member 1048a of the normal electric accessory 1048 is in a projecting state or a retracting state, the starting opening solenoid 1118 and the shutter 1040 are driven, and the special winning opening 1039 is opened or closed. The special winning opening solenoid 1120 and the like are connected.

  Further, the main control circuit 1060 has an external terminal used for transmitting data to a calling device (not shown) having a function of calling a hall staff member and a function of displaying the number of hits, and a hall computer 1400 that manages pachinko machines for the entire hall. A plate 1310 is connected.

  Further, in the main control circuit 1060, for example, when the game ball passes through the area in the big winning opening 1039, a count switch 1104 that supplies a predetermined detection signal to the main control circuit 1060, and each general winning opening 1056 are game balls. When the game ball has passed through the general winning opening switches 1106, 1108, 1110, 1112 and the passage gate 1054, the main control circuit 60 supplies a predetermined detection signal to the main control circuit 60 when the game ball passes. When the game ball wins the passage gate switch 1114 and the first starting opening 1023 supplied to the 1060, the first starting winning opening switch 1116 and the second starting opening 1044 which supply a predetermined detection signal to the main control circuit 1060 are played. A second start winning opening switch 1117 for supplying a predetermined detection signal to the main control circuit 1060 when the ball wins, the power is cut off Such as backup clear switch 1124 to clear depending on the administrator of the operation of the game arcade is connected to a backup data in such.

  A payout / launch control circuit 1126 is connected to the main control circuit 1060. To the payout / launch control circuit 1126, a payout device 1128 for paying out game balls, a launching device 1130 for launching game balls, and a card unit 1300 are connected. The card unit 1300 can perform transmission / reception with a ball lending operation panel 1155 that outputs a signal requesting the card unit 1300 to lend a game ball, by an operation of the player.

  The payout / launch control circuit 1126 receives the prize ball control command supplied from the main control circuit 1060, the loan ball control signal supplied from the card unit 1300, and transmits a predetermined signal to the payout device 1128. The payout device 1128 is caused to pay out the game balls. In addition, the payout / launch control circuit 1126 supplies electric power to the firing solenoid in accordance with the turning angle when the firing handle 1026 is gripped by the player and is rotated in the clockwise direction, and the game is played. Controls to launch a ball.

  The sub control circuit 1200 is connected to the command output port 1072. The sub control circuit 1200 performs display control in the liquid crystal display device 1032, control regarding sound generated from the speaker 1046, control of lamps including a decorative lamp, and the like in accordance with various commands supplied from the main control circuit 1060. The sub-control circuit 1200 has the same configuration as the sub-control circuit 70 described in the pachi-slot gaming machine of the present embodiment, and can execute various processes.

  As described above, according to the pachinko gaming machine according to the present embodiment, it is possible to obtain the same effect as that of the pachi-slot gaming machine according to the above-described embodiment.

1 gaming machine 1a housing 1b front door 2 door keys 3L, 3C, 3R reels 4L, 4C, 4R symbol display area (symbol display means)
5 Liquid crystal display device (display unit, display device)
6S start switch (start operation detection means)
7LS, 7CS, 7RS Stop switch (stop operation detection means)
20S setting key switch (setting device)
23 Liquid crystal display area (holding memory display means)
23S reset switch (state release command input means)
29S Door open / close switch (door open state detection means)
31 main CPU (internal winning combination determination means, command transmission means, command data transmission means, arithmetic processing circuit of the first control unit)
32 main ROM (storage means)
39 Motor drive circuit (design variation means, stop control means)
40 hopper (dispensing means)
41 Hopper drive circuit (dispensing means)
49L, 49C, 49R Stepping motor (design variation means, stop control means)
50 reel position detection circuit (symbol change means, stop control means)
60, 1060 Main control circuit (main control unit, first control unit)
70, 1200 Sub control circuit (sub control unit, second control unit)
70a Built-in RTC (time keeping means)
71 sub CPU (winning combination acquisition means, winning combination acquisition means, winning determination means, determination processing means, payout determination means, effect content determination means, effect control means, command receiving means, command data receiving means, communication disconnection determining means, display Processing means, processing means)
71a Communication error detecting means (error detecting means)
71b Procedure detection means 71c Data destruction detection means 71d Error information registration means (communication disconnection storage means)
71e Received data log storage means 71f Error information history display means 71g Two-dimensional code conversion means 72 Sub ROM (storage means, symbol storage area)
72a OS area 72b Sub-control program area 72c Game data initialization setting data area 72d Staff operation initial setting data area 72e Various program table areas 72f Program management data area 72g Image data (still image / moving image)
72h sound data 72i accessory moving data 73-1 DRAM (storage unit, storage unit)
73a-1 Sub-control game data area (game data storage area)
73b-1 Sub control game data sum value area 73c-1 Work area 73d-1 Error information history storage area (abnormality occurrence storage area)
73e-1 communication log collection ring buffer area 73f-1 communication error storage buffer area 73-2 SRAM (holding storage means)
73a-2 Backup data 1 area 73b-2 Backup data 1 sum value 73c-2 Backup data 2 area 73d-2 Backup data 2 sum value 73e-2 Staff backup data area 73f-2 Error information history storage area 73g-2 Staff backup Data sum value 74 GPU
75 VRAM
300 two-dimensional code 330 QR code (registered trademark)
400 Mobile communication terminal with camera (mobile terminal)
500 data management server (server)
600 PC for analysis (analysis means)

Claims (2)

A main body and a front door that is openably and closably attached to the main body,
A lock mechanism capable of switching the front door to a locked state or an unlocked state with the front door and the main body closed,
A display device for displaying an image,
A first control unit that performs first control;
A second controller connected to the display device and the first controller to perform second control;
An error detection unit that detects that an error has occurred,
The second control unit
Storage means including an error information history storage area for storing error information relating to the error detected by the error detection means,
Error information registration means for sequentially storing the error information related to the error in the error information history storage area based on the occurrence of the error detected by the error detection means,
Error information history display means for displaying the error information history stored in the error information history storage area on the display device;
With an RTC that can measure the passage of time and provide timed time information,
The lock mechanism can switch the locked state to the unlocked state by rotating the inserted door key in a predetermined direction,
The lock mechanism is capable of rotating the door key in a direction opposite to the predetermined direction,
The second control unit displays the error information history on the display device when a state in which the door key is rotated in a direction opposite to the predetermined direction is maintained for a certain time or more,
The error information history displayed on the display device includes, on the horizontal axis, character string information indicating an error detected by the error detection unit and time information provided by the RTC based on the detection of the error. A gaming machine characterized by being displayed side by side.   In the error information history displayed on the display device, the time information displayed downward in the vertical direction of the displayed time information is older than the time information displayed in the vertical direction. The gaming machine according to claim 1, wherein:

Images