JP2020047277A - Methods and systems including co-processors and storage devices to identify fpga and ssd pairing in multi-device environment - Google Patents

Abstract

To provide methods and systems for establishing the pairing of storage devices such as SSDs, an FPGA and other co-processors.SOLUTION: A system includes a Solid State Drive (SSD) and a co-processor. The SSD includes a storage for data, a storage for a unique SSD identifier (ID), and a storage for a co-processor ID. The co-processor include a storage for the unique SSD ID, and a storage for the co-processor ID. A hardware interface permits communication between the SSD and the co-processor.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a computer system, and more particularly, to a system and method including a storage device and a co-processor for identifying an FPGA and an SSD to be paired in a multiple device environment.

  Field Programmable Gate Array (FPGA) and Solid State Drive (SSD) sub-devices are often (but not always) packaged in a single enclosure for form factor, power, density, and performance benefits. The FPGA and the SSD are expressed as separate physical functions (PFs) from the viewpoint of a host's PCI (Peripheral Component Interconnect). The FPGA and SSD sub-devices are mounted on separate unrelated input / output (I / O) stacks (particularly storage and OpenCL).

  A form factor that includes both FPGA and SSD devices should exhibit three PFs. That is, a Data PF (referred to as a user space PF), a management PF, and an NVMe (Non-Volatile Memory Express) PF. The first two PFs are for FPGA and the third PF is for SSD.

  If the machine includes only one FPGA / SSD pair, the separate PF does not matter for pairing identification (eg, from an x86 host server). However, if more than one device is present (eg, a dense x86 host server), it is not identified which FPGA is paired with which SSD. The problem is even more acute in a virtualized environment where PCIe pass-through is enabled and multi-function devices appear as multiple single-function devices.

  Pairing is necessary for peer-to-peer (P2P) computing to function properly. Without pairing, P2P fails because the data is loaded into the context of the wrong FPGA device and directed to the kernel of the hardware that does not hold the correct data. The problem is exacerbated when the host user cannot identify the application with the pairing requirements.

  It is necessary to establish a pairing of a storage device such as an SSD, an FPGA, and another coprocessor.

U.S. Pat. No. 8,417,880 US Patent No. 9712619 US Patent No. 9801219 US Patent Application Publication No. 2018/0357018

  The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a system and method for constructing a pairing of a storage device such as an SSD, an FPGA, and another coprocessor. Is to provide.

  To achieve the above object, a system according to an aspect of the present invention includes an SSD including a first storage for data, a second storage for a unique SSD ID (identifier), and a third storage for a unique coprocessor ID. Solid State Drive), a coprocessor including a fourth storage for the unique coprocessor ID, a fifth storage for the unique SSD ID, and a hardware interface between the SSD and the coprocessor.

  According to the present invention, having a SSD / FPGA device pairing solution is beneficial for more useful use of the device. In the short term, the pairing solution can handle the identification interval. In the long run, the pairing solution will help you make decisions about what to do with your acceleration device.

FIG. 2 illustrates a machine designed to support pairing of a storage device and a coprocessor according to one embodiment of the present invention. FIG. 2 is a diagram illustrating a different form of the coprocessor of FIG. 1. FIG. 2 shows additional details of the machine of FIG. 1. FIG. 2 is a diagram illustrating an operating system of the device in FIG. 1. FIG. 2 shows the device of FIG. 1 arranged to store information about pairing. FIG. 2 is a diagram illustrating an operating system for querying the SSD and the coprocessor of FIG. 1 to pair devices. FIG. 2 illustrates the SSD and coprocessor of FIG. 1 as a single form factor in one embodiment of the present invention. FIG. 3 illustrates the SSD and coprocessor of FIG. 1 as a single form factor in another embodiment of the present invention. FIG. 2 is a diagram illustrating the SSD and the coprocessor of FIG. 1 for establishing pairing according to an embodiment of the present invention; FIG. 7 is a diagram illustrating the SSD and the coprocessor of FIG. 1 for establishing a pairing according to another embodiment of the present invention; FIG. 2 is a diagram illustrating a first topology including the SSD and the coprocessor of FIG. 1 according to an embodiment of the present invention; FIG. 6 is a diagram illustrating a second topology including the SSD and the coprocessor of FIG. 1 according to another embodiment of the present invention; FIG. 4 is a diagram illustrating a third topology including the SSD and the coprocessor of FIG. 1 according to an embodiment of the present invention; FIG. 7 is a diagram illustrating a fourth topology including the SSD and the coprocessor of FIG. 1 according to another embodiment of the present invention; 2 is a flowchart illustrating a procedure of the SSD of FIG. 1 (or the coprocessor of FIG. 1) for querying a partner for pairing data according to an embodiment of the present invention. 2 is a flowchart illustrating a procedure of the SSD in FIG. 1 (or the coprocessor in FIG. 1) for receiving a query for pairing data from a partner according to an embodiment of the present invention. 6 is a flowchart illustrating a procedure of the SSD and / or coprocessor of FIG. 1 for responding to queries from a pairing partner and the associated operating system of FIG. 5 according to one embodiment of the present invention. 6 is a flowchart illustrating a procedure of the operating system of FIG. 5 for querying and pairing the SSD and the coprocessor of FIG. 1 according to an embodiment of the present invention. 6 is a flowchart illustrating a procedure of the operating system of FIG. 5 for responding to a query from an application regarding pairing information for a device according to an embodiment of the present invention.

  Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following detailed description, various specific embodiments are provided to facilitate a thorough understanding of the teachings of the present invention. However, those having ordinary skill in the art can implement the technical idea of the present invention without these specific embodiments. As other examples, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure the present invention.

  Here, terms such as first and second are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one element from another. By way of example, without departing from the spirit of the invention, the first module is named the second module. Similarly, the second module is named the first module.

  In the description of the technical concept of the present invention, terms used are used only for the purpose of describing a specific embodiment and are not intended to limit the technical concept of the present invention. As used in the description and claims of the present invention, the singular forms "a" and "an" include plural references unless the context clearly dictates otherwise. The term "and / or" is referred to as including any and all possible combinations of one or more of the associated items. The terms “comprise” and / or “comprising”, when used in the detailed description, specify the presence of the property, integer, step, operation, element, and / or component it refers to. However, it does not exclude the existence or addition of one or more other properties, integers, steps, acts, elements, components, and / or groups thereof. The components and characteristics of the drawings are not necessarily proportional to the actual ratio.

  If one or more Solid State Drive (SSD) / Field Programmable Gate Array (FPGA) pairs of the device are available on the same server, the user of the host application will be able to peer over these two separate pairings ( There is a possibility to select a buffer and SSD. Such a selection results in inaccurate results of data corruption and acceleration. The SSD / FPGA pair exposes three physical functions (PFs). That is, the data PF (for the FPGA) (also referred to as the user space PF), the management PF (for the FPGA), and the NVMe (Non-Volatile Memory Express) PF (for the SSD). This problem is alleviated if the three PFs are based on the same device. However, using the “Xilinx®” three-port switch design approach, the FPGA and SSD appear as separate devices without details about their physical associations (“Xilinx®” Xilinx (registered trademark) "). This problem is further complicated by the OpenCL software interface that exposes Xilinx to its own applications. The software interface virtualizes details of a bus / device / function (Bus / Device / Function: BDF), and indicates each FPGA device by a logical number such as 0, 1, or 2. Such additional indirection at the software level completely obscures the previously inferred pairing association at the Peripheral Component Interconnect (PCI) BDF level. The application or user must be familiar with the connectivity of multi-function devices at the PCI BDF level, the inside of the Xilinx driver, and the complexity of mapping at the file system level.

  This arrangement is error prone and manifests as different issues based on the environment in which it is used. These arrangements can be cumbersome to debug, as peering requests can lead to users.

  <High-density system>

  In the above case, it is expected that all devices are under the same root complex. However, systems with densely packed SSD / FPGA devices require the use of one or more PCIe (PCI Express) switches configured under each root complex connected to each CPU socket. For access control services (ACS) that are leveraged in the context of virtualization and have diversified CPU / chipset support, peering is not evenly supported and application users understand these nuances in the topology. Burdensome.

  P2P transmission from an SSD to P2P-DDR (Dial On Demand Routing) is not supported, so that P2P transmission may fail. This result is due to the fact that the PCI root complex is not required to support the transmission of packets between root ports. This design choice is substantially good for P2P use in a storage acceleration context, but not good for the user experience.

  High-density SSD / FPGA deployments are built with any Intel / AMD solution from a variety of system vendors, with limited or no control over how the systems interact. This fact introduces complexity for what works and what doesn't.

  <PCI pass-through in virtualized environment>

  In a specific Linux virtualization environment, if a multi-function device such as an SSD / FPGA device is mapped to a pass-through attribute for a virtual machine (VM), a separate single function for each physical function Appears as a device. Thus, the three PFs exposed between the SSD and the FPGA are mapped as three single function devices that are not associated with each other.

  <Users without PCI knowledge>

  In addition to the above cases, the user of the application may not have enough knowledge to know the connection of the BDF. This is because the user may be a higher-level application user who does not need to be educated about the details of this level of the system. This problem leads to situations where a high level of abstraction is required to close this knowledge gap.

  <Proposed solution>

  SSD / FPGA devices are considered a new SSD device class by providing storage acceleration and distinguishing them from other stand-alone SSDs and FPGAs. New devices need a clear way to identify themselves. That is, FPGA with near storage capacity or NVMe SSD with near acceleration? And the solution includes the following configuration.

  Low-level device interface changes include private hardware interfaces, such as SMBus (System Management Bus), between the FPGA and SSD to share characteristics, and acceleration attributes. A small update to the NVMe SSD firmware, and an update to the FPGA firmware that queries the SSD and informs the SSD of the identifying pairing attributes.

  Changes in the high-level software interface enhance the management software module by querying the details of the low-level pairing, exposing the new features of the NVMe identification controller to the existing software path, and enhancing the FPGA and Includes interface to FPGA to query SSD.

  Includes an API enabled to adopt an ecosystem that includes application interface calls that identify pairings by device name, file name, etc.

  These changes must be small enough to maintain the NVMe SSD as generally as necessary. As an example, an existing NVMe SSD is reprogrammed to be accommodated as an SSD in an SSD / FPGA device.

  <Change to NVMe SSD for pairing including FPGA>

  Minor hardware changes allow the FPGA and SSD to communicate with each other.

  The SSD controller supports two SMBus master interfaces (as shown and described below with reference to FIGS. 7, 8 and text). The first SMBus master interface is connected to a BMC (Board Management Controller) or an external SMBus (Out of Band: OOB) output via a connector from such a management item. The second SMBus master port on the SSD is connected to the slave or master SMBus port of the FPGA device. The out-of-band (OOB) SMBus interface is used to implement a management protocol such as the NVMe management interface (NMVe-MI). The internal SMBus interface between the SSD controller and the FPGA is used exclusively for communication between the two devices. The firmware of the SSD controller queries the FPGA device for a unique identification. This interface is used by the SSD controller under the guidance of the BMC or host for the configuration, status and monitoring of the FPGA device. When the host or BMC queries the SSD controller for the identification information of the FPGA using a management protocol such as NVMe-MI, the SSD controller fetches necessary information from the FPGA and returns it to the host or BMC.

  The SSD controller communicates with the FPGA device using a message-based protocol. The SSD controller writes various command messages to the slave SMBus port of the FPGA and polls for the availability of the response. When the FPGA response message is prepared, the SSD controller reads the response message. If the FPGA needs the attention of the SSD controller, the FPGA sets a flag that is periodically polled by the SSD controller.

  A small change contained in the SSD firmware supports the hardware configuration described above. The completion of the initialization of the PCIe device occurs in advance in an embedded operating system (O / S) environment in the multi-function device. Thereafter, the multifunction device is reinitialized in the context of the x86 host.

  As part of the PCIe initialization phase, a software component (firmware of the SSD device) queries and finds local and connected devices for the multi-function device. Once the NVMe SSD and FPGA components have been initialized, the software components query the FPGA for device details that provide a unique (unique) serial number and product part number. Such details are written to the SSD register at a private offset in a memory-mapped NVMe BAR (Base Address Register) space. The write window is made available by the SSD's firmware before a PCI configuration access is made after reset to accept this update. This keeps the updates within the control of the OS.

  The NVMe specification defines the identification controller and the Namespace command to find out the capabilities of the NVMe SSD. As part of these functions, the controller defines the following to signal the acceleration (acceleration) function.

  <Data structure of identification controller>

  <Extended Features>

  <Change to FPGA to notify SSD device pairing>

  Like the NVMe SSD, the FPGA is programmed from the specific SSD details by the embedded O / S components. These details are used for x86 host software components via the interface.

  <Components of embedded O / S for pairing>

  Software components (as well as SSD firmware) can query and locate devices that are local and coupled to the multi-function device. Once the NVMe SSD and FPGA components have been initialized, the software components query the FPGA for device details that provide a unique serial number and product part number. These details are written to the SSD register at the private offset in the memory-mapped NVMe BAR space. Similarly, software components are programmed into the FPGA with unique SSD details to be paired with each other.

Sample list at power ON / RESET on SMBus 1. FPGA issues NVMe (Read Identification Controller) to SSD 2. SSD responds to identification data 3. FPGA stores details of serial number and model number The FPGA issuing NVMe (identification data setting-extended feature offset-provider details 3072-4095 bytes) includes:
Operation type: FPGA, count, exclusive / shared Operation type: CPU-ARM, count, exclusive / shared FPGA issues NVMe (identification data setting)
6. The issue of the NVMe by the FPGA (LogPage-compute_FPGA setting) includes the following.
Serial number, model number,
Hardware functions (LUTs, BRAM, URAM, Reg, DSP, DRAM)
7. SSD confirms NVMe (sets LogPage-compute_FPGA)

  A private interface exists between the x86 host software and components for additional queries for pairing and other features.

  <Changes in manageability software to accommodate new pairings>

  The BMC generally interfaces with the SSD on the SMBus. This interface is extended to accommodate pairs of FPGAs, and further includes properties and other attributes for usability and manageability.

The flow of the sample is as follows.
1. BMC issues NVMe to SSD (sets LogPage Temp2)
2. 2. SSD requests FPGA with read temperature sensor FPGA returns temperature data (return)
4. 4. SSD returns LogPage data. BMC issues NVMe to SSD (Read LogPage FPGA Utilization)
6. 6. Request for FPGA with SSD including LogPage FPGA Utilization 7. FPGA returns Utilization data SSD returns LogPage data

  <Components of x86 host software for pairing>

  This software component is available as a library and provides details of the pairing between the NVMe SSD and the FPGA coexisting in the multifunction device. This component works with the x86 SD Accel runtime driver and library to provide pairing details.

  The current OpenCL interface does not disclose the BDF level details of the device, but provides a logical abstraction by numbers starting at offset 0. The interface is modified internally by the provider to query low-level details exposed on the hardware, so that the details of the pairing to the computer side are also provided. Here, the provider is responsible for changing the interface.

  <Command line tool for querying pairing>

  The command line tool, when performed without options, provides the details as described in Table 4 below. References to the two I / O stacks and the programmable device will be reflected in the details. / Dev / nvme2 of the NVMe SSD is paired with an acceleration device (accelerator or accelerator) of index 0. It should be noted that the order of SSD devices does not increase as much as FPGA accelerated devices, as shown on the server.

  <Command line tool output>

  Command line tools can also support verbose options that provide more important additional details in private fields, like system administrators. These additional details include NVMe SSD attributes that are unique via device class such as serial number, model, firmware details, namespace, and partition mapping information. The unique detailed set includes a PCIe device chain that identifies the slot to which the device was linked. Table 5 below shows an example of such information.

  <Output of command line tool>

  In the case of device "/ dev / nvme0", the SSD / FPGA device is connected to slot number 1 which is also close to the "numa node 0" CPU. This information is used at the field level as well as at the application level for CPU affinity. This information, when included in a deeply nested PCIe switch fabric, can be used to understand the hierarchical structure of the device, for example, to isolate device problems for a system administrator.

  <Advantages>

  Having a pairing solution for SSD / FPGA devices is beneficial for using these devices more effectively. In the short term, this pairing solution addresses the identification gap. In the long run, this pairing solution will help you make decisions about what to do with your acceleration device. This solution includes GPUs, embedded CPUs such as the Advanced Reduced Instruction Set Computer (RISC) Machine (ARM), RISC-V, TPU (Tensor Processing Unit), and certain hardware-based accelerators or NVMe specification extensions. Used for other accelerator types, such as some other mechanisms.

  FIG. 1 is a diagram illustrating a machine designed to support pairing of a storage device and a coprocessor according to an embodiment of the present invention. FIG. 1 illustrates the machine 105. Machine 105 includes a processor 110. Processor 110 is any of a variety of processors. For example, Intel Xeon (registered trademark), Celeron (registered trademark), Itanium (registered trademark), or Atom (registered trademark) processor, AMD Opteron (registered trademark) processor, and ARM (registered trademark) processor. Although FIG. 1 illustrates one processor 110 in machine 105, machine 105 can include any number of processors, each of which is a single-core or multi-core processor, They can be mixed in any desired combination.

  Machine 105 includes memory 115. Memory 115, a flash memory such as MRAM (Magnetoresistive Random Access Memory), DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), PRAM (Persistent Random Access Memory), FeRAM (Ferroelectric Random Access Memory), or NVRAM (Non-Volatile Random Access Memory). The memory 115 can be any desired combination of different memory types. The memory 115 is managed by the memory controller 120.

  The machine 105 includes storage devices (125-1, 125-2) that can be controlled by a device (apparatus) driver (not shown). The storage devices (125-1, 125-2) are storage devices of any desired form. By way of example, the storage device (125-1, 125-2) is a solid state drive (SSD) such as a non-volatile memory express (NVMe) SSD, a hard disk drive, or any other desired form of storage device. . Note that the storage devices (125-1, 125-2) may be of different types, manufacturers, and / or models. For example, the storage device 125-1 may be an SSD and the storage device 125-2 may be a hard disk drive.

  The machine 105 also includes coprocessors (130-1 to 130-2). The coprocessors (130-1 to 130-2) provide any necessary functions to support the storage devices (125-1, 125-2). By way of example, coprocessor 125-1 may provide functions such as data acceleration, data deduplication, data integrity, data encryption, data compression, and / or erasure coding. Each of the coprocessors (130-1 to 130-2) provides one such function, and each of the coprocessors (130-1 to 130-2) provides a number of these functions. The coprocessors (130-1 to 130-2) are embodied using any desired components.

  FIG. 2 is a diagram illustrating a different form of the coprocessor of FIG. 1, and includes an FPGA (Field Programmable Gate Array) 205, an ASIC (Application-Specific Integrated Circuit) 210, a GPU (Graphics Processing Unit), and a GPU (Graphics Processing Unit) ) 220, an erasure coding controller 225, and a small processor core 230. However, embodiments of the present invention may include other embodiments of the coprocessors (130-1 to 130-2).

  Referring again to FIG. 1, although FIG. 1 illustrates two storage devices with one coprocessor for each storage device, embodiments of the present invention may be used with any number of storage devices and other types as desired. May include any number of coprocessors for each storage device. Note that in some embodiments, some storage devices have coprocessors and other storage devices do not have coprocessors. However, since there is no concern about pairing a storage device with a coprocessor, as with only one storage device and one coprocessor, most embodiments of the present invention provide at least two storage devices with corresponding coprocessors. including. In the following, the term “pairing” refers to a device in which one paired device supports another device and should not be understood as limiting the pairing to only two devices. As an example, if a storage device includes both an FPGA and a GPU, all three devices are considered "paired". (Alternatively, the FPGA and GPU are considered separately paired with the common storage device, and if necessary, the association between the FPGA and GPU is indirectly determined.)

  Although FIG. 1 illustrates the machine 105 as a server (which may be a stand-alone or rack server), embodiments of the present invention include, without limitation, any desired type of machine 105. By way of example, machine 105 may be replaced with a desktop, laptop computer, or any other machine that can benefit from embodiments of the present invention. Machine 105 includes specialized portable computing machines, tablet computers, smartphones, and other computing machines.

  FIG. 3 is a diagram illustrating additional details of the machine of FIG. In FIG. 3, machine 105 generally includes one or more processors 110 that include a memory controller 120 and a clock 305 that can be used to coordinate the operation of components of the device (machine 105). The processor 110 is connected to a memory 115 including, for example, a random access memory (RAM), a read-only memory (ROM), or another state storage medium. The processor 110 is connected to the storage device 125 and a network connector 310 which is, for example, an Ethernet (registered trademark) (Ethernet (registered trademark)) connector or a wireless connector. The processor 110 is coupled to a bus 315, which implements a user interface 320 and an input / output interface port managed using an input / output engine 325, among other components.

  FIG. 4 is a diagram showing an operating system of the device shown in FIG. In a conventional system, the operating system 405 uses the SSDs (125-1, 125-2) and the coprocessors (130-1 to 130-2) using virtual identifiers (IDs) (410, 415, 420, and 425). -2). (While the discussion herein focuses on SSDs as specific examples of storage devices that include a coprocessor, embodiments of the present invention may still be extended to other types of storage devices than SSDs.) The IDs (410, 415, 420, and 425) are assigned during device enumeration by a controller, such as a Peripheral Component Interconnect (PCI) enumerator, or in the machine 105 of FIG. This includes "configuring" a virtual machine (VM). In either case, operating system 405 has only the information provided as a result of the virtual IDs (410, 415, 420, and 425). Due to the fact that the SSDs 125-1 and 125-2 are SSDs, the operating system 405 determines that the assigned virtual ID 410, the SSD 125-1 includes the data storage device 430 and the assigned virtual ID 415, the SSD 125-2, It is known that the storage device 435 is included. However, the operating system 405 may require that the coprocessor 130-1 assigned the virtual ID 420 support the operation of the SSD 125-1 assigned the virtual ID 410, or that the coprocessor 130-2 assigned the virtual ID 425 may You may not know to support the second operation.

  FIG. 5 is a diagram showing the device of FIG. 1 arranged to store information about pairing. In FIG. 5, the devices (125-1, 125-2, 130-1, and 130-2) include storage for various pieces of information about the pairing. Thus, SSD 125-1 includes storage devices (505-1, 505-2) for information about itself and the paired coprocessor (coprocessor 130-1), while SSD 125-2 includes itself and It includes storage (515-1, 515-2) for information about the paired coprocessor (coprocessor 130-2), which stores itself and the paired SSD (SSD 125-1). ), Storage for information about itself and the paired SSD (SSD 125-2). 520-2). In some embodiments, the information stored in the storage devices (505-1, 505-2, 510-1, 510-2, 515-1, 515-2, 520-1, and 520-2) is: The information includes information unique to each device, such as a serial number of a GUID (Globally Unique ID). In another embodiment, the storage devices (505-1, 505-2, 510-1, 510-2, 515-1, 515-2, 520-1, 520-2) are unique or almost certainly unique. Store the agreed information between the paired devices. An example is an algorithm where two parties agree on a shared secret used for communication security between the two parties via an unsecured connection. That is, the SSD 125-1 and the coprocessor 130-1 can use these algorithms that agree on a shared secret to be used as agreed information. Alternatively, when the SSD 125-1 and the coprocessor 130-1 are physically paired, a common piece of data at the time of manufacturing is allocated. If the paired device uses some unique information that is not used by other devices, the devices (125-1, 125-2, 130-1, and 130-2) will use each device in the pairing Instead of storing information about, it may only be necessary to store unique information, at least for pairing purposes.

  When the operating system 405 queries individual devices for information about itself, each device returns information about the pairing. Therefore, as an example, the SSD 125-1 stores its own information in the storage device 505-1 and stores information on the coprocessor 130-1 in the storage device 505-2. Similarly, the coprocessor 130-1 stores its own information in the storage 515-2, and stores information on the SSD 125-1 in the storage 515-1. Next, the operating system 405 uses the information from the storage devices (505-1 to 505-2, 515-1 to 515-2) to determine whether the SSD 125-1 and the coprocessor 130-1 have been paired. Is determined. This information may be, for example, a GUID or other information that is expected to be unique, such as a calculated shared secret, or the serial numbers of various devices. By way of example, if each of two (or more) devices provides its own serial number and the serial number of their pair, and the serial numbers correspond as expected, the operating system 405 may determine that the two devices are paired. You can consider being ringed. Similarly, if each of the two (or more) devices provides a unique identifier (or an identifier that is expected to be unique), the fact that all of the devices provide that identifier means that Should be considered to have been done. In this manner, the operating system 405 can properly generate the pairing of the virtual IDs (410, 415, 420, and 425).

  FIG. 6 is a diagram illustrating the operating system 405 of FIG. 5 that queries the SSD 125-1 and the coprocessor (130-1) of FIG. 1 to pair devices. In FIG. 6, the operating system 405 transmits a query 605 to the SSD 125-1 requesting details of the device. Existing operating systems query the device to determine device characteristics and characteristics as part of the boot. The BIOS (Basic Input / Output System) may also query to find out which device is connected. What is new in response 610 is that SSD 125-1 includes information about itself and information about coprocessor 130-1. Similarly, the operating system 405 sends a query 615 to the coprocessor 130-1 requesting details of the device. That is, the coprocessor (130-1) transmits a response 620 including information on itself and information on the SSD 125-1. When the operating system 405 receives the responses (610 and 620), the operating system 405 uses the information to determine whether the SSD 125-1 and the coprocessor 130-1 have been paired, as shown in operation 625. judge. Thereafter, the operating system 405 stores the pairing information.

  When the operating system 405 knows which storage device is paired with which coprocessor, the operating system 405 makes this information available to applications and / or users. By way of example, operating system 405 provides an API (Application Programming Interface) used by applications to query operating system 405 to pair information. For example, the application transmits a query requesting the SSD 125-1 paired with the device to the SSD 125-1 via the API. Next, the operating system 405 responds with the information that the coprocessor 130-1 has been paired with the SSD 125-1. Other applications request information about a paired device associated with a particular piece of data. By way of example, a particular file (or key value object) that a storage device has stored its data and another device has been paired with that storage device, or may be stored in another format on the storage device. Data). Thereafter, the operating system 405 determines which storage device stores the data, and then returns information on the storage device and the pairing. (Of course, the application can transmit two API queries: one determines a specific storage device to store the target data, and the other is paired with the storage device. Determine the device. Combining the two queries into one is a simplification.)

  When the application knows which device is paired via the API, the application uses that information accordingly. As an example, the coprocessors (130-1, 130-2) of FIG. 1 are two FPGAs that provide a data acceleration service. When the application knows the storage device storing the target data, the application transmits the request to the FPGA paired with the storage device requesting the data acceleration service of the target data. The same principle applies to any other functions provided by the coprocessors (130-1, 130-2) of FIG. That is, data acceleration is used only as an example of a function.

  At this point, one question remains. That is, how does the device recognize information that identifies the device in pairing? The answer is clear if the information is assigned as unique data shared by the paired device at the time of manufacture. However, if the devices use a serial number or other data that is unique to each device to help identify their pairing, the answer is not so easy. 7 to 9 show how the device obtains this information.

  FIG. 7 is a diagram illustrating the SSD 125-1 and the coprocessor 130-1 of FIG. 1 as a single form factor in one embodiment of the present invention. In FIG. 7, the SSD 125-1 and the coprocessor 130-1 communicate using a hardware interface connecting the devices. As an example, this hardware interface is an SMBus (System Management Bus) that connects the SSD 125-1 and the coprocessor 130-1. When the SMBus is used, either the device SSD125-1 or the coprocessor 130-1 is a master device, and the other is a slave device or both are master devices on a multi-master bus. By way of example, in some embodiments, SSD 125-1 is the master of SMBus 705 and coprocessor 130-1 is the slave.

  As shown, the SSD 125-1 is connected to the machine 105 of FIG. 1 via an out-of-band connection and an in-band connection. For example, the in-band connection 710 includes a message transmitted via a PCI Express (PCIe) connection, while the out-of-band connection 715 includes, for example, (the SSD 125-1 is a slave and a BMC (Board Management)). Controller is the master, or both SMB125-1 and BMC are masters on multiple master buses). In general, the in-band connection 710 is used for a conventional request such as a read / write request issued to the SSD 125-1 and uses the function of the coprocessor 130-1 while the out-of-band connection is used. 715 is used for control type requests. For example, it includes a query for the current operating temperature of SSD 125-1 and / or coprocessor 130-1. When in-band concatenation 710 is used to communicate with coprocessor (130-1), SSD 125-1 operates as a pass-through device that relies on messages to coprocessor 130-1. Alternatively, the SSD 125-1 operates with some translator functions that convert the request received from the machine 105 of FIG. 1 into another format for transmission to the coprocessor (130-1).

  FIG. 8 is a diagram illustrating the SSD 125-1 and the coprocessor 130-1 of FIG. 1 as a single form factor in another embodiment of the present invention, in contrast to FIG. In the embodiment shown in FIG. 8, the coprocessor 130-1 is directly connected to the in-band connection 710 instead of the SSD 125-1. In this embodiment, coprocessor 130-1 operates as a pass-through device that relies on messages intended for SSD 125-1 to be sent to SSD 125-1. Alternatively, co-processor 130-1 operates with some translator functions that translate requests received from machine 105 of FIG. 1 into another format for transmission to SSD 125-1. In all other aspects, the SSD 125-1 and the coprocessor 130-1 operate similarly to the SSD 125-1 and the coprocessor 130-1 as in FIG.

  7 and 8 illustrate the possibility that both the SSD 125-1 and the coprocessor 130-1 may be sold in the same form factor, and the SSD 125-1 and the coprocessor 130-1 may be used in a system in which If there are some forms of hardware interface 505 that allow communication between two paired devices to share pairing information with system 405, they may be sold as separate components.

  FIG. 9 is a diagram illustrating the SSD 125-1 and the coprocessor 130-1 of FIG. 1 that construct a pairing according to an embodiment of the present invention. The SSD 125-1 and the coprocessor 130-1 use FIG. 9 when sharing a hardware interface such as the hardware interface 705 in FIGS. 7 and 8. In FIG. 9, the SSD 125-1 starts an inquiry about the device information from the coprocessor 125-1. The SSD 125-1 transmits the identification device 905 to the coprocessor 130-1 (this command and all other commands in FIGS. 9 and 10 are NVMe commands or commands using other protocols). . Coprocessor 130-1 responds with an identification response 910 containing unique information related to the pairing of SSD 125-1 and coprocessor 130-1. This information includes, by way of example, a GUID or manufacturer model number and serial number of coprocessor 130-1. Upon receiving the identification response 910, the SSD 125-1 stores the information of the coprocessor 130-1. As an example, it is stored in the storage 502-2 of FIG. Thereafter, the SSD 125-1 transmits the setting information 915 including the unique information of the SSD 125-1, for example, the GUID or the model number and the serial number of the manufacturer of the SSD 125-1. After that, the coprocessor 130-1 stores the information of the SSD 125-1. As an example, it is stored in the storage 515-1 of FIG. Next, the coprocessor 130-1 transmits a setting response 920 to notify the SSD 125-1 that the pairing data of the setting pairing data (Set Pairing Data) command has been received. Finally, the SSD 125-1 transmits the set advanced data (Set Advanced Data) 925 to inform the coprocessor 130-1 of any other data that the coprocessor 130-1 wants to know. Responds with an identification response (Set Response) 930.

  FIG. 10 is a diagram illustrating the SSD 125-1 and the coprocessor 130-1 of FIG. 1 that construct a pairing according to another embodiment of the present invention. FIG. 10 is similar to FIG. 9 except that coprocessor 130-1 initiates the exchange of information instead of SSD 125-1. In FIG. 10, the coprocessor 130-1 transmits the read identification data 1005 to the SSD 125-1. SSD 125-1 responds with a read response 1010 that contains unique information about the pairing of coprocessor 130-1 with SSD 125-1. This information includes, by way of example, a GUID or manufacturer model number and SSD125-1 serial number. Upon receiving the read response 1010, the coprocessor 130-1 stores, for example, information of the SSD 125-1. As an example, it is stored in the storage device 505-2 of FIG. Next, the coprocessor 130-1 transmits the setting identification data 1015 including information unique to the coprocessor 130-1. As an example, the configuration identification data 1015 including the GUID or the model number and serial number of the manufacturer of the coprocessor 130-1 is transmitted. Next, the SSD 125-1 stores the information of the coprocessor 130-1 in the storage 515-1 of FIG. 5 as an example. Next, the SSD 125-1 transmits a setting response 1020 to notify the coprocessor 130-1 that the pairing data of the setting identification data command has been received. Finally, the coprocessor 130-1 transmits a setting log page (Set Log Page) 1025 to notify the SSD 125-1 of any other data that the SSD 125-1 wants to know. Respond at 1030.

  FIG. 11 is a diagram illustrating a first topology including the SSD 125-1 and the coprocessor 130-1 of FIG. 1 according to an embodiment of the present invention. FIGS. 11-14 are US Patent Application No. filed on November 30, 2018, claiming the benefit of provisional application No. 16 / 207,080, filed on October 12, 2018, both of which are pending. No. 16 / 226,629, all applications being incorporated herein by reference for all purposes. However, while co-pending US patent application Ser. No. 16 / 260,087 considers the overall combination of PCIe switches including erasure coding, this specification is further considered with SSD and coprocessor architecture.

  FIG. 11 illustrates a PCIe switch having Look-Aside erasure coding logic 1105 embodied as a separate component of machine 105 of FIG. That is, the PCIe switch having the Look-Aside erasure coding logic 1105 is manufactured and sold separately from any other components such as the processor 110, the storage device 125-1, or the coprocessor 130-1 of FIG. .

  A PCIe switch having Look-Aside erasure coding logic 1105 is connected to the storage device 125-1. In FIG. 11, the PCIe switch having the Look-Aside erasure coding logic 1105 is illustrated as being connected to only one storage device that may not support erasure coding. In other words, the erasure coding is to perform striping, chunking, grouping, and parity or use of code information or at least two storage devices or at least two of the storage devices. Request part. However, a single storage device PCIe switch with Look-Aside erasure coding logic 1105 also offers some advantages. As an example, the PCIe switch having the Look-Aside erasure coding logic 1105 uses an error correcting code in the storage device 125-1 when the service is not natively provided by the storage device 125-1. Or encrypt the data stored in the storage device 125-1.

  Storage device 125-1 is coupled to FPGA 205, which is an example of coprocessor 130-1 in FIG. 1 (for the remainder of the description of FIGS. 11-14, any reference to FPGA 205 is shown in FIG. 2). Any alternative coprocessor, or more generally, is understood to include a reference to coprocessor 130-1 of FIG. 1). The FPGA 205 supports acceleration. That is, there are situations where data must be processed and discarded. Loading all of the data into the processor 110 of FIG. 1 to perform the processing is costly and time consuming. That is, the calculations are made easier near the data. The FPGA 205 supports performing calculations near a storage device while avoiding the need for data to be loaded into the processor 110 of FIG. 1 to perform the calculations. That is, this concept is referred to as "acceleration". FPGA-based acceleration is described in US Provisional Patent Application No. 62 / 642,568 filed on March 13, 2018, US Provisional Application No. 62 / 641,267 filed on March 13, 2018, and This is further described in US Patent Application No. 16 / 122,865, filed September 5, 2018, claiming the benefit of US Provisional Patent Application No. 62 / 638,904, filed March 5, 2018, US Patent Application No. 16 / 124,179 filed on September 6, 2018, which is a continuation application of US Patent Application No. 16 / 122,865 filed on September 5, 2018; US Patent Application No. 16 / 124,182 filed on September 6, 2018 and US Patent Application No. 16 / 124,1 filed on September 6, 2018 3 is coupled referenced together herein. FIG. 11 shows an FPGA 205 that is closer to the storage device 125-1 because the purpose of acceleration is to process the data without transmitting it to the processor 110 of FIG. However, it is noted that the particular arrangement shown in FIG. 11 may not be required. That is, the FPGA 205 may be located between the PCIe switch having the Look-Aside erasure coding logic 1105 and the storage device 125-1.

  Apart from data acceleration, the FPGA 205 provides another function that supports the storage device 125-1. For example, the FPGA 205 implements a data deduplication function on the storage device 125-1 in order to reduce the number of times that the same data is stored in the storage device 125-1. The FPGA 205 determines whether the particular data has been stored more than once on the storage device 125-1, and determines the various logical block addresses (or other information used by the host to identify the data) and storage. Build an association between the location on the device where the data is stored and delete additional copies.

  Alternatively, the FPGA 205 may use a T10DIF (Data Integrity) that uses a CRC (Cyclic Redundancy Correction) for data loss due to an error in the operation of the storage device 125-1 or end-to-end protection. In order to protect the data from the storage device 125-1, a function of data integrity on the storage device 125-1 such as adding an error correction code is implemented. As described above, the FPGA 205 detects when an error occurs in data being transmitted or read on the storage device 125-1 or when data is being transmitted, or restores the original data. The FPGA 205 implements a data integrity function so that the host does not recognize that the data integrity function is provided. That is, the host sees only the data itself which is not the error correction code.

  Alternatively, the FPGA 205 can implement a data encryption function on the storage device 125-1 for protection from a party who is not authorized to access data on the storage device 125-1. That is, if an appropriate encryption key is not provided, the data returned from FPGA 205 may be meaningless to the requestor. The host provides an encryption key used when reading and writing data. Alternatively, the FPGA 205 automatically performs encryption and decryption of data. That is, the FPGA 205 stores the encryption key (and generates the encryption key on behalf of the host) and determines the appropriate encryption key to use based on who requests the data.

  Alternatively, the FPGA 205 implements a data compression function on the storage device 125-1 to reduce the amount of space required to store data in the storage device 125-1. When writing data to the storage device 125-1, the FPGA 205 implements a function of compressing the data provided by the host into a smaller amount of storage device, and reads the compressed data (reads data from the storage device 125-1). Sometimes it stores (along with any information needed to restore the original data). When reading data from the storage device 125-1, the FPGA 205 reads the compressed data (along with any information necessary to restore the original data from the compressed data) and restores the original data. Uncompress.

  Any desired implementation of data deduplication, data integrity, data encryption, and data compression may be used. Embodiments of the present invention are not limited to any particular implementation of any of these features.

  The FPGA 205 can also implement any combination of functions on the storage device 125-1 as needed. As an example, the FPGA 205 implements both data compression and data integrity (since data compression increases the sensitivity of the data to errors, a single error in the data stored in the storage device 125-1 can be very large). May render the data unusable). Alternatively, FPGA 205 implements both data encryption and data compression (to protect data while using as little storage for data as possible). Another combination of two or more functions is provided by FPGA 205.

  When implementing any of these functions in terms of overall operation, FPGA 205 reads data from an appropriate source. Although the term “source” is a singular noun, embodiments of the present invention may read data from multiple sources (eg, multiple storage devices) where appropriate. The FPGA 205 performs appropriate operations on the data, such as data acceleration, data integration, data encryption, and / or data compression. Next, the FPGA 205 takes an appropriate action according to the result of the operation. That is, as an example, the result is transmitted to the machine 105 of FIG. 1 or the data is written to the storage device 125-1.

  Although the above functions have been described with reference to the FPGA 205 of FIG. 11, the embodiment of the present invention includes these functions at an arbitrary position in the system including the FPGA. Note that embodiments of the present invention allow the FPGA 205 to access data from “distant” storage devices. By way of example, returning to FIG. 1, assume that storage device 125-1 includes an FPGA similar to FPGA 205, but storage device 125-2 does not have such a coprocessor. The FPGA included in the storage device 125-1 is used to apply a function to the storage device 125-2 by transmitting a request to the storage device 125-2. As an example, if the FPGA of the storage device 125-1 provides data acceleration, the FPGA of the storage device 125-1 reads data from the storage device 125-2, performs appropriate acceleration, and then performs To the appropriate destination (such as machine 105 in FIG. 1).

  In FIG. 11 (and in the topology shown in FIGS. 12-14 below), a PCIe switch having Look-Aside erasure coding logic 1105 is mounted on a device that is not suitable for erasure coding. By way of example, a PCIe switch with Look-Aside erasure coding logic 1105 may be another storage device with built-in erasure coding capability or a device other than a storage device such as the FPGA 205 of FIG. 11 or the GPU 215 of FIG. Attached to. All of these devices are described as devices that are not compatible with erasure coding (or at least for erasure coding with a PCIe switch that includes Look-Aside erasure coding logic 1105).

  If the PCIe switch with Look-Aside erasure coding logic 1105 is coupled to a device that is not suitable for erasure coding, the system has a variety of alternative approaches that can be used. In one embodiment of the present invention, the Look-Aside erasure coding logic of the PCIe switch having the Look-Aside erasure coding logic 1105 is disabled when including any devices that are not suitable for erasure coding. Thus, as an example, if the PCIe switch having the Look-Aside erasure coding logic 1105 is connected to the FPGA 205 of FIG. 11 or the GPU 215 of FIG. 2, or the storage device having the native erasure coding logic, the Look-Aside erasure coding logic 1105 is used. Cannot be used with erasure coding. A decision to disable the Look-Aside erasure coding logic of a PCIe switch that includes the Look-Aside erasure coding logic 1105 is not necessarily translated to another PCIe switch that includes the Look-Aside erasure coding logic in the same or another chassis. Note that this is not the case. By way of example, looking briefly at FIG. 13, FIG. 13 shows two PCIe switches having Look-Aside erasure coding logic (1105 and 1305), one of which is enabled with Look-Aside erasure coding logic. The other has Look-Aside erasure coding logic disabled.

  Other embodiments of the present invention can disable devices that are not suitable for erasure coding and treat them as if they were not tied to a PCIe switch containing Look-Aside erasure coding logic 1105 at all. In such an embodiment of the present invention, a PCIe switch having Look-Aside erasure coding logic 1105 enables Look-Aside erasure coding logic for storage device 125-1, and any other suitable for erasure coding. The storage device is disabled as if it were not connected to a PCIe switch having Look-Aside erasure coding logic 1105.

  In another embodiment of the present invention, a PCIe switch having Look-Aside erasure coding logic 1105 enables Look-Aside erasure coding logic for storage devices covered by the Look-Aside erasure coding logic, but without access. The other devices that are not suitable for erasure coding are still enabled. This embodiment of the invention is the most complex implementation. That is, the PCIe switch having Look-Aside erasure coding logic 1105 determines which device is compatible with erasure coding and which device is not, and then analyzes the traffic and transmits the traffic to the virtual storage device. (In this case, the traffic is intercepted by the Look-Aside erasure coding logic) or not (in this case, the traffic is transmitted to its original destination).

  The machine 105 of FIG. 1 is an embodiment of the present invention that does not provide all the functions of the installed device. That is, in one embodiment of the present invention, erasure coding is disabled by the presence of devices that are not suitable for erasure coding, or these devices are disabled by a PCIe switch that includes Look-Aside erasure coding logic 1105. Yes, the machine 105 of FIG. 1 informs the user of this fact. This notification is provided by the processor 110 of FIG. 1, a PCIe switch including BMC and Look-Aside erasure coding logic. In addition to notifying the user that some features have been disabled, the notification may also inform the user how to reconfigure the machine 105 of FIG. 1 to allow for the added features. . For example, the notification suggests that devices that are not suitable for erasure coding are coupled to specific slots in the midplane (possibly these slots are coupled to PCIe switches that include Look-Aside erasure coding logic 1305). ). The storage device that is not suitable for erasure coding is connected to another slot such as a slot connected to a PCIe switch including the erasure coding logic 1105. In this way, at least some storage devices suitable for erasure coding can benefit from an erasure coding scheme without blocking access to other devices not suitable for erasure coding.

  FIG. 12 is a diagram illustrating a second topology including the SSD and the coprocessor of FIG. 1 according to another embodiment of the present invention. In FIG. 12, a PCIe switch having Look-Aside erasure coding logic 1105 is located within FPGA 205. That is, the FPGA 205 implements a PCIe switch having the Look-Aside erasure coding logic 1105. The FPGA 205 having the Look-Aside erasure coding logic 1105 and the PCIe switch are connected to the storage devices (125-1 to 125-4). Although FIG. 12 illustrates an FPGA 205 and a PCIe switch having Look-Aside erasure coding logic 1105 coupled to four storage devices (125-1 to 125-4), embodiments of the present invention may be implemented in any number of storage devices. Storage devices (125-1 to 125-4).

  In general, the topology shown in FIG. 12 is embodied in a single shell or housing containing all the components shown (SSDs (125-1 through 125-4) (It may be a separate flash memory instead of a self-contained SSD). That is, instead of being sold as a separate component, the entire structure shown in FIG. 12 is sold as a single unit. However, embodiments of the present invention provide a U.S.M. 2, M. 3, or a riser card that has a connector such as SFF-TA-1008 and that connects to the machine 105 of FIG. 1 (possibly to the midplane) having a connector on one end. FIG. 12 shows a PCIe switch having the Look-Aside erasure coding logic 1105 as a part of the FPGA 205, and the PCIe switch having the Look-Aside erasure coding logic 1105 is embodied as a part of the smart SSD.

  FIG. 13 is a diagram illustrating a third topology including the SSD and the coprocessor of FIG. 1 according to an embodiment of the present invention. The third topology for using the PCIe switch having the Look-Aside erasure coding logic 1105 of FIG. Show the topology. FIG. 13 shows two PCIe switches having Look-Aside erasure coding logic (1105 and 1305) connecting up to 24 storage devices (125-1 to 125-6) between them. Each of the PCIe switches having Look-Aside erasure coding logic (1105 and 1305) has four PCIe lanes used in each direction to communicate with any of the storage devices (125-1 to 125-6). ) With 96 PCIe lanes. That is, each PCIe switch having Look-Aside erasure coding logic (1105 and 1305) supports up to 12 storage devices. In order to support erasure coding for the entire storage device supported by multiple PCIe switches having Look-Aside erasure coding logic (1105 and 1305), one PCIe switch having Look-Aside erasure coding logic 1105 requires all PCIe switches. It has Look-Aside erasure coding logic that is designated and responsible for erasure coding across the device. Other PCIe switches with Look-Aside erasure coding logic 1305 operate purely as PCIe switches with Look-Aside erasure coding logic disabled. The selection of which PCIe switch to select to handle erasure coding is accomplished in any desired manner. That is, by way of example, two PCIe switches negotiate between them, or the first listed PCIe switch is designated to handle erasure coding. PCIe switches selected to handle erasure coding report virtual storage devices (across two PCIe switches), while PCIe switches that do not handle erasure coding may not report downstream devices. There is (the processor 110 of FIG. 1 prevents attempts to access storage devices that are part of the erasure coding scheme).

  Note that PCIe switches with Look-Aside erasure coding logic (1105 and 1305) can all be in the same chassis, while PCIe switches with Look-Aside erasure coding logic (1105 and 1305) can be in different chassis. That is, the erasure coding scheme can extend the storage device across multiple chassis. What is needed is that the PCIe switches of the various chassis must be able to negotiate with each other about where the storage devices that will be part of the erasure coding scheme are located. Also, embodiments of the present invention are not limited to two PCIe switches having Look-Aside erasure coding logic (1105 and 1305). That is, the storage device included in the erasure coding scheme is connected to an arbitrary number of PCIe switches having the Look-Aside erasure coding logic 1105.

  The host logical block address (LBA) is split into PCIe switches with Look-Aside erasure coding logic (1105 and 1305) in any desired manner. As an example, the least significant bit of the host LBA is used to identify which PCIe switch with Look-Aside erasure coding logic (1105 or 1305) includes a storage device that stores the data containing that host LBA. Is done. When two or more PCIe switches having Look-Aside erasure coding logic are used, a plurality of bits are used to determine which PCIe switch having Look-Aside erasure coding logic manages a storage device storing data. used. Once the appropriate PCIe switch with Look-Aside erasure coding logic is identified, the transmission is routed to the appropriate PCIe switch with Look-Aside erasure coding logic (Look-Aside erasure coding logic enabled). (It is assumed that transmission is not scheduled to a storage device connected to a PCIe switch having Look-Aside erasure coding logic.)

  In another embodiment of the present invention, a single PCIe switch having Look-Aside erasure coding logic virtualizes all storage devices connected to two PCIe switches having Look-Aside erasure coding logic. Each PCIe switch with Look-Aside erasure coding logic creates a separate virtual storage device (including a separate erasure coding domain). In this way, different erasure coding domains are generated for different customers, albeit with smaller capacities.

  FIG. 13 shows that only the storage devices (125-1 to 125-6) are connected to PCIe switches having Look-Aside erasure coding logic (1105 and 1305), and all the storage devices (125-1 to 125-6) are connected. Although meant to be used with an erasure coding scheme, the embodiments of the invention described above are not so limited. That is, PCIe switches having Look-Aside erasure coding logic (1105 and 1305) may have devices coupled to them that are not suitable for erasure coding. Along with storage devices suitable for erasure coding grouped under other PCIe switches with Look-Aside erasure coding logic 1105, these devices are under a single PCIe switch with Look-Aside erasure coding logic. Be grouped. In this manner, one (or some) PCIe switch with Look-Aside erasure coding logic that enables the Look-Aside erasure coding logic, and Look-Aside erasure coding logic that disables the Look-Aside erasure coding. The optimal functionality of the machine 105 of FIG. 1 is achieved with one (or several) PCIe switches having

  FIG. 14 is a diagram illustrating a fourth topology including the SSD and the coprocessor of FIG. 1 according to another embodiment of the present invention. In FIG. 14, as compared with FIG. 13, the PCIe switches having the Look-Aside erasure coding logic (1105, 1305, and 1405) are hierarchically configured. The PCIe switch with Look-Aside erasure coding logic 1105 at the top of the hierarchy manages and thereby enables erasure coding for all storage devices below the PCIe switch with Look-Aside erasure coding logic 1105 in the hierarchy. Look-Aside erasure coding logic. On the other hand, PCIe switches having Look-Aside erasure coding logic (1305 and 1405) are required to be managed by the Look-Aside erasure coding logic of the PCIe switch having Look-Aside erasure coding logic 1105. ) With their Look-Aside erasure coding logic disabled.

  FIG. 14 shows three PCIe switches having Look-Aside erasure coding logic (1105, 1305, and 1405) configured in a two-tier hierarchy, but the present invention provides a method for implementing these PCIe switches. It is not limited to the number of PCIe switches included in the agreement or within its hierarchical agreement. Thus, the present embodiment supports any number of PCIe switches with Look-Aside erasure coding logic negotiated at any desired tier.

  The embodiment of the present invention described above with reference to FIGS. 1 to 14 focuses on a single port storage device. However, embodiments of the present invention are extended to dual port storage devices in which one (or more) storage devices communicate with multiple PCIe switches having Look-Aside erasure coding logic. In these embodiments of the present invention, if the PCIe switch having the Look-Aside erasure coding logic 1105 of FIG. 11 cannot communicate with the dual port storage device, the PCIe switch having the Look-Aside erasure coding logic 1105 may be connected to the storage device. Send the transmission to the PCIe switch with Look-Aside erasure coding logic 1305 to attempt communication. The PCIe switch having the Look-Aside erasure coding logic 1305 effectively operates as a bridge that allows the PCIe switch having the Look-Aside erasure coding logic 1105 to communicate with the storage device.

  FIG. 15 is a flowchart illustrating a procedure of the SSD 125-1 of FIG. 1 (or the coprocessor 130-1 of FIG. 1) for querying a partner for pairing data according to an embodiment of the present invention. In FIG. 15, in step 1505, the SSD 125-1 of FIG. 1 transmits the identification device 905 of FIG. 9 to its partner (or the coprocessor 130-1 of FIG. 1 converts the read identification data 1005 of FIG. Transmit to partner). At step 1510, the SSD 125-1 of FIG. 1 receives the identification response 910 of FIG. 9 (or the coprocessor 130-1 of FIG. 1 receives the read response 1010 of FIG. 10). In step 1515, the SSD 125-1 of FIG. 1 stores the received pairing information in the storage device 505-2 of FIG. 5 (or the coprocessor 130-1 of FIG. 1 stores the received pairing information in FIG. In the storage 515-1). At step 1520, the SSD 125-1 of FIG. 1 accesses its own pairing information from the storage device 505-1 of FIG. 5 (or the coprocessor 130-1 of FIG. 1 accesses the storage 515-2 of FIG. 5). To access that pairing information). Finally, in step 1525, the SSD 125-1 of FIG. 1 transmits the set of pairing data 915 of FIG. 9 to its partner (or the coprocessor 130-1 of FIG. 1 transmits the set of identification data of FIG. 10). 1015), whereby the partner stores the pairing information.

  FIG. 16 is a flowchart illustrating a procedure of the SSD 125-1 of FIG. 1 (or the coprocessor 130-1 of FIG. 1) for receiving a query for pairing data from a partner according to an embodiment of the present invention. In FIG. 16, in step 1605, the SSD 125-1 of FIG. 1 receives the read identification data 1005 of FIG. 10 from the coprocessor 130-1 of FIG. 1 (or the coprocessor 130-1 of FIG. Of the identification device 905 of FIG. At step 1610, the SSD 125-1 of FIG. 1 accesses the pairing information from the storage device 505-1 of FIG. (Or, the coprocessor 130-1 in FIG. 1 accesses the pairing information from the storage 515-2 in FIG. 5). In operation 1615, the SSD 125-1 of FIG. 1 transmits the pairing information of the read response 1010 of FIG. 10 to the coprocessor 130-1 of FIG. 1 (or the coprocessor 130-1 of FIG. The pairing information of the identification response 910 is transmitted). In step 1620, the SSD 125-1 of FIG. 1 receives the setting identification data 1015 of FIG. 10 from the coprocessor 130-1 of FIG. 1 (or the coprocessor 130-1 of FIG. The setting pairing data 915 shown in FIG. Finally, in step 1625, the SSD 125-1 of FIG. 1 stores the pairing information of the coprocessor 130-1 of FIG. 1 in the storage device 505-2 of FIG. 5 (the coprocessor 130-1 of FIG. The pairing information of the SSD 125-1 in FIG. 1 is stored in the storage 515-1 in FIG. 5).

  FIG. 17 is a flowchart illustrating a procedure of the SSD 125-1 and / or coprocessor 130-1 of FIG. 1 to respond to a query from the pairing partner and the associated operating system 405 of FIG. 5 according to one embodiment of the present invention. It is. 17, at step 1705, the SSD 125-1 and / or the coprocessor 130-1 of FIG. 1 receives the query (605 and / or 615) of FIG. 6 from the operating system 405 of FIG. In operation 1710, the SSD 125-1 and / or the coprocessor 130-1 of FIG. 1 communicates with the storage device (505-1 and / or 515-2) of FIG. ) Access pairing information such as a unique ID or manufacturer model number and / or serial number. In step 1715, the SSD 125-1 and / or the coprocessor 130-1 of FIG. 1 communicates with the partner device from the storage device (505-2 and / or 515-1) of FIG. Access pairing information such as model number and / or serial number. Finally, in step 1720, the SSD 125-1 and / or the coprocessor 130-1 of FIG. 1 transmits pairing information regarding the paired device to the operating system 405 of FIG.

  FIG. 18 is a flowchart illustrating a procedure of the operating system 405 of FIG. 5 for querying and pairing the SSD 125-1 and the coprocessor 130-1 of FIG. 1 according to an embodiment of the present invention. In FIG. 18, at step 1805, the operating system 405 of FIG. 5 transmits (to the operating system 405 of FIG. 5) a query such as the query (605 and / or 615) of FIG. 6 to the device indicated by the virtual ID. In operation 1810, the operating system 405 of FIG. 5 receives the pairing information from the device. At step 1815, the operating system 405 of FIG. 5 transmits (to the operating system 405 of FIG. 5) another query, such as the query (605 and / or 615) of FIG. 6, to another device indicated by the virtual ID. At step 1820, the operating system 405 of FIG. 5 receives the pairing information from the device. At step 1825, the operating system 405 of FIG. 5 determines that the two devices have provided the same pairing information, and somehow pairs the devices within the operating system 405 of FIG. Finally, at step 1830, operating system 405 of FIG. 5 provides an API to the application that supports the query for device pairing.

  FIG. 19 is a flowchart illustrating a procedure of the operating system of FIG. 5 for responding to a query from an application regarding pairing information for a device according to an embodiment of the present invention. In FIG. 19, in step 1905, the operating system 405 of FIG. 5 receives a request for pairing of a specific device from an application. In operation 1910, the operating system 405 of FIG. 5 detects the requested device in the table storing the pairing information. At step 1915, the operating system 405 of FIG. 5 determines the pairing of the devices in the table. At step 1920, the operating system 405 of FIG. 5 returns to the application information regarding device pairing.

  Alternatively, in operation 1925, the operating system 405 of FIG. 5 receives a request for pairing information on an identifier of a data (a file, an object, a key, etc.) from an application. In operation 1930, the operating system 405 of FIG. 5 determines a device that stores the data identified by the data identifier. At this point, as indicated by arrow 1935, operating system 405 of FIG. 5 performs steps 1910 and 1915 as described above. Next, as indicated by arrow 1940, operating system 405 of FIG. 5 returns to application information for both the data storage device and its pair.

  15 to 19 show some embodiments of the present invention. However, a person having ordinary skill in the art may change the order of each step, omit some steps, or include a connection not shown in the drawings, thereby changing the other embodiments of the present invention. You should realize that it is possible. All these variations of the flowchart, whether explicitly described or not, are considered embodiments of the present invention.

  Embodiments of the present invention provide technical advantages over the prior art. Embodiments of the present invention allow the SSDs (125-1 to 125-2) and the coprocessors (130-1 to 130-2) of FIG. 1 to determine pairing information for a pairing partner. Next, the SSDs (125-1 to 125-2) and the coprocessors (130-1 to 130-2) of FIG. 1 provide the pairing information to the operating system 405 of FIG. 405 stores information on whether any device is paired with another device. If the operating system 405 of FIG. 5 has a properly paired device, the operating system 405 of FIG. 5 provides this information to the application via an API and determines which service is performed. An application can request a service from the coprocessor (130-1 to 130-2) of FIG. 1 paired with the SSD (125-1 to 125-2) of FIG. 1 that stores data.

  The following description provides a brief, general description of a suitable machine or machine in which some aspects of the present inventive concepts may be embodied. One or more machines may include instructions, at least in part received from other machines, interaction with a virtual reality (VR) environment, biofeedback, other input signals, as well as keyboards, mice, etc. It is controlled by an input from a normal input device. As used herein, the term "machine" broadly includes a single machine, a virtual machine, multiple machines or multiple virtual machines, or systems coupled to communicate with devices that work together. Intend. Exemplary machines include, for example, personal computers, workstations, servers, portable computers, handheld devices, portable devices, as well as transportation devices such as personal or public transportation, such as cars, trains, taxis, and the like. Includes computing devices such as phones, tablets, and the like.

  The machine or machines include embedded controllers such as programmable or non-programmable logic devices or arrays, ASICs (Application Specific Integrated Circuits), embedded computers, smart cards, and the like. A machine or machines utilize one or more connections to one or more remote machines, such as via a network interface, modem, or other communication connection. The machines are interconnected by means of a physical and / or logical network such as an intranet, the Internet, local area networks (LANs), wide area networks (WANs), and the like. Those skilled in the art will recognize that network communications can be performed on a variety of wired and / or wireless networks, including radio frequency (RF), satellite, microwave, IEEE 802.11, Bluetooth, optical, infrared, cable, laser, and the like. You will understand that it utilizes short-range or long-range carriers and protocols.

  Embodiments of the present invention provide functions, procedures, data structures, applications, etc., that, when accessed by a machine, trigger the machine to perform work or define an abstract data type or low-level hardware context. It will be explained with reference or in cooperation with relevant data including. Associated data includes, for example, volatile and / or non-volatile memory such as RAM, ROM, etc., other storage devices, hard disk drives, floppy disks, optical storage, tape, flash memory, memory sticks ( (Registered trademark), digital video disc, biological storage, and the like. Related data is transmitted in the form of packets, serial data, parallel data, transmission signals, etc. via a transmission environment including a physical and / or logical network, and is used in a compressed or encrypted format. . The associated data is used in a distributed environment and stored locally and / or remotely for machine access.

  Embodiments of the present invention can be performed by one or more of a number of processors, and as described herein, existent non-transitory machine-readable devices that include commands that perform the components of the present inventive concepts. Including various recording media.

  The various operations of the methods described above may be performed by any suitable means of performing the operations, such as various hardware and / or software components, circuits, and / or modules. The software constitutes an ordered list of executable commands for implementing the logical functions, and is based on or associated with a device, such as a system, a device, a single or multi-core processor, or a system including a processor, for performing the commands. Embedded in any "processor readable storage medium" for use.

  The methods or algorithms and blocks or steps of the functions described in connection with the embodiments disclosed herein may be embodied by software modules or a combination of both executed by a processor directly in hardware. When embodied in software, the functions are stored or transmitted as one or more commands or codes on a tangible and non-transitory computer readable medium. RAM (Random Access Memory), Flash Memory, ROM (Read Only Memory), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Register, Drivable, Rek, DvR Embedded in any other form of storage medium.

  Where there are principles of the inventive concept described and illustrated with reference to the illustrated embodiments, the illustrated embodiments may be modified in arrangement and detail without departing from these principles, and in any required manner. It should be understood that they are combined. Although the above description has concentrated on specific embodiments, other configurations are also contemplated. In spite of the specifics, such as "according to an embodiment of the present invention" and the like used herein, these phrases generally refer to the possibilities of the embodiments, It is not intended to limit the technical idea of the present invention to the configuration of the specific embodiment. As used herein, these terms refer to the same or different embodiments that can be combined with other embodiments.

  The above embodiments are not to be construed as limiting the technical idea of the present invention thereto. Although only a few embodiments have been described, those skilled in the art will appreciate that many modifications can be made to these embodiments without substantially departing from the novel description and advantages described herein. Will understand well. Accordingly, all such modifications are intended to be within the scope of the invention.

  Embodiments of the present invention are extended without being limited to the following description. That is, the following matters.

Explanation 1. A system according to one embodiment of the present invention includes:
A first storage for data;
A second storage for a unique SSD ID (identifier);
A third storage for a unique coprocessor ID;
A fourth storage for a unique coprocessor ID;
A fifth storage for the unique SSD ID;
A hardware interface between the SSD and the coprocessor.

  Explanation 2. One embodiment of the present invention includes the system according to Description 1, wherein the coprocessors include a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), a Graphics Processing Unit (GPU), a GPU, and a GPU (TPU). It includes one of an erasure coding controller and a small processor core.

Explanation 3. Embodiments of the invention include a system according to Description 1, the hardware interface includes a SMBus (System Management Bus) and ^{I 2 C (Inter-Integrated Circuit} ) bus.

  Explanation 4. An embodiment of the present invention includes the system according to Description 1, wherein the fourth storage is a one-time programmable memory (OTP), a programmable read-only memory (PROM), an eraseable programmable read-only memory (EPROM), and an eraseable programmable read-only memory (EPROM). Electrically Erasable Programmable Read-Only Memory).

  Explanation 5. Embodiments of the present invention include a system according to Description 1, wherein the coprocessor operates to query the SSD of the unique SSD ID and store the unique SSD ID of the fifth storage.

  Explanation 6. An embodiment of the present invention includes a system according to Description 1, wherein the coprocessor operates to provide an SSD including a unique coprocessor ID.

  Description 7. Embodiments of the present invention include a system according to Description 1, wherein the SSD operates to query the coprocessor for a unique coprocessor ID and to store the unique coprocessor ID of the third storage.

  Explanation 8. Embodiments of the present invention include a system according to Description 1, wherein the SSD operates to provide a coprocessor that includes a unique SSD ID.

  Explanation 9. Embodiments of the present invention include a system according to Description 1, wherein the SSD operates to receive queries for the SSD and the coprocessor out-of-band.

  Explanation 10. An embodiment of the present invention includes a system according to description 9, wherein the SSD includes an SMBus concatenation for receiving queries out-of-band.

  Description 11. Embodiments of the present invention include a system according to description 9, wherein the SSD operates to respond to queries for both the unique SSD ID and the unique coprocessor ID.

  Description 12. An embodiment of the present invention includes the system according to description 9, wherein the query includes a non-volatile memory expression (NVMe) command (Management Interface).

  Description 13. One embodiment of the present invention includes the system according to Description 1, wherein the coprocessor operates to receive queries for the SSD and the coprocessor out of band.

  Description 14. Embodiments of the invention include a system according to description 13, wherein the coprocessor operates to respond to queries for both the unique SSD ID and the unique coprocessor ID.

  Description 15. An embodiment of the present invention includes the system according to description 13, wherein the query includes a non-volatile memory expression (NVMe) command (Management Interface).

  Description 16. An embodiment of the present invention includes a system according to Description 1, wherein the SSD operates to receive queries for the SSD and the coprocessor in-band.

  Description 17. An embodiment of the present invention includes a system according to Description 16, wherein the SSD includes a PCIe (Peripheral Component Interconnect Express) concatenation for receiving queries in-band.

  Description 18. An embodiment of the present invention includes a system according to description 16, wherein the SSD operates to respond to queries for both the unique SSD ID and the unique coprocessor ID.

  Description 19. An embodiment of the present invention includes the system according to Description 16, wherein the query includes a non-volatile memory expression (NVMe) command (Management Interface).

Description 20. The method according to one embodiment of the invention comprises:
Transmitting a query from the first device to the second device;
Receiving at the first device a response including the first pairing data from the second device;
Storing the first pairing data in a second storage of the first device;
Accessing the second pairing data from the first storage of the first device;
Transmitting the second pairing data from the first device to the second device.

  Description 21. An embodiment of the present invention includes a method according to Description 20, wherein each of the first device and the second device is a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU). It includes any one of a TPU (Tensor Processing Unit), an erasure coding controller, and a small processor core.

Description 22. An embodiment of the present invention includes a method according to description 20, wherein
Transmitting the query from the first device to the second device includes transmitting the query from the first device to the second device through a hardware interface between the first device and the second device,
Receiving a response from the second device at the first device includes receiving a response from the second device at the first device through a hardware interface between the first device and the second device;
The step of transmitting the second pairing data from the first device to the second device includes transmitting the second pairing data from the first device to the second device through a hardware interface between the first device and the second device. Includes the step of:

  Description 23. Embodiments of the invention include a method according to Description 20, wherein the second storage is an OTP (one-time programmable) memory, a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory and EROM), Electrically Erasable Programmable Read-Only Memory).

Description 24. The method according to one embodiment of the invention comprises:
Receiving at the first device a query from the second device;
Accessing the first pairing data from the first storage of the first device;
Transmitting a response including the first pairing data from the first device to the second device;
Receiving the second pairing data from the second device at the first device;
Storing the second pairing data in the second storage of the first device.

  Description 25. An embodiment of the present invention includes a method according to description 24, wherein each of the first device and the second device is a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), and the like. (Tensor Processing Unit), an erasure coding controller, and a small processor core.

Description 26. An embodiment of the present invention includes a method according to description 24,
Receiving a query from the second device at the first device includes receiving a query from the second device at the first device through a hardware interface between the first device and the second device;
Transmitting the response from the first device to the second device includes transmitting the response from the first device to the second device through a hardware interface between the first device and the second device;
The receiving of the second pairing data from the second device by the first device may include receiving the second pairing data from the second device by the first device through a hardware interface between the first device and the second device. Including stages.

  Description 27. Embodiments of the present invention include a method according to Description 24, wherein the second storage is a one-time programmable memory (OTP) memory, a programmable read-only memory (PROM), an eraseable programmable read-only memory (EPROM), and an electronic random access memory (EROM). Electrically Erasable Programmable Read-Only Memory).

Description 28. The method according to one embodiment of the invention comprises:
Receiving a query at the first device;
Accessing a first unique ID (Identifier) for the first device from the first storage of the first device;
Accessing a second unique ID for a second device paired with the first device from a second storage of the first device;
Transmitting a response including both the first unique ID and the second unique ID from the first device to the query.

Description 29. An embodiment of the present invention includes a method according to description 28,
Receiving the query at the first device includes receiving the query at the first device out of band.
Transmitting the response to the query from the first device includes transmitting the response to the query from the first device out of band.

Description 30. An embodiment of the present invention includes a method according to description 29,
Out-of-band, receiving the query on the first device includes receiving the query on the first device via a System Management Bus (SMBus) connection;
Transmitting a response to the query from the first device on the out-of-the-band includes transmitting a response to the query from the first device via the SMBus connection.

Description 31. An embodiment of the present invention includes a method according to description 28,
Receiving the query at the first device includes receiving the query at the first device in-band.
Transmitting the response to the query from the first device includes transmitting the response to the query from the first device in-band.

Description 32. An embodiment of the present invention includes a method according to description 31, wherein
Receiving the query on the first device includes receiving the query on the first device via a PCIe (Peripheral Component Interconnect Express) connection;
Transmitting a response to the query from the first device in-band includes transmitting a response to the query from the first device via a PCIe connection.

  Description 33. An embodiment of the present invention includes the method according to the description 31, wherein the query includes a non-volatile management expression (NVMe) command (Management Interface).

Description 34. The method according to one embodiment of the invention comprises:
Transmitting a first query to an SSD (Solid State Drive) indicated by the first virtual ID;
Receiving a unique SSD ID and a unique coprocessor ID from the SSD in response to the first query;
Transmitting a second query to the coprocessor indicated by the second virtual ID;
Receiving a unique SSD ID and a unique coprocessor ID from the coprocessor in response to the second query;
Pairing the first virtual ID and the second virtual ID.

  Description 35. An embodiment of the present invention includes the method according to Description 34, wherein transmitting the first query to the SSD includes transmitting the first query to the SSD out-of-band.

  Description 36. An embodiment of the present invention includes the method according to Description 35, wherein transmitting the first query to the SSD out-of-band includes transmitting the first query to the SSD via an SMBus connection.

  Description 37. An embodiment of the present invention includes the method according to Description 34, wherein transmitting the first query to the SSD includes transmitting the first query to the SSD in-band.

  Description 38. An embodiment of the present invention includes the method according to Description 37, wherein transmitting the first query to the SSD in-band includes transmitting the first query to the SSD via a PCIe connection.

  Description 39. An embodiment of the present invention includes the method according to description 34, wherein the first query includes a NVMe MI command.

  Description 40. An embodiment of the present invention includes the method according to description 34, wherein transmitting the second query to the coprocessor includes transmitting the second query to the coprocessor out of band.

  Description 41. An embodiment of the present invention includes the method according to Description 40, wherein transmitting the second query to the coprocessor out-of-band includes transmitting the second query to the coprocessor via an SMBus connection.

  Description 42. Embodiments of the present invention include a method according to description 34, wherein the second query includes a NVMe MI command.

  Description 43. Embodiments of the present invention include a method according to description 34, wherein the step of pairing the first virtual ID and the second virtual ID includes both the SSD and the coprocessor returning the unique SSD ID and the unique coprocessor ID. Pairing the first virtual ID and the second virtual ID in response.

  Description 44. Embodiments of the present invention include the method according to the description 34, further comprising providing an API (Application Programming Interface) that operates to respond to a query regarding pairing of the first virtual ID and the second virtual ID.

Description 45. An embodiment of the present invention includes a method according to description 44,
Receiving a pairing query for a pair for the first virtual ID;
Returning a second virtual ID in response to the pairing of the first virtual ID and the second virtual ID.

Description 46. An embodiment of the present invention includes a method according to description 45,
Receiving a query for pairing for the pair for the first virtual ID includes receiving a query for pairing for the pair for the first virtual ID from an application via an API,
Returning the second virtual ID in response to the pairing of the first virtual ID and the second virtual ID includes providing the application with the second virtual ID in response to the pairing of the first virtual ID and the second virtual ID. Including returning.

Description 47. An embodiment of the present invention includes a method according to description 44,
Receiving a file query for a pair associated with the file;
Identifying the SSD that stores the file;
Returning the first virtual ID and the second virtual ID in response to the query for the file.

Description 48. An embodiment of the present invention includes a method according to description 47,
Receiving the query for the file for the pair associated with the file includes receiving the query for the file for the pair associated with the file from the application via the API;
Returning the first virtual ID and the second virtual ID in response to the file query includes returning the first virtual ID and the second virtual ID to the application in response to the file query.

Description 49. A non-transitory computer readable storage medium according to one embodiment of the present invention includes a stored command, and the method by which the command is executed by a machine comprises:
Transmitting a query from the first device to the second device;
Receiving, at the first device, a response including first pairing data from the second device;
Storing the first pairing data in a second storage of the first device;
Accessing the second pairing data from the first storage of the first device;
Transmitting the second pairing data from the first device to the second device.

  Description 50. An embodiment of the present invention includes a recording medium according to description 49, wherein each of the first device and the second device is an FPGA (Field Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit), a GPU (Graphics Processing Unit). It includes any one of a TPU (Tensor Processing Unit), an erasure coding controller, and a small processor core.

Description 51. An embodiment of the present invention includes a recording medium according to Description 49,
Transmitting the query from the first device to the second device includes transmitting the query from the first device to the second device through a hardware interface between the first device and the second device,
Receiving a response from the second device at the first device includes receiving a response from the second device at the first device via a hardware interface between the first device and the second device;
The step of transmitting the second pairing data from the first device to the second device may include transmitting the second pairing data from the first device to the second device via a hardware interface between the first device and the second device. Transmitting.

  Description 52. An embodiment of the present invention includes a recording medium according to description 49, wherein the second storage is an OTP (one-time programmable) memory, a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory), and an EPROM (Erasable Programmable Read-Only Memory). (Electrically Erasable Programmable Read-Only Memory).

Description 53. A non-transitory computer readable storage medium according to one embodiment of the present invention includes a stored command, and the method by which the command is executed by a machine comprises:
Receiving at the first device a query from the second device;
Accessing the first pairing data from the first storage of the first device;
Transmitting a response including the first pairing data from the first device to the second device;
Receiving the second pairing data from the second device at the first device;
Storing the second pairing data in the second storage of the first device.

  Description 54. The embodiment of the present invention includes the recording medium according to the description 53, and each of the first device and the second device includes an FPGA (Field Programmable Gate Array), an ASIC (Application-Specific Integrated Circuit), and a GPU (Graphics Processing Unit). It includes any one of a TPU (Tensor Processing Unit), an erasure coding controller, and a small processor core.

Description 55. An embodiment of the present invention includes a recording medium according to Description 53,
Receiving a query from the second device at the first device includes receiving a query from the second device at the first device through a hardware interface between the first device and the second device;
Transmitting the response from the first device to the second device includes transmitting the response from the first device to the second device through a hardware interface between the first device and the second device;
The receiving of the second pairing data from the second device by the first device may include transmitting the second pairing data from the second device by the first device via a hardware interface between the first device and the second device. Including receiving.

  Description 56. An embodiment of the present invention includes a recording medium according to Description 53, wherein the second storage is an OTP (one-time programmable) memory, a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory), and an EPROM (Erasable Programmable Read-Only Memory). (Electrically Erasable Programmable Read-Only Memory).

Description 57. A non-transitory computer readable storage medium according to one embodiment of the present invention includes a stored command, and the method by which the command is executed by a machine comprises:
Receiving a query at the first device;
Accessing a first unique ID (Identifier) for the first device from the first storage of the first device;
Accessing a second unique ID for a second device paired with the first device from a second storage of the first device;
Transmitting a response including both the first unique ID and the second unique ID from the first device to the query.

Description 58. An embodiment of the present invention includes a recording medium according to Description 53,
Receiving the query at the first device includes receiving the query at the first device out of band.
Transmitting the response to the query from the first device includes transmitting the response to the query from the first device out of band.

Description 59. An embodiment of the present invention includes a recording medium according to Description 58,
Out-of-band, receiving the query on the first device includes receiving the query on the first device via a System Management Bus (SMBus) connection;
Transmitting a response to the query from the first device on the out-of-the-band includes transmitting a response to the query from the first device via the SMBus connection.

Description 60. An embodiment of the present invention includes a recording medium according to Description 57,
Receiving the query at the first device includes receiving the query at the first device in-band.
Transmitting the response to the query from the first device includes transmitting the response to the query from the first device in-band.

Description 61. An embodiment of the present invention includes a recording medium according to Description 57,
Receiving the query on the first device includes receiving the query on the first device via a PCIe (Peripheral Component Interconnect Express) connection;
Transmitting a response to the query from the first device in-band includes transmitting a response to the query from the first device via the PCIe connection.

  Description 62. An embodiment of the present invention includes the recording medium according to the description 57, and the query includes an NVMe (Non-Volatile Management Express) MI (Management Interface) command.

Description 63. A non-transitory computer readable storage medium according to one embodiment of the present invention includes a stored command, wherein the method wherein the command is executed by a machine comprises:
Transmitting a first query to an SSD (Solid State Drive) indicated by the first virtual ID;
Receiving a unique SSD ID and a unique coprocessor ID from the SSD in response to the first query;
Transmitting a second query to the coprocessor indicated by the second virtual ID;
Receiving a unique SSD ID and a unique coprocessor ID from the coprocessor in response to the second query;
Pairing the first virtual ID and the second virtual ID.

  Description 64. An embodiment of the present invention includes the recording medium according to Description 63, and transmitting the first query to the SSD includes transmitting the first query to the SSD out-of-band.

  Description 65. The embodiment of the present invention includes the recording medium according to the description 65, and transmitting the first query to the SSD out-of-band includes transmitting the first query to the SSD via an SMBus connection.

  Description 66. The embodiment of the present invention includes the recording medium according to the description 63, and transmitting the first query to the SSD includes transmitting the first query to the SSD in-band.

  Description 67. An embodiment of the present invention includes the recording medium according to Description 66, and transmitting the first query to the SSD in-band includes transmitting the first query to the SSD via a PCIe connection.

  Description 68. An embodiment of the present invention includes a recording medium according to Description 63, and the first query includes an NVMe MI command.

  Description 69. An embodiment of the present invention includes the recording medium according to Description 63, wherein transmitting the second query to the coprocessor includes transmitting the second query to the coprocessor out of band.

  Description 70. An embodiment of the present invention includes the recording medium according to Description 69, and transmitting the second query to the coprocessor out-of-band includes transmitting the second query to the coprocessor via an SMBus connection. .

  Description 71. An embodiment of the present invention includes a recording medium according to Description 63, and the second query includes an NVMe MI command.

  Description 72. An embodiment of the present invention includes a recording medium according to Description 63, wherein the step of pairing the first virtual ID and the second virtual ID includes both the SSD and the coprocessor returning the unique SSD ID and the unique coprocessor ID. And pairing the first virtual ID and the second virtual ID in response to

  Description 73. An embodiment of the present invention includes a recording medium according to Description 63, wherein the method provides an API (Application Programming Interface) operable to respond to a query regarding pairing of the first virtual ID and the second virtual ID. Further included.

Description 74. An embodiment of the present invention includes a recording medium according to Description 73, wherein the method comprises:
Receiving a pairing query for a pair for the first virtual ID;
Returning a second virtual ID in response to the pairing of the first virtual ID and the second virtual ID.

Description 75. An embodiment of the present invention includes a recording medium according to Description 74,
Receiving the query for pairing for the pair for the first virtual ID includes receiving a query for pairing for the pair for the first virtual ID from the application via the API;
Returning the second virtual ID in response to the pairing of the first virtual ID and the second virtual ID includes providing the application with the second virtual ID in response to the pairing of the first virtual ID and the second virtual ID. Including returning.

Description 76. An embodiment of the present invention includes a recording medium according to Description 73, wherein the method comprises:
Receiving a file query for a pair associated with the file;
Identifying the SSD that stores the file;
Returning the first virtual ID and the second virtual ID in response to the query for the file.

Description 77. An embodiment of the present invention includes a recording medium according to Description 73,
Receiving the query for the file for the pair associated with the file includes receiving the query for the file for the pair associated with the file from the application via the API;
Returning the first virtual ID and the second virtual ID in response to the file query includes returning the first virtual ID and the second virtual ID to the application in response to the file query.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the technical idea of the present invention. It is possible to implement.

105 machine 110 processor 115 memory 120 memory controller 125, 125-1, 125-2, 125-3, 125-4, 125-5, 125-6, 505-1, 505-2, 510-1, 510-2 , 515-1, 515-2, 520-1, 520-2 Storage device 130-1, 130-2 Coprocessor 205 FPGA
210 ASIC
215 GPU
220 TPU
225 Erasure coding controller 230 Small processor core 305 Clock 310 Network connector 315 Bus 320 User interface 325 Input / output engine 405 Operating system 410, 415, 420, 425 Virtual identifier (ID) 1-4
430, 435 Data storage device 1105, 1305, 1405 Erasure coding logic

Claims (20)

An SSD (Solid State Drive) including a first storage for data, a second storage for a unique SSD ID (identifier), and a third storage for a unique coprocessor ID;
A coprocessor including a fourth storage for the unique coprocessor ID, a fifth storage for the unique SSD ID,
A hardware interface between the SSD and the coprocessor.   The co-processor includes a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), a Graphics Processing Unit (GPU), a controller of a TPU (Tensor Process Unit), and a TPU (Tensor Processing Unit), or a TPU (Tensor Processing Unit) or a core unit. The system of claim 1, comprising:   The system of claim 1, wherein the coprocessor is operative to query an SSD for the unique SSD ID and store the unique SSD ID in the fifth storage.   The system of claim 1, wherein the coprocessor is operative to provide the unique coprocessor ID to the SSD.   The system of claim 1, wherein the SSD operates to provide the unique SSD ID to the coprocessor.   The system of claim 1, wherein the SSD is operative to receive queries for the SSD and the coprocessor out-of-band.   The system of claim 6, wherein the SSD is operable to respond to the query including both the unique SSD ID and the unique coprocessor ID.   The system of claim 1, wherein the coprocessor is operative to receive queries for the SSD and the coprocessor out of band.   The system of claim 8, wherein the coprocessor is operable to respond to the query including both the unique SSD ID and the unique coprocessor ID.   The system of claim 1, wherein the SSD is operative to receive queries for the SSD and the coprocessor in-band.   The system of claim 10, wherein the SSD is operative to respond to the query including both the unique SSD ID and the unique coprocessor ID. Transmitting a query from the first device to the second device;
Receiving a response including first pairing data from the second device at the first device;
Storing the first pairing data in a first storage of the first device;
Accessing second pairing data from a second storage of the first device;
Transmitting the second pairing data from the first device to the second device. The transmitting of the query from the first device to the second device may include transmitting the query from the first device to the second device via a hardware interface between the first device and the second device. Including
The step of receiving the response from the second device at the first device includes the step of receiving the response from the second device at the first device via a hardware interface between the first device and the second device. Including receiving,
The transmitting of the second pairing data from the first device to the second device may include transmitting the second pairing data from the first device to the second device via a hardware interface between the first device and the second device. The method of claim 12, further comprising transmitting the second pairing data to the second pairing device. Transmitting a first query to an SSD (Solid State Drive) indicated by the first virtual ID;
Receiving a unique SSD ID and a unique coprocessor ID from the SSD in response to the first query;
Transmitting a second query to the coprocessor indicated by the second virtual ID;
Receiving the unique SSD ID and the unique coprocessor ID from the coprocessor in response to the second query;
Pairing the first virtual ID and the second virtual ID.   The step of pairing the first virtual ID and the second virtual ID includes responsive to both the SSD and the coprocessor returning the unique SSD ID and the unique coprocessor ID. The method of claim 14, comprising pairing an ID with the second virtual ID.   The method of claim 14, further comprising providing an API (Application Programming Interface) that operates to respond to a query related to the pairing of the first virtual ID and the second virtual ID. Method. Receiving a pairing query for a pair for the first virtual ID;
The method of claim 16, further comprising: returning the second virtual ID in response to the pairing of the first virtual ID and the second virtual ID. Receiving the pairing query for the pair for the first virtual ID includes receiving a pairing query for the pair for the first virtual ID from an application via the API;
The step of returning the second virtual ID in response to the pairing of the first virtual ID and the second virtual ID includes the step of returning the application in response to the pairing of the first virtual ID and the second virtual ID. 18. The method of claim 17, comprising returning the second virtual ID to a second virtual ID. Receiving a file query for a pair associated with the file;
Identifying the SSD storing the file;
17. The method of claim 16, further comprising: returning the first virtual ID and the second virtual ID in response to a query for the file. Receiving a query for a file for the pair associated with the file includes receiving a query for a file for the pair associated with the file from an application via the API;
Returning the first virtual ID and the second virtual ID in response to the file query includes returning the first virtual ID and the second virtual ID to the application in response to the file query. 20. The method of claim 19, comprising:

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