JP2020036092A - Imaging element and control method of the same, program, and storage medium - Google Patents

Abstract

To provide an imaging element having a high production yield and capable of suppressing cost.SOLUTION: The imaging element includes a plurality of pixels each having a light reception unit for receiving light and a counting unit for counting the number of photons incident on the light reception unit, at least some of the plurality of pixels are connected so as to form counting units included in each of the at least some of the pixels.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an image sensor and a control method thereof.

  In recent years, as described in Patent Document 1, a solid-state imaging device in which a 1-bit AD converter and a counter are provided for each pixel has been proposed. In the solid-state imaging device described in Patent Document 1, AD conversion is performed for each light-receiving pixel, and thereafter, output data of all pixels is sequentially output by the scanning circuit. Therefore, it is possible to eliminate the trade-off between the number of scanning lines and the reading speed, as compared with the conventional solid-state imaging device that performs AD conversion for each column.

  In this method, the photoelectric conversion element is reset every time a certain amount of charge is accumulated in the light receiving element, so that the photoelectric conversion element is not saturated. The amount of light that can be detected is determined by the upper limit of a counter that counts pulses output when the voltage of the storage capacitor matches the reference voltage.

JP 2015-173432 A

  However, in the technique proposed in Patent Literature 1, there is a possibility that a short circuit occurs in a wiring portion due to miniaturization of a semiconductor pattern. In such a case, there has been a problem that the manufacturing yield of the imaging device is reduced and the cost of the imaging device is increased.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an imaging device having a high manufacturing yield and capable of suppressing costs.

  An image sensor according to the present invention includes a light receiving unit that receives light, and a counting unit that counts the number of photons that have entered the light receiving unit, and includes a plurality of pixels each having a pixel, and at least a part of the plurality of pixels. The pixel is characterized in that the counting means of each of the at least some of the pixels are connected to each other.

  According to the present invention, it is possible to provide an imaging device having a high production yield and capable of suppressing costs.

FIG. 2 is a diagram illustrating a configuration of an image sensor according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a unit pixel in the image sensor according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a configuration of a counter included in a unit pixel according to the first embodiment. 4 is a timing chart illustrating driving of a unit pixel according to the first embodiment. FIG. 3 is a diagram illustrating a stacked structure of an imaging element. FIG. 6 is a diagram illustrating a configuration of an image sensor according to a second embodiment. 9 is a timing chart illustrating driving of a unit pixel according to the second embodiment. FIG. 9 is a diagram illustrating a configuration of an image sensor according to a third embodiment. 13 is a timing chart illustrating driving of a unit pixel according to the third embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiment described below is merely an example, and the present invention is not limited to the configuration of the following embodiment.

<First embodiment>
FIG. 1 is a diagram illustrating a configuration of an image sensor 300 according to the first embodiment of the present invention. The image sensor 300 has a large number of unit pixels 100 arranged two-dimensionally. However, for simplicity of description, FIG. 1 illustrates an example in which 3 × 3 unit pixels 100 are arranged.

  FIG. 2 is a diagram illustrating a configuration of the unit pixel 100 in the imaging element 300. The unit pixel 100 includes an avalanche photodiode (hereinafter, APD) 101, a quench resistor 102, a waveform shaping circuit 103, and a counter 104 as a counting unit. Hereinafter, each component of the unit pixel 100 will be described.

  The APD 101 is connected to a reverse bias voltage VAPD via a quench resistor 102, and generates a charge by avalanche multiplication when a photon enters. The charge generated by the APD 101 is discharged via the quench resistor 102. The waveform shaping circuit 103 generates a voltage pulse by performing amplification and edge detection with respect to a change in potential due to generation and discharge of charges according to the incidence of photons.

  As described above, the APD 101 (light receiving unit), the quench resistor 102, and the waveform shaping circuit 103 function as a 1-bit AD converter by converting the presence or absence of photons into a voltage pulse.

  The counter 104 is a counter for counting the number of voltage pulses generated by the waveform shaping circuit 103, and outputs a multi-bit pixel value during an exposure period by outputting a count result. The counter 104 sets data in a flip-flop 400 described later based on the control signal LOAD_EN and the data signal LOAD_DATA input to the unit pixel 100.

  FIG. 3 is a diagram illustrating a specific configuration of the counter 104. The counter 104 includes a flip-flop 400 that holds data, an adder 401 that performs counting, and a counter selector 402.

  The counter selection unit 402 determines whether to set the value of the counter to the data signal LOAD_DATA or the output of the addition unit 401 based on the control signal LOAD_EN.

  The flip-flop 400 is initialized to an initial value 0 asynchronously with a clock by an asynchronous reset signal. In the present embodiment, the clock signal and the asynchronous reset signal are signals common to the entire imaging unit of the imaging device.

  In the arrangement of 3 × 3 unit pixels as shown in FIG. 1, initial value data 304 is input to the data signal LOAD_DATA of the upper leftmost unit pixel 100 (first pixel). The output of the counter of each unit pixel 100 is connected to the subsequent data signal LOAD_DATA of the unit pixel 100. That is, the counters (counters) of the unit pixels 100 are connected.

  The output of each unit pixel 100 is CNT00, CNT01, CNT02 in the first row, CNT10, CNT11, CNT12 in the second row, and CNT20, CNT21, CNT22 in the third row from left to right in FIG. The control signals LOAD_EN of all the unit pixels 100 are controlled by the output of the read control circuit 303 and operate like a shift register (shift register operation). In the present embodiment, 0 is set as the value of the initial value data 304.

  A timing generator (hereinafter, TG) 306 generates timing such as an imaging period and a transfer period based on a counter (not shown), and notifies the read control circuit 303 of the timing. The read control circuit 303 issues a control signal LOAD_EN based on the timing notified by the TG 306.

  The control signal LOAD_EN is issued during the initialization period and the readout period, and when the unit pixels 100 are arranged in a 3 × 3 array, the control signal LOAD_EN is issued for nine clocks that operate synchronously. The number of cycles is a period until the value of the initial value data 304 propagates to the output CNT 22.

  Next, FIG. 4 is a timing chart showing the operation of the image sensor 300. FIG. 4 shows imaging driving in one unit pixel 100. By performing this driving in a plurality of unit pixels 100 in parallel, an optical image is converted into a digital signal.

  In FIG. 4, APD00 is a waveform generated by the APD 101 and the quench resistor 102 in the unit pixel 100 that outputs CNT00, and PLS00 is an output of the waveform shaping circuit 103 in the same unit pixel 100. RESET_VALUE is initial value data, and READ_DATA is output data from the image sensor 300 that is valid while the control signal LOAD_EN is H.

  Subsequently, driving of the unit pixel 100 will be described.

  At time t200, initialization of the value of the flip-flop 400 of the unit pixel 100 starts, and the control signal LOAD_EN becomes H. At this time, the values of the outputs CNT00 to CNT22 are X (undefined). Further, the light is controlled so as not to enter the APD 101 by a light shielding unit (not shown).

  At time t201, the value of the initial value data RESET_VALUE is loaded to the output CNT00 in synchronization with a clock (not shown). Thereafter, until time t202, the control signal LOAD_EN becomes H (reset control) until the value of the initial value data RESET_VALUE propagates from the output CNT00 to the output CNT22.

  At time t202, the control signal LOAD_EN becomes L, the output CNT22 becomes 0, and the initialization is completed.

  At time t203, the light shielding of the unit pixel 100 by the light shielding unit (not shown) ends. Then, when light is incident on the APD 101 and the output PLS00 of the waveform shaping circuit 103 rises, the output CNT00 changes to a value obtained by adding 1 to the initial value at substantially the same timing.

  The value of the output CNT00 increases by one each time one photon enters the APD 101 during the imaging period until time t204. Similar processing is performed in the outputs CNT01 to CNT22 according to the change in the APD 101 of the corresponding pixel.

  At time t204, the values of the outputs CNT00 to CNT22 become the count results C00 to C22, and the imaging period ends, and the light-shielding means (not shown) blocks light from entering the APD 101. At substantially the same timing, the control signal LOAD_EN becomes H, the reading period starts, and the counting result C22 of the output CNT22 is output from the image sensor 300 as output data READ_DATA.

  Time t205 is a timing when one cycle has elapsed with a clock (not shown) from time t204, and the value of the initial value data RESET_VALUE is propagated to the output CNT00. The value of the output CNT00 is propagated to the output CNT01, and the values of the outputs CNT01 to CNT21 are similarly propagated to the outputs CNT02 to CNT22. At this timing, the counting result C21 transmitted to the output CNT22 is output from the image sensor 300 as output data READ_DATA.

  As described above, the count result C22 of the output CNT22 is output first as output data, then the count result is output from the image sensor 300 as output data READ_DATA in the order of the count result C21 and then the count result C20. That is, pixel values are sequentially output as in a shift register.

  At time t206, the count result C00 of the output CNT00 propagates to the output CNT22 and is output as output data READ_DATA.

  At time t207, the control signal LOAD_EN becomes L, the initial value data RESET_VALUE propagates to the CNT 22, and the initialization of the unit pixel 100 outputting the outputs CNT00 to CNT22 is completed. After time t208, the imaging period and the readout period are repeated as in the period from time t203 to time t208.

  In the present embodiment, the output data READ_DATA is valid while the control signal LOAD_EN is H, but the present invention is not limited to this. For example, a signal indicating the validity of the output data READ_DATA may be provided separately from the control signal LOAD_EN. By doing so, it is possible to handle output data READ_DATA during initialization processing described later as invalid data. Although the outputs CNT00 to CNT22 perform a counting operation based on the output of the waveform shaping circuit 103, a control signal for controlling the counting period may be individually provided.

  Note that the present invention does not limit the physical configuration of the image sensor 100. For example, a circuit portion for handling an analog signal and a circuit portion for handling a digital signal may be formed on different substrates and have a stacked structure.

  The specific configuration of the stacked structure will be described with reference to FIG. FIG. 5A is a diagram illustrating the function of the unit pixel 100 divided into a circuit section that handles analog signals and a circuit section that handles digital signals. FIG. 5B is a diagram illustrating a stacked configuration of the image sensor 300.

  The analog signal processing unit 700 in FIG. 5A includes the APD 102 and the waveform shaping circuit 103. The counter 104 is a digital circuit unit that counts digital signal pulses.

  As shown in FIG. 5B, the analog signal processing units 700 are two-dimensionally arranged on the upper substrate 702. Similarly, on the lower substrate 703, the counters 104 are similarly arranged two-dimensionally, and digital circuits such as the read control circuit 303 and the TG 306 are arranged.

  Generally, an analog signal is more susceptible to noise than a digital signal. Thus, by converting the analog signal into a digital signal and transmitting the digital signal to the lower substrate 703, robustness against noise can be maintained.

  In addition, by arranging, on the lower substrate 703, a portion where the circuit scale increases as the number of output bits increases, such as the counter 104, the integration rate can be increased. Even in such a case, it goes without saying that reducing the number of wirings and control lines lowers the failure rate.

  As described above, according to the present embodiment, in the image sensor in which each pixel has a 1-bit AD converter and a counter, it is possible to simplify wiring and control lines for reading from the image sensor. In addition, it is possible to reduce the manufacturing cost of the imaging device.

<Second embodiment>
In the first embodiment, the configuration in which the flip-flops, which are the storage elements of each unit pixel, are arranged like a shift register and the counters are connected to simplify the wiring and control lines has been described. However, the effect is not necessarily limited unless the counters of all the unit pixels are connected to each other. In the second embodiment, a description will be given of a structure of an image sensor in a case where counters between some unit pixels are connected to each other.

  FIG. 6 is a diagram illustrating a configuration of an image sensor 600 according to the second embodiment. In the image sensor 600 of the present embodiment, the control signals LOAD_EN0, LOAD_EN1, and LOAD_EN2 of the unit pixel 100 are supplied for each row. Further, a transmission read switch 605 is provided for each row, and an OR gate element 601 is added. Further, a vertical selection circuit 603 is provided instead of the read control circuit 303 of the first embodiment.

  The vertical selection circuit 603 sets the control signal LOAD_EN0 to H at the timing of reading the output of the counter 104 of the unit pixel 100 in the first row for which accumulation has been completed. Similarly, at the timing of reading the output of the counter 104 of the unit pixel 100 in the second row, the control signal LOAD_EN1 is set to H, and in the third row, the control signal LOAD_EN2 is set to H.

  When the control signal LOAD_EN0 becomes H, the read switch 605 in the first row is turned on. Similarly, when the control signal LOAD_EN1 becomes H, the read switch 605 in the second row becomes conductive, and when the control signal LOAD_EN2 becomes H, the read switch 605 in the third row becomes conductive. Then, the output of the OR gate element 601 becomes the output of the image sensor 600. Note that the OR gate element may be configured by a wired OR with an open drain.

  FIG. 7 is a timing chart illustrating the operation of the image sensor 600 according to the second embodiment.

  At time t500, initialization of the value of the flip-flop 400 of the unit pixel 100 starts, and the control signals LOAD_EN0, LOAD_EN1, and LOAD_EN2 become H. At this time, the values of the outputs CNT00 to CNT22 are X (undefined). Further, the light is controlled so as not to enter the APD 101 by a light shielding unit (not shown).

  At time t501, the value of the initial value data RESET_VALUE is loaded to the outputs CNT00, CNT10, and CNT20 in synchronization with a clock (not shown). Thereafter, until the time t502, the control signals LOAD_EN0, LOAD_EN1, and LOAD_EN2 become H until the value of the initial value data RESET_VALUE propagates to each of CNT02, CNT12, and CNT22.

  At time t502, the control signals LOAD_EN0, LOAD_EN1, and LOAD_EN2 become L, and the outputs CNT02, CNT12, and CNT22 become 0, and the initialization is completed.

  At time t503, the light shielding by the light shielding means (not shown) ends. Then, when light is incident on the APD 101 and the output PLS00 of the waveform shaping circuit 103 rises, the output CNT00 changes to a value obtained by adding 1 to the initial value at substantially the same timing.

  The value of the output CNT00 increases by one each time one photon enters the APD 101 during the imaging period until time t504. Similar processing is performed in the outputs CNT01 to CNT22 according to the change in the APD 101 of the corresponding pixel.

  At time t504, the values of the outputs CNT00 to CNT22 become the count results C00 to C22 and the imaging period ends, and the light-shielding means (not shown) cuts off the incidence of light on the APD 101. At substantially the same timing, the control signal LOAD_EN0 becomes H, the reading period starts, and the count result C02 of the output CNT02 is output as output data READ_DATA via the OR gate element 601.

  Time t505 is a timing at which one cycle has elapsed with a clock (not shown) with respect to time t504, and the value of the initial value data RESET_VALUE is propagated to the output CNT00. The value of the output CNT00 is propagated to CNT01, and the value of the output CNT01 is propagated to CNT02. At this timing, the count result C01 propagated to the output CNT02 is output as output data READ_DATA.

  At time t506, the control signal LOAD_EN0 becomes L, and the read control of the first row is completed. Further, the value of the initial value data RESET_VALUE is transmitted to the output CNT02, and the initialization is completed. At substantially the same timing, LOAD_EN1 becomes H, reading of the second row is started, and the count result C12 of the output CNT12 is output as output data READ_DATA via the OR gate element 601.

  Time t507 is a timing at which one cycle has elapsed with a clock (not shown) with respect to time t506, and the value of the initial value data RESET_VALUE is propagated to the output CNT10. The value of the output CNT10 is propagated to the CNT11, and the value of the output CNT11 is propagated to the CNT12. At this timing, the count result C11 propagated to the output CNT12 is output as output data READ_DATA.

  At time t508, similarly to time t506, the control of reading and initialization of the second row is completed. Further, LOAD_EN2 becomes H similarly to the time t506, reading of the third row is started, and the count result C22 of the output CNT22 is output as output data READ_DATA via the OR gate element 601.

  At time t509, LOAD_EN2 becomes L, the initial value data RESET_VALUE propagates to the CNT 22, reading of all rows is completed, and initialization of all rows is completed.

  After time t510, the imaging period and the readout period are repeated as in the period from time t503 to time t510.

  By performing the processing as described above, even when the counters are connected between some of the unit pixels, it is possible to simplify wiring and control lines for reading from the image sensor. In addition, it is possible to reduce the manufacturing cost of the imaging device.

  In this embodiment, the counters of the plurality of unit pixels are connected to each other in units of odd-numbered rows and even-numbered rows. However, the present invention is not limited to this. For example, columns such as odd columns and even columns are used. A configuration may be adopted in which counters of a plurality of unit pixels are connected in the direction.

  Further, the present invention can be applied to a known technique of arranging sub-pixels obtained by dividing an exit pupil into two parts under a microlens. For example, the configuration may be such that the counting result of the divided left pixel is transmitted to the counting result of the right pixel. By performing such processing, it is possible to reduce the number of control lines for controlling the read switch.

  Further, in a case where a mode in which pixels are read out at regular intervals, such as a field readout of a CCD sensor, is provided, a counter of a plurality of unit pixels may be connected in units of thinning out reading. That is, the present invention does not impose any limitation on a unit having a configuration for connecting counters of a plurality of unit pixels.

  In the first embodiment, the pixel values are output in the order of the third, second, and first rows, whereas in the present embodiment, the pixel values are output in the order of the first, second, and third rows. The pixel value was output. The present invention is not limited to such an output order, and the output can be performed in an arbitrary order by changing the connection relation and the output order of the control signal LOAD_EN. Further, a plurality of control signals LOAD_EN may be provided, and the output order may be determined by a control procedure.

<Third embodiment>
In the first and second embodiments, a method has been described in which the initial value data RESET_VALUE is set to a uniform fixed value of 0 and is loaded before counting is started. However, the initial value does not need to be a fixed value. For example, by setting an initial value individually for each pixel in advance, it becomes possible to utilize the OB clamp correction of the pixel value and the limiter processing for each pixel.

  When performing the OB clamp correction and the limiter processing in the image sensor, it is necessary to individually have a flip-flop for holding the correction value. However, as in the present embodiment, the correction value is set to the initial value of the counter. This eliminates the need for a flip-flop for holding the correction value. In the third embodiment, a method of setting an initial value in the flip-flop 400 of the unit pixel 100 for each pixel will be described.

  FIG. 8 is a diagram illustrating a configuration of an image sensor 900 according to the third embodiment. In the image sensor 900, an initialization signal generator 901 is added to the image sensor 300 described in the first embodiment.

  The initialization signal generation unit 901 includes a pattern generation circuit for generating a pattern of an initial value and a storage element typified by an SRAM, and outputs an initial value for each pixel. The initialization signal generation unit 901 switches and outputs the initial value of the unit pixel 100 according to the control signal LOAD_EN output from the read control circuit 303.

  A specific operation will be described with reference to FIG. FIG. 9 is a timing chart showing the operation of the image sensor 900.

  At time t800, the initialization of the value of the flip-flop 400 of the unit pixel 100 starts, and the control signal LOAD_EN becomes H. At this time, the values of the outputs CNT00 to CNT22 are X (undefined). Further, the light is controlled so as not to enter the APD 101 by a light shielding unit (not shown). Further, the initialization signal generation unit 901 outputs the correction value 202 for the output CNT 22 as initial value data RESET_VALUE.

  At time t801, the value of the initial value data RESET_VALUE is loaded into the output CNT00 in synchronization with a clock (not shown), and at the same time, the initialization signal generation unit 901 sets the correction value 201 for correcting the output CNT21 to the initial value data RESET_VALUE. Output as

  At time t802, the value of the output CNT00 is loaded on the CNT01 in synchronization with a clock (not shown), and at the same time, the value of the initial value data RESET_VALUE is loaded on the output CNT00. Further, the initialization signal generation unit 901 outputs a correction value 200 for correcting the CNT 20 as initial value data RESET_VALUE.

  Thereafter, during a period until time t803, the initialization signal generation unit 901 sequentially generates an initial value of the counter 104 of each unit pixel 100 and loads the initial value into the flip-flop 400 of each counter 104 by a shift register configuration.

  At time t803, when the control signal LOAD_EN becomes L and the correction value 202 is loaded to the output CNT22, the initialization is completed. At this time, the correction values 000 to 202 are loaded on the outputs CNT00 to CNT22.

At time t804, the light shielding by the light shielding means (not shown) ends. Then, when light is incident on the APD 101 and the output PLS00 of the waveform shaping circuit 103 rises, the output CNT00 changes to a value obtained by adding 1 to the initial value at substantially the same timing.
The value of the output CNT00 increases by one each time one photon enters the APD 101 during the imaging period until time t805. The same processing is performed in the outputs CNT01 to CNT22 by changing the APD 101 of the corresponding pixel.

  At time t805, the values of the outputs CNT00 to CNT22 become the count results C00 to C22, and the imaging period ends, and the light-shielding means (not shown) blocks light from entering the APD 101. At substantially the same timing, the control signal LOAD_EN becomes H, the reading period is started, and the counting result C22 of the output CNT22 is output from the imaging device 900 as output data READ_DATA.

  At this time, the count results C00 to C22 are values obtained by adding the result of counting the output PLS of the waveform generation unit 103 to the initial value generated by the initialization signal generation unit 901. That is, by setting the inverted value of the offset value for performing the OB clamp to the initial value, it is not necessary to provide a circuit for performing the OB clamp correction on the output of the image sensor 900.

  Time t806 is a timing at which one cycle has elapsed with a clock (not shown) from time t805, and the value of the initial value data RESET_VALUE is propagated to the output CNT00. The value of the initial value data RESET_VALUE is generated based on the output of the initialization signal generation unit 901 as in the description of the time t801.

  The value of the output CNT00 is propagated to CNT01, and the values of the outputs CNT01 to CNT21 are similarly propagated to the outputs CNT02 to CNT22. At this timing, the counting result C21 propagated to the output CNT22 is output from the image sensor 900 as output data READ_DATA.

  Thereafter, at times t807, t808, and t809, the same processing as at times t206, t207, and t208 is performed.

  As described above, by arbitrarily setting the initial value of the flip-flop included in the counter, it is not necessary to separately provide a flip-flop for holding the correction value, and the circuit scale can be reduced.

  Although the OB clamp correction has been described in the present embodiment, it may be used for other purposes. For example, when it is desired to change the limiter value for each horizontal image height, in order to provide a limiter for the output of each pixel, a threshold setting flip-flop of the limiter, a comparator for comparison, and a selector for output control are required.

  On the other hand, by setting the sign inversion signal of the threshold value in advance as the initial value, it may be configured to output 0 when the counting result becomes 0 or more. Generally, compared to the variable limiter, the limiter to be compared with 0 can be configured to have a smaller circuit scale. In such a case, the original count result can be restored by adding the initial value for each image height set in the flip-flop to the output result.

(Other embodiments)
The present invention supplies a program for realizing one or more functions of the above-described embodiments to a system or an apparatus via a network or a storage medium, and one or more processors in a computer of the system or the apparatus read and execute the program. This processing can be realized. Further, it can also be realized by a circuit (for example, an ASIC) that realizes one or more functions.

100: unit pixel, 101: avalanche photodiode (APD), 102: quench resistor, 103: waveform shaping circuit, 104: counter, 300: image sensor

Claims (13)

A light receiving unit that receives light, and a counting unit that counts the number of photons incident on the light receiving unit, including a plurality of pixels each having,
An image sensor, wherein the counting means of each of the at least some pixels is connected to at least some of the plurality of pixels.   The said counting means has the generation means which the said light-receiving part generates a pulse based on the electric charge which generate | occur | produces with the incidence of a photon, and the counter which counts the pulse which the said generation means generated, The characterized by the above-mentioned. 2. The imaging device according to 1.   The imaging device according to claim 1, wherein the counting unit performs a shift register operation in control of reading a signal from the pixel or reset control of the pixel.   The apparatus further comprises initialization signal generation means for generating an initial value of the pixel signal, wherein the initialization signal generation means is connected to a first counting means of the plurality of counting means. Item 4. The image sensor according to any one of Items 1 to 3.   The imaging device according to claim 4, wherein the initialization signal generation unit outputs a uniform fixed value.   The imaging device according to claim 4, wherein the initialization signal generation unit outputs an individual value for each pixel.   The counting means corresponding to the pixels in the even-numbered rows of the imaging device are connected to each other, and the counting means corresponding to the pixels in the odd-numbered rows are connected to each other. Imaging device.   The counting means corresponding to the pixels in the even-numbered columns of the imaging device are connected to each other, and the counting means corresponding to the pixels in the odd-numbered columns are connected to each other. Imaging device.   The imaging device according to claim 1, wherein the light receiving unit has at least two sub-pixels that divide an exit pupil below one microlens.   The imaging device according to claim 1, wherein each of the counting units corresponding to the pixels read out by thinning out of the plurality of pixels is connected to each other. A light receiving unit that receives light, and a counting unit that counts the number of photons incident on the light receiving unit, a method of controlling an imaging device including a plurality of pixels each having:
A method for controlling an image sensor, wherein a signal of the pixel is transferred between the plurality of counting units by using the counting unit included in at least a part of the plurality of pixels.   A program for causing a computer to execute the control method according to claim 11.   A computer-readable storage medium storing a program for causing a computer to execute the control method according to claim 11.

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