JP2020035837A - Method of manufacturing epitaxial wafer, method of manufacturing semiconductor device, and epitaxial wafer - Google Patents

Method of manufacturing epitaxial wafer, method of manufacturing semiconductor device, and epitaxial wafer Download PDF

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JP2020035837A
JP2020035837A JP2018159716A JP2018159716A JP2020035837A JP 2020035837 A JP2020035837 A JP 2020035837A JP 2018159716 A JP2018159716 A JP 2018159716A JP 2018159716 A JP2018159716 A JP 2018159716A JP 2020035837 A JP2020035837 A JP 2020035837A
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composition layer
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JP7325939B2 (en
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田中 治
Osamu Tanaka
治 田中
寛郎 田崎
Hiroo Tazaki
寛郎 田崎
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Dowa Electronics Materials Co Ltd
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Abstract

To provide a method of manufacturing an epitaxial wafer having a current confinement layer in which variation in an amount of oxidation in a wafer surface is suppressed than before.SOLUTION: The method of manufacturing an epitaxial wafer includes the steps of: forming a semiconductor laminate including a high Al composition layer made of at least AlGaAs (0.9≤x≤1) on a substrate; forming a mesa structure exposing at least a side surface of the high Al composition layer; and oxidizing a part of the high Al composition layer from the exposed side surface of the high Al composition layer to form a current confinement layer. In the oxidation step, oxidation is performed at 480 to 580°C in an atmosphere containing water vapor at 0.001 to 0.01 g/L.SELECTED DRAWING: Figure 1

Description

本発明は、部分酸化を用いて製造するエピタキシャルウエハの製造方法及びそれを用いる半導体素子の製造方法、並びに、高Al組成層が部分酸化された電流狭窄層を有するエピタキシャルウエハに関する。   The present invention relates to a method for manufacturing an epitaxial wafer manufactured by using partial oxidation, a method for manufacturing a semiconductor device using the same, and an epitaxial wafer having a current confinement layer in which a high Al composition layer is partially oxidized.

面発光レーザ(VCSEL; Vertical Cavity Surface Emitting Laserともいう)は、光通信、DVDやCD、プリンター、光学マウスなど様々な用途に使用されてきたが、顔認証システムに使用されてからは、各種の3Dセンサー用途としても注目されている。また、レーザ発振はしないが電流狭窄層を有する点光源LEDなどの発光素子も各種センサー用途に使用される。   VCSELs (Vertical Cavity Surface Emitting Lasers) have been used in various applications such as optical communication, DVDs, CDs, printers, and optical mice. Attention has also been paid to 3D sensor applications. Light emitting elements that do not perform laser oscillation but have a current confinement layer, such as point light source LEDs, are also used for various sensor applications.

特許文献1には、半導体基板上に積層された半導体層をドライエッチングすることでメサ構造を作製し、そのメサ構造の側壁から、高温水蒸気により高Al組成層の一部を外周側から水蒸気酸化して絶縁領域を形成した酸化型VCSELが開示されている。   Patent Document 1 discloses that a semiconductor layer stacked on a semiconductor substrate is dry-etched to form a mesa structure, and a part of the high Al composition layer is steam-oxidized from a side wall of the mesa structure by high-temperature steam from an outer peripheral side. An oxidized VCSEL in which an insulating region is formed as described above is disclosed.

特許文献2には、熱酸化工程におけるウエハの反りやヒータ形状に依存するウエハ内での酸化のばらつきを防止した酸化装置が開示されている。   Patent Literature 2 discloses an oxidizing apparatus that prevents a wafer from being warped in a thermal oxidation process and a variation in oxidation in a wafer depending on a heater shape.

酸化方法は、特許文献1には例えば、窒素をキャリアガスとする350℃の水蒸気雰囲気に30分間晒すと記載されている。また、特許文献2には、熱酸化温度を例えば400℃〜500℃の間に設定することが好ましいと記載されている。   As for the oxidation method, Patent Document 1 describes, for example, that the substrate is exposed to a steam atmosphere of 350 ° C. using nitrogen as a carrier gas for 30 minutes. Patent Document 2 describes that it is preferable to set the thermal oxidation temperature between, for example, 400 ° C. and 500 ° C.

特開2004−327862号公報JP-A-2004-327862 特開2017−50389号公報JP 2017-50389 A

エピタキシャルウエハ(以下、ウエハと略記することがある。)が大口径化するほどに、ウエハ面内での特性、すなわち、絶縁領域を形成するための酸化工程での酸化量のばらつきをいかに抑制するが課題となる。酸化量のウエハ面内ばらつきが大きいと、狭窄形状の大きさもウエハ面内でばらつく。したがって、ウエハから得られる半導体素子の順方向電圧の素子間でのばらつきも大きくなり、さらには信頼性の問題も生じやすくなる。特許文献2に記載の遊星駆動技術や温度の均一化は酸化量のばらつきを抑制するには有効ではあるが、さらなるばらつきの抑制が求められる。   As the diameter of an epitaxial wafer (hereinafter may be abbreviated as a wafer) increases, how the characteristics in the wafer surface, that is, the variation in the amount of oxidation in the oxidation step for forming the insulating region, is suppressed. Is an issue. If the variation in the oxidation amount in the wafer surface is large, the size of the constricted shape also varies in the wafer surface. Therefore, the variation in the forward voltage of the semiconductor device obtained from the wafer among the devices becomes large, and further, the problem of reliability tends to occur. Although the planetary driving technique and temperature uniformization described in Patent Document 2 are effective for suppressing the variation in the oxidation amount, further suppression of the variation is required.

そこで本発明は、ウエハ面内の酸化量のばらつきを抑制した電流狭窄層を有するエピタキシャルウエハの製造方法を提供することを目的とする。また、本発明は、この製造方法を用いる半導体素子の製造方法を提供することを目的とする。さらに本発明は、ウエハ面内の酸化量のばらつきを抑制した電流狭窄層を有するエピタキシャルウエハを提供することを目的とする。   Accordingly, an object of the present invention is to provide a method for manufacturing an epitaxial wafer having a current confinement layer in which variation in the amount of oxidation in a wafer surface is suppressed. Another object of the present invention is to provide a method for manufacturing a semiconductor device using this manufacturing method. Still another object of the present invention is to provide an epitaxial wafer having a current confinement layer in which variation in the amount of oxidation in a wafer surface is suppressed.

上記課題を解決するために、本発明者らは鋭意検討した。そして本発明者らは、酸化処理を行う対象の高Al組成層に、従来から推奨されていた水蒸気雰囲気での熱酸化の条件とは異なる条件下において酸化を行うことを想起した。その結果、ウエハ面内の酸化量による電流狭窄径のばらつき、および、電流狭窄径の影響を大きく受ける順方向電圧の値のばらつきを、従来よりも改善できることを知見し、本発明を完成するに至った。   In order to solve the above-mentioned problems, the present inventors diligently studied. The present inventors have recalled that the high Al composition layer to be oxidized is oxidized under conditions different from the conventionally recommended conditions of thermal oxidation in a steam atmosphere. As a result, it was found that the variation in the current confinement diameter due to the oxidation amount in the wafer surface and the variation in the forward voltage greatly affected by the current confinement diameter can be improved as compared with the conventional art. Reached.

すなわち、本発明の要旨構成は以下の通りである。
(1)基板上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層を含む半導体積層体を形成する工程と、
少なくとも前記高Al組成層の側面を露出させるメサ構造を形成する工程と、
前記高Al組成層の露出した前記側面から前記高Al組成層の一部を酸化処理することで電流狭窄層を形成する酸化工程を有し、
前記酸化工程において、水蒸気を0.001〜0.01g/L含む雰囲気で、480〜580℃で酸化処理することを特徴とするエピタキシャルウエハの製造方法。
That is, the gist configuration of the present invention is as follows.
(1) forming a semiconductor laminate including a high Al composition layer made of at least Al x Ga 1 -x As (0.9 ≦ x ≦ 1) on a substrate;
Forming a mesa structure exposing at least a side surface of the high Al composition layer;
Oxidizing a part of the high Al composition layer from the exposed side surface of the high Al composition layer to form a current confinement layer,
The method of manufacturing an epitaxial wafer, wherein the oxidizing step is oxidized at 480 to 580 ° C. in an atmosphere containing water vapor at 0.001 to 0.01 g / L.

(2)前記半導体積層体を形成する工程において、前記基板上に下部反射層、発光層、前記高Al組成層、上部反射層を順に形成する、前記(1)に記載のエピタキシャルウエハの製造方法。 (2) The method of manufacturing an epitaxial wafer according to (1), wherein in the step of forming the semiconductor laminate, a lower reflective layer, a light emitting layer, the high Al composition layer, and an upper reflective layer are sequentially formed on the substrate. .

(3)前記酸化工程の温度が510℃以上である、前記(1)又は(2)に記載のエピタキシャルウエハの製造方法。 (3) The method for producing an epitaxial wafer according to (1) or (2), wherein the temperature of the oxidation step is 510 ° C. or higher.

(4)前記高Al組成層のAl組成xが0.9≦x<1である、前記(1)〜(3)のいずれかに記載のエピタキシャルウエハの製造方法。 (4) The method for manufacturing an epitaxial wafer according to any one of (1) to (3), wherein the Al composition x of the high Al composition layer satisfies 0.9 ≦ x <1.

(5)前記(1)〜(4)のいずれかに記載の製造方法により得られたエピタキシャルウエハをダイシングする工程を含む、半導体素子の製造方法。 (5) A method for manufacturing a semiconductor device, comprising a step of dicing the epitaxial wafer obtained by the method according to any one of (1) to (4).

(6)3インチ以上の基板上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層を含む半導体積層体を有し、
少なくとも前記高Al組成層を含む電流狭窄層の側面が露出したメサ構造を具え、
前記高Al組成層は、前記メサ構造の外周側に設けられた酸化領域に挟持されて電流狭窄層を構成し、
酸化されていない狭窄領域を俯瞰してウエハ面内の19個以上の狭窄形状を測定した場合に、狭窄形状の結晶方位<01−1>の幅と、結晶方位<010>の幅との標準偏差がいずれも0.6μm以下であることを特徴とするエピタキシャルウエハ。
(6) a semiconductor laminate including a high Al composition layer made of at least Al x Ga 1 -x As (0.9 ≦ x ≦ 1) on a substrate of 3 inches or more;
A mesa structure in which a side surface of a current confinement layer including at least the high Al composition layer is exposed,
The high Al composition layer constitutes a current confinement layer sandwiched between oxidized regions provided on an outer peripheral side of the mesa structure,
When 19 or more constricted shapes in the wafer surface are measured while looking down on the confined region that has not been oxidized, the standard of the width of the crystal orientation <01-1> and the width of the crystal orientation <010> of the constricted shape is measured. An epitaxial wafer having a deviation of 0.6 μm or less.

なお、本明細書では、結晶方位
を、結晶方位<01−1>と表記する。
In this specification, the crystal orientation
Is expressed as a crystal orientation <01-1>.

(7)前記狭窄形状が円形であり、
前記結晶方位<01−1>の幅に対する前記結晶方位<010>の幅の比の平均が100〜102%である、前記(6)に記載のエピタキシャルウエハ。
(7) the constriction shape is circular;
The epitaxial wafer according to (6), wherein the average of the ratio of the width of the crystal orientation <010> to the width of the crystal orientation <01-1> is 100 to 102%.

本発明によれば、従来よりウエハ面内の酸化量のばらつきを抑制した電流狭窄層を有するエピタキシャルウエハの製造方法を提供することができる。また、本発明は、この製造方法を用いる半導体素子の製造方法を提供することができる。さらに本発明は、ウエハ面内の酸化量のばらつきを抑制した電流狭窄層を有するエピタキシャルウエハを提供することができる。   According to the present invention, it is possible to provide a method for manufacturing an epitaxial wafer having a current confinement layer in which variation in the amount of oxidation in a wafer surface is suppressed more than conventionally. Further, the present invention can provide a method for manufacturing a semiconductor device using this manufacturing method. Further, the present invention can provide an epitaxial wafer having a current confinement layer in which variation in the amount of oxidation in a wafer surface is suppressed.

本発明の一実施形態に従う面発光レーザの製造工程を説明する図である。FIG. 4 is a diagram illustrating a manufacturing process of the surface emitting laser according to the embodiment of the present invention. 本発明の製造方法に適用できる水蒸気酸化装置の一例の概略図である。It is a schematic diagram of an example of a steam oxidation device applicable to the manufacturing method of the present invention. 本発明のエピタキシャルエハの狭窄形状を測定するときのウエハ面内の19個の測定箇所を示す模式図である。It is a schematic diagram which shows 19 measurement places in the wafer surface when measuring the constriction shape of the epitaxial wafer of this invention. 実施例において狭窄径を測定した際の赤外線カメラ写真の代表例である。It is a typical example of an infrared camera photograph at the time of measuring a stenosis diameter in an Example. 実施例におけるAl組成と酸化レートとの関係を示すグラフである。4 is a graph showing a relationship between an Al composition and an oxidation rate in Examples. 実施例におけるAl組成と酸化レートとの関係を示すグラフである。4 is a graph showing a relationship between an Al composition and an oxidation rate in Examples. 実施例におけるウエハ面内の順方向電圧Vfのばらつきを示すグラフである。4 is a graph showing a variation of a forward voltage Vf in a wafer surface in the example.

(エピタキシャルウエハの製造方法)
本発明は高Al組成層を含む半導体積層体を有する半導体素子を得るためのエピタキシャルウエハに適用される。具体的には、基板の厚み方向において複数の半導体層に挟まれた状態の高Al組成層を、その側面から酸化することで部分的に酸化し、基板面内方向で高Al組成層が酸化層により挟持された電流狭窄層を形成する技術に関する。得られたエピタキシャルウエハをダイシングすることにより半導体素子を得ることができる。高Al組成層を基板の厚み方向において挟む層が何かは任意であり、様々な形態をとることができる。
(Method of manufacturing epitaxial wafer)
The present invention is applied to an epitaxial wafer for obtaining a semiconductor device having a semiconductor laminate including a high Al composition layer. Specifically, the high Al composition layer sandwiched between a plurality of semiconductor layers in the thickness direction of the substrate is partially oxidized by oxidizing from the side surface, and the high Al composition layer is oxidized in the in-plane direction of the substrate. The present invention relates to a technique for forming a current confinement layer sandwiched between layers. A semiconductor device can be obtained by dicing the obtained epitaxial wafer. What kind of layer sandwiches the high Al composition layer in the thickness direction of the substrate is arbitrary, and can take various forms.

<半導体素子及びその態様としての面発光レーザ>
以下、図1の符号を参照しつつ本実施形態においては、半導体素子1の例として、基板10上に下部反射層20、発光層30、AlxGa1-xAs(0.9≦x≦1)からなる高Al組成層41を含む電流狭窄層40、上部反射層50を順に形成した面発光レーザに関して説明を行う。
<Semiconductor device and surface emitting laser as its mode>
Hereinafter, in the present embodiment with reference to the reference numerals in FIG. 1, as an example of the semiconductor device 1, a lower reflective layer 20, a light emitting layer 30, and Al x Ga 1 -x As (0.9 ≦ x ≦ A surface emitting laser in which a current confinement layer 40 including a high Al composition layer 41 of 1) and an upper reflection layer 50 are sequentially formed will be described.

本発明によるエピタキシャルウエハの製造方法は、基板10上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層41を含む半導体積層体(図1の例では符号20,30,41、50)を形成する工程(図1ステップA)と、少なくとも高Al組成層41の側面を露出させるメサ構造を形成する工程(図1ステップB)と、高Al組成層41の露出した側面から高Al組成層41の一部を酸化処理することで電流狭窄層40を形成する酸化工程を有する(図1ステップC)。当該酸化処理により、高Al組成層41は、上記メサ構造の外周側に設けられた酸化領域42に挟持されて電流狭窄層40を構成する。そして、詳細を後述するように、酸化工程(図1ステップC)において、水蒸気を0.001〜0.010g/L含む雰囲気で、480〜580℃で酸化処理する。また、図1ステップDに示すように、上部反射層50の上に上面電極61を設けてもよく、基板10の裏面に下面電極62を設けてもよい。こうして得られた半導体素子構造を有するエピタキシャルウエハをダイシングすれば、半導体素子1を得ることができる。 The method for manufacturing an epitaxial wafer according to the present invention is directed to a semiconductor laminated body including at least a high Al composition layer 41 made of Al x Ga 1 -x As (0.9 ≦ x ≦ 1) on a substrate 10 (in FIG. 20, 30, 41, 50) (Step A in FIG. 1), a step of forming a mesa structure exposing at least the side surface of the high Al composition layer 41 (Step B in FIG. 1), and a high Al composition layer 41. An oxidation step of oxidizing a part of the high Al composition layer 41 from the exposed side surface to form the current confinement layer 40 (Step C in FIG. 1). By the oxidation treatment, the high Al composition layer 41 is sandwiched between the oxidized regions 42 provided on the outer peripheral side of the mesa structure to form the current confinement layer 40. Then, as described in detail later, in the oxidation step (Step C in FIG. 1), oxidation treatment is performed at 480 to 580 ° C. in an atmosphere containing 0.001 to 0.010 g / L of water vapor. Further, as shown in Step D of FIG. 1, an upper electrode 61 may be provided on the upper reflective layer 50, and a lower electrode 62 may be provided on the back surface of the substrate 10. The semiconductor element 1 can be obtained by dicing the thus obtained epitaxial wafer having the semiconductor element structure.

なお、図1は面発光レーザの具体例を示すものに過ぎず、本発明の製造方法を適用する高Al組成層41の位置は上記面発光レーザの例に何ら限定されない。下部反射層20と発光層30の間に高Al組成層41を設けることもできるし、様々な層を高Al組成層41の前後(図1の紙面上下方向)に挟むことができる。また、基板上に下部反射層、下部クラッド層、発光層、電流狭窄層、上部クラッド層を設けた半導体発光素子のように、上部反射層を持たない点光源LEDを得るために本製造方法を適用することもできるし、上下共に反射層を持たない電流狭窄型LEDに適用してもよい。半導体発光素子に限らず、半導体受光素子に本製造方法を適用してもよい。なお、反射層(下部反射層20および上部反射層50)とは、発光層30から放出される光を反射させるために設けられる層である。こうした反射層として、Al組成の異なるAlGaAs層(符号21,22及び51,52を参照)を交互に繰り返し積層したブラック反射層(DBR)や、金属反射層を用いることができる。   FIG. 1 shows only a specific example of the surface emitting laser, and the position of the high Al composition layer 41 to which the manufacturing method of the present invention is applied is not limited to the above example of the surface emitting laser. The high Al composition layer 41 can be provided between the lower reflective layer 20 and the light emitting layer 30, and various layers can be sandwiched between the high Al composition layer 41 and the front and back (in the vertical direction on the paper of FIG. 1). Further, the present manufacturing method is used to obtain a point light source LED having no upper reflective layer, such as a semiconductor light emitting device having a lower reflective layer, a lower clad layer, a light emitting layer, a current confinement layer, and an upper clad layer provided on a substrate. The present invention may be applied to a current confinement type LED having no reflective layer on both the upper and lower sides. The present manufacturing method may be applied not only to a semiconductor light emitting element but also to a semiconductor light receiving element. The reflection layers (the lower reflection layer 20 and the upper reflection layer 50) are layers provided for reflecting light emitted from the light emitting layer 30. As such a reflective layer, a black reflective layer (DBR) in which AlGaAs layers having different Al compositions (see reference numerals 21 and 22 and 51 and 52) are alternately and repeatedly laminated, or a metal reflective layer can be used.

以下、本発明の製造方法の各工程を順次説明する。   Hereinafter, each step of the manufacturing method of the present invention will be sequentially described.

<半導体積層体を形成する工程>
まず、図1ステップAに示すように、基板10上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層41を含む半導体積層体を形成する。
<Step of forming semiconductor laminate>
First, as shown in FIG. 1 step A, a semiconductor laminate including a high Al composition layer 41 made of at least Al x Ga 1 -x As (0.9 ≦ x ≦ 1) is formed on a substrate 10.

<<高Al組成層の組成>>
高Al組成層41は、AlxGa1-xAs(0.9≦x≦1)からなり、0.9≦x<1であることがより好ましい。Al組成xの値は、SIMSまたはTEM−EDSを用いて測定することができる。Al組成xが0.9未満の場合、高Al組成層と他の半導体層との酸化速度の差が小さく、高Al組成層41の選択的な酸化が困難となり、その結果、電流狭窄層40の形成も困難となる。また、AlAs(すなわちx=1)の場合、本発明によってウエハ面内での酸化量のばらつきを抑制できるものの、面方位の影響が強く残る(例えばメサ形状が円形でも狭窄形状が四角に近づく)傾向がある。そのため、酸化量だけでなく形状も均一にしたい場合には、0.9≦x<1とすることが好ましく、例えば0.9≦x≦0.98とすることがより好ましい。
<<<< composition of high Al composition layer >>
The high Al composition layer 41 is made of Al x Ga 1 -x As (0.9 ≦ x ≦ 1), and more preferably 0.9 ≦ x <1. The value of the Al composition x can be measured using SIMS or TEM-EDS. When the Al composition x is less than 0.9, the difference in oxidation rate between the high Al composition layer and another semiconductor layer is small, and it becomes difficult to selectively oxidize the high Al composition layer 41. As a result, the current confinement layer 40 Is also difficult to form. In the case of AlAs (that is, x = 1), the present invention can suppress the variation of the oxidation amount in the wafer surface, but the influence of the plane orientation remains strong (for example, even if the mesa shape is circular, the constriction shape approaches a square). Tend. Therefore, when it is desired to make not only the amount of oxidation but also the shape uniform, it is preferable that 0.9 ≦ x <1, and more preferably, for example, 0.9 ≦ x ≦ 0.98.

<高Al組成層以外の半導体層の組成>
高Al組成層41以外の半導体層については、高Al組成層41よりもAl組成が低く、高Al組成層41より酸化されにくい半導体層を用いることが好ましい。こうした半導体層としては、エピタキシャル成長において上記の電流狭窄層40を厚み方向に挟んで成長できる層であればよく、例えば、AlGaAs、AlInGaP、InGaAs、AlInP、InGaPとすることができる。
<Composition of semiconductor layer other than high Al composition layer>
As for the semiconductor layers other than the high Al composition layer 41, it is preferable to use a semiconductor layer having a lower Al composition than the high Al composition layer 41 and less susceptible to oxidation than the high Al composition layer 41. Such a semiconductor layer may be any layer that can be grown by sandwiching the current constriction layer 40 in the thickness direction in epitaxial growth, and may be, for example, AlGaAs, AlInGaP, InGaAs, AlInP, or InGaP.

<基板>
基板10は、エピタキシャル成長に用いる成長用基板のことを指す。なお、成長用の基板10上に半導体積層体をエピタキシャル成長した後に、支持用の任意の基板を半導体積層体上に接合して、成長用に用いた基板10を除去してもよい。こうした基板10としては、GaAs基板のほかに、InP基板を使用することもできる。ウエハが大口径化するほどに、ウエハ面内での特性、すなわち、酸化工程での酸化量のばらつきをいかに抑制するが課題となる。そこで、本発明の製造方法を適用することが好ましい基板は、3インチ以上である。
<Substrate>
The substrate 10 refers to a growth substrate used for epitaxial growth. After epitaxial growth of the semiconductor laminate on the growth substrate 10, an arbitrary substrate for support may be joined onto the semiconductor laminate to remove the substrate 10 used for growth. As such a substrate 10, an InP substrate can be used in addition to a GaAs substrate. As the diameter of the wafer increases, it becomes an issue how to suppress the variation in the characteristics within the wafer surface, that is, the variation in the oxidation amount in the oxidation step. Therefore, the substrate to which the manufacturing method of the present invention is preferably applied is 3 inches or more.

<高Al組成層の側面を露出させるメサ構造を形成する工程>
次に、図1ステップBに示すように高Al組成層41の側面を露出させるメサ構造を形成する。高Al組成層41を含む半導体積層体に、特定の形状と配置パターンを有するメサ構造を形成することで、高Al組成層の側面を露出させる。メサ構造を形成するためには、フォトリソグラフィなどの一般的な手法を適用すればよい。
<Step of Forming Mesa Structure Exposing Side of High Al Composition Layer>
Next, as shown in Step B of FIG. 1, a mesa structure for exposing the side surface of the high Al composition layer 41 is formed. A side surface of the high Al composition layer is exposed by forming a mesa structure having a specific shape and an arrangement pattern on the semiconductor laminate including the high Al composition layer 41. In order to form a mesa structure, a general method such as photolithography may be applied.

メサ構造を形成した後の半導体積層体の形状としては、半導体積層体を俯瞰した形が円形、四角形や六角形などの多角形とすることができ、また、長方形のように縦横比を変えてもよい。さらに、メサ構造を形成した後の半導体積層体の電流狭窄層40の全ての側面を露出させるように周囲を除去する場合と、高Al組成層の一部の側面は露出させずに残し、所定間隔の空隙を設けた凹形状の溝を形成する場合とがある。いずれの場合であっても、高Al組成層が酸化するために水蒸気が高Al組成層の側面に十分に触れることができるメサ構造となればよい。   As the shape of the semiconductor laminate after the formation of the mesa structure, the shape of the semiconductor laminate viewed from above can be a circle, a polygon such as a square or a hexagon, and the aspect ratio is changed like a rectangle. Is also good. Furthermore, the case where the periphery is removed so as to expose all the side surfaces of the current constriction layer 40 of the semiconductor laminate after the formation of the mesa structure, and the case where a part of the side surface of the high Al composition layer is left unexposed and In some cases, a concave groove having a gap is formed. In any case, the mesa structure is sufficient as the high Al composition layer is oxidized so that the steam can sufficiently touch the side surface of the high Al composition layer.

<高Al組成層の露出した側面から高Al組成層の一部を酸化する酸化工程>
メサ構造を形成する工程に続き、酸化工程を行う(図1ステップC)。本工程はAlxGa1-xAs(0.9≦x≦1)の高Al組成層を酸化する工程であり、酸化によって絶縁性のAl酸化物を主成分とする複合酸化物が生成すると考えられる。この酸化工程は、水蒸気を用いて行う酸化工程であり、水蒸気を0.001〜0.01g/L含む雰囲気で行うものとし、0.008g/L以下とすることが好ましい。なお、酸化工程中の高Al組成層41周辺の雰囲気中の水蒸気含有量が大きく変化しないように水蒸気を0.001〜0.01g/L含むガスを10〜30L/分で高Al組成層41に向けて流し続けることがより好ましい。また、水蒸気を0.001〜0.01g/L含むガスは、酸化速度の再現性を確保するために窒素やアルゴンなどの不活性ガスに水蒸気を含ませることがより好ましい。
<Oxidation step of oxidizing a part of the high Al composition layer from the exposed side surface of the high Al composition layer>
Following the step of forming the mesa structure, an oxidation step is performed (Step C in FIG. 1). This step is a step of oxidizing a high Al composition layer of Al x Ga 1 -x As (0.9 ≦ x ≦ 1). When the oxidation produces a complex oxide containing an insulating Al oxide as a main component, Conceivable. This oxidation step is an oxidation step performed using water vapor, and is performed in an atmosphere containing 0.001 to 0.01 g / L of water vapor, and preferably 0.008 g / L or less. In addition, a gas containing 0.001 to 0.01 g / L of steam is used at 10 to 30 L / min at a rate of 10 to 30 L / min so that the water vapor content in the atmosphere around the high Al composition layer 41 during the oxidation step does not greatly change. It is more preferable to keep flowing toward. It is more preferable that the gas containing 0.001 to 0.01 g / L of water vapor contains water vapor in an inert gas such as nitrogen or argon in order to secure reproducibility of the oxidation rate.

発明者らは、酸化速度が供給律速となるか反応律速となるかが本発明の水蒸気の濃度と関係があるのではないかと予想している。水蒸気濃度が0.01g/L以下であると、酸化速度は主に供給律速となって、温度のばらつきに起因する反応速度のばらつきが酸化速度に及ぼす影響が小さくなる。一方、水蒸気の濃度が0.01g/Lを超えると供給が十分となって酸化速度は反応律速となり、温度のばらつきに起因する反応速度のばらつきが酸化速度に及ぼす影響が過剰になると予想される。そして、供給律速となる条件では、結晶異方性の影響(結晶方位によって反応速度が異なる影響)も低減されているのではないかと予想している。なお、水蒸気の濃度が0.001g/L未満であると、酸化レートが小さすぎて酸化工程に必要な時間が長くなりすぎ、製造工程として実用的ではなくなるため、水蒸気濃度の下限を0.001g/L未満とした。   The inventors anticipate that whether the oxidation rate is rate-limiting or reaction-limited is related to the water vapor concentration of the present invention. When the water vapor concentration is 0.01 g / L or less, the oxidation rate is mainly controlled by the supply, and the influence of the variation in the reaction rate due to the variation in temperature on the oxidation rate is reduced. On the other hand, if the concentration of water vapor exceeds 0.01 g / L, the supply becomes sufficient and the oxidation rate becomes the reaction rate-determining, and it is expected that the variation in the reaction rate caused by the temperature variation will have an excessive effect on the oxidation rate. . It is expected that the influence of crystal anisotropy (the effect that the reaction rate varies depending on the crystal orientation) may be reduced under the conditions that control the supply. If the concentration of water vapor is less than 0.001 g / L, the oxidation rate is too small and the time required for the oxidation step becomes too long, which is not practical as a production step. / L.

酸化処理が行われる温度(ステージ温度)は、従来適正といわれる温度より高い温度が適しており、480〜580℃で行うものとし、510〜580℃で行うことが好ましい。なお、酸化処理が行われている最中の半導体積層体の表面温度を厳密に測定することは困難であるため、ウエハ搭載後の酸化処理直前のステージ温度(設定温度)を酸化処理の温度とする。ステージ温度が480℃未満では、上記の水蒸気の濃度では、酸化レートが小さすぎて酸化工程に必要な時間が長くなりすぎ、製造工程としての実用的ではなくなる。一方、ステージ温度が580℃を超えると、酸化が急激に起こるために酸化をさせる予定ではない高Al組成層以外の半導体層への影響も大きく、半導体積層体の表面荒れなどの悪影響が起こる恐れが生じる。また、本工程における酸化時間は、必要な狭窄形状に応じて、水蒸気濃度と酸化処理が行われる温度(ステージ温度)に合わせて適宜設定すればよい。限定を意図しないが、例えば酸化時間を10分〜3時間とすることができる。   The temperature at which the oxidation treatment is performed (stage temperature) is suitably higher than the temperature which is conventionally regarded as appropriate, and the oxidation is performed at 480 to 580 ° C, and preferably at 510 to 580 ° C. Since it is difficult to accurately measure the surface temperature of the semiconductor laminate during the oxidation process, the stage temperature (set temperature) immediately after the oxidation process after mounting the wafer is set to the temperature of the oxidation process. I do. If the stage temperature is lower than 480 ° C., the oxidation rate is too small and the time required for the oxidation step becomes too long at the above-mentioned water vapor concentration, which is not practical as a production step. On the other hand, if the stage temperature exceeds 580 ° C., the oxidation rapidly occurs, so that the semiconductor layers other than the high Al composition layer which is not supposed to be oxidized have a large influence, and there is a possibility that adverse effects such as surface roughening of the semiconductor laminate may occur. Occurs. In addition, the oxidation time in this step may be appropriately set according to the steam concentration and the temperature at which the oxidation treatment is performed (stage temperature) according to the required constriction shape. Although not intended to be limiting, for example, the oxidation time can be between 10 minutes and 3 hours.

このような酸化工程を行うための水蒸気酸化装置100の構成例を図2に示す。マスフローコントローラーにより一定量で水を供給するとともに純水気化器において100度以上(例えば180度)に加熱された蒸気を一定の水蒸気量で供給する機構110と、水蒸気を予熱した(例えば120度の)窒素ガスなどの不活性ガスを用いてステージまで送る機構120と、ステージ上にウエハWを搬送・回収する機構(図示せず)と、ステージを特定の温度(ステージ温度)に加熱する機構130と、を有する。さらに、水蒸気を含むガスをステージ上のウエハに供給を開始してから供給を停止するまでの酸化時間に対し、高Al組成層の酸化の停止を確実に行うために、水蒸気を含むガスの停止とともにウエハに水蒸気を含まないガスをウエハに噴霧する機構140を有していてもよい。図2には、チャンバ内に導入したガスを排出するための排出口150を併せて図示した。   FIG. 2 shows a configuration example of the steam oxidation apparatus 100 for performing such an oxidation step. A mechanism 110 for supplying a fixed amount of water by a mass flow controller and supplying a steam heated to 100 degrees or more (for example, 180 degrees) in a pure water vaporizer with a constant amount of steam, and preheating the steam (for example, 120 degrees) A) a mechanism 120 for feeding the wafer W to the stage using an inert gas such as nitrogen gas, a mechanism (not shown) for transferring and collecting the wafer W on the stage, and a mechanism 130 for heating the stage to a specific temperature (stage temperature). And Further, in order to reliably stop the oxidation of the high Al composition layer for the oxidation time from the start of supplying the gas containing water vapor to the wafer on the stage until the supply is stopped, the gas containing water vapor is stopped. Also, a mechanism 140 for spraying a gas containing no water vapor on the wafer may be provided. FIG. 2 also shows an outlet 150 for discharging the gas introduced into the chamber.

以上の各工程を経て得られたエピタキシャルウエハをダイシングすることで、半導体素子を得ることができる。なお、ダイシングに先立ち、図1ステップDに示すように、上部反射層50の上に上面電極61を設けてもよく、基板10の裏面に下面電極62を設けてもよいことは前述のとおりである。また、電極の形態はこの例に何ら限定されず、半導体素子の態様に応じて適宜設ければよい。   By dicing the epitaxial wafer obtained through each of the above steps, a semiconductor element can be obtained. Prior to dicing, as shown in Step D of FIG. 1, an upper electrode 61 may be provided on the upper reflective layer 50, and a lower electrode 62 may be provided on the back surface of the substrate 10 as described above. is there. The form of the electrode is not limited to this example at all, and may be provided as appropriate depending on the mode of the semiconductor element.

<エピタキシャルウエハ>
図1の符号を参照する。上記の製造方法によって得られるエピタキシャルウエハは、3インチ以上の基板10上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層41を含む半導体積層体を有する。そして、高Al組成層41と同一面内で高Al組成層41を挟持する酸化領域42により電流狭窄層40を構成する。そして、このエピタキシャルウエハは、電流狭窄層40の側面が露出したメサ構造を有しており、電流狭窄層40のウエハ面内での酸化量のばらつきを抑制することができる。ここで、ウエハ面内での酸化量のばらつきが抑制されるとは、すなわち、電流狭窄層40の酸化されていない狭窄領域の、ウエハ面内の19個以上の測定箇所について、狭窄形状の結晶方位<01−1>の幅と結晶方位<010>の幅とをそれぞれ測定した場合に、各結晶方位の幅の標準偏差が小さく、標準偏差が0.6μm以下であることをいう。標準偏差が0.4μm以下であることがより好ましい。
<Epitaxial wafer>
Reference is made to the reference numerals in FIG. The epitaxial wafer obtained by the above-described manufacturing method has a semiconductor laminate including a high Al composition layer 41 made of at least Al x Ga 1 -x As (0.9 ≦ x ≦ 1) on a substrate 10 of 3 inches or more. . Then, the current confinement layer 40 is constituted by the oxidized region 42 sandwiching the high Al composition layer 41 in the same plane as the high Al composition layer 41. The epitaxial wafer has a mesa structure in which the side surface of the current confinement layer 40 is exposed, and the variation of the oxidation amount of the current confinement layer 40 in the wafer surface can be suppressed. Here, that the variation in the oxidation amount in the wafer surface is suppressed, that is, in the non-oxidized narrow region of the current narrowing layer 40, at least 19 measurement points in the wafer surface have a narrow crystal. When the width of the orientation <01-1> and the width of the crystal orientation <010> are measured, it means that the standard deviation of the width of each crystal orientation is small and the standard deviation is 0.6 μm or less. More preferably, the standard deviation is 0.4 μm or less.

なお、(100)面を上面とする閃亜鉛鉱型の半導体結晶における結晶方位において、使用する基板のオリエンテーションフラット(OF)が(011)面である場合、結晶方位<01−1>はOF水平方向に相当し、結晶方位<010>はOFに対して45度斜め方向に相当する。   When the orientation flat (OF) of the substrate used is the (011) plane in the crystal orientation of the zinc blende type semiconductor crystal having the (100) plane as the upper surface, the crystal orientation <01-1> is OF horizontal. The crystal orientation <010> corresponds to a direction inclined by 45 degrees with respect to the OF.

<電流狭窄層の酸化されていない領域(狭窄形状)の測定方法>
ウエハ面内の19個以上の測定箇所は、ウエハ面内の中心P1を含む図3に示す19箇所の位置(P1〜P19)を有するものとする。19個を超えて測定する場合には、図3に示す19箇所と重ならない位置を測定箇所に選ぶものとする。測定箇所P1〜P19の位置は、下記のとおり定める。
<Method of measuring non-oxidized region (constriction shape) of current confinement layer>
19 or more measurement points in the wafer surface is assumed to have the position of the 19 locations shown in FIG. 3 including the center P 1 of the wafer surface (P 1 to P 19). When measuring more than 19 points, a position that does not overlap with the 19 points shown in FIG. 3 is selected as a measurement point. Position of the measuring points P 1 to P 19 are determined as follows.

まず、ウエハ中心を点P1とする。OFと平行かつ点P1を通過する直線において、ウエハエッジから距離L1内側の2点をそれぞれ点P2、P3と定める。次に、OFと平行な辺を含み、一辺の長さをL2とする正方形の各辺の頂点及び各辺を3等分した点を、時計回りにP4、P5、・・・P15と定める。さらに、OFと平行な辺を含み、一辺の長さをL3とする正方形の各辺の頂点を時計回りにP16、P17、P18、P19と定める。距離L1、L2、L3は、それぞれウエハ径の5/76、11/20、11/64とする。 First, the wafer center and the point P 1. In a straight line passing through the OF and parallel and point P 1, defined as the distance L 1 point inside the two points respectively P 2, P 3 from the wafer edge. Next, the vertices of each side of the square including the side parallel to the OF and the length of each side being L 2 and the points obtained by dividing each side into three equal parts are clockwise P 4 , P 5 ,. Determined as 15 . Further, the vertices of each side of a square including a side parallel to the OF and having a length of one side of L 3 are defined as P 16 , P 17 , P 18 , and P 19 in a clockwise direction. The distances L 1 , L 2 and L 3 are respectively 5/76, 11/20 and 11/64 of the wafer diameter.

狭窄形状の測定方法としては、酸化によって透過率が変わることを利用して、狭窄形状を俯瞰した位置から例えば赤外線カメラを用いて撮影すればよい。撮影画像を観察し、酸化した領域と酸化していない領域とのコントラスト差から電流狭窄層の酸化されていない領域(狭窄形状)のサイズを測定することができる。   As a method for measuring the stenosis shape, an image may be taken from a position overlooking the stenosis shape using, for example, an infrared camera, utilizing the fact that the transmittance changes due to oxidation. By observing the captured image, the size of the non-oxidized region (constricted shape) of the current confinement layer can be measured from the contrast difference between the oxidized region and the non-oxidized region.

<電流狭窄層の酸化されていない領域(狭窄形状)の形について>
メサ構造と同じく電流狭窄層の酸化されていない領域(狭窄形状)は、半導体積層体を俯瞰してみた場合の形が円形、四角形や六角形などの多角形とすることができ、また、長方形のように縦横比を変えてもよい。
<About the shape of the non-oxidized region (constriction shape) of the current confinement layer>
Similarly to the mesa structure, the non-oxidized region (constriction shape) of the current confinement layer can have a polygonal shape such as a circle, a quadrangle or a hexagon when the semiconductor laminate is viewed from above, and a rectangular shape. The aspect ratio may be changed as follows.

<異方性の抑制について>
本発明の製造方法に従い、電流狭窄層40の酸化されていない領域(狭窄形状)、つまり高Al組成層41の形状精度が上がる。メサ構造の特定パターンが円形であり、AlxGa1−xAs(0.9≦x<1)からなる高Al組成層41を含む電流狭窄層40を形成する場合、狭窄形状も円形となる。そして、円形における結晶方位<01−1>の幅(狭窄形状の直径)に対する結晶方位<010>の幅(狭窄形状の直径)の比の平均を、100〜102%と、従来に比べて高精度にすることができる。メサ構造と狭窄形状がともにひずみの無い円であると、電流の広がり方が均一となりやすく、半導体素子としての効率を上げることができるため好ましい。なお、以下の実施例において狭窄形状の直径を狭窄径とも記載する。
<Reducing anisotropy>
According to the manufacturing method of the present invention, the shape accuracy of the non-oxidized region of the current constriction layer 40 (constriction shape), that is, the high Al composition layer 41 is improved. When the specific pattern of the mesa structure is circular and the current confinement layer 40 including the high Al composition layer 41 of AlxGa1-xAs (0.9 ≦ x <1) is formed, the constriction shape also becomes circular. The average of the ratio of the width (diameter of the constriction shape) of the crystal orientation <010> to the width (diameter of the constriction shape) of the crystal orientation <01-1> in the circle is 100 to 102%, which is higher than the conventional one. Precision can be achieved. It is preferable that both the mesa structure and the constricted shape are circles having no distortion, because the current spreads easily uniformly and the efficiency as a semiconductor element can be increased. In the following examples, the diameter of the stenosis shape is also described as the stenosis diameter.

次に、実施例を用いて本発明をさらに詳細に説明するが、本発明は以下の実施例に何ら限定されるものではない。   Next, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to the following Examples.

[実施例1]
3インチのn型GaAs基板を用意した。次いで、MOCVD法により、上記GaAs基板(100)面上に、Al0.86Ga0.14As(70nm)とAl0.06Ga0.94As(60nm)のペアを繰り返して46ペア積層することで合計膜厚6μmの下部反射層(下部DBR)を結晶成長させた。下部反射層上に、発光層としてIn0.23Ga0.77Asを厚さ30nm結晶成長させた後、高Al組成層としてAl0.963Ga0.037Asを30nm結晶成長させた。高Al組成層上に、Al0.86Ga0.14As(70nm)とAl0.06Ga0.94As(60nm)のペアを繰り返して18ペア積層することで合計膜厚2.3μmの上部反射層(上部DBR)を結晶成長させた。
[Example 1]
A 3-inch n-type GaAs substrate was prepared. Next, 46 pairs of pairs of Al 0.86 Ga 0.14 As (70 nm) and Al 0.06 Ga 0.94 As (60 nm) are repeatedly laminated on the GaAs substrate (100) surface by MOCVD to form a lower part having a total film thickness of 6 μm. The reflection layer (lower DBR) was grown. On the lower reflective layer, a crystal of In 0.23 Ga 0.77 As was grown as a light emitting layer with a thickness of 30 nm, and then a crystal of Al 0.963 Ga 0.037 As was grown as a high Al composition layer with a thickness of 30 nm. An upper reflection layer (upper DBR) having a total film thickness of 2.3 μm is formed by repeatedly stacking 18 pairs of Al 0.86 Ga 0.14 As (70 nm) and Al 0.06 Ga 0.94 As (60 nm) on the high Al composition layer. Crystals were grown.

次いで、上記上部反射層の上面にレジストを塗布し、フォトリソグラフィにより直径50μmの円が220μm間隔で縦横に並ぶパターンに配置されたレジストマスクを形成した。その後、ドライエッチング装置によって、レジストマスクによりマスクされていない領域を上部反射層から下部反射層の一部が露出するまでエッチングした。これにより、上部反射層、高Al組成層、発光層、および下部反射層の一部が円筒状に特定のパターンで立ち並ぶメサ構造を作製した、高Al組成層の側壁は円筒の外周として露出した状態となる。   Next, a resist was applied to the upper surface of the upper reflective layer, and a resist mask in which circles having a diameter of 50 μm were arranged in a pattern in which the circles having a diameter of 50 μm were arranged vertically and horizontally at intervals of 220 μm was formed by photolithography. Thereafter, a region not masked by the resist mask was etched by a dry etching apparatus until a part of the lower reflective layer was exposed from the upper reflective layer. As a result, a mesa structure in which a part of the upper reflective layer, the high Al composition layer, the light emitting layer, and the lower reflective layer were arranged in a specific pattern in a cylindrical shape was produced. The side wall of the high Al composition layer was exposed as the outer periphery of the cylinder. State.

続いて、水蒸気酸化装置を用いて酸化処理を行った。酸化処理では、Al組成比の大きい層(本実施例1では、高Al組成層および下部反射層と上部反射層の一部に相当)が上記の円筒状の側壁から円筒の中心に向かう方向に酸化される。水蒸気酸化装置では、純水気化器において製造された180℃の水蒸気を、120℃の窒素ガスと混合し、処理チャンバ―内において540℃に加熱されたステージに搭載されたウエハの上記メサ構造に吹き付けた。このとき、処理チャンバ―の圧力は常圧とし、水蒸気を0.1g/min、および窒素ガスのガス流量を20L/minに調整することによって、吹き付けるガスの水蒸気濃度を1分あたり0.005g/Lとし、高Al組成層周辺の雰囲気中の水蒸気含有量が0.005g/Lとなるようにした。酸化処理の時間を110分間とし、水蒸気を含むガスの供給を停止すると共に25℃の窒素ガスをウエハの上記メサ構造に吹き付けることで酸化処理を停止させた。   Subsequently, an oxidation treatment was performed using a steam oxidation device. In the oxidation treatment, a layer having a large Al composition ratio (corresponding to a high Al composition layer and a part of the lower reflection layer and the upper reflection layer in the first embodiment) is moved from the cylindrical side wall toward the center of the cylinder. Oxidized. In the steam oxidation apparatus, 180 ° C steam produced in a pure water vaporizer is mixed with 120 ° C nitrogen gas, and the above mesa structure of a wafer mounted on a stage heated to 540 ° C in a processing chamber. Sprayed. At this time, the pressure of the processing chamber was set to normal pressure, the steam flow was adjusted to 0.1 g / min, and the gas flow rate of the nitrogen gas was adjusted to 20 L / min, so that the steam concentration of the gas to be blown was 0.005 g / min. L, so that the water vapor content in the atmosphere around the high Al composition layer was 0.005 g / L. The oxidation process was performed for 110 minutes, the supply of the gas containing water vapor was stopped, and the nitrogen gas at 25 ° C. was sprayed on the mesa structure of the wafer to stop the oxidation process.

続いて、酸化処理後のウエハの酸化量の計測を行った。赤外線カメラを用いて、上部反射層側からウエハ面内の19カ所(OFを紙面下方向にし、前述した図3に示す位置)において、メサ径(外周径)と、酸化されていない領域の径(狭窄径)をそれぞれ測定した。   Subsequently, the oxidation amount of the wafer after the oxidation treatment was measured. Using an infrared camera, the mesa diameter (outer diameter) and the diameter of the non-oxidized area were set at 19 places in the wafer surface (the position shown in FIG. 3 with the OF being downward in the drawing) from the upper reflective layer side. (Stenosis diameter) was measured.

レジストマスクを円形としたため、ドライエッチングにより形成されるメサ形状は円形であり、メサ径は当該円形の直径に相当する。そのため、メサ径は基板のオリフラ(011面)と水平方向の直径を代表値として測定した。酸化による狭窄径については、オリフラと水平方向である<01−1>方位の直径(水平狭窄径)だけでなく、オリフラに対し45°傾いた斜め方向である<010>方位の直径(斜め狭窄径)についても測定した。
なお、狭窄径は、赤外線カメラ(浜松ホトニクス製C9597−42U)を用いて観察した。酸化された領域と酸化されていない領域とでコントラスト差が生じるために、内蔵されている2点間距離計測の機能によって直径(狭窄径)を測定した。狭窄径を測定する際の赤外線カメラ写真のうち、点P16及び点P4の写真を代表例として図に示す。なお、各写真の中央部における濃色部が非酸化領域であり、当該濃色部を取囲む淡色部が酸化領域である。
Since the resist mask is circular, the mesa shape formed by dry etching is circular, and the mesa diameter corresponds to the diameter of the circle. Therefore, the mesa diameter was measured using the orientation flat (011 plane) of the substrate and the diameter in the horizontal direction as representative values. Regarding the constriction diameter due to oxidation, not only the diameter in the <01-1> direction (horizontal constriction diameter) that is horizontal to the orientation flat (horizontal constriction diameter), but also the diameter in the <010> direction (diagonal constriction) inclined 45 ° with respect to the orientation flat. Diameter) was also measured.
The stenosis diameter was observed using an infrared camera (C9597-42U manufactured by Hamamatsu Photonics). In order to cause a contrast difference between the oxidized region and the non-oxidized region, the diameter (constriction diameter) was measured by the built-in function of measuring the distance between two points. Of the infrared camera photographs in measuring the confinement diameter, shown in FIG photographs of the point P 16 and the point P 4 as a representative example. Note that the dark portion at the center of each photograph is a non-oxidized region, and the light portion surrounding the dark portion is an oxidized region.

[実施例2]
酸化処理の時間を100分間とした以外は、実施例1と同様にした。
[Example 2]
The procedure was the same as in Example 1, except that the time for the oxidation treatment was changed to 100 minutes.

[実施例3]
酸化処理の時間を40分間とした以外は、実施例1と同様にした。
[Example 3]
The procedure was the same as in Example 1, except that the oxidation time was set to 40 minutes.

[比較例1]
酸化処理において、水蒸気を1.2g/minおよび窒素ガスのガス流量を20L/minに調整することによって、吹き付けるガスの水蒸気濃度を1分あたり0.06g/Lとして高Al組成層周辺の雰囲気中の水蒸気含有量が0.06g/Lとなるようにし、ステージ温度を520℃、酸化処理の時間を29分40秒間(29.7分間)とした以外は、実施例1と同様にした。また、狭窄径を測定する際の赤外線カメラ写真のうち、点P16及び点P4の写真を代表例として図に示す。
[Comparative Example 1]
In the oxidation treatment, the steam concentration of the gas to be sprayed is adjusted to 0.06 g / L per minute by adjusting the steam flow rate to 1.2 g / min and the gas flow rate of the nitrogen gas to 20 L / min. Was adjusted to 0.06 g / L, the stage temperature was set to 520 ° C., and the oxidation treatment time was set to 29 minutes and 40 seconds (29.7 minutes). Also, of the infrared camera photographs in measuring the confinement diameter, shown in FIG photographs of the point P 16 and the point P 4 as a representative example.

[比較例2]
酸化処理において、水蒸気を1.2g/minおよび窒素ガスのガス流量を20L/minに調整することによって、吹き付けるガスの水蒸気濃度を1分あたり0.06g/Lとして高Al組成層周辺の雰囲気中の水蒸気含有量が0.06g/Lとなるようにし、酸化処理の時間を15分間とした以外は、実施例1と同様にした。
[Comparative Example 2]
In the oxidation treatment, the steam concentration of the gas to be sprayed is adjusted to 0.06 g / L per minute by adjusting the steam flow rate to 1.2 g / min and the gas flow rate of the nitrogen gas to 20 L / min. Was made in the same manner as in Example 1 except that the water vapor content was 0.06 g / L and the oxidation treatment time was 15 minutes.

[比較例3]
酸化処理において、水蒸気を0.4g/minおよび窒素ガスのガス流量を20L/minに調整することによって、吹き付けるガスの水蒸気濃度を1分あたり0.02g/Lとして高Al組成層周辺の雰囲気中の水蒸気含有量が0.02g/Lとなるようにし、酸化処理の時間を40分間とした以外は、実施例1と同様にした。
[Comparative Example 3]
In the oxidation treatment, by adjusting the steam flow rate to 0.4 g / min and the gas flow rate of the nitrogen gas to 20 L / min, the water vapor concentration of the gas to be blown is set to 0.02 g / L per minute, thereby reducing the atmosphere around the high Al composition layer. Example 2 was carried out in the same manner as in Example 1 except that the water vapor content was 0.02 g / L and the oxidation treatment time was 40 minutes.

実施例1〜3および比較例1〜3に係る酸化処理による酸化による狭窄径の評価を行った結果を表1に示す。なお、表中の水平狭窄径(μm)と斜め狭窄径(μm)については、図3に示す19か所の平均値と標準偏差(σ)の値をそれぞれ示し、斜め狭窄径と水平狭窄径との比率を「斜め/水平」(%)として表1に記載した。   Table 1 shows the results of evaluating the stenosis diameter due to oxidation by the oxidation treatment according to Examples 1 to 3 and Comparative Examples 1 to 3. As for the horizontal stenosis diameter (μm) and the oblique stenosis diameter (μm) in the table, the average value and the standard deviation (σ) of the 19 locations shown in FIG. 3 are shown, respectively. Are shown in Table 1 as “oblique / horizontal” (%).

表1の結果より、実施例1〜3においては比較例1〜3に比べて酸化処理時間は長くなるものの、狭窄径のばらつきを示す標準偏差(σ)の値が小さい。したがって、実施例1〜3では、ウエハ面内での酸化量のばらつきを抑制できることが分かった。また、斜め/水平の割合が100%に近いことから、メサ形状に対してより等方的に(異方性の影響を抑えて)酸化させることができることが分かった。   From the results in Table 1, the oxidation treatment time is longer in Examples 1 to 3 than in Comparative Examples 1 to 3, but the value of the standard deviation (σ) indicating the variation in the stenosis diameter is small. Therefore, in Examples 1 to 3, it was found that the variation of the oxidation amount in the wafer surface can be suppressed. In addition, since the ratio of oblique / horizontal is close to 100%, it was found that oxidation can be performed more isotropically (with the effect of anisotropy suppressed) on the mesa shape.

(評価1:Al組成による酸化レートの違いの評価)
上記の実施例1と比較例1ではAl0.963Ga0.037Asを30nm結晶成長後、酸化処理して電流狭窄層を形成した。これに替えて、電流狭窄層をAl0.976Ga0.024Asから形成したサンプルと、電流狭窄層をAlAsから形成したサンプルとを用意して、ウエハ中央(図3の点P1)における電流狭窄層のAl組成の違いによる酸化レート(=(メサ径−狭窄径)/2/処理時間)を測定した。水蒸気濃度0.06g/L・分、520℃での酸化処理の結果を図5に、水蒸気濃度0.005g/L・分、540℃での酸化処理の結果を図6に、それぞれ示す。
(Evaluation 1: Evaluation of difference in oxidation rate depending on Al composition)
In the above Example 1 and Comparative Example 1, Al 0.963 Ga 0.037 As was grown to a thickness of 30 nm and then oxidized to form a current confinement layer. Instead, a sample in which the current confinement layer is formed of Al 0.976 Ga 0.024 As and a sample in which the current confinement layer is formed of AlAs are prepared, and the current confinement layer is formed at the center of the wafer (point P 1 in FIG. 3). The oxidation rate (= (mesa diameter−constriction diameter) / 2 / treatment time) due to the difference in Al composition was measured. FIG. 5 shows the result of the oxidation treatment at 520 ° C. at a steam concentration of 0.06 g / L · min, and FIG. 6 shows the result of the oxidation treatment at 540 ° C. at a steam concentration of 0.005 g / L · min.

図5,6のグラフより、本製造方法に従って酸化処理を行った方が、Al組成差による酸化レートの変化を僅かに小さくできることが分かった。このことが、表1の狭窄径のばらつきの抑制につながっている可能性がある。   From the graphs of FIGS. 5 and 6, it was found that when the oxidation treatment was performed according to the present manufacturing method, the change in the oxidation rate due to the Al composition difference could be slightly reduced. This may have led to suppression of the variation in the stenosis diameter in Table 1.

(評価2:順方向電圧の評価)
酸化処理後のウエハについて、上面反射層上にAu/Znからなる金属層を蒸着し、460℃でのアニール処理を行って上面電極とした。その後、GaAs基板裏面にAu/Ni/Geからなる金属層を蒸着し裏面電極とし、410℃でのアニール処理を行って裏面電極とした。
(Evaluation 2: Evaluation of forward voltage)
With respect to the wafer after the oxidation treatment, a metal layer made of Au / Zn was vapor-deposited on the upper reflection layer, and an annealing treatment was performed at 460 ° C. to form an upper electrode. Thereafter, a metal layer made of Au / Ni / Ge was deposited on the back surface of the GaAs substrate to form a back electrode, and an annealing process at 410 ° C. was performed to form a back electrode.

ダイサーを用いてメサ構造の下部反射層の一部が露出した部分を切断して、個々の面発光レーザのチップとなるように分割した。チップを金属ステム上で銀ペーストを用いてマウントし、金ワイヤーを用いて上面電極にワイヤボンディングを行った。   A portion where the lower reflective layer of the mesa structure was exposed was cut using a dicer, and divided into individual surface emitting laser chips. The chip was mounted on a metal stem using a silver paste, and wire bonding was performed on the upper electrode using a gold wire.

定電流電圧測定装置を用いて電流10mAを流した時の順方向電圧を、ウエハ面内のウエハ中央からウエハ外周まで径方向に等間隔に10カ所(オリフラ水平方向)にわたって測定した。比較例1、比較例3、実施例1における測定結果を図7に示す。   Using a constant current voltage measuring device, the forward voltage when a current of 10 mA was passed was measured at equal intervals in the radial direction from the center of the wafer on the wafer surface to the outer periphery of the wafer over 10 locations (horizontal direction of the orientation flat). FIG. 7 shows the measurement results in Comparative Example 1, Comparative Example 3, and Example 1.

図7より、本発明の製造方法における酸化工程のように、水蒸気濃度を小さくすることで、ウエハ面内での順方向電圧のばらつきを低減できることが確認できた。   From FIG. 7, it was confirmed that, as in the oxidation step in the manufacturing method of the present invention, the variation in the forward voltage in the wafer surface can be reduced by reducing the water vapor concentration.

本発明によれば、従来よりもウエハ面内での酸化量のばらつきを抑制し、狭窄形状のばらつきが少ない品質が安定した面発光レーザなどの半導体素子を大量に提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the fluctuation | variation of the oxidation amount in a wafer surface is suppressed more conventionally, and the semiconductor element, such as a surface emitting laser with a stable quality with little fluctuation | variation of a constriction shape, can be provided.

1 半導体素子
10 基板
20 下部反射層
30 発光層
40 電流狭窄層
41 高Al組成層
42 酸化領域
50 上部反射層
100 水蒸気酸化装置
DESCRIPTION OF SYMBOLS 1 Semiconductor element 10 Substrate 20 Lower reflective layer 30 Light emitting layer 40 Current confinement layer 41 High Al composition layer 42 Oxidation area 50 Upper reflective layer 100 Steam oxidation device

Claims (7)

基板上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層を含む半導体積層体を形成する工程と、
少なくとも前記高Al組成層の側面を露出させるメサ構造を形成する工程と、
前記高Al組成層の露出した前記側面から前記高Al組成層の一部を酸化処理することで電流狭窄層を形成する酸化工程を有し、
前記酸化工程において、水蒸気を0.001〜0.01g/L含む雰囲気で、480〜580℃で酸化処理することを特徴とするエピタキシャルウエハの製造方法。
Forming a semiconductor laminate including a high Al composition layer made of at least Al x Ga 1 -x As (0.9 ≦ x ≦ 1) on a substrate;
Forming a mesa structure exposing at least a side surface of the high Al composition layer;
Oxidizing a part of the high Al composition layer from the exposed side surface of the high Al composition layer to form a current confinement layer,
The method of manufacturing an epitaxial wafer, wherein the oxidizing step is oxidized at 480 to 580 ° C. in an atmosphere containing water vapor at 0.001 to 0.01 g / L.
前記半導体積層体を形成する工程において、前記基板上に下部反射層、発光層、前記高Al組成層、上部反射層を順に形成する、請求項1に記載のエピタキシャルウエハの製造方法。   The method of manufacturing an epitaxial wafer according to claim 1, wherein in the step of forming the semiconductor laminate, a lower reflective layer, a light emitting layer, the high Al composition layer, and an upper reflective layer are sequentially formed on the substrate. 前記酸化工程の温度が510℃以上である、請求項1又は2に記載のエピタキシャルウエハの製造方法。   The method for producing an epitaxial wafer according to claim 1, wherein the temperature of the oxidation step is 510 ° C. or higher. 前記高Al組成層のAl組成xが0.9≦x<1である、請求項1〜3のいずれか1項に記載のエピタキシャルウエハの製造方法。   The method of manufacturing an epitaxial wafer according to claim 1, wherein an Al composition x of the high Al composition layer satisfies 0.9 ≦ x <1. 5. 請求項1〜4のいずれか1項に記載の製造方法により得られたエピタキシャルウエハをダイシングする工程を含む、半導体素子の製造方法。   A method for manufacturing a semiconductor device, comprising a step of dicing an epitaxial wafer obtained by the manufacturing method according to claim 1. 3インチ以上の基板上に少なくともAlxGa1-xAs(0.9≦x≦1)からなる高Al組成層を含む半導体積層体を有し、
少なくとも前記高Al組成層を含む電流狭窄層の側面が露出したメサ構造を具え、
前記高Al組成層は、前記メサ構造の外周側に設けられた酸化領域に挟持されて電流狭窄層を構成し、
酸化されていない狭窄領域を俯瞰してウエハ面内の19個以上の狭窄形状を測定した場合に、狭窄形状の結晶方位<01−1>の幅と、結晶方位<010>の幅との標準偏差がいずれも0.6μm以下であることを特徴とするエピタキシャルウエハ。
A semiconductor laminate including a high Al composition layer made of at least Al x Ga 1-x As (0.9 ≦ x ≦ 1) on a substrate of 3 inches or more;
A mesa structure in which a side surface of a current confinement layer including at least the high Al composition layer is exposed,
The high Al composition layer constitutes a current confinement layer sandwiched between oxidized regions provided on an outer peripheral side of the mesa structure,
When 19 or more constricted shapes in the wafer surface are measured while looking down on the confined region that has not been oxidized, the standard of the width of the crystal orientation <01-1> and the width of the crystal orientation <010> of the constricted shape is measured. An epitaxial wafer having a deviation of 0.6 μm or less.
前記狭窄形状が円形であり、
前記結晶方位<01−1>の幅に対する前記結晶方位<010>の幅の比の平均が100〜102%である、請求項6に記載のエピタキシャルウエハ。
The constriction shape is circular,
The epitaxial wafer according to claim 6, wherein an average of a ratio of a width of the crystal orientation <010> to a width of the crystal orientation <01-1> is 100 to 102%.
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