JP2020021450A - In-vehicle detection system - Google Patents

Abstract

To provide an in-vehicle detection system capable of increasing the accuracy of onboard sensors while suppressing the increase of memory capacity for larger capacity and more applications in the vehicle.SOLUTION: An in-vehicle detection system 100 includes: a non-volatile memory 101; a system-on-chip (SoC) 102 for reading and writing data to and from the non-volatile memory 101; and a detector 103 that outputs detection information to the SoC102. The SoC 102 changes the control signal of the non-volatile memory 101 according to the output of the detection unit 103.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a vehicle-mounted detection system including a system-on-chip.

  For the purpose of realizing various applications such as automatic driving and the like, development of an in-vehicle detection system provided with a system-on-chip (SoC) for processing information detected by a camera or the like is under way.

  In a conventional vehicle-mounted detection system, a DRAM (Dynamic Random Access Memory) that can be accessed at high speed has been mounted as a memory that functions as a work area of the SoC. In addition, since the DRAM is a volatile memory, in order to store programs executed by the SoC, in a conventional vehicle-mounted detection system, in addition to the DRAM, a ROM (Read Only Memory) having the same memory capacity as the DRAM is used. ) Also had to be implemented (Patent Document 1).

Japanese Patent No. 4739870

  However, along with the increase in the accuracy and capacity of camera sensors (imaging sensors) for the realization of automatic driving in the future, along with the further increase in applications in vehicles, conventional in-vehicle detection systems require DRAM and The memory capacity including the ROM increases. When the memory capacity, that is, the ratio of the area of the DRAM and the ROM to the mounting substrate increases, the substrate area must be increased, which causes a problem that the degree of freedom of mounting the system on the vehicle is restricted.

  Further, in the conventional vehicle-mounted detection system, it is necessary to transfer data from the ROM to the DRAM when the power is turned on. Therefore, as the system scale increases and the memory capacity increases, the time required for the system to enter the standby state becomes longer. That is, there is a practical problem that the time required from the start of the system to the start of the vehicle becomes long.

  The present disclosure solves the problems described above, and provides an in-vehicle detection system that can suppress an increase in memory capacity in response to an increase in the accuracy and capacity of a vehicle-mounted sensor and an increase in applications in a vehicle. The purpose is to:

  In order to achieve the above object, one embodiment of the on-vehicle detection system according to the present disclosure includes a nonvolatile memory, a system-on-chip that reads and writes data from and to the nonvolatile memory, and a system-on-chip A detection unit that outputs information, and the system-on-chip changes a write time of the nonvolatile memory by changing a control signal of the nonvolatile memory in accordance with an output of the detection unit, and changes a writing time of the nonvolatile memory. By setting the clock cycle longer than the maximum value of the writing time, the clock cycle of the nonvolatile memory is kept constant.

  Another embodiment of the in-vehicle detection system according to the present disclosure includes a nonvolatile memory, a system-on-chip that reads and writes data from and to the nonvolatile memory, and a detection unit that outputs detection information to the system-on-chip. The system-on-chip changes the write time of the nonvolatile memory by changing the control signal of the nonvolatile memory according to the output of the detection unit, and adjusts the write time of the nonvolatile memory according to the change. To change the clock cycle of the nonvolatile memory.

  According to the vehicle-mounted detection system according to the present disclosure, the system-on-chip changes the control signal of the nonvolatile memory according to the output of the detection unit. Therefore, the performance of the nonvolatile memory can be improved even in a severe vehicle environment. For example, if a type of non-volatile memory whose retention performance is degraded at high temperatures is used, when the ambient temperature of the non-volatile memory becomes, for example, 50 ° C. or more, the writing time of the non-volatile memory becomes longer. The retention performance of the nonvolatile memory can be maintained by changing the control signal.

  As described above, according to the in-vehicle detection system according to the present disclosure, the performance of the nonvolatile memory can be improved, so that at least a part of the data stored in the nonvolatile memory is a RAM such as a DRAM that functions as a work area. Can be directly read and written from the system-on-chip to the non-volatile memory without separately providing a memory. Therefore, an increase in the memory capacity and the number of memory devices, that is, an increase in the board area can be suppressed, so that the degree of freedom in mounting the system on the vehicle can be ensured. Further, since the power consumption of the system can be reduced, the size of the housing can be reduced and the components can be optimized, so that the cost can be reduced.

  Further, according to the on-vehicle detection system according to the present disclosure, by improving the performance of the nonvolatile memory, a configuration in which only the nonvolatile memory is used and a configuration in which the capacity of a DRAM or the like functioning as a work area is reduced can be adopted. Therefore, not only can the data be retained by the non-volatile memory when the power is turned off, but also the data transfer from the non-volatile memory to the DRAM or the like when the power is turned on becomes unnecessary, and the time required for the data transfer can be shortened. Therefore, it is possible to put the system in a standby state at high speed.

  According to the present disclosure, it is possible to provide an in-vehicle detection system capable of suppressing an increase in memory capacity in response to an increase in the accuracy and capacity of a vehicle-mounted sensor and an increase in applications in a vehicle. That is, it is possible to realize an in-vehicle detection system in which the degree of freedom of mounting the system on the vehicle is ensured and the waiting time until standby is short.

FIG. 1 is a block diagram of the vehicle-mounted detection system according to the embodiment. FIG. 2 is a block diagram of a vehicle-mounted detection system according to a comparative example. FIG. 3 is a block diagram of the vehicle-mounted detection system according to the first embodiment. FIG. 4 is an example of a timing diagram illustrating a relationship between an ambient temperature of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the first embodiment. FIG. 5 is an example of a timing chart illustrating a relationship between an ambient temperature of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the first embodiment. FIG. 6 is an example of a timing chart illustrating a relationship between an ambient temperature of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the first embodiment. FIG. 7 is an example of a timing chart illustrating a relationship between an ambient temperature of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the first embodiment. FIG. 8 is a block diagram of the vehicle-mounted detection system according to the second embodiment. FIG. 9 is an example of a timing diagram illustrating a relationship between a control signal and a rewrite frequency of a nonvolatile memory in the vehicle-mounted detection system according to the second embodiment. FIG. 10 is an example of a timing chart illustrating a relationship between a rewrite frequency of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the second embodiment. FIG. 11 is an example of a timing chart illustrating a relationship between a rewriting frequency of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the second embodiment. FIG. 12 is an example of a timing chart illustrating a relationship between a rewrite frequency of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the second embodiment. FIG. 13 is a configuration diagram of the nonvolatile memory in the vehicle-mounted detection system according to the first modification. FIG. 14 is an example of a timing chart showing a relationship between an ambient temperature of a nonvolatile memory and a control signal in the vehicle-mounted detection system according to the first modification. FIG. 15 is a block diagram of the vehicle-mounted detection system according to the second modification. FIG. 16 is a block diagram of the vehicle-mounted detection system according to the third modification.

  Hereinafter, a vehicle-mounted detection system according to an embodiment of the present disclosure will be described with reference to the drawings.

  FIG. 1 is a block diagram of the vehicle-mounted detection system according to the present embodiment. As shown in FIG. 1, a vehicle-mounted detection system 100 includes a nonvolatile memory 101, a system-on-chip (SoC) 102 that reads and writes data from and to the nonvolatile memory 101, and a detection that outputs detection information to the SoC 102. The SoC 102 changes the control signal of the nonvolatile memory 101 according to the output of the detection unit 103.

  As the nonvolatile memory 101, a nonvolatile memory that can be randomly accessed may be used. For example, a resistance change memory (Resistance RAM), a ferroelectric memory (Ferroelectric RAM), a magnetoresistive memory (Magnetic RAM), A change memory (Phase Change Memory) or the like may be used.

  The SoC 102 includes a processor that operates according to a program stored in the nonvolatile memory 101 as a main hardware configuration. The processor is not limited to a particular type as long as the function can be realized by executing a program. For example, the processor includes one or more electronic circuits including a semiconductor integrated circuit (IC) or an LSI (large scale integration). May be. The plurality of electronic circuits may be integrated on one chip, or may be provided on a plurality of chips. A plurality of chips may be integrated in one device, or may be provided in a plurality of devices.

  The detection unit 103 detects information related to the performance, operation, and the like of the nonvolatile memory 101, such as the ambient temperature and the rewriting frequency of the nonvolatile memory 101.

  The on-vehicle detection system 100 further includes a sensor 104 such as a camera sensor (imaging sensor) for photographing the outside of the vehicle. The information obtained by the sensor 104 is output to the SoC 102, and the SoC 102 processes the output information from the sensor 104 using, for example, a program read from the nonvolatile memory 101.

  Further, the on-vehicle detection system 100 may be connected to a CAN (Controller Area Network) 200 which is a communication network for interconnecting a plurality of control units mounted on the vehicle. The CAN 200 interconnects a plurality of control units mounted on the vehicle, various in-vehicle sensors, a switch device, and the like via, for example, a bus, thereby sharing data between the control units. Here, the in-vehicle detection system 100 may further include a CAN microcomputer 105 for performing communication between the SoC 102 and the CAN 200, and an EEPROM 106 that is a memory for the CAN microcomputer 105.

  The vehicle-mounted detection system 100 may further include a power supply circuit 107 for supplying a predetermined voltage to each of the nonvolatile memory 101, the SoC 102, the detection unit 103, the CAN microcomputer 105, and the EEPROM 106. The power supply circuit 107 may be supplied with power from an external power supply 300.

  According to the present embodiment described above, the SoC 102 changes the control signal of the nonvolatile memory 101 according to the output of the detection unit 103. Therefore, the performance of the nonvolatile memory 101 can be improved even in a severe vehicle environment. For example, if the non-volatile memory 101 whose retention performance is degraded at high temperatures is used, when the ambient temperature of the non-volatile memory 101 becomes, for example, 50 ° C. or more, the writing time of the non-volatile memory 101 is reduced. By changing the control signal so as to be longer, it is possible to compensate for a change in the retention performance of the nonvolatile memory 101.

  As described above, according to the present embodiment, since the performance of the nonvolatile memory 101 can be improved, data can be directly read and written from the SoC 102 to the nonvolatile memory 101 without separately providing a DRAM or the like functioning as a work area. be able to. Therefore, an increase in the memory capacity and the number of memory devices, that is, an increase in the board area can be suppressed, so that the degree of freedom in mounting the system on the vehicle can be ensured. Further, since the power consumption of the system can be reduced, the size of the housing can be reduced and the components can be optimized, so that the cost can be reduced.

  Further, according to the present embodiment, since the performance of the nonvolatile memory 101 can be improved, a configuration in which the SoC 102 uses only the nonvolatile memory 101 can be adopted. In other words, a DRAM or the like functioning as a work area of the SoC 102 may not be provided. For this reason, not only can the data be retained by the nonvolatile memory 101 when the power is turned off, but also the data transfer from the nonvolatile memory 101 to the DRAM or the like when the power is turned on can be eliminated, so that the system can be brought into a standby state at high speed. Become.

  In the present embodiment, if the control signal is changed so that the writing time of the nonvolatile memory 101 becomes longer when the ambient temperature of the nonvolatile memory 101 becomes, for example, 50 ° C. or more, the on-board detection system 100 Response to external devices may be slow. Therefore, the in-vehicle detection system 100 may output a signal to notify an external device via the CAN that the writing time of the nonvolatile memory 101 is controlled to be longer, for example.

  FIG. 2 is a block diagram of a vehicle-mounted detection system according to a comparative example. As shown in FIG. 2, the on-vehicle detection system 150 includes a ROM 151 such as a flash memory, an SoC 152, and a RAM 153 such as a DRAM that can be accessed at high speed. The ROM 151 stores programs executed by the SoC 152 and the like, and data is transferred from the ROM 151 to the RAM 153 when the power is turned on. Therefore, the ROM 151 and the RAM 153 have the same memory capacity. When the system is operating, the SoC 152 reads and writes data from and to the RAM 153. In addition, the vehicle-mounted detection system 150 includes a sensor 154, a CAN microcomputer 155, and an EEPROM 156, similarly to the vehicle-mounted detection system 100 shown in FIG. Further, the vehicle-mounted detection system 150 includes a power supply circuit 157 for supplying a predetermined voltage to the ROM 151, the SoC 152, the RAM 153, the CAN microcomputer 155, and the EEPROM 156, respectively.

  According to the in-vehicle detection system 150 of the comparative example, the memory capacity of the ROM 151 and the RAM 153 increases as the number of applications in the vehicle further increases, the accuracy of the mounted sensor increases, and the capacity increases. That is, as the area ratio of the ROM 151 and the RAM 153 to the mounting board increases, the board area must be increased, so that the degree of freedom of mounting the system on the vehicle is restricted.

  According to the vehicle-mounted detection system 150 of the comparative example, it is necessary to transfer data from the ROM 151 to the RAM 153 when the power is turned on. Therefore, as the system scale increases and the memory capacity increases, the time required for the system to enter the standby state becomes longer. That is, there is a practical problem that the time required from the start of the system to the start of the vehicle becomes long.

(Example 1)
FIG. 3 is a block diagram of the vehicle-mounted detection system according to the first embodiment. In FIG. 3, the same components as those in the vehicle-mounted detection system 100 shown in FIG.

  The in-vehicle detection system 100A according to the first embodiment illustrated in FIG. 3 includes, as the detection unit 103, a temperature detection circuit 103A that detects an ambient temperature of the nonvolatile memory 101 that affects the retention performance of the nonvolatile memory 101. The temperature detection circuit 103A may be arranged inside or near the nonvolatile memory 101. In the first embodiment, the SoC 102 changes the control signal of the non-volatile memory 101 according to the output of the temperature detection circuit 103A. The writing time of 101 can be adjusted. Therefore, since the fluctuation of the retention performance due to the ambient temperature of the nonvolatile memory 101 can be compensated, the performance of the nonvolatile memory 101 can be improved even in a severe vehicle environment.

  FIG. 4 is an example of a timing chart showing the relationship between the ambient temperature of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100A according to the first embodiment. In FIG. 4, “TEMP” is the output of the temperature detection circuit 103A (the ambient temperature of the nonvolatile memory 101), “CK” is a clock signal, “/ WE” is a write signal, “address” is an address signal, and “data”. Represents a data signal, and “write” represents a write time of the nonvolatile memory 101 (the same applies to FIGS. 5 to 7). In this example, the non-volatile memory 101 whose retention performance deteriorates at high temperatures is targeted.

  As shown in FIG. 4, the cycle of the clock signal CK is kept constant regardless of the ambient temperature TEMP. Further, when the clock signal CK rises to high, the nonvolatile memory 101 starts to take in the write signal / WE and a new address and data, so that writing to the nonvolatile memory 101 is started. In this example, the SoC 102 gives write time information according to the ambient temperature TEMP to the address signal. Specifically, as shown in FIG. 4, when the ambient temperature TEMP is lower than 50 ° C., the SoC 102 performs writing in a normal writing time (writing time 1: for example, 1 microsecond). Is set in the address signal, and when the ambient temperature TEMP is equal to or higher than 50 ° C., it is set in the address signal that writing is performed in a longer writing time than usual (writing time 2: for example, 100 μsec). As a result, the SoC 102 compensates for fluctuations in retention performance due to the ambient temperature of the nonvolatile memory 101. In this example, the SoC 102 sets the cycle of the clock signal CK longer than “write time 2” (that is, the maximum value of the write time) so that the cycle of the clock signal CK is constant regardless of the ambient temperature TEMP. Is held in.

  In the above description, "writing time 1" is, for example, 1 microsecond, and "writing time 2" is, for example, 100 microseconds. In the timing chart of FIG. 4, the width of “writing time 2” is expressed smaller than the actual one for easy understanding. Such an expression is the same in other timing diagrams described below.

  FIG. 5 is another example of a timing chart showing the relationship between the ambient temperature of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100A of the first embodiment. In this example, too, the non-volatile memory 101 whose retention performance deteriorates at high temperatures is targeted.

  As shown in FIG. 5, when the clock signal CK rises to a high level, the write signal / WE and a new address and data start to be fetched by the nonvolatile memory 101, so that writing to the nonvolatile memory 101 starts. Is done. Also in this example, the SoC 102 adds write time information corresponding to the ambient temperature TEMP to the address signal. Specifically, as shown in FIG. 5, when the ambient temperature TEMP is lower than 50 ° C., the SoC 102 sets the address signal to perform writing in a normal writing time (writing time 1). When the ambient temperature TEMP is equal to or higher than 50 ° C., it is set in the address signal that writing is performed for a writing time longer than usual (writing time 2). As a result, the SoC 102 compensates for fluctuations in retention performance due to the ambient temperature of the nonvolatile memory 101. In this example, when the ambient temperature TEMP is equal to or higher than 50 ° C., the SoC 102 raises the clock signal CK to high after the end of the writing (elapse of the writing time 2). Until the clock signal CK is kept low, the cycle of the clock signal CK is made longer than in the case where the ambient temperature TEMP is lower than 50 ° C.

  FIG. 6 is another example of a timing chart showing the relationship between the ambient temperature of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100A according to the first embodiment. In this example, too, the non-volatile memory 101 whose retention performance deteriorates at high temperatures is targeted.

  As shown in FIG. 6, the cycle of the clock signal CK is kept constant regardless of the ambient temperature TEMP. Further, when the clock signal CK rises to high, the nonvolatile memory 101 starts to take in the write signal / WE and a new address and data, so that writing to the nonvolatile memory 101 is started. In this example, the SoC 102 ends the writing to the nonvolatile memory 101 at the timing when the write signal / WE rises to high. Specifically, as shown in FIG. 6, when the ambient temperature TEMP is lower than 50 ° C., the SoC 102 raises the write signal / WE to high at a normal timing, thereby setting a normal write time. (Write time 1) is set. On the other hand, when the ambient temperature TEMP is equal to or higher than 50 ° C., the SoC 102 raises the write signal / WE to high at a timing later than usual, thereby increasing the write time longer than usual (write time 2). Set. As a result, the SoC 102 compensates for fluctuations in retention performance due to the ambient temperature of the nonvolatile memory 101. In this example, the SoC 102 sets the cycle of the clock signal CK longer than “write time 2” (that is, the maximum value of the write time) so that the cycle of the clock signal CK is constant regardless of the ambient temperature TEMP. Is held in.

  FIG. 7 is another example of a timing chart showing the relationship between the ambient temperature of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100A of the first embodiment. In this example, too, the non-volatile memory 101 whose retention performance deteriorates at high temperatures is targeted.

  As shown in FIG. 7, when the clock signal CK rises to a high level, the write signal / WE and a new address and data are started to be fetched by the nonvolatile memory 101, so that writing to the nonvolatile memory 101 starts. Is done. Also in this example, the SoC 102 ends the writing to the nonvolatile memory 101 at the timing when the write signal / WE rises to high. More specifically, as shown in FIG. 7, when the ambient temperature TEMP is lower than 50 ° C., the SoC 102 raises the write signal / WE to high at normal timing, thereby increasing the normal write time. (Write time 1) is set. On the other hand, when the ambient temperature TEMP is equal to or higher than 50 ° C., the SoC 102 raises the write signal / WE to high at a timing later than usual, thereby increasing the write time longer than usual (write time 2). Set. As a result, the SoC 102 compensates for fluctuations in retention performance due to the ambient temperature of the nonvolatile memory 101. In this example, when the ambient temperature TEMP is equal to or higher than 50 ° C., the SoC 102 raises the clock signal CK to high after the end of the writing (elapse of the writing time 2). Until the clock signal CK is kept low, the cycle of the clock signal CK is made longer than in the case where the ambient temperature TEMP is lower than 50 ° C.

  In the first embodiment, the threshold value of the ambient temperature at which the write time of the nonvolatile memory 101 is changed is described as 50 ° C., but is not particularly limited. May be set higher or lower. Further, the threshold value of the ambient temperature may be set in multiple stages as needed. The range of the threshold value of the ambient temperature, that is, the accuracy may be, for example, ± 10% (if the threshold value is 50 ° C., the range is from 45 ° C. to 55 ° C.). This range can also be set as appropriate according to the memory characteristics and the like.

  In the first embodiment, the non-volatile memory 101 whose retention performance is degraded at high temperatures is targeted. Alternatively, a non-volatile memory whose retention performance is improved at high temperatures is used. , SoC 102 may perform writing in a writing time shorter than usual when the ambient temperature becomes equal to or higher than the threshold.

  Further, in the first embodiment, the case where the “write time 1” is 1 microsecond and the “write time 2” is 100 microseconds is illustrated, but “write time 1” and “write time 2” are used. Is not particularly limited and can be set as appropriate according to memory characteristics and the like. For example, if the nonvolatile memory 101 to be used is a resistance change type memory, as described above, the “write time 1” is 1 microsecond, the “write time 2” is 100 microseconds, and the nonvolatile memory to be used is If 101 is a magnetoresistive memory, “writing time 1” may be, for example, about 10 nanoseconds to 100 nanoseconds, and “writing time 2” may be 100 microseconds. The description of such “writing time 1” and “writing time 2” is the same in the following Example 2.

(Example 2)
FIG. 8 is a block diagram of the vehicle-mounted detection system according to the second embodiment. In FIG. 8, the same components as those in the vehicle-mounted detection system 100 shown in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

  The in-vehicle detection system 100B according to the second embodiment illustrated in FIG. 8 includes, as the detection unit 103, a rewrite frequency that detects the rewrite frequency (the number of rewrites per unit time) of the nonvolatile memory 101 that affects the retention performance of the nonvolatile memory 101. The detection circuit 103B is provided. The rewrite frequency detection circuit 103B may be arranged inside or near the nonvolatile memory 101. In the second embodiment, the SoC 102 changes the control signal of the non-volatile memory 101 according to the output of the rewrite frequency detection circuit 103B. The writing time of the memory 101 can be adjusted. Therefore, since the fluctuation of the retention performance due to the rewriting frequency of the nonvolatile memory 101 can be compensated, the performance of the nonvolatile memory 101 can be improved even in a severe vehicle environment.

  FIG. 9 is an example of a timing chart showing the relationship between the rewriting frequency of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100B of the second embodiment. In FIG. 9, “DET” is the output of the rewrite frequency detection circuit 103B (the rewrite frequency of the nonvolatile memory 101 (the number of rewrites per unit time)), “CK” is a clock signal, “/ WE” is a write signal, and “/ WE” is a write signal. “Address” indicates an address signal, “Data” indicates a data signal, and “Write” indicates a writing time of the nonvolatile memory 101 (the same applies to FIGS. 10 to 12). In this example, the non-volatile memory 101 is of a type in which the retention performance deteriorates as the rewriting frequency increases.

  As shown in FIG. 9, the cycle of the clock signal CK is kept constant regardless of the rewriting frequency DET. Further, when the clock signal CK rises to high, the nonvolatile memory 101 starts to take in the write signal / WE and a new address and data, so that writing to the nonvolatile memory 101 is started. In this example, the SoC 102 adds write time information according to the rewrite frequency DET to the address signal. Specifically, as shown in FIG. 9, when the rewriting frequency DET (the number of rewritings per unit time) is less than 1000, the SoC 102 performs writing in the normal writing time (writing time 1). Is set in the address signal, and when the rewriting frequency DET is 1000 times or more, writing in a longer writing time (writing time 2) than usual is set in the address signal. As a result, the SoC 102 compensates for fluctuations in the retention performance due to the rewriting frequency of the nonvolatile memory 101. In this example, the SoC 102 sets the cycle of the clock signal CK longer than “write time 2” (that is, the maximum value of the write time) so that the cycle of the clock signal CK is constant regardless of the ambient temperature TEMP. Is held in.

  FIG. 10 is another example of a timing chart showing the relationship between the rewriting frequency of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100B of the second embodiment. This example also targets the nonvolatile memory 101 of the type in which the retention performance deteriorates as the rewriting frequency increases.

  As shown in FIG. 10, when the clock signal CK rises to a high level, the write signal / WE and a new address and data start to be fetched by the nonvolatile memory 101, so that writing to the nonvolatile memory 101 starts. Is done. Also in this example, the SoC 102 adds write time information according to the rewrite frequency DET to the address signal. Specifically, when the rewriting frequency DET (the number of rewritings per unit time) is less than 1000 times, the SoC 102 informs the address signal that writing is performed in the normal writing time (writing time 1). When the rewriting frequency DET is 1000 times or more, it is set in the address signal that writing is performed with a longer writing time (writing time 2) than usual. As a result, the SoC 102 compensates for fluctuations in the retention performance due to the rewriting frequency of the nonvolatile memory 101. In this example, when the rewriting frequency DET is 1000 times or more, the SoC 102 raises the clock signal CK to high after the end of writing (elapse of the writing time 2), in other words, the end of writing. Until the clock signal CK is kept low, the cycle of the clock signal CK is made longer than in the case where the rewrite frequency DET is less than 1000 times.

  FIG. 11 is another example of a timing chart showing the relationship between the rewrite frequency of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100B of the second embodiment. This example also targets the nonvolatile memory 101 of the type in which the retention performance deteriorates as the rewriting frequency increases.

  As shown in FIG. 11, the cycle of the clock signal CK is kept constant regardless of the rewriting frequency DET. Further, when the clock signal CK rises to high, the nonvolatile memory 101 starts to take in the write signal / WE and a new address and data, so that writing to the nonvolatile memory 101 is started. In this example, the SoC 102 ends the writing to the nonvolatile memory 101 at the timing when the write signal / WE rises to high. Specifically, as shown in FIG. 11, when the rewriting frequency DET (the number of rewritings per unit time) is less than 1,000, the SoC 102 raises the write signal / WE to high at normal timing. Thus, a normal writing time (writing time 1) is set. On the other hand, when the rewriting frequency DET is 1000 times or more, the SoC 102 raises the write signal / WE to high at a timing later than usual, thereby increasing the write time longer than usual (write time 2). Set. As a result, the SoC 102 compensates for fluctuations in the retention performance due to the rewriting frequency of the nonvolatile memory 101. In this example, the SoC 102 sets the cycle of the clock signal CK longer than “write time 2” (that is, the maximum value of the write time) so that the cycle of the clock signal CK is constant regardless of the ambient temperature TEMP. Is held in.

  FIG. 12 is another example of a timing chart showing the relationship between the rewrite frequency of the nonvolatile memory 101 and the control signal of the SoC 102 in the vehicle-mounted detection system 100B of the second embodiment. This example also targets the nonvolatile memory 101 of the type in which the retention performance deteriorates as the rewriting frequency increases.

  As shown in FIG. 12, when the clock signal CK rises to a high level, the write signal / WE and a new address and data start to be fetched by the nonvolatile memory 101, so that writing to the nonvolatile memory 101 starts. Is done. Also in this example, the SoC 102 ends the writing to the nonvolatile memory 101 at the timing when the write signal / WE rises to high. Specifically, as shown in FIG. 12, when the rewriting frequency DET (the number of rewritings per unit time) is less than 1000, the SoC 102 raises the write signal / WE to high at normal timing. Thus, a normal writing time (writing time 1) is set. On the other hand, when the rewriting frequency DET is 1000 times or more, the SoC 102 raises the write signal / WE to high at a timing later than usual, thereby increasing the write time longer than usual (write time 2). Set. As a result, the SoC 102 compensates for fluctuations in the retention performance due to the rewriting frequency of the nonvolatile memory 101. In this example, when the rewriting frequency DET is 1000 times or more, the SoC 102 raises the clock signal CK to high after the end of writing (elapse of the writing time 2), in other words, the end of writing. Until the clock signal CK is kept low, the cycle of the clock signal CK is made longer than in the case where the rewrite frequency DET is less than 1000 times.

  In the second embodiment, the threshold value of the rewriting frequency for changing the writing time of the nonvolatile memory 101 has been described as being 1000 times, but is not particularly limited. May be set to be large (however, up to about 10 million times) or small (but up to about 100 times). That is, the threshold value of the rewriting frequency has a range from about 100 times to about 10 million times depending on the type of the nonvolatile memory 101, and thus may be appropriately set to memory characteristics or the like. Further, the threshold value of the rewriting frequency may be set in multiple stages as needed. Further, the range of the threshold value of the rewriting frequency, that is, the accuracy may be, for example, ± 10% (if the threshold value is 1000 times, the range from 900 times to 1100 times). This range can also be set as appropriate according to the memory characteristics and the like.

  In the second embodiment, the non-volatile memory 101 whose retention performance is deteriorated when the rewriting frequency is increased is targeted. Alternatively, a non-volatile memory in which the retention performance is improved when the rewriting frequency is increased is used. When used, the SoC 102 may perform writing with a shorter writing time than usual when the rewriting frequency becomes equal to or higher than the threshold.

  In the first and second embodiments, the control signal of the non-volatile memory is changed according to the ambient temperature and the rewriting frequency of the non-volatile memory. May be detected, and the control signal of the nonvolatile memory may be changed according to the detected information.

(Modification 1)
In the first and second embodiments, the SoC 102 changes the control signal of the non-volatile memory 101 according to the output of the detection unit 103 (the temperature detection circuit 103A and the rewrite frequency detection circuit 103B), so that the non-volatile memory 101 The writing time was changed.

  On the other hand, in the first modification, the non-volatile memory 101 has a plurality of memory arrays, and the SoC 102 changes the control signal of the non-volatile memory 101 in accordance with the output of the detection unit 103, so that the non-volatile memory 101 The write target memory array of the memory 101 is changed.

  FIG. 13 is a schematic diagram illustrating an example of the configuration of the nonvolatile memory 101 according to the first modification. As shown in FIG. 13, the nonvolatile memory 101 according to the first modification includes a memory array 101a (memory array 1) having a normal retention performance at a high temperature and a memory array 101b (memory) having an excellent retention performance at a high temperature. Array 2).

  Hereinafter, a case will be described in which the vehicle-mounted detection system according to the first modification has the same configuration as the vehicle-mounted detection system according to the first embodiment illustrated in FIG.

  According to the first modification, the SoC 102 changes the control signal of the non-volatile memory 101 in accordance with the output of the temperature detection circuit 103A, so that the writing target of the non-volatile memory 101 is changed in accordance with the ambient temperature of the non-volatile memory 101. The memory array can be changed. Therefore, since the fluctuation of the retention performance due to the ambient temperature of the nonvolatile memory 101 can be compensated, the performance of the nonvolatile memory 101 can be improved even in a severe vehicle environment.

  FIG. 14 is an example of a timing chart showing the relationship between the ambient temperature of the nonvolatile memory 101 and the control signal of the SoC 102 in the first modification. In FIG. 14, “TEMP” is the output of the temperature detection circuit 103A (the ambient temperature of the nonvolatile memory 101), “CK” is a clock signal, “/ WE” is a write signal, “address” is an address signal, and “data”. Represents a data signal, and “write” represents a write time of the nonvolatile memory 101, respectively.

  As shown in FIG. 14, the cycle of the clock signal CK is kept constant regardless of the ambient temperature TEMP. Further, when the clock signal CK rises to high, the nonvolatile memory 101 starts to take in the write signal / WE and a new address and data, so that writing to the nonvolatile memory 101 is started. In the first modification, the SoC 102 adds the write target memory array information corresponding to the ambient temperature TEMP to the address signal. More specifically, as shown in FIG. 14, when the ambient temperature TEMP is lower than 50 ° C., the SoC 102 uses an address signal indicating that the retention performance at a high temperature is to be written to the normal memory array 1. When the ambient temperature TEMP is equal to or higher than 50 ° C., writing to the memory array 2 having excellent retention performance at high temperatures is set in the address signal. As a result, the SoC 102 compensates for fluctuations in retention performance due to the ambient temperature of the nonvolatile memory 101.

  As described above, the case where the in-vehicle detection system according to the first modification has the same configuration as the in-vehicle detection system 100A according to the first embodiment shown in FIG. 3 has been described. The present invention is also applicable to the vehicle-mounted detection system 100B of Example 2.

  That is, the non-volatile memory 101 has a memory array (memory array 1) having a normal retention performance when the rewriting frequency is high, and a memory array (memory array 2) having an excellent retention performance when the rewriting frequency is high. , The SoC 102 changes the control signal of the non-volatile memory 101 according to the output of the rewriting frequency detection circuit 103B, thereby changing the memory array to be written to the non-volatile memory 101 according to the rewriting frequency of the non-volatile memory 101. You may. This makes it possible to compensate for fluctuations in the retention performance due to the frequency of rewriting of the nonvolatile memory 101, so that the performance of the nonvolatile memory 101 can be improved even in a severe vehicle environment.

  In this case, the non-volatile memory 101 is controlled, for example, by setting an address signal to perform writing to the memory array 1 with a normal retention performance when the rewriting frequency is high when the rewriting frequency is lower than a threshold value, and When the frequency is equal to or higher than the threshold, writing to the memory array 2 having excellent retention performance when the rewriting frequency is high may be set in the address signal.

  In the first modification, the ambient temperature and the threshold value of the rewriting frequency for changing the memory array to be written into the nonvolatile memory 101 are not particularly limited, and can be arbitrarily set according to the memory characteristics and the like. May be set in multiple stages in accordance with.

  Further, in the first modification, the control signal of the nonvolatile memory 101 is changed according to the ambient temperature and the rewriting frequency of the nonvolatile memory 101, but instead, the control signal related to the performance and operation of the nonvolatile memory 101 is changed. Other information may be detected, and the control signal of the nonvolatile memory may be changed according to the detected information.

(Modification 2)
FIG. 15 is a block diagram of the vehicle-mounted detection system according to the second modification. In FIG. 15, the same components as those in the vehicle-mounted detection system 100 shown in FIG. 1 are denoted by the same reference numerals, and the duplicate description will be omitted.

  In the first and second embodiments, the temperature detection circuit 103A and the rewrite frequency detection circuit 103B are provided as the detection unit 103, and the SoC 102 stores the non-volatile memory 101 according to the output of the temperature detection circuit 103A and the rewrite frequency detection circuit 103B. The control signal was changed.

  On the other hand, in the vehicle-mounted detection system 100C of the second modification shown in FIG. 15, for example, a sensor 104C such as a camera sensor (image sensor) for photographing the outside of the vehicle is used, and the SoC 102 according to the output of the sensor 104C. Changes the control signal of the nonvolatile memory 101. That is, in the second modification, the detection unit 103 of the vehicle-mounted detection system 100 shown in FIG. 1 is configured by the sensor 104C.

  If the sensor 104C is an imaging sensor, for example, by changing the control signal of the nonvolatile memory 101 according to the importance of the imaging information, the writing time of the nonvolatile memory 101 and the memory array to be written are changed. Is also good.

  Note that Modification 2 is also applicable when the sensor 104C is a sensor other than the image sensor.

  In addition, the detection unit 103 such as the temperature detection circuit 103A according to the first embodiment or the rewrite frequency detection circuit 103B according to the second embodiment, and the sensor 104C according to the second modification are used in combination, and the SoC 102 is nonvolatile depending on the combination of these outputs. The control signal of the volatile memory 101 may be changed.

(Modification 3)
FIG. 16 is a block diagram of the vehicle-mounted detection system according to the third modification. In FIG. 16, the same components as those in the vehicle-mounted detection system 100 shown in FIG. 1 are denoted by the same reference numerals, and overlapping description will be omitted.

  In the on-vehicle detection system 100 shown in FIG. 1, the detection unit 103 directly outputs the detected information to the SoC 102.

  On the other hand, in the vehicle-mounted detection system 100D of the third modification shown in FIG. 16, the information detected by the detection unit 103D is output to the SoC 102 via the CAN (Controller Area Network) 200D and the CAN microcomputer 105.

  In the third modification, the SoC 102 may be one of the vehicle CPUs connected to the CAN 200D.

  In the third modification, the sensor 104C of the second modification may be provided instead of the detection unit 103D.

  The description of the above-described embodiments (including each example and modified examples; the same applies hereinafter) is merely an example in nature, and is not intended to limit the present invention, its application, or its use. Instead, various modifications are possible within the scope of the invention. For example, any combination of the embodiment and the modified example is possible.

  Further, in the above-described embodiment, the write time of the nonvolatile memory or the memory array to be written is changed by changing the control signal of the nonvolatile memory by the SoC. However, the present invention is not limited to these.

  In the embodiment described above, only the nonvolatile memory is provided as the memory used for the SoC. However, depending on the application in the vehicle, at least a part of the data stored in the nonvolatile memory functions as a work area. DRAM or the like may be separately provided. Also in this case, the capacity of the DRAM and the like can be reduced as compared with a conventional in-vehicle detection system in which a ROM and a DRAM having the same memory capacity are mounted, so that the degree of freedom of mounting the system on a vehicle is ensured. be able to. Further, the time required for data transfer from the nonvolatile memory to the DRAM or the like when the power is turned on can be reduced.

  Further, in the above-described embodiments, the configuration in which the sensor is provided is described, but the configuration in which the sensor is not provided may be employed. For example, the in-vehicle detection system may be an ECU (Electronic Control Unit) having a built-in temperature detection circuit as a detection unit. In this case, the in-vehicle detection system may change the control signal of the nonvolatile memory according to the detected temperature and output the detected temperature to an external device via, for example, the CAN. In this way, a vehicle-mounted detection system for outputting the temperature of the ECU is configured.

  INDUSTRIAL APPLICABILITY The present disclosure is useful as a vehicle-mounted detection system including a system-on-chip.

100, 100A, 100B, 100C, 100D In-vehicle detection system 101 Non-volatile memory 101a Memory array 1
101b Memory array 2
102 SoC
103, 103D detection unit 103A temperature detection circuit 103B rewrite frequency detection circuit 104, 104C sensor 105 CAN microcomputer 106 EEPROM
107 power supply circuit 200, 200D CAN
300 external power supply

Claims (11)

A non-volatile memory;
A system-on-chip that reads and writes data from and to the nonvolatile memory;
A detection unit that outputs detection information to the system-on-chip,
The system-on-chip changes a write time of the nonvolatile memory by changing a control signal of the nonvolatile memory according to an output of the detection unit, and changes a clock cycle of the nonvolatile memory to the write cycle. Setting the clock cycle of the nonvolatile memory to be constant,
In-vehicle detection system. A non-volatile memory;
A system-on-chip that reads and writes data from and to the nonvolatile memory;
A detection unit that outputs detection information to the system-on-chip,
The system-on-chip changes a write time of the non-volatile memory by changing a control signal of the non-volatile memory according to an output of the detection unit, and changes a write time of the non-volatile memory. Changing the clock cycle of the nonvolatile memory in accordance with
In-vehicle detection system. The in-vehicle detection system according to claim 1 or 2,
The non-volatile memory has a plurality of memory arrays,
The system-on-chip changes a write target memory array of the nonvolatile memory by changing a control signal of the nonvolatile memory.
In-vehicle detection system. The in-vehicle detection system according to claim 1 or 2,
The detection unit is a detection circuit that detects an ambient temperature of the nonvolatile memory,
In-vehicle detection system. The in-vehicle detection system according to claim 1 or 2,
The detection unit is a detection circuit that detects a rewrite frequency of the nonvolatile memory,
In-vehicle detection system. In claim 4 or 5,
The detection circuit is disposed inside or near the nonvolatile memory,
In-vehicle detection system. The in-vehicle detection system according to any one of claims 1 to 3,
The detection unit is configured by a sensor,
In-vehicle detection system. The in-vehicle detection system according to claim 7,
The sensor is an image sensor,
In-vehicle detection system. The in-vehicle detection system according to any one of claims 1 to 3, 7, and 8,
The apparatus further includes a CAN (Controller Area Network) interposed between the detection unit and the system-on-chip.
In-vehicle detection system. The in-vehicle detection system according to any one of claims 1 to 9,
The non-volatile memory is a randomly accessible memory,
In-vehicle detection system. The in-vehicle detection system according to claim 10,
The nonvolatile memory is a resistance change memory (Resistance RAM), a ferroelectric memory (Ferroelectric RAM), a magnetoresistive memory (Magnetic RAM), or a phase change memory (Phase Change Memory).
In-vehicle detection system.

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