JP2020013826A - Coil substrate - Google Patents

Abstract

To provide a coil substrate which makes it easy to change coil characteristics on front and back surfaces.SOLUTION: A coil substrate 10 includes a first surface 10F and a second surface 10S opposite to the first surface 10F and is formed by stacking a plurality of conductor layers 21, 23 and 25 having spiral coil patterns 30, 31 and 32 via interlayer insulating layers 22 and 24. Among the plurality of interlayer insulating layers 22 and 24, the outermost first interlayer insulating layer 22 on the first surface 10F side is made of resin containing no reinforcing material and the outermost second interlayer insulating layer 24 on the second surface 10S side is made of resin containing a reinforcing material.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a coil substrate.

  Patent Literature 1 discloses a coil substrate in which a plurality of conductor layers having a coil pattern and a plurality of insulating layers are alternately stacked.

Japanese Patent No. 5339974 ([0012], FIG. 12)

  Provided is a coil substrate which makes it easy to change coil characteristics on front and back surfaces.

  In order to solve the above-mentioned problem, the invention according to claim 1 has a first surface and a second surface opposite to the first surface, and the plurality of conductor layers having a spiral coil pattern have interlayer insulation. It is a coil substrate that is laminated via layers. Of the plurality of interlayer insulating layers, the outermost first interlayer insulating layer on the first surface side is made of a resin not containing a reinforcing material, and the outermost second interlayer insulating layer on the second surface side is made of a reinforcing material. It is composed of resin containing.

Side sectional view of coil substrate 1A is a plan cross-sectional view of a first conductor layer taken along a section AA in FIG. 1, and FIG. 1B is a plan cross-sectional view of a second conductor layer taken along a section BB in FIG. 1A is a cross-sectional plan view of the third conductor layer taken along the line CC in FIG. 1, and FIG. 1B is a cross-sectional plan view of the fourth conductor layer taken along the line DD in FIG. Enlarged side sectional view of coil substrate Sectional side view showing the manufacturing process of the coil substrate Sectional side view showing the manufacturing process of the coil substrate Sectional side view showing the manufacturing process of the coil substrate Sectional side view showing the manufacturing process of the coil substrate Sectional side view showing the manufacturing process of the coil substrate Sectional side view showing the manufacturing process of the coil substrate Side sectional view showing an example of using a coil substrate

  Hereinafter, the present embodiment will be described with reference to FIGS. As shown in FIG. 1, the coil substrate 10 of the present embodiment is configured by alternately stacking a plurality of conductor layers 21, 23, 25 and a plurality of interlayer insulating layers 22, 24. Then, solder resist layers 26, 26 are laminated on both the front and back surfaces. In the following, the front surface of the coil substrate 10 is referred to as a first surface 10F, and the rear surface is referred to as a second surface 10S.

  When the plurality of conductor layers 21, 23, and 25 are distinguished, the first conductor layers 21 are arranged in order from the outermost conductor layer 21 on the first surface 10F side to the outermost conductor layer 25 on the second surface 10S side. The conductor layer 21, the second conductor layer 23, the third conductor layer 25A, the fourth conductor layer 25B, and the fifth conductor layer 25C are referred to as the conductor layers 21, 23, 25A, and 25C. When the plurality of interlayer insulating layers 22 and 24 are distinguished, the interlayer insulating layer 22 adjacent to the first conductor layer 21 is referred to as a first interlayer insulating layer 22, and the other interlayer insulating layers 24 are referred to as a second interlayer insulating layer 24.

  Each conductor layer 21, 23, 25 is provided with a coil pattern 30, 31, 32, respectively. The coil patterns 30, 31, 32 are arranged in the thickness direction of the coil substrate 10. FIG. 2A shows the planar shape of the first conductor layer 21 as viewed from the first surface 10F side, together with the planar shape of the coil substrate 10. The planar shape of the coil substrate 10 is a horizontally long rectangle. The first conductor layer 21 has a coil pattern 30. The coil pattern 30 has a straight portion and a bent portion that bends at a right angle alternately connected from the outer end to the inner end. That is, the coil pattern 30 has a substantially rectangular shape as a whole, and has a spiral shape counterclockwise from the outer end to the inner end. The number of turns of the coil is five.

  FIG. 2B shows a planar shape of the second conductor layer 23 as viewed from the first surface 10F side. The second conductor layer 23 has a coil pattern 31 and a land 33 connected to the outer end of the coil pattern 30 of the first conductor layer 21. The coil pattern 31 forms a clockwise spiral from the outer end to the inner end. The number of turns of the coil is four.

  FIG. 3A shows the planar shape of the third conductor layer 25A viewed from the first surface 10F side. The fifth conductor layer 25C has the same planar shape as the third conductor layer 25A when viewed from the first surface 10F side. The third conductor layer 25A and the fifth conductor layer 25C have a coil pattern 32A and a land portion 33. The coil pattern 32A forms a counterclockwise spiral from the outer end to the inner end. The number of turns of the coil is three.

  FIG. 3B shows a planar shape of the fourth conductor layer 25B viewed from the first surface 10F side. The fourth conductor layer 25B has a coil pattern 32B and a land 33. The coil pattern 32B forms a clockwise spiral from the outer end to the inner end. The number of turns of the coil is three.

  As shown in FIG. 1, the coil patterns 30, 31, 32 are connected in series by via conductors 17 penetrating through the interlayer insulating layers 22, 24. Each via conductor 17 is reduced in diameter from the second surface 10S side to the first surface 10F side. The coil patterns 30, 31, 32 of the adjacent conductor layers 21, 23, 25 are connected in order of the inner ends, the outer ends, the inner ends, and the outer ends from the first surface 10F side. Thus, a series circuit of a plurality of coil patterns 30, 31, 32 is configured. Thereby, when a current flows through the series circuit of the plurality of coil patterns 30, 31, 32, the magnetic fluxes generated in the coil patterns 30, 31, 32 are directed in the same direction.

  A plurality of openings 26H that expose a part of the fifth conductor layer 25C are formed in the solder resist layer 26 on the S surface 10S side. The land portion 33 (not shown in FIG. 1) of the fifth conductor layer 25C and a part of the inner end of the coil pattern 32A are exposed from the opening 26H to form the pad 29. Also, an opening 26A is formed in the solder resist layer 26 on the F surface 10F side. The coil pattern 30 of the first conductor layer 21 is exposed from the opening 26A.

  Here, in the coil substrate 10 of the present embodiment, the first interlayer insulating layer 22 and the second interlayer insulating layer 24 are made of different materials. The first interlayer insulating layer 22 is made of an insulating resin containing no reinforcing material. For example, the first interlayer insulating layer 22 is a resin film for build-up obtained by adding a silica filler to an epoxy resin. The second interlayer insulating layer 24 is formed of an insulating resin layer having a reinforcing material. For example, the second interlayer insulating layer 24 is formed of a prepreg obtained by impregnating a glass cloth with a resin.

  As shown in FIG. 4, in the coil substrate 10 of the present embodiment, a part of the resin of the first interlayer insulating layer 22 is filled in the gap between the wirings of the coil pattern 30 of the first conductor layer 21. I have. The cross-sectional shape of the coil pattern 30 is substantially rectangular.

  In the coil substrate 10 of the present embodiment, the number of turns of the coil pattern 30 disposed on the first surface 10F side is larger than the number of turns of the coil pattern 32 disposed on the second surface 10S side. In addition, the number of turns of the coil patterns 30, 31, 32 gradually increases from the second surface 10S toward the first surface 10F. Specifically, as described above, the number of turns is 5 in the coil pattern 30 of the first conductor layer 21 located on the outermost surface on the first surface 10F side of the plurality of conductor layers 21, 23, and 25. Further, the number of turns of the coil pattern 31 of the second conductor layer 23 near the first surface 10F side next to the first conductor layer 21 is four. The number of turns of the coil pattern 32 of the other conductor layer 25 is three.

  The wiring width L1 of the coil pattern 30 of the first conductor layer 21 is smaller than the wiring widths L2 and L3 of the coil patterns 31 and 32 of the other conductor layers 23 and 25. Further, the spacing S1 between the wirings of the coil pattern 30 of the first conductor layer 21 is smaller than the spacing S2, S3 of the wiring of the coil patterns 31 and 32 of the other conductor layers 23 and 25. The wiring width L1 of the coil pattern 30 in the first conductor layer 21 is 13 to 20 [μm], and the interval S1 between the wirings is 13 to 20 [μm]. The wiring width L2 of the coil pattern 31 in the second conductor layer 23 is 15 to 25 [μm], and the interval S2 between the wirings is 15 to 25 [μm]. The wiring width L3 of the coil pattern 32 in the other conductor layer 25 is 20 to 40 [μm], and the spacing S3 between the wirings is 20 to 40 [μm].

  Next, a method for manufacturing the coil substrate 10 of the present embodiment will be described.

  (1) As shown in FIG. 5A, a support in which copper carriers 34, 34 are laminated on an F surface 50F, which is a front surface, and an S surface 50S, which is a back surface, of the support substrate 50. A member 51 is prepared. The support substrate 50 is formed by laminating copper foil 50D on both the front and back surfaces of a resin layer 50A, and the outer periphery of the copper foil 50D of the support substrate 50 and the carrier 34 are bonded to each other. The same process is performed on the carrier 34 on the F surface 50F side of the support substrate 50 and on the carrier 34 on the S surface 50S side.

  (2) As shown in FIG. 5B, a plating resist 35 having a predetermined pattern is formed on the carrier 34 of the support member 51.

  (3) As shown in FIG. 5C, an electrolytic copper plating process is performed to form a copper plating layer 36 on a portion of the carrier 34 that is exposed from the plating resist 35.

  (4) The plating resist 35 is peeled off, and the first conductor layer 21 having the coil pattern 30 is formed from the remaining copper plating layer 36 as shown in FIG.

  (5) As shown in FIG. 5 (E), the first interlayer insulating layer 22 is laminated on the first conductor layer 21 and hot-pressed. Then, the resin forming the first interlayer insulating layer 22 enters the gap between the coil patterns 30 formed on the adjacent first conductor layers 21.

  (6) As shown in FIG. 6A, the first interlayer insulating layer 22 is irradiated with a CO2 laser to form a via hole 22H. The via hole 22H is arranged on the first conductor layer 21.

  (7) Next, an electroless plating process is performed to form an electroless plating film (not shown) on the first interlayer insulating layer 22 and in the via hole 22H. Next, as shown in FIG. 6B, a plating resist 35 having a predetermined pattern is formed on the electroless plating film.

  (8) As shown in FIG. 6C, an electrolytic plating process is performed, the plating is filled in the via hole 22H to form the via conductor 17, and further, the electroless plating on the first interlayer insulating layer 22 is performed. An electrolytic plating film 38 is formed on a portion of the plating film (not shown) exposed from the plating resist 35.

  (9) While the plating resist 35 is peeled off, the electroless plating film (not shown) below the plating resist 35 is removed, and as shown in FIG. The film forms the second conductor layer 23 having the coil pattern 31 on the first interlayer insulating layer 22. Then, the first conductor layer 21 and the second conductor layer 23 are connected by the via conductor 17.

  (10) As shown in FIG. 7A, a second interlayer insulating layer 24 and a copper foil 24C overlaid on the second interlayer insulating layer 24 are laminated on the second conductor layer 23, and heated. Pressed.

  (11) As shown in FIG. 7B, the copper foil 24C and the second interlayer insulating layer 24 are irradiated with a CO2 laser to form via holes 24H. The via hole 24H is arranged on the second conductor layer 23.

  (12) Next, an electroless plating process is performed to form an electroless plating film (not shown) on the copper foil 24C and in the via hole 24H. Next, as shown in FIG. 7C, a plating resist 35 having a predetermined pattern is formed on the electroless plating film.

  (13) As shown in FIG. 8A, an electrolytic plating process is performed, the plating is filled in the via hole 24H to form the via conductor 17, and further, the electroless plating film ( Electrolytic plating film 38 is formed on a portion of plating resist 35 exposed (not shown).

  (14) While the plating resist 35 is peeled off, the electroless plating film (not shown) below the plating resist 35 and the copper foil 24C are removed, and as shown in FIG. The third conductor layer 25A having the coil pattern 32A is formed on the second interlayer insulating layer 24 by the foil 24C, the electrolytic plating film 38, and the electroless plating film. Then, the second conductor layer 23 and the third conductor layer 25A are connected by the via conductor 17.

  (15) By the same processing as (10) to (14) described above, as shown in FIGS. 8C and 9A, the fourth conductor layer 25B and the second conductor layer 25B are interposed via the second interlayer insulating layer 24. A fifth conductor layer 25C is formed.

  (16) As shown in FIG. 9B, the carrier 34 is separated from the support substrate 50.

  (17) As shown in FIG. 10A, the carrier 34 is removed by etching.

  (18) As shown in FIG. 10B, a solder resist layer 26 is formed on the first conductor layer 21 and the fifth conductor layer 25C.

  (19) As shown in FIG. 10C, an opening 26A is formed in the solder resist layer 26 on the F surface 10F side, and the coil pattern 30 of the first conductor layer 21 is exposed. Further, a tapered opening 26H is formed at a predetermined position of the solder resist layer 26 on the S surface 10S side, and a portion of the fifth conductor layer 25C exposed from the opening 26H becomes a pad 29. Thus, the coil substrate 10 shown in FIG. 1 is completed.

  The description of the structure and the manufacturing method of the coil substrate 10 of the present embodiment is as described above. Next, an example of use of the coil substrate 10 and the effects thereof will be described. The coil substrate 10 of the present embodiment is arranged so that the first surface 10F is brought close to the magnet 90, for example, as shown in FIG.

  In the coil substrate 10 of the present embodiment, the first interlayer insulating layer 22 disposed on the magnet 90 side among the plurality of interlayer insulating layers 22 and 24 is formed of a resin having no reinforcing material, while the second surface is formed. The second interlayer insulating layer 24 disposed on the 10S side is made of a resin having a reinforcing material. That is, unlike the conventional coil substrate in which the interlayer insulating layers on the front and back sides of the coil substrate 10 are formed of the same composition as in the conventional case, the coil substrate 10 of the present embodiment has the first interlayer on the first surface 10F side. The insulating layer 22 and the second interlayer insulating layer 24 on the second surface 10S side have different compositions. Thereby, the coil characteristics on both the front and back surfaces of the coil substrate 10 can be easily changed.

  The gap between the coil patterns 30 of the first conductor layer 21 is filled with the resin of the first interlayer insulating layer 22. Thereby, the strength can be improved as compared with the case where the gap between the coil patterns 30 of the first conductor layer 21 is not filled with the resin of the first interlayer insulating layer 22. Since the first interlayer insulating layer 22 does not have a reinforcing material, the gap between the coil patterns 30 is easily filled.

  Also, the number of turns of the coil pattern 30 of the first conductor layer 21 formed on the first surface 10F closest to the magnet 90 may be larger than the number of turns of the coil pattern 31 of the other conductor layers 23. Easy.

  Further, since the cross-sectional shape of the coil pattern 30 of the first conductor layer 21 is substantially rectangular, the space factor of the coil pattern 30 can be increased as compared with the coil pattern 30 having a trapezoidal cross-sectional shape. In the manufacturing process (5), the gap between the coil patterns 30 of the first conductor layer 21 is filled with a part of the resin of the first interlayer insulating layer 22. Thereby, when the carrier 34 is removed in the manufacturing process (17), the coil pattern 30 of the first conductor layer 21 is suppressed from being etched from the lateral direction.

The number of turns of the coil pattern 31 of the second conductor layer 23 formed on the first interlayer insulation layer 22 is the same as that of the third conductor layer 25A, fourth conductor layer 25B, The number of turns can be larger than the number of turns of the coil patterns 32A and 32B of the fifth conductor layer 25C.
[Other embodiments]

  (1) In the above embodiment, the configuration has only one first interlayer insulating layer 22 containing no reinforcing material. However, the configuration may have a plurality of first interlayer insulating layers 22.

  (2) In the above embodiment, the number of turns of each of the coil patterns 30, 31, and 32 is different, but may be the same. Further, a configuration in which the number of turns of the coil patterns 31 and 32 is larger than the number of turns of the coil pattern 30 may be employed.

  (3) In the above embodiment, the wiring width L1 of the coil pattern 30 and the wiring width L2 of the coil pattern 31 are different, but may be the same. In this case, the space S1 between the wires of the coil pattern 30 and the space S2 between the wires of the coil pattern 31 may be the same or different.

  (4) In the above embodiment, the interval S1 between the wirings of the coil pattern 30 and the interval S2 between the wirings of the coil pattern 31 are different, but they may be the same. In this case, the wiring width L1 of the coil pattern 30 and the wiring width L2 of the coil pattern 31 may be the same or different.

DESCRIPTION OF SYMBOLS 10 Coil board 10F 1st surface 10S 2nd surface 17 Via conductor 21, 23, 25 Conductive layer 22, 24 Interlayer insulating layer 29 Pad 30, 31, 32 Coil pattern 50 Support substrate 90 Magnet

Claims (8)

A coil substrate having a first surface and a second surface opposite to the first surface, wherein a plurality of conductor layers having a spiral coil pattern are stacked via an interlayer insulating layer,
Of the plurality of interlayer insulating layers, the outermost first interlayer insulating layer on the first surface side is made of a resin containing no reinforcing material, and the outermost second interlayer insulating layer on the second surface side is reinforced. It is composed of resin containing material. The coil substrate according to claim 1, wherein
The space between the coil patterns included in the outermost conductor layer on the first surface side is filled with a resin constituting the first interlayer insulating layer. It is a coil board of Claim 1 or 2, Comprising:
A wiring width of the coil pattern included in the outermost conductor layer on the first surface side is smaller than a wiring width of the coil pattern included in another conductor layer. The coil substrate according to claim 3, wherein
The wiring width of the coil pattern included in the conductor layer formed on the surface on the second surface side of the first interlayer insulating layer is the wiring width included in the outermost conductor layer on the second surface side. It is narrower than the wiring width of the coil pattern. The coil substrate according to claim 1, wherein:
An interval between the wirings of the coil pattern included in the outermost conductor layer on the first surface side is smaller than an interval between the wirings of the coil pattern included in the other conductor layers. The coil substrate according to claim 5, wherein
Further, a plurality of via conductors penetrating the interlayer insulating layer and connecting the coil patterns included in the conductor layer,
All the via conductors are reduced in diameter from the second surface side to the first surface side. The coil substrate according to claim 1, wherein:
The wiring of the coil pattern included in the outermost conductor layer on the first surface side has a rectangular cross section. The coil substrate according to claim 1, wherein:
Further, a solder resist layer is formed on the outermost conductor layer on the first surface side,
The solder resist layer has an opening for exposing the coil pattern included in the outermost conductor layer on the first surface side.