JP2020008509A - Zero-point detection device - Google Patents

Abstract

To output both rising and falling zero points with the same polarity by performing zero point detection determination and zero point detection by one comparator.SOLUTION: A reference voltage/threshold voltage generation circuit 1 and a zero-point detection part 2 are provided. The reference voltage/threshold voltage generation circuit 1 generates a reference voltage VREF, a first threshold voltage (+ side threshold voltage) VTHP, and a second threshold voltage (- side threshold voltage) VTHM. The zero-point detection part 2 detects a point of time when an input voltage VI exceeds VTHP and then falls below VREF as a zero point, and detects a point of time when the input voltage VI falls below VTHM and then exceeds VREF as a zero point. In this configuration, VTHP also serves as a zero-point detection start voltage when starting detection from a falling zero point and VTHM also serves as a zero-point detection start voltage when starting detection from a rising zero point.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a zero point detecting device that detects a voltage whose magnitude and direction periodically changes as an input voltage, and detects a rising point and a falling point of the input voltage from a reference voltage as a zero point, and in particular, relates to an ultrasonic flow rate. The present invention relates to a zero point detecting device suitable for use in a meter.

  In an ultrasonic flowmeter, the flow rate of a fluid is measured using two piezoelectric elements. For example, as shown in FIG. 13, a sound wave is propagated from the piezoelectric element 101 to the flow path 107 using the transmission circuit (TX) 103, and the sound wave is received by the other piezoelectric element 102. The reception signal is amplified and filtered by a reception circuit (RX) 104, and then a comparator 105 detects a zero point (a point crossing a reference potential (zero cross point)), and a transmission start time and a zero point detection time. , A propagation time is measured using a time-to-digital converter (TDC). In the example shown in FIG. 13, since the flow of the sound wave is in the forward direction with respect to the direction of the fluid, the time is measured at a speed in which the flow velocity and the sound velocity are combined.

  Similarly, as shown in FIG. 14, a sound wave is propagated from the piezoelectric element 102, and the piezoelectric element 101 receives the sound wave. Since the flow of the sound wave is in the opposite direction to the direction of the fluid, the time is measured at a speed obtained by subtracting the flow velocity from the sound speed. The flow velocity is determined from the difference between the time measurement in the forward direction and the reverse direction (more precisely, the difference between the reciprocals) and the propagation distance, and the flow rate of the fluid can be determined from the pipe diameter. 13 and 14, the side on which the piezoelectric element 101 is installed is defined as the DOWN side, and the side on which the piezoelectric element 102 is installed is defined as the UP side.

  FIG. 15 shows transmission / reception waveforms of the ultrasonic flowmeter. The transmission waveform is a burst wave, and the pulse is transmitted several times. A sound wave is transmitted from the piezoelectric element 101 (DOWN side), and after a propagation time (T delay), a signal is received by the other piezoelectric element 102 (UP side). Tdelay is determined by the propagation distance, the speed of sound, and the speed of the fluid. The sound speed varies depending on temperature, gas type, and the like. After a certain time (Talt), a sound wave is transmitted from the other piezoelectric element 102 (UP side) and received by the opposite piezoelectric element 101 (DOWN side). This operation is repeated at a certain interval (Tint).

Japanese Patent No. 2859751

  As described above, in the ultrasonic flow meter, the zero point is detected by the comparator when measuring the propagation time. This comparator corresponds to the zero point detecting device according to the present invention. The comparator must output a pulse exactly at the zero point of the input waveform. The input waveform is a signal in which the magnitude and direction of the voltage periodically changes around the reference potential, and detects the zero point at both the rise and fall of this signal.

  The comparator needs to be provided with hysteresis in order to avoid malfunction due to noise, and a simple comparator cannot detect both the rising and falling zero points. Further, in the propagation time measurement, in order to avoid erroneous detection due to noise, a mechanism for starting detection of a zero point from a point when a signal exceeds a certain threshold (zero point detection start voltage) is required. Further, from the viewpoint of signal processing in the subsequent stage, it is necessary to determine whether the detected zero point is a rising zero point or a falling zero point, and output the determination result together.

  Note that Patent Document 1 discloses a comparator that outputs both rising and falling zero points with the same polarity. In the comparator disclosed in Patent Document 1, it is possible to determine whether it is a rising zero point or a falling zero point by using an edge detector.

  However, when the comparator disclosed in Patent Document 1 is used as a comparator (zero-point detection device) in an ultrasonic flowmeter, the comparator (zero-point detection) cannot be set because a zero-point detection start voltage cannot be set. It is necessary to separately provide a comparator for determining the start of zero point detection in the device).

  Ultrasonic flowmeters require a high-speed comparator (zero-point detector) to perform accurate time measurement, and tend to increase power consumption. In such an ultrasonic flowmeter, when a plurality of comparators are provided in a comparator (zero point detection device), power consumption further increases. The power consumption of the ultrasonic flowmeter is severely restricted, for example, a 10-year warranty is required for battery operation, and an increase in power consumption is not preferable.

  The present invention has been made in order to solve such a problem, and an object of the present invention is to perform zero point detection start determination and zero point detection with one comparator, and to detect zero at both rising and falling. It is an object of the present invention to provide a zero-point detecting device that can output points with the same polarity and consumes less power.

  In order to achieve such an object, the present invention sets a voltage whose magnitude and direction periodically changes as an input voltage (VI), and determines a rising point and a falling point of the input voltage from a reference voltage (VREF). In a zero point detecting device (100) for detecting a zero point, a reference voltage (VREF), a first threshold voltage (VTHP) defined on the plus side with respect to the reference voltage, and a minus side with respect to the reference voltage. A reference voltage / threshold voltage generation circuit (1) configured to generate a predetermined second threshold voltage (VTHM), an input voltage (VI), a reference voltage (VREF), a first threshold voltage ( VTHP) and a second threshold voltage (VTHM), and a point in time when the input voltage falls below the reference voltage after exceeding the first threshold voltage is detected as a falling zero point. And a zero point detection unit (2) configured to detect a time point when the voltage exceeds the reference voltage after the voltage falls below the threshold voltage as a rising zero point, and the first threshold voltage (VTHP) is The second threshold voltage (VTHM) also serves as a zero point detection start voltage (VTHSM) when starting the detection from the zero point when the detection is started from the zero point. It is characterized in that it also serves.

  In the present invention, the time when the input voltage falls below the reference voltage after exceeding the first threshold voltage is detected as a falling zero point, and the time when the input voltage exceeds the reference voltage after falling below the second threshold voltage is detected. Is detected as a rising zero point. In this case, the first threshold voltage forms a dead zone between the detection of the rising zero point and the detection of the next falling zero point, and the second threshold voltage defines the falling zero point. A dead zone is created before the next rising zero point is detected after the detection, and this dead zone serves as hysteresis for avoiding malfunction due to noise. The first threshold voltage also serves as a zero point detection start voltage when starting detection from a falling zero point, and the second threshold voltage is used for zero point detection when starting detection from a rising zero point. Also serves as a starting voltage.

  As a result, in the present invention, it is possible to perform the zero point detection start determination and the zero point detection with one comparator, and output both the rising and falling zero points with the same polarity. In the present invention, when the detection of the zero point is started, the detection may be started from the falling zero point, or may be started from the rising zero point. For example, a reset signal or a set signal is used to select and set whether to start detection from a falling zero point or to start detection from a rising zero point.

  In the above description, as an example, components on the drawings corresponding to the components of the invention are indicated by reference numerals with parentheses.

  As described above, according to the present invention, a point in time when the input voltage falls below the reference voltage after exceeding the first threshold voltage is detected as a falling zero point, and the input voltage falls below the second threshold voltage. After that, the time when the voltage exceeds the reference voltage is detected as a rising zero point, and the first threshold voltage is also used as a zero point detection starting voltage when the detection is started from the falling zero point. Since the threshold voltage is also used as the zero point detection start voltage when detection is started from the rising zero point, one comparator performs zero point detection start determination and zero point detection, and performs both rising and falling detection. The zero point can be output with the same polarity, and the power consumption can be reduced.

FIG. 1 is a circuit diagram showing a main part of a zero point detecting device according to an embodiment of the present invention. FIG. 2 is a diagram showing input / output waveforms of the zero point detecting device. FIG. 3 is a diagram illustrating a control state (first control mode) of the operation of the switch unit by the switch control unit at point t0 in FIG. 2. FIG. 4 is a diagram illustrating a control state (second control mode) of the operation of the switch unit by the switch control unit at a point t1 in FIG. FIG. 5 is a diagram illustrating a control state (third control mode) of the operation of the switch unit by the switch control unit at a point t2 in FIG. FIG. 6 is a diagram illustrating a control state (fourth control mode) of the operation of the switch unit by the switch control unit at a point t3 in FIG. FIG. 7 is a diagram illustrating a control state (first control mode) of the operation of the switch unit by the switch control unit at point t4 in FIG. FIG. 8 is a diagram corresponding to FIG. 2A in a case where the detection is started from the zero point of the rising edge. FIG. 9 is a circuit diagram showing a main part of a zero point detection device having an offset cancel function. FIG. 10 is a diagram showing an excerpt of peripheral circuits centered on the comparator in FIG. FIG. 11 is a diagram showing a state when the clock CLK_CMP is set to the “L” level in FIG. FIG. 12 shows a state when clock CLK_CMP is set to “H” level in FIG. FIG. 13 is a diagram illustrating time measurement (time measurement from the DOWN side to the UP side) of the ultrasonic flowmeter. FIG. 14 is a diagram illustrating time measurement (time measurement from the UP side to the DOWN side) of the ultrasonic flowmeter. FIG. 15 is a diagram showing transmission / reception waveforms of the ultrasonic flowmeter.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a main part of a zero point detection device 100 (100A) according to an embodiment of the present invention. This zero point detection device 100A is used as a comparator 105 in the ultrasonic flow meter shown in FIG.

  The zero point detection device 100A of the present embodiment includes a reference voltage / threshold voltage generation circuit 1 and a zero point detection unit 2. The zero point detection unit 2 includes a switch unit 3, a comparator (amplifier for comparator) 4, And a switch control unit 5.

  In the zero point detection device 100A, the reference voltage / threshold voltage generation circuit 1 includes a reference voltage VREF, a first threshold voltage (+ threshold voltage) VTHP defined on the plus side with respect to the reference voltage VREF, A second threshold voltage (−threshold voltage) VTHM defined on the negative side with respect to the voltage VREF, output a reference voltage VREF from a terminal 1a, output a + threshold voltage VTHP from a terminal 1b, The negative threshold voltage VTHM is output from the terminal 1c.

  The switch unit 3 includes switches SW1 to SW6, and one ends of the switches SW1 and SW2 are connected to the input terminal PI1. The reception waveform of the sound wave received by the piezoelectric element 102 shown in FIG. 13 is input to the input terminal PI1. That is, a voltage whose magnitude and direction change periodically is input as the input voltage VI.

  In the switch section 3, one end of the switch SW3 is connected to a terminal 1b of the reference voltage / threshold voltage generation circuit 1 to which the + side threshold voltage VTHP is input, and one end of the switches SW4 and SW5 is connected to the reference voltage of the reference voltage / threshold voltage generation circuit 1. One terminal of the switch SW6 is connected to the terminal 1c of the reference voltage / threshold voltage generating circuit 1 to which the negative threshold voltage VTHM is input. The other ends of the switches SW1, SW5, and SW6 are connected to the non-inverting input terminal of the comparator 4, and the other ends of the switches SW2, SW3, and SW4 are connected to the inverting input terminal of the comparator 4.

  The switch control unit 5 includes an inverter circuit 6, NOR circuits 7_1 to 7_4, and a D flip-flop circuit 8. The input terminal of the inverter circuit 6 is connected to the output terminal of the comparator 4, and the output terminal of the inverter circuit 6 is connected to the clock input terminal of the D flip-flop circuit 8. The Q output terminal of the D flip-flop circuit 8 is connected to the output terminal PO2, the Q bar output terminal of the D flip-flop circuit 8 is connected to the D input terminal of the D flip-flop circuit 8, and the reset terminal of the D flip-flop circuit 8 is Connected to input terminal PI2. The output terminal PO1 is connected to a connection line between the output terminal of the inverter circuit 6 and the clock input terminal of the D flip-flop circuit 8.

  In the switch control unit 5, the Q output of the D flip-flop circuit 8 is output from the output terminal PO2 as the voltage VQ. The voltage generated at the output terminal of the inverter circuit 6 is output from the output terminal PO1 as the voltage VO. As will be described later, the voltage VO output from the output terminal PO1 is a signal indicating a zero point (zero point detection signal), and the voltage VQ output from the output terminal PO2 is a falling zero point. It is a signal indicating whether or not it is the rising zero point. A reset signal RN is input from the input terminal PI2 to the D flip-flop circuit 8 as a signal for selecting and setting to start detection from the falling zero point.

  In the switch control unit 5, the NOR circuit 7_1 receives the output voltage VOX of the comparator 4 and the Q output (voltage VQ) of the D flip-flop circuit 8, and outputs a logic voltage VOPX. The NOR circuit 7_2 receives the output voltage VO of the inverter circuit 6 and the Q output (voltage VQ) of the D flip-flop circuit 8, and outputs a logic voltage VOP. The NOR circuit 7_3 receives the output voltage VO of the inverter circuit 6 and the Q bar output (voltage VQN) of the D flip-flop circuit 8 and outputs a logic voltage VOM. The NOR circuit 7_4 receives the output voltage VOX of the comparator 4 and the Q bar output (voltage VQN) of the D flip-flop circuit 8 and outputs a logic voltage VOMX.

  In the switch unit 3, the switch SW1 is turned on when the Q bar output (voltage VQN) of the D flip-flop circuit 8 is at the “H” level, and is turned off when it is at the “L” level. The switch SW2 is turned on when the Q output (voltage VQ) of the D flip-flop circuit 8 goes to “H” level, and turned off when it goes to “L” level. The switch SW3 is turned on when the logic voltage VOPX from the NOR circuit 7_1 goes to "H" level, and turned off when it goes to "L" level. The switch SW4 is turned on when the logic voltage VOP from the NOR circuit 7_2 goes to "H" level, and turned off when it goes to "L" level. The switch SW5 is turned on when the logic voltage VOM from the NOR circuit 7_3 goes to “H” level, and turned off when it goes to “L” level. The switch SW6 is turned on when the logic voltage VOMX from the NOR circuit 7_4 goes to “H” level, and turned off when it goes to “L” level.

  FIG. 2 shows input / output waveforms of the zero point detection device 100A. 2A shows the input voltage VI input to the input terminal PI1, FIG. 2B shows the reset signal RN input to the input terminal PI2, and FIG. 2C shows the output signal from the output terminal PO2. 2D shows the voltage VQ (the Q output of the D flip-flop circuit 8), and FIG. 2D shows the voltage VO (the output voltage of the inverter circuit 6) output from the output terminal PO1.

  In the zero point detection device 100A, first, a reset signal RN is given to the D flip-flop circuit 8. That is, the reset signal RN to the D flip-flop circuit 8 is set to the “H” level (point t0 in FIG. 2). As a result, the D flip-flop circuit 8 is reset, and the Q output (voltage VQ) of the D flip-flop circuit 8 goes low and the Q bar output (voltage VQN) goes high. Further, the logic voltage VOPX output from the NOR circuit 7_1 becomes "H" level (see FIG. 3). In this example, the voltage VQ is at the “L” level and the voltage VO is at the “H” level before the reset signal RN is supplied to the D flip-flop circuit 8.

  As a result, in the switch unit 3, the switches SW1 and SW3 are turned on, the input voltage VI is input to the non-inverting input terminal of the comparator 4, and the + threshold voltage VTHP is set to the inverting input terminal of the comparator 4. Will be done. The control state of the operation of the switch unit 3 by the switch control unit 5 that turns on the switches SW1 and SW3 is referred to as a first control mode M1.

  In the first control mode M1, the + threshold voltage VTHP is set at the inverting input terminal of the comparator 4. As a result, as described later, detection starts from the falling zero point. In the present embodiment, when starting detection of a zero point, the D flip-flop circuit 8 is reset using the reset signal RN, and selection and setting to start detection from the falling zero point are selected. .

  In the first control mode M1, the output voltage VOX of the comparator 4 maintains the “L” level until the input voltage VI exceeds the + threshold voltage VTHP (points t0 to t1 in FIG. 2). When the input voltage VI exceeds the + side threshold voltage VTHP (point t1 in FIG. 2), the output voltage VOX of the comparator 4 becomes “H” level, and the output voltage VO of the inverter circuit 6 becomes “L” level (FIG. 4). reference). Therefore, the logic voltage VOPX output from the NOR circuit 7_1 becomes “L” level, and the logic voltage VOP output from the NOR circuit 7_2 becomes “H” level.

  As a result, in the switch section 3, the switch SW3 is turned off, the switch SW4 is turned on, and the voltage set to the inverting input terminal of the comparator 4 is switched from the + threshold voltage VTHP to the reference voltage VREF. Note that the switch SW1 keeps the ON state because the voltage VQN maintains the state of the “H” level, and the input voltage VI is continuously input to the non-inverting input terminal of the comparator 4. The control state of the operation of the switch unit 3 by the switch control unit 5 that turns on the switches SW1 and SW4 is referred to as a second control mode M2.

  In the second control mode M2, the output voltage VOX of the comparator 4 is maintained at the “H” level until the input voltage VI falls below the reference voltage VREF (points t1 to t2 in FIG. 2), and the output voltage VO of the inverter circuit 6 is maintained. Maintain the “L” level. When the input voltage VI falls below the reference voltage VREF (point t2 in FIG. 2), the output voltage VOX of the comparator 4 becomes “L” level, and the output voltage VO of the inverter circuit 6 becomes “H” level (see FIG. 5). .

  When the output voltage VO of the inverter circuit 6 becomes “H” level, the Q output (voltage VQ) of the D flip-flop circuit 8 becomes “H” level, the Q bar output (voltage VQN) becomes “L” level, and the NOR circuit 7_2 Output from the NOR circuit 7_4 to the "H" level.

  As a result, in the switch unit 3, the switches SW1 and SW4 are turned off, the switches SW2 and SW6 are turned on, and the input voltage VI is input to the inverting input terminal of the comparator 4, and the non-inverting input of the comparator 4 The negative threshold voltage VTHM is set at the end. The control state of the operation of the switch unit 3 by the switch control unit 5 that turns on the switches SW2 and SW6 is referred to as a third control mode M3.

  In the third control mode M3, the output voltage VOX of the comparator 4 becomes “L” level until the input voltage VI falls below the negative threshold voltage VTHM (points t2 to t3 in FIG. 2), and the output voltage of the inverter circuit 6 VO keeps "H" level. When the input voltage VI falls below the negative threshold voltage VTHM (point t3 in FIG. 2), the output voltage VOX of the comparator 4 goes to the “H” level, and the output voltage VO of the inverter circuit 6 goes to the “L” level (FIG. 6). reference). Therefore, the logic voltage VOMX output from the NOR circuit 7_4 becomes “L” level, and the logic voltage VOM output from the NOR circuit 7_3 becomes “H” level.

  As a result, in the switch section 3, the switch SW6 is turned off, the switch SW5 is turned on, and the voltage set to the non-inverting input terminal of the comparator 4 is switched from the negative threshold voltage VTHM to the reference voltage VREF. Note that the switch SW2 keeps the ON state because the voltage VQ maintains the “H” level state, and the input voltage VI is continuously input to the inverting input terminal of the comparator 4. The control state of the operation of the switch unit 3 by the switch control unit 5 that turns on the switches SW2 and SW5 is referred to as a fourth control mode M4.

  In the fourth control mode M4, the output voltage VOX of the comparator 4 is maintained at the “H” level until the input voltage VI exceeds the reference voltage VREF (point t3 to t4 in FIG. 2), and the output voltage VO of the inverter circuit 6 is maintained. Maintain the “L” level. When the input voltage VI exceeds the reference voltage VREF (point t4 in FIG. 2), the output voltage VOX of the comparator 4 becomes “L” level, and the output voltage VO of the inverter circuit 6 becomes “H” level (see FIG. 7). .

  When the output voltage VO of the inverter circuit 6 becomes “H” level, the Q output (voltage VQ) of the D flip-flop circuit 8 becomes “L” level, the Q bar output (voltage VQN) becomes “H” level, and the NOR circuit 7_1 Output from the NOR circuit 7_3 attains an "H" level, and the logic voltage VOM output from the NOR circuit 7_3 attains an "L" level.

  As a result, in the switch unit 3, the switches SW2 and SW5 are turned off, the switches SW1 and SW3 are turned on, and the input voltage VI is input to the non-inverting input terminal of the comparator 4. The positive side threshold voltage VTHP is set at the end. That is, the control state of the operation of the switch unit 3 by the switch control unit 5 returns to the first control mode M1. Similarly, the switch control unit 5 repeats the control of the operation of the switch unit 3 in the order of the first control mode M1, the second control mode M2, the third control mode M3, and the fourth control mode M4. .

  As described above, in the zero point detecting apparatus 100A of the present embodiment, the voltage VO changes to the “H” level every time the waveform of the input voltage VI crosses the reference voltage VREF, and both the rising and falling have the same polarity. Is obtained from the output terminal PO1 as the zero point detection signal. Also, when detecting the falling zero point, the voltage VQ changes to the “H” level, and when detecting the rising zero point, the voltage VQ changes to the “L” level, and the level changes when the zero point is detected. The voltage VQ is obtained from the output terminal PO2 as a signal indicating whether the detected zero point is a falling zero point or a rising zero point.

  In the zero point detection device 100A, the time point at which the input voltage VI falls below the reference voltage VREF after exceeding the positive side threshold voltage VTHP is detected as a falling zero point ZPD, and the input voltage VI falls below the negative side threshold voltage VTHM. After that, the point when the voltage exceeds the reference voltage VREF is detected as the rising zero point ZPU. In this case, the + side threshold voltage VTHP forms a dead zone α before detecting the next falling zero point ZPD after detecting the rising zero point ZPU, and the − side threshold voltage VTHM is A dead zone β is created before the detection of the next rising zero point ZPU after the detection of the zero point ZPD, and these dead zones α and β serve as hysteresis for avoiding malfunction due to noise. In the zero point detection device 100A, the positive threshold voltage VTHP also serves as a zero point detection start voltage VTHSP when starting detection from the falling zero point ZPD. This makes it possible to reduce the influence of noise and perform accurate time measurement.

  As described above, according to the zero point detecting apparatus 100A of the present embodiment, one comparator (comparator amplifier) 4 performs the zero point detection start determination and the detection of the zero point, and detects both the rising and falling zeros. Points can be output with the same polarity, and power consumption can be reduced.

  In the above-described embodiment, the D flip-flop circuit 8 is reset by using the reset signal RN, and selection to start detection from the falling zero point is selected and set. The D flip-flop circuit 8 may be set to a set state by using a set signal (not shown) to the circuit 8, and selection and setting to start detection from the rising zero point may be made.

  In this case, as shown in FIG. 8, the control of the operation of the switch unit 3 is repeated in the order of the third control mode M3, the fourth control mode M4, the first control mode M1, and the second control mode M2. To do. In this case, the zero-side threshold voltage VTHM also serves as the zero-point detection start voltage VTHSM when the detection starts from the zero point at the rise.

  9, a capacitor C is connected to the input line of the voltage to the non-inverting input terminal of the comparator 4, and the offset voltage generated at the non-inverting input terminal of the comparator 4 is detected. You may make it cancel.

  In the zero point detection device 100B, switches SWA1, SWA2, and SWA3 and switches SWB1 and SWB2 are provided, and a signal obtained by inverting the clock (clock of the offset cancel function) CLK_CMP is referred to as SEL, and a signal obtained by further inverting the SEL is referred to as SELB. , When SEL is at “H” level, switches SWA1, SWA2, and SWA3 are turned on, and when SELB is at “H” level, switches SWB1 and SWB2 are turned on. An offset cancel function is obtained.

FIG. 10 shows an excerpt of a peripheral circuit centered on the comparator (amplifier) 4. When the clock CLK_CMP is set to the “L” level (see FIG. 11), the switches SWA1, SWA2, and SWA3 are turned on. In this case, the comparator 4 becomes a voltage follower circuit, given as _{Vo = A · (V R +} V os -Vo). Incidentally, Vo is the output of the comparator 4 (amplifier output), the V _R voltage terminal 1a, V _os is the non-inverting input occurring offset voltage of the comparator 4, A is a comparator (amplifier) 4 amplification factor of.

In this case, the charge storage capacitor C, C · - a _{(V R (A / (A} + 1)) · (V R + V os)) = C · (V A -V IN). Here, _VA is the voltage of the non-inverting input terminal of the comparator 4 of the capacitor C, and _VIN is the voltage of the terminal PI1.

When the clock CLK_CMP is set to the “H” level (see FIG. 12), the switches SWB1 and SWB2 are turned on. In this case, V _A = V _IN + (1 / (1 + A)) · V _R- (A / (1 + A)) · V _os ≒ V _IN -V _os . As a result, the non-inverting input terminal of the comparator 4 receives the voltage V _IN from which the offset voltage V _os is canceled.

  In the above-described embodiment, the zero point detecting device according to the present invention has been described as an example in which the zero point detecting device is used for an ultrasonic flowmeter. Further, the present invention is not limited to time measurement, and can be used for various signal processing in which a voltage whose magnitude and direction periodically change is used as an input voltage.

[Expansion of Embodiment]
As described above, the present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the technical idea of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Reference voltage / threshold voltage generation circuit, 2 ... Zero point detection part, 3 ... Switch part, 4 ... Comparator, 5 ... Switch control part, 6 ... Inverter circuit, 7_1-7_4 ... NOR circuit, 8 ... D flip-flop circuit M1, first control mode, M2, second control mode, M3, third control mode, M4, fourth control mode, VREF, reference voltage, VTHP, first threshold voltage (+ side threshold voltage) ), VTHM: second threshold voltage (−side threshold voltage), VTHSP, VTHSM: zero point detection start voltage, ZPD: zero point at falling, ZPU: zero point at rising, α, β: dead zone, C: capacitor , 100 (100A, 100B)... Zero point detecting device.

Claims (4)

A zero-point detection device that detects a voltage whose magnitude and direction periodically changes as an input voltage, and detects a rising point and a falling point of the input voltage from a reference voltage as a zero point.
The reference voltage, a first threshold voltage set to a plus side with respect to the reference voltage, and a second threshold voltage set to a minus side with respect to the reference voltage are generated. A reference voltage / threshold voltage generation circuit,
The input voltage, the reference voltage, the first threshold voltage and the second threshold voltage as an input, the fall of the time when the input voltage falls below the reference voltage after exceeding the first threshold voltage A zero point detecting unit configured to detect a zero point, and detect a time point when the input voltage exceeds the reference voltage after the input voltage falls below the second threshold voltage as a rising zero point.
The first threshold voltage is
Also serves as a zero point detection start voltage when starting detection from the falling zero point,
The second threshold voltage is
A zero point detection device, which also serves as a zero point detection start voltage when starting detection from the rising zero point. The zero point detecting device according to claim 1,
The zero point detection unit,
A switch unit that receives the input voltage, the reference voltage, the first threshold voltage, and the second threshold voltage,
A switch control unit that controls the operation of the switch unit,
Comprising a single comparator provided between the switch unit and the switch control unit,
The switch control unit includes:
A first control mode for controlling the operation of the switch unit so as to apply the input voltage to a non-inverting input terminal of the comparator and the first threshold voltage to an inverting input terminal of the comparator;
After the operation of the switch unit is controlled by the first control mode, when the output of the comparator becomes “H” level, the state where the input voltage is applied to the non-inverting input terminal of the comparator A second control mode for controlling the operation of the switch unit so as to apply the reference voltage to the inverting input terminal of the comparator;
A third control mode for controlling the operation of the switch unit so as to apply the input voltage to an inverting input terminal of the comparator and the second threshold voltage to a non-inverting input terminal of the comparator;
After the operation of the switch unit is controlled by the third control mode, if the output of the comparator becomes “H” level, the input voltage is supplied to the inverting input terminal of the comparator. A fourth control mode for controlling the operation of the switch section so as to apply the reference voltage to the non-inverting input terminal of the comparator.
After the operation of the switch unit is controlled by the second control mode, when the output of the comparator becomes the “L” level, the point is detected as the falling zero point,
After the operation of the switch unit is controlled by the fourth control mode, when the output of the comparator becomes “L” level, the point is detected as the zero point of the rising edge. apparatus. The zero point detecting device according to claim 2,
A zero point detecting device, wherein a capacitor for canceling an offset voltage generated at a non-inverting input terminal of the comparator is connected to an input line of a voltage to a non-inverting input terminal of the comparator. The zero point detection device according to any one of claims 1 to 3,
The zero point detection unit,
A zero point detection device, comprising: a selection / setting unit for determining whether to start detection from the falling zero point or to start detection from the rising zero point.

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