JP2019215804A - Multicore microcomputer and parallelizing method - Google Patents

Abstract

To provide a multicore microcomputer with which it is possible to heighten a parallel execution frequency in processing units by a plurality of cores while preventing mutual interferences, even when the parallelism of parallel programs is low.SOLUTION: Among a plurality of processing units of each task that is a candidate for execution task in cores 31c, 31d of a multicore microcomputer 31, a processing unit for which the data scheduled to be used is accessible when the processing unit is executed, is determined as the processing unit to be executed. Furthermore, a disabling process for disabling the data scheduled to be used from being accessed by a processing unit executed in the other core is executed. When, as the result of execution of the disabling process in some core, it is determined, with respect to processing units in the other core, that the data scheduled to be used cannot be accessed, another processing unit by which the data scheduled to be used is accessible in the other core is determined as the processing unit to be executed.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a multicore microcomputer that executes a parallel program generated from a single program, and a parallelization method that generates a parallel program for a multicore microcomputer from a single program for a single core microcomputer.

  2. Description of the Related Art Conventionally, as an example of a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer, a parallelization compile method disclosed in Patent Document 1 is known.

  In this parallel compilation method, lexical analysis and syntax analysis of the source code of a single program are performed to develop into an intermediate language, and this intermediate language is used to analyze and optimize the dependencies of a plurality of macro tasks (processing units). And so on. In the conventional parallelizing compilation method, a parallel program is generated by allocating to cores and scheduling based on the dependency of each macro task and the execution time of each macro task.

JP-A-2015-1807

  However, when the degree of parallelism of a parallel program generated from a single program is low, that is, when the number of processing units that can be executed in parallel by a plurality of cores in the parallel program is small, the processing capability of the multi-core microcomputer cannot be fully utilized. .

  The present invention has been made in view of the above points, and it is possible to increase the frequency of parallel execution of a processing unit in a plurality of cores while preventing mutual interference even if the degree of parallelism of a generated parallel program is low. It is an object of the present invention to provide a possible multi-core microcomputer and a parallelization method.

In order to achieve the above object, a multi-core microcomputer according to the present invention provides a parallel program for a multi-core microcomputer having a plurality of cores (31c, 31d) generated from a single program for a single-core microcomputer having one core. 31a1 ′), and
A parallel program is one in which the assignment of multiple processing units to multiple cores and the execution order are determined based on the dependencies of multiple processing units for each task consisting of multiple processing units included in a single program And
Each of the plurality of cores of the multi-core microcomputer selects a processing unit to be executed from among the processing units belonging to the plurality of tasks allocated to the own core (S110 to S200, S310 to S400, 510 to S610). , S670),
The selection unit is
A determination unit (S140, S340, S540) that determines whether or not the data to be used can be accessed when the processing unit is executed, with respect to the processing unit of each task;
Prohibition processing for determining the processing unit determined to be accessible to the data to be used by the determination unit as the processing unit to be executed, and prohibiting the processing unit executed in another core from accessing the corresponding data (S150) , S350, S550, S670) at the time of determination (S150-S160, S350-S360, S550-S560, S670).
Each of the plurality of cores is configured to execute an instruction included in the processing unit determined by the determination-time processing unit.

  As described above, according to the multi-core microcomputer according to the present invention, in each core, among a plurality of processing units of each assigned task, a processing unit capable of accessing data to be used when the processing unit is executed, It is determined as a processing unit to be executed. Further, a prohibition process is executed to prohibit the data to be used from being accessed by a processing unit executed in another core. Thereby, it is possible to prevent the processing units executed in the plurality of cores from interfering with each other.

  Then, as a result of the execution of the above-described prohibition process in one core, if it is determined that the data to be used is inaccessible for the processing unit of another core, another processing unit that can access the data to be used in another core Is determined as a processing unit to be executed. Therefore, when there is a possibility that mutual interference may be caused by execution of a processing unit in another core, another processing unit which is not likely to cause such mutual interference is executed in the other core. For this reason, even if the degree of parallelism of the generated parallel program is low, it is possible to increase the parallel execution frequency of the processing unit in a plurality of cores.

Further, the parallelization method of the present invention generates a parallel program (31a1) for a multi-core microcomputer having a plurality of cores (31c, 31b) from a single program for a single-core microcomputer having one core. hand,
Core assignment and execution order determination for determining the assignment of a plurality of processing units to a plurality of cores and the execution order based on the dependency of the plurality of processing units for each task including a plurality of processing units included in a single program Procedures (10a to 10d),
A parallel program is generated such that a plurality of processing units are executed by a plurality of cores of the multi-core microcomputer in accordance with the assignment to the plurality of cores determined in the execution order determination procedure and the execution order, and each processing unit of the parallel program And a parallel program generation procedure (10e, 10f) for adding a start point instruction to the start point of the above and an end point instruction to the end point.
The start point instruction and the end point instruction allow the multi-core microcomputer to perform data access arbitration so that the same data is not accessed by an instruction included in a processing unit executed by a plurality of cores at the same time. In the prohibited core, a processing unit of another task other than the processing unit of the corresponding task is executed.

  Therefore, the parallelization method according to the present invention provides a multi-core microcomputer capable of increasing the frequency of parallel execution of processing units in a plurality of cores while preventing mutual interference between processing units executed in the plurality of cores. A program can be generated.

  The reference numbers in parentheses above are merely one example of a correspondence relationship with a specific configuration in the embodiment described later in order to facilitate understanding of the present disclosure, and are intended to limit the scope of the invention. It was not done.

  Further, technical features described in each claim of the claims other than the above-described features will be apparent from the description of the embodiments and the accompanying drawings described later.

FIG. 2 is a block diagram illustrating a schematic configuration of a computer as an automatic parallelization tool in the embodiment. FIG. 4 is a block diagram illustrating functions of a computer as an automatic parallelization tool in the embodiment. FIG. 4 is a diagram showing an example of each task consisting of a plurality of processing units and assigning the plurality of processing units to each core. FIG. 2 is a diagram illustrating an example of a configuration of an in-vehicle device including a multi-core microcomputer. FIG. 2 is a block diagram conceptually showing a configuration in each core of the multi-core microcomputer. 6 is a flowchart for explaining processing operations in each core of the multi-core microcomputer when executing a parallel program in the first embodiment. FIG. 9 is a block diagram conceptually showing a configuration in each core of a multi-core microcomputer in a second embodiment. FIG. 9 is a flowchart illustrating a processing operation in each core of the multi-core microcomputer when executing a parallel program in the second embodiment. FIG. 13 is a block diagram conceptually showing a configuration in each core of a multi-core microcomputer in a third embodiment. FIG. 13 is a flowchart illustrating a processing operation in each core of the multi-core microcomputer when executing a parallel program in the third embodiment.

(First embodiment)
Hereinafter, a first embodiment for carrying out the invention will be described with reference to the drawings. In the present embodiment, the computer 10 as a parallelization tool is a single program for a single core microcomputer having one core, and is converted into a parallel program 31a1 for a multicore microcomputer 31 having two or more cores 31c and 31d. An example of generating is described. The number of cores of the multi-core microcomputer 31 may be three or more.

  As described above, the background of generating the parallel program 31a1 from the single program is that the amount of the program tends to increase year by year due to the sophistication of the control, but the performance improvement of the single core microcomputer is limited. That is, for example, even if an attempt is made to increase the operating frequency by increasing the operating frequency of a single-core microcomputer, there is a limit in increasing the operating frequency, and increasing the operating frequency causes an increase in heat generation and an increase in power consumption. . For this reason, it is considered effective to apply the multi-core microcomputer 31 which improves the processing capability by increasing the number of cores.

  At this time, if the program developers must properly allocate processing to each core and schedule it so that the multi-core capability can be maximized, the program development load will increase Resulting in. It is of technical significance to automatically generate the parallel program 31a1 from a single program in order to reduce the development load of such a program. Further, by automatically generating the parallel program 31a1 from the single program, it is possible to effectively use the existing software resources developed for the single processor.

  First, the configuration of the computer 10 will be described with reference to FIG. The computer 10 corresponds to a parallelization tool that executes a parallelization method, and generates a parallel program 31a1 from a single program. In the present embodiment, the computer 10 is configured to generate a parallel program 31a1 described in C language based on a single program described in C language. For this reason, the parallel program 31a1 ′ stored in a ROM (code ROM) 31a of the multi-core microcomputer 31 described later and executed by the multi-core microcomputer 31 is further compiled by the compiler 20, for example, as shown in FIG. Will be translated.

  However, the present invention is not limited to this. The single program may be described in a programming language different from the C language. The parallel program 31a1 may be described in, for example, an intermediate language used when analyzing a single program. Alternatively, the computer 10 may generate both a parallel program written in the C language and a parallel program written in the intermediate language. Further, the computer 10 may incorporate the function as the compiler 20 and directly generate the binary code parallel program 31a1 '.

  As shown in FIG. 1, the computer 10 includes a display 11, an HDD 12, a CPU 13, a ROM 14, a RAM 15, an input device 16, a reading unit 17, and the like. The computer 10 can read the storage content stored in the storage medium 18 by the reading unit 17. As shown in FIG. 1, the storage medium 18 stores, for example, the automatic parallelizing compiler 1. Since the computer 10 and the storage medium 18 are the same as the personal computer 100 and the storage medium 180 described in JP-A-2015-1807, refer to JP-A-2015-1807 for details.

  The automatic parallelizing compiler 1 is software that causes the computer 10 to execute a procedure for generating the parallel program 31a1. Therefore, the automatic parallelizing compiler 1 enables the computer 10 to execute the parallelizing method. In other words, the automatic parallelizing compiler 1 is a program including a parallelizing method. The computer 10 executes the automatic parallelizing compiler 1 to generate a parallel program 31a1 as a parallelizing tool.

  Next, with reference to FIG. 2, functions and processing procedures of the computer 10 as a parallelization tool for generating the parallel program 31a1 from the single program will be described. FIG. 2 is a diagram showing functions and processing procedures of the computer 10 as functional blocks. As shown in FIG. 2, the computer 10 includes a lexical analysis unit 10a, a syntax / semantic analysis unit 10b, a dependency analysis unit 10c, a core allocation and scheduling unit 10d, a synchronization point instruction addition unit 10e, and a code generation unit 10f. Has a function.

  In the present embodiment, as shown in FIG. 2, the computer 10 does not analyze the entire single program for controlling the control target device at a time to generate the parallel program 31 a 1, but instead executes independent processing functions (tasks). ), The parallel program 31a1 is generated for the single program divided for each of the programs. The parallel program 31a1 generated according to the present embodiment can increase the execution speed when it is executed by the multi-core microcomputer 31. Therefore, the parallel program 31a1 is mounted on a vehicle that requires a high processing speed, for example, as a control target device. It is preferable to use an engine or an electric motor. In this case, as shown in FIG. 4, the multi-core microcomputer 31 is embodied as an in-vehicle device 30 such as an engine control device, a motor control device, or a hybrid control device mounted on a vehicle.

  The single program divided for each task includes a plurality of processing units, and by executing the plurality of processing units, a target processing function for each task can be realized. As described above, the plurality of processing units cooperate to realize a target processing function. For example, the processing unit after referring to the variable data processed in the previous processing unit, the previous processing unit And the subsequent processing unit executed by the conditional branch.

  Here, the processing unit refers to a core arrangement unit which is a minimum unit when allocating to each core, or a function. The core arrangement unit can be rephrased as a processing block, a macro task, or a simple processing unit. The relationship between the core arrangement unit and the function is such that core arrangement unit ≧ function. That is, the function may be the core arrangement unit itself, or may be a parent function or subfunction included in the core arrangement unit.

  The lexical analysis unit 10a and the syntax / semantic analysis unit 10b perform lexical analysis, syntax and semantic analysis on the source code of a single program described in the C language, and develop the intermediate code. The intermediate language developed by the lexical analyzer 10a and the syntax / semantic analyzer 10b includes general-purpose instructions. Note that the lexical analysis unit 10a and the syntax / semantic analysis unit 10b correspond to FE3 in JP-A-2015-1807, so refer to JP-A-2015-1807 for details.

  The dependency analysis unit 10c analyzes the dependency of the processing units included in the single program developed in the intermediate language, and extracts the processing units that can be executed in parallel. Dependencies include data dependencies, such as a processing unit executed later referring to updated variable data in a processing unit executed first, and a processing unit executed later in a processing unit executed earlier. Control dependencies such as conditional branch destinations are included. A plurality of processing units having such a dependency need to be executed in a processing order according to the dependency. In the present embodiment, a single program divided for each task as described above is a target of parallelization. A plurality of processing units included in a single program divided for each task have a data dependency and a control dependency.

  The core allocation and scheduling unit 10d allocates (allocates) a plurality of processing units to two or more cores 31c and 31d based on the analysis result analyzed by the dependency analysis unit 10c. At this time, the core allocation and scheduling unit 10d allocates a plurality of processing units so that, for example, processing units that can be executed in parallel are executed in parallel by two or more cores 31c and 31d.

  FIG. 3 shows an example of the assignment of each of the plurality of processing units to each of the cores 31c and 31d. In the example shown in FIG. 3, the single program includes three tasks of task A, task B, and task C. Although FIG. 3 shows only three tasks for the sake of explanation, a single program may actually include more tasks in some cases.

  As shown in FIG. 3, the core allocation and scheduling unit 10d allocates the processing units A1 and A2 to the first core 31c for the processing units A1 to A3 of the task A, and executes the processing unit A3 that can be executed in parallel with the processing unit A2. Is allocated to the second core 31d. In addition, regarding the processing units B1 and B2 of the task B, the processing units B1 and B2 are allocated to the second core 31d. Then, for the processing units C1 to C4 of the task C, the processing units C1 and C2 are allocated to the first core 31c, and the processing units C3 and C4 that can be executed in parallel with them are allocated to the second core 31d.

  Then, the core allocation and scheduling unit 10d performs scheduling of the plurality of processing units A1 to A3, B1 to B2, and C1 to C4 allocated to the first core 31c and the second core 31d. Specifically, the core allocation and scheduling unit 10d performs, for each task, the first core 31c and the second core 31d based on the dependency of the processing units A1 to A3, B1 to B2, and C1 to C4 of each task. The execution schedule (execution order) of each of the processing units A1 to A3, B1 to B2, and C1 to C4 allocated to is determined. Note that the dependency analysis unit 10c and the core assignment and scheduling unit 10d correspond to MP5 in JP-A-2015-1807, so refer to JP-A-2015-1807 for details.

  The synchronization point instruction adding unit 10e adds a start point instruction to each start point of each of the plurality of processing units of each task constituting the parallel program, which is scheduled by the core allocation and scheduling unit 10d, and adds an end point instruction to the end point. Is to be added. The synchronization point instruction adding unit 10e has a program as a start point instruction to be added and a program as an end point instruction, and a start point instruction and an end point are added to each start point and end point while corresponding to each processing unit. Add an end point instruction.

  The start point instruction indicates the start point of the corresponding processing unit, and also includes information and instructions described below. First, a start point instruction is a data to be accessed when an instruction included in a corresponding processing unit accesses (reads, updates, etc.) data stored in a memory (RAM 31b, register, or the like). Is included. The synchronization point command addition unit 10e can acquire information on data to be accessed from the syntax / semantic analysis unit 10b.

  Thus, at the start of execution of each processing unit included in the parallel program 31a1 '(before the start of substantial processing), the multicore microcomputer 31 accesses any data based on the start point instruction. It is possible to know in advance whether the event is scheduled. This access data information is temporarily stored in access data tables 43a and 43b in an access data control unit 43 provided in each of the cores 31c and 31d, as described later. If the processing unit does not access data stored in the memory, the start point instruction does not include access data information or includes access data information indicating that there is no data to be accessed.

  Further, the start point instruction includes an instruction for determining whether or not the data indicated by the access data information can be accessed. Based on this instruction, the access data control unit 43 of each of the cores 31c and 31d determines whether or not the data indicated by the access data information can be accessed. More specifically, the access data control unit 43 checks the state of the prohibition flag corresponding to the data to be accessed according to the instruction. The prohibition flag is set so as to individually correspond to data accessed by each processing unit of each task of the parallel program 31a1 ', and is stored in a predetermined storage area of a memory readable and writable by each of the cores 31c and 31d. Is done. For example, when the state of the prohibition flag is the set state, the access data control unit 43 determines that the corresponding data cannot be accessed. On the other hand, when the state of the prohibition flag is the reset state, the access data control unit 43 determines that the corresponding data can be accessed.

  The start point instruction includes an instruction for the access data control unit 43 to lock the data when the access data control unit 43 determines that the data indicated by the access data information is accessible. Based on this lock command, when the access data control unit 43 determines that the prohibition flag is in the reset state and the corresponding data is accessible, the access data control unit 43 changes the referred prohibition flag to the set state and locks the data. Thus, when an instruction in a processing unit after the start point instruction is started, it is possible to prohibit access to the corresponding data by a processing unit executed by another core while executing the instruction in the processing unit. Become.

  Further, the start point instruction includes an instruction for instructing switching to a processing unit of another task when the access data control unit 43 determines that the data indicated by the access data information is inaccessible. Based on this instruction, the process switching unit 44 sets the processing unit to be executed to the processing unit of another task when the access data control unit 43 determines that the data indicated by the access data information is inaccessible. Switch. As a result, in the cores 31c and 31d for which it is determined that the data cannot be accessed, the execution of the processing unit is not waited until the corresponding data is released, but the switched processing unit can be executed. For this reason, it is possible to increase the execution frequency of the processing unit in each of the cores 31c and 31d. It should be noted that whether or not the execution target processing unit is executable is determined again by the access data control unit 43 based on whether or not access to the data to be accessed is possible.

  Describing in more detail, each task to which one of the processing units is assigned to each of the cores 31c and 31d has a predetermined processing priority. The process switching unit 44 initially determines the processing unit to be executed as the processing unit of the task having the highest processing priority. When the access data control unit 43 determines that access to the data to be accessed is not possible for the processing unit, the process switching unit 44 assigns the processing unit to be executed to the task having the next highest processing priority. Switch to processing unit.

  Regarding the processing priority of each task, the start point instruction may include information indicating the processing priority of each task. In that case, the processing priority information included in the start point instruction is developed in the priority table 44c of the process switching unit 44. The process switching unit 44 determines which task has the highest processing priority, which task has the next highest processing priority, based on the processing priority information of each task expanded in the priority table 44c, and the like. Can be determined. Alternatively, for the instruction queues 42a and 42b for storing instructions included in the processing unit of each task, the correspondence between each task is determined in advance so as to correspond to each task on a one-to-one basis, and the priority table 44c stores Alternatively, the processing priority of each of the instruction queues 42a and 42b may be determined.

  The end point instruction includes an instruction described below, in addition to indicating the end point of the corresponding processing unit. That is, the end point instruction includes an instruction for the access data control unit 43 to unlock the data when the data is locked based on the data lock instruction included in the start point instruction. This is because it is no longer necessary to prohibit a processing unit executed by another core from accessing the corresponding data when all the instructions of the processing unit are completed. Based on the lock release command included in the end point command, the access data control unit 43 changes the state of the prohibition flag from the set state to the reset state.

  The code generation unit 10f executes a plurality of processing units of the corresponding task according to the allocation and execution order to each of the cores 31c and 31d determined by the core allocation and scheduling unit 10d, and also includes a start point and an end point of each processing unit. Then, a program code corresponding to the parallel program 31a1 is generated so that the above-described start point instruction and end point instruction are executed. The computer 10 outputs the program code generated by the code generator 10f as a parallel program 31a1.

  Next, the configuration of the vehicle-mounted device 30 will be described. As shown in FIG. 4, the in-vehicle device 30 includes a multi-core microcomputer 31, a communication unit 32, a sensor unit 33, an input / output port 34, and the like. The multi-core microcomputer 31 includes a ROM 31a, a RAM 31b, a first core 31c, a second core 31d, and the like. The in-vehicle device 30 can be applied to, for example, an engine control device or a hybrid control device mounted on an automobile. Hereinafter, an example in which the in-vehicle device 30 is applied as an engine control device will be described.

  The first core 31c and the second core 31d execute, for example, engine control by executing a parallel program 31a1 'stored in a ROM 31a as a code ROM. Specifically, a fuel injection amount, an ignition timing, an intake air amount, and the like are controlled by driving each actuator as a control target device. The ROM 31a also stores constant data used for engine control. The RAM 31b temporarily stores variable data and the like, and is appropriately accessed by the cores 31c and 31d when the multi-core microcomputer 31 executes the parallel program 31a1 '. The communication unit 32 communicates with another ECU connected via an in-vehicle LAN or the like. The sensor unit 33 includes various sensors for detecting the state of the engine. The input / output port 34 transmits and receives various signals for controlling the engine.

  FIG. 5 is a block diagram conceptually showing a configuration in each of the cores 31c and 31d. Since the cores 31c and 31d have the same configuration, FIG. 5 shows the internal configuration of only the first core 31c. In FIG. 5, for simplicity of explanation, it is determined whether two tasks, task_H having a relatively high processing priority and task_L having a relatively low processing priority, are executed. A description will be given of an example in which execution task candidates to be executed are set as execution task candidates.

  As shown in FIG. 5, each of the cores 31c and 31d has instruction cache memories 40a and 40b for storing instruction codes included in a processing unit (task_H, task_L) of each task read from the ROM 31a. I have. The instruction code of each processing unit stored in the instruction cache memories 40a and 40b is read out by the instruction fetch / decode unit 41, decoded, and transferred to the respective instruction queues 42a and 42b.

  Although FIG. 5 illustrates that the instruction codes of the processing units of task_H and task_L are stored in the separated code ROM 31a, it is not always necessary that the code ROM 31a be physically separated. is not. For example, a plurality of tasks may be stored in the common code ROM 31a. In this case, since each of the cores 31c and 31d has the number of program counters corresponding to each of the tasks to be executed task candidates, it is possible to read out the instruction code of the processing unit of each task from the common ROM 31a. On the other hand, the instruction queues 42a and 42b preferably include a plurality of instruction queues corresponding to the number of execution task candidates. This is because processing units can be switched immediately.

  However, each of the cores 31c and 31d may not have the number of instruction queues corresponding to all the tasks allocated to the respective cores 31c and 31d. If the instructions of the processing units of the plurality of tasks as the execution task candidates are accumulated in the plurality of instruction queues, in most cases, the switching of the processing units can be performed without any trouble, and each of the cores 31c and 31d is in the standby state. This is because it can be avoided. For example, as for a plurality of tasks to be executed task candidates, a required number of tasks can be selected from tasks having a high processing priority among tasks whose processing order is not specified among tasks. Then, when the execution of all the processing units is completed for one task of the execution task candidate, it may be replaced with the task having the highest processing priority among the unprocessed tasks.

  Each of the cores 31c and 31d has an access data control unit 43 as shown in FIG. The access data control unit 43 has access data tables 43a and 43b for each execution task candidate. As described above, the access data information included in the start point instruction is stored in the access data tables 43a and 43b. Thus, the access data control unit 43 can grasp the data to be accessed before the execution of the processing unit when the processing unit of the task which is the execution task candidate is executed. Then, the access data control unit 43 determines whether or not the data indicated by the access data information can be accessed by referring to the state of the prohibition flag corresponding to the data indicated by the access data information. In this determination, when it is determined that the data indicated by the access data information is accessible, the access data control unit 43 changes the prohibition flag corresponding to the data to a set state and locks the data. This completes the preparation for executing the instruction in the processing unit. On the other hand, if it is determined that the data indicated by the access data information cannot be accessed, the access data control unit 43 gives the determination result to the process switching unit 44.

  As described above, the process switching unit 44 includes the priority table 44c that stores information indicating the processing priority of each task of the execution task candidates. The process switching unit 44 initially determines the processing unit of the task having the highest processing priority as the execution target processing unit based on the information indicating the processing priority of each task in the priority table 44c. Specifically, the process switching unit 44 corresponds to the task having the highest processing priority among the registers 44a and 44b storing the instruction of the processing unit of each task that is a candidate for the execution task. The instruction stored in the register is transferred to the operation unit 45. However, when the process switching unit 44 obtains, from the access data control unit 43, a determination result that the processing unit of the task having the highest processing priority is inaccessible to data, the process switching unit 44 With reference to 44c, the processing unit of the task having the next highest processing priority is set as the execution target processing unit. In other words, the process switching unit 44 switches the processing unit to be executed from the processing unit of the task having the highest processing priority to the processing unit of the task having the next highest processing priority. At this time, the process switching unit 44 sets the register corresponding to the task having the next highest processing priority among the registers 44a and 44b storing the instruction of the processing unit of each task that is a candidate for the execution task. Is transferred to the arithmetic unit 45.

  The operation unit 45 has an operation unit 45a and a register 45b. The instruction transferred from the process switching unit 44 is temporarily stored in the register 45b. Then, processing according to the instruction stored in the register 45b is executed by the arithmetic unit 45a. As described above, in each of the cores 31c and 31d, when the data cannot be accessed by the processing unit, the processing unit to be executed is switched, so that the execution frequency of the processing unit in each of the cores 31c and 31d is increased. Will be able to do it.

  The data cache memory 46 stores data accessed by a processing unit to be executed by reading from the memory in advance and storing the data. When the data is updated by execution of the processing unit, the updated data is temporarily stored in the data cache memory 46, and then the data in the memory is rewritten by the updated data.

  Here, in a single program for an embedded system such as the in-vehicle device 30 described above, the processing order is often not defined between the tasks. For this reason, in a case where the execution processing of the processing unit is interrupted due to the data access waiting in each of the cores 31c and 31d, the processing unit of the task whose processing order is not defined is executed instead. The frequency of parallel execution in the cores 31c and 31d can be increased. As a result, it is possible to increase the execution speed of the generated parallel program 31a1 '.

  Therefore, in the present embodiment, by configuring the parallel program 31a1 ′ and the multi-core microcomputer 31 as described above, it is possible to prevent mutual interference between the processing units executed by the cores 31c and 31d, and to reduce the This makes it possible to increase the frequency of parallel execution of processing units in 31d.

  Hereinafter, the operation of the multi-core microcomputer 31 when executing the parallel program 31a1 'will be described with reference to the flowchart of FIG. 6, so that mutual interference between processing units executed by the cores 31c and 31d can be prevented. Meanwhile, a more detailed description will be given as to whether the frequency of parallel execution of the processing unit in each of the cores 31c and 31d can be increased. Although the flowchart of FIG. 6 illustrates the processing executed by the first core 31c, the same processing is executed by other cores.

  In step S100 of FIG. 6, the instructions included in each processing unit are loaded for each execution task candidate, and enqueued in the corresponding instruction queues 42a and 42b. In step S110, a task having the highest processing priority among the execution task candidates is selected, and the instructions in the instruction queues 42a and 42b corresponding to the selected task are referred to. In step S120, it is determined whether the referred command is a start point command. If it is determined in step S120 that the command is a start point command, the process proceeds to step S130, in which access data information included in the start point command is acquired and stored in the access data table 43a. Then, in step S140, it is determined whether the data indicated by the access data information is accessible, that is, whether the prohibition flag corresponding to the data is reset. If the processing unit does not access data stored in the memory, the determination result in step S140 is always “Yes”.

  If it is determined in step S140 that the data indicated by the access data information can be accessed, the process proceeds to step S150. In step S150, the state of the prohibition flag corresponding to the data determined to be accessible is changed to the set state. As a result, a preparation for executing the instruction in the processing unit after the start point instruction is completed. Therefore, in step S160, the process returns to step S120 after referring to the next instruction in the processing unit of the task. In this case, in step S120, it is determined that the instruction is not a start point instruction, and the process proceeds to step S210. Further, since the referred command is a command related to the substantive processing of the processing unit, it is also determined in step S210 that the command is not an end point command, and the process proceeds to step S250.

  In step S250, the referred instruction is executed. That is, the corresponding instruction is transferred from the process switching unit 44 to the arithmetic unit 45, and the processing according to the transferred instruction is executed in the arithmetic unit 45a. After that, in step S260, the process returns to step S120 after referring to the next instruction in the processing unit of the task. Such processing is repeated until the referenced instruction becomes an end point instruction, that is, until the end point of the processing unit is reached. When the command to be referred to is the end point command, the determination result in step S210 becomes “Yes”. In this case, the process proceeds to step S220, and the data in the memory is updated by the calculation output data from the calculation unit 45. However, if the processing unit being executed is not for rewriting data in the memory, this processing is skipped.

  In subsequent step S230, the state of the prohibition flag corresponding to the data to be accessed is changed from the set state to the reset state. As a result, the lock of the data is released, and the data can be accessed by the processing unit executed in the other core 31d. Then, in step S240, the process returns to step S120 after referring to the instruction of the next processing unit of the task. In this way, as long as data can be accessed, the processing units of the task having the highest processing priority are sequentially executed.

  If access to the data used during execution of the processing unit is not possible, the result of the determination in step S140 is “No”. In this case, the process proceeds to step S170, and it is determined whether the task to be executed is the task having the lowest processing priority among the execution task candidates. If the determination result in step S170 is “No”, it means that among the execution task candidates, there is a task having a lower processing priority than the task to be executed. Therefore, the process proceeds to step S180, where the task having the next highest processing priority is set as an execution target, the command stored in the command queue 42b corresponding to the task is referred to, and then the process returns to step S120. When such task switching is performed, the referenced instruction becomes the start point instruction of the processing unit of the task having the next highest processing priority. Therefore, the result of the determination in step S120 is "Yes", and as described above, whether or not the processing unit to be executed can be executed again is determined based on whether or not access to the data to be accessed is possible. You.

  On the other hand, in step S170, if it is determined that the task to be executed has the lowest processing priority among the execution task candidates, a good low processing priority is assigned to the execution task candidates. There are no tasks to have. Therefore, when the result of the determination in step S170 is “Yes”, the process proceeds to step S190 and waits for a certain time. Then, in the processing of step S200, the instruction of the processing unit of the task having the highest processing priority among the execution task candidates is referred to. In other words, if it is necessary to switch the processing unit when the task with the lowest processing priority is the execution target, after waiting for a certain time, the processing of the task with the highest processing priority Switch to units. This makes it possible to determine again whether or not the data to be accessed can be accessed in order from the processing unit of the task having the highest processing priority, and then determine the instruction of the executable processing unit. Can be executed.

  As described above, according to the first embodiment of the present invention, a prohibition flag set to individually correspond to data accessed by each processing unit of each task of the parallel program 31a1 'is used. This makes it possible to determine whether or not the processing unit of the task to be executed by each of the cores 31c and 31d can access data used at the time of execution. Therefore, when it is determined that the data cannot be accessed, it is possible to switch to an executable processing unit instead of waiting until the data can be accessed. Therefore, even if the degree of parallelism of the generated parallel program 31a1 # is low, it is possible to increase the frequency of parallel execution of the processing units in the plurality of cores 31c and 31d.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the above-described first embodiment, the cores 31c and 31d use the prohibition flags set so as to individually correspond to the data accessed by the respective processing units of the respective tasks of the parallel program 31a1 ′. A method for preventing mutual interference of processing units executed, however, a method of prohibiting access by a processing unit executed by another core to data accessed by a processing unit executed by one core Is not limited to the method of the first embodiment described above. In the second embodiment, an example of a method different from the first embodiment will be described.

  FIG. 7 shows the configuration of the multi-core microcomputer 31 according to the second embodiment. As shown in FIG. 7, the multi-core microcomputer 31 of the present embodiment includes a memory protection unit (MPU) 47 for managing access to a memory. The MPU 47 operates to permit access to the same data to only the single cores 31c and 31d. That is, when there is an access request from any of the cores 31c and 31d for data not accessed by any of the cores 31c and 31d, the MPU 47 permits the access request. However, even if there is an access request from another core 31c, 31d for data accessed by one of the cores 31c, 31d, the MPU 47 rejects the access request.

  A data access request to the MPU 47 is output from the access data control unit 43 of each of the cores 31c and 31d as shown in FIG. In response to this access request, the MPU 47 returns a permission notice for permitting the access or a rejection notice for denying the access to the access data control unit 43. The access data control unit 43 of each of the cores 31c and 31d determines whether or not to access the data stored in the memory based on the permission notification or the rejection notification from the MPU 47 in step S340 of FIG.

  When the access data control unit 43 receives the permission notification from the MPU 47, the core reads out the corresponding data for execution of the processing unit and stores the data in the data cache memory 46. Further, in step S350 of the flowchart in FIG. 8, the access data control unit 43 of the core requests the MPU 47 to lock the read data. In response to this lock request, the MPU 47 prohibits access to the data from other cores.

  Then, when all the instructions related to the substantive processing of the processing unit are completed and the end point of the processing unit is reached, the determination result in step S410 of the flowchart of FIG. 8 becomes “Yes”, and the processing of steps S420 to S440 is performed. Be executed. In the process of step S430, the access data control unit 43 requests the MPU 47 to unlock the locked data. In response to the unlock request, the MPU 47 releases the corresponding data to access from another core.

  The other configuration of the multi-core microcomputer 31 and the processing in the flowchart of FIG. 8 are the same as those of the first embodiment described above, and thus the description is omitted.

  According to the above-described second embodiment, similarly to the first embodiment, it is determined whether or not the processing unit of the task to be executed by each of the cores 31c and 31d can access data used at the time of execution. can do. Therefore, when it is determined that the data cannot be accessed, it is possible to switch to an executable processing unit instead of waiting until the data can be accessed. Therefore, even if the degree of parallelism of the generated parallel program 31a1 # is low, it is possible to increase the frequency of parallel execution of the processing units in the plurality of cores 31c and 31d.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the first and second embodiments described above, mutual interference by processing units executed by a plurality of cores is prevented by prohibiting another core from accessing data accessed by one core. Met.

  In the present embodiment, in addition to the configuration of the first embodiment or the second embodiment described above, for example, one core accesses data that is particularly important for control and updates the data. In this case, the switching of the other core to the processing unit of another task is prohibited. Thus, it is possible to reliably prevent the important data from being erroneously affected by the processing unit of another task after switching in another core. In addition, between processing units in the same task, it is possible to add a queuing process according to the dependency by, for example, a synchronization point instruction adding unit by the conventional parallelizing compilation method. As a result, it is possible to reliably prevent the important data from being erroneously affected by the processing units in the same task. For details, refer to JP-A-2015-1807.

  As shown in FIG. 9, the multi-core microcomputer 31 according to the present embodiment is configured so that the access data control units 43 of the cores 31c and 31d can communicate with each other. Then, the access data control unit 43 of each of the cores 31c and 31d sets a case in which, following the start point command, a start command of an exclusive section that prohibits another core from switching to a processing unit of another task is set (FIG. 10). In step S660 of the flowchart of step (Yes), a preemption prohibition request that is a request to prohibit switching to a control unit of another task is output to the access data control unit of another core (step S670 of the flowchart of FIG. 10). Although the flowchart of FIG. 10 is based on the premise that the operation according to the configuration of the first embodiment is performed, the configuration of the present embodiment may be added to the configuration of the second embodiment.

  The access data control unit of the other core that has received the preemption prohibition request, even if the control process of the task to be executed cannot access the data to be accessed (step S540 in the flowchart of FIG. 10: No). As shown in step S570 of the flowchart of FIG. 10, in response to the preemption prohibition request, the process returns to the process of step S120, thereby prohibiting the switching to the processing unit of another task.

  An exclusive section end command is set immediately before the end point command so as to form a pair with the exclusive section start command. When the substantive processing of the processing unit ends and the exclusive section end instruction is referred to, the determination result in the flowchart of FIG. 10 becomes “Yes”. In this case, the process proceeds to step S720 to stop the preemption prohibition request output to the other core.

  The other configuration of the multi-core microcomputer 31 and the processing in the flowchart of FIG. 8 are the same as those of the first embodiment described above, and thus the description is omitted.

  The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the gist of the present invention.

  For example, in the above-described first and second embodiments, regarding the processing unit of the task having the highest processing priority, it is determined whether or not the data to be accessed is accessible by the instruction of the processing unit. If it is impossible, the processing unit to be executed is switched to the processing unit of the task having the next highest processing priority. However, for example, first, it is determined whether or not the data to be accessed is accessible by the instruction of the processing unit of each task of the execution task candidate, and the task having the highest processing priority among the accessible tasks is determined. May be determined as an execution target.

  Further, in the above-described embodiment, an example in which the multi-core microcomputer 31 is applied as the in-vehicle device 30 has been described, but the application target of the multi-core microcomputer 31 is not limited thereto.

1: Automatic parallelizing compiler, 10: Computer, 10a: Lexical analysis section, 10b: Semantic analysis section, 10c: Dependency analysis section, 10d: Core allocation and scheduling section, 10e: Synchronization point instruction addition section, 10f: Code generation , 11: display, 12: HDD, 13: CPU, 14: ROM, 15: RAM, 16: input device, 17: reading unit, 18: storage medium, 20: compiler, 30: in-vehicle device, 31: multi-core microcomputer 31a: ROM 31a1: parallel program, 31b: RAM, 31c: first core, 31d: second core, 32: communication unit, 33: sensor unit, 34: input / output port, 40a, 40b: instruction cache memory, 41: Instruction fetch / decode unit, 42a, 42b: instruction queue, 43: access data control unit, 43a 43 b: the access data table 44: process switching unit, 44a, 44b: register, 44c: priority table, 45: operation unit, 45a: arithmetic unit, 45b: register, 46: data cache memory, 47: MPU

Claims (20)

A multi-core microcomputer (31) for executing a parallel program (31a1 ′) for a multi-core microcomputer having a plurality of cores (31c, 31d) generated from a single program for a single-core microcomputer having one core,
The parallel program is included in the single program, for each task consisting of a plurality of processing units, based on the dependency of the plurality of processing units, the allocation of the plurality of processing units to the plurality of cores and the execution order Has been determined,
Each of the plurality of cores of the multi-core microcomputer selects a processing unit to be executed from among processing units belonging to a plurality of tasks allocated to its own core (S110 to S200, S310 to S400, 510). ~ S610, S670),
The selection unit includes:
A determination unit (S140, S340, S540) that determines whether or not data to be used can be accessed at the time of execution of the processing unit, with respect to the processing unit of each task;
Prohibition processing for determining the processing unit determined to be accessible to the data to be used by the determination unit as the processing unit to be executed, and prohibiting access to the data by the processing unit executed in another core ( Determination processing units (S150 to S160, S350 to S360, S550 to S560, and S670) for executing S150, S350, S550, and S670);
A multi-core microcomputer, wherein each of the plurality of cores executes an instruction included in a processing unit determined by the determination-time processing unit. The selecting unit includes a specifying unit (S110, S310, S510) for specifying a processing unit belonging to a task having a relatively highest processing priority based on the processing priority of each of the plurality of tasks.
The determining unit, for the processing unit specified by the specifying unit, determines whether or not the data to be used is accessible,
When the determining unit determines that the data to be used is inaccessible, the selecting unit switches the processing unit to be determined by the determining unit to a processing unit belonging to a task having the next highest processing priority. The multi-core microcomputer according to claim 1, further comprising a switching unit (S170 to S200, S370 to S400, S580 to S610).   The switching unit, when the processing unit determined to be inaccessible to the data by the determination unit belongs to the task of the lowest processing priority, the processing unit to be determined by the determination unit, the highest processing priority 3. The multi-core microcomputer according to claim 2, wherein the processing is switched to a processing unit belonging to the task.   The switching unit, when switching a processing unit to be determined by the determination unit from a processing unit belonging to a task having the lowest processing priority to a processing unit belonging to a task having the highest processing priority, a predetermined waiting time elapses. The multi-core microcomputer according to claim 3, wherein the switching is performed later. A plurality of instruction queues (42a, 42b) for storing at least instructions included in each processing unit of the plurality of tasks allocated to the own core;
An arithmetic processing unit (45) for executing arithmetic processing according to the instruction given from the instruction queue;
Instructions included in each processing unit belonging to the plurality of tasks are stored in the plurality of instruction queues,
The multi-core microcomputer according to claim 2, wherein the switching unit switches an instruction queue serving as a source of instructions to the arithmetic processing unit. Each processing unit of the parallel program includes a start point instruction indicating a start point thereof,
6. The multi-core microcomputer according to claim 1, wherein the start point instruction includes access data information indicating data to be used when the data is accessed by an instruction included in a corresponding processing unit.   7. The multi-core microcomputer according to claim 6, wherein the determination unit determines whether or not the data to be used can be accessed when the processing unit is executed, in accordance with the start point instruction. Each processing unit of the parallel program includes an end point instruction indicating its end point,
8. The multi-core microcomputer according to claim 6, wherein the prohibition processing by the determination-time processing unit is released in response to the end point instruction. 9. The determination-time processing unit performs a process of setting a flag indicating that the data to be used is in use as the prohibition process (S150, S550), locks the data,
9. The device according to claim 1, wherein the determination unit determines whether the data is accessible based on whether a flag corresponding to the data to be used is set and locked. 9. Multi-core microcomputer. A memory accessible by the plurality of cores;
A memory management unit (47) for managing access to the memory;
The data used by the plurality of cores when executing the respective processing units of the assigned tasks is stored in the memory,
The determination-time processing unit performs, as the prohibition process (S350), a process of instructing the memory management unit to lock the data to be used,
9. The multi-core microcomputer according to claim 1, wherein the determination unit determines whether the data to be used is accessible by the memory management unit based on whether the data is locked. .   The multi-core microcomputer according to claim 9, wherein the determination-time processing unit further outputs, as the prohibition process (S 670), an instruction to prohibit the other core from switching to a processing unit of another task.   The multi-core microcomputer is applied to a vehicle-mounted device for controlling a vehicle-mounted device mounted on a vehicle, and controls the vehicle-mounted device by executing the parallel program. Multi-core microcomputer. A parallelization method for generating a parallel program (31a1) for a multi-core microcomputer having a plurality of cores (31c, 31b) from a single program for a single-core microcomputer having one core,
Core assignment for determining, for each task including a plurality of processing units included in the single program, allocation of the plurality of processing units to the plurality of cores and execution order based on a dependency of the plurality of processing units. And an execution order determination procedure (10a to 10d);
Generating the parallel program so that the plurality of processing units are executed by the plurality of cores of the multi-core microcomputer according to the allocation and execution order to the plurality of cores determined in the execution order determination step; A parallel program generation procedure (10e, 10f) for adding a start point instruction to a start point of each processing unit of the parallel program and adding an end point instruction to an end point.
The start point instruction and the end point instruction cause the multi-core microcomputer to perform data access arbitration so as not to access the same data by an instruction included in a processing unit executed simultaneously by the plurality of cores. A parallelization method for executing a processing unit of another task other than a processing unit of a corresponding task in a core for which data access is prohibited.   14. The parallelization method according to claim 13, wherein when the data is accessed by an instruction included in a corresponding processing unit, the start point instruction includes access data information indicating data to be accessed.   15. The parallelization method according to claim 14, wherein the start point instruction includes an instruction for determining whether or not the data indicated by the access data information is accessible.   16. The parallelization method according to claim 15, wherein the start point instruction includes an instruction to switch to a processing unit of another task when it is determined that the data indicated by the access data information cannot be accessed.   17. The parallelization method according to claim 15, wherein the start point instruction includes an instruction to lock the data when it is determined that the data indicated by the access data information is accessible.   18. The parallelization method according to claim 17, wherein the end point instruction includes an instruction for unlocking the data.   18. The parallel program generation procedure according to claim 17, further comprising, after the start point instruction including the data lock instruction instruction, a prohibition instruction for prohibiting another core from switching to a processing unit of another task. 19. The parallelization method according to 18.   20. The parallelization method according to claim 19, wherein the parallel program generation procedure adds a release instruction for releasing the prohibited instruction immediately before the end point instruction.

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