JP2019212293A - Secure access to peripheral device via bus - Google Patents

Abstract

To provide a device and a method for secure access of a host device to a peripheral device via a bus.SOLUTION: In a device and a method for secure access to a peripheral device via a bus, a security device 36 comprises an interface 40 and a processor 44. The interface 40 is set to be connected to a bus 32 which provides service to one or more peripheral devices 28. Transmission of the bus 32 comprises (i) one or more dedicated signals each of which is dedicated to mutually corresponding one of one or more peripheral devices 28, and (ii) one or more common signals which are shared among one or more peripheral devices which receive service from the bus. The processor is connected to the bus, and functions as an additional device other than one or more peripheral devices, and interrupts a dedicated signal related to a specific peripheral device, and thus, interrupts transaction of a bus master device 24 which attempts to access the specific peripheral device on the bus.SELECTED DRAWING: Figure 1

Description

  See related applications

  This application is a continuation-in-part (CIP) filed on June 8, 2015, which is a continuation-in-part of US Patent Application No. 15 / 075,219 filed March 21, 2016. Based on US Provisional Patent Application No. 62 / 172,298, the disclosure of which is incorporated herein by reference.

  The present invention relates to the security of electronic systems, and more particularly to a method and system for securely accessing and protecting peripheral devices.

Electronic systems use various bus interfaces to communicate between host devices and peripheral devices. As an example, the bus interface includes an I ² C (Inter-Integrated-Circuit) bus and a serial peripheral interface (SPI) bus. Related contents of the I ² C bus, ^{"I 2} C-bus specification and user manual" UM10204, NXP Semiconductors as an example, revised sixth edition, are described in the April 4, 2014, incorporated herein by reference .

US Pat. No. 9,323,953

  As an embodiment in the present invention, a safety device including an interface and a processor is provided. The interface is set to connect to a bus that services one or more peripheral devices. Bus transmission is shared between (i) one or more dedicated signals dedicated to one or more mutually corresponding peripheral devices and (ii) one or more peripheral devices serviced by the bus. One or more shared signals are included. A processor is connected to the bus and functions as an attached device other than one or more peripheral devices, and accesses a specific peripheral device on the bus by interrupting dedicated signals associated with the specific peripheral device. The transaction of the bus master device is interrupted.

  In one embodiment, when a processor interrupts a transaction, it maintains a shared signal on the bus and does not interrupt it. In one embodiment, the interface includes (i) an input used to receive a dedicated signal from the bus master device, and (ii) an output used to output the dedicated signal to a particular peripheral device. In addition, the processor prevents the received dedicated signal from being transmitted from the output, thereby interrupting the transaction. In one embodiment, the processor is configured to respond to the bus master device but not to a particular peripheral device when the dedicated signal is interrupted. In the illustrative embodiment, the dedicated signal includes a chip select signal.

  In the disclosed embodiment, the processor detects aborting transactions by monitoring the bus. In an alternative embodiment, the processor detects interrupted transactions by communicating with the bus master device via an auxiliary interface external to the bus.

  In one embodiment, the processor is set to continue interrupting the dedicated signal until a reset signal appears. In another embodiment, the processor is set to suspend the dedicated signal within a finite time after detecting the transaction. In one embodiment, by interrupting a transaction, the processor is configured to generate a transaction abort at one or more peripheral locations. In one embodiment, the processor is configured to restore normal bus operation after a transaction interruption.

  In accordance with an embodiment of the present invention, a safety device including an interface and a processor is provided. The interface is used to connect to a bus that provides service to one or more peripheral devices. The processor is connected to the bus in addition to one or more peripheral devices, and further responds to the bus master device but does not respond to one or more peripheral devices, and the bus master tries to access a specific peripheral device. Suspend the device transaction.

  In one embodiment, bus transmission includes (i) one or more dedicated signals dedicated to one or more peripheral devices corresponding to each other, and (ii) one or more serviced by the bus. Including one or a plurality of shared signals shared among peripheral devices. Among them, the processor (i) suspends a dedicated signal associated with a particular peripheral device, and (ii) suspends the transaction by responding to the bus master device when the dedicated signal is interrupted.

  In one embodiment, the particular peripheral device includes a storage device. The processor is configured to identify a request from the bus master device to read data from the storage device in a transaction and respond to the request with alternative data stored in the safety device. In the illustrative embodiment, the processor is configured to interrupt the transaction and respond with alternate data when the bus master device identifies a request to access a defined address area in the storage device.

  In another embodiment, the processor is configured in a transaction to identify a bus master device transaction attempting to access a particular peripheral device based on data returned from the particular peripheral device to the bus master device. Is done. In yet another embodiment, the processor is configured to identify a bus master device transaction attempting to access a particular peripheral device based on the command code used in the transaction.

  Embodiments of the present invention further provide a method for securely accessing a peripheral device via a bus, which communicates via the bus using a safety device, wherein the safety device is connected to the bus, and It becomes an auxiliary device other than one or a plurality of peripheral devices, and transmission of the bus is performed by (i) one or a plurality of dedicated signals respectively dedicated to one or a plurality of peripheral devices corresponding to each other and (ii) a bus. Including one or more shared signals shared between one or more serviced peripherals, using the safety device and interrupting dedicated signals associated with a particular peripheral device on the bus In this case, the transaction of the bus master device attempting to access a specific peripheral device is interrupted.

  In accordance with an embodiment of the present invention, a method is provided for secure access to peripheral devices over a bus. A safety device is used to communicate via the bus, the safety device being connected to the bus and being an attached device other than one or more peripheral devices. The safety device is used to interrupt the bus master device's transaction to access the specific peripheral device on the bus in a manner that responds to the bus master device but not to the specific peripheral device.

  In another embodiment, an apparatus is provided that includes an interface and a processor. The interface is set to communicate on the bus, and the processor forces one or more dummy values to be paralleled on at least one line of the bus when the bus master device attempts to access a peripheral device without authorization. Write to interrupt at least some transactions.

  In one embodiment, the processor forces a dummy value to be written to the data line on the bus and sets the data line to block receiving or transmitting the respective data value of the peripheral device. Additionally or alternatively, the processor forces a dummy value to be written to the clock line on the bus and sets the clock signal used for the transaction to be interrupted. Additionally or alternatively, the processor is configured to forcibly write a dummy value to the chip select line on the bus to interrupt the peripheral device selected by the bus master device.

  In one embodiment, the bus comprises an open collector bus or an open drain bus having a preset logic value, and the processor forces a dummy value that contradicts the preset logic value to at least one line on the bus. Set to write.

  In one embodiment, by forcing a dummy value, the processor is set to overlay at least one line of the corresponding value written to the bus master device or peripheral device. In an exemplary embodiment, the processor overlays at least one line of corresponding values written on the bus master device or peripheral device by driving at least one line of greater drive strength than the bus master device or peripheral device. Is set as follows. In another embodiment, the device has at least one resistor, which is set on at least one line. The resistor is set so that the value written in the bus master device or peripheral device is attenuated to be weaker than the dummy value written by the processor.

  In one embodiment, the processor is configured to force a dummy value through only one existing line of the bus used for communication between the bus master device and the peripheral device. In one embodiment, the processor is configured to detect aborting transactions by monitoring the bus. In one embodiment, the processor is configured to detect aborting transactions by communicating with the bus master device over an auxiliary interface external to the bus master device.

  In one disclosed embodiment, the processor is set to force an unlimited number of dummy values until the device is reset. In another embodiment, the processor is set to force a dummy value to be written within a finite time when a transaction is detected. In one embodiment, the processor is set to properly resume normal operation of the bus when a transaction is interrupted.

  In accordance with an embodiment of the present invention, a system is further provided that includes peripheral devices and safety devices. Peripheral devices access one or more bus master devices by a bus. This safety device forcibly writes one or more dummy values to at least one line of the bus and interrupts at least some transactions when the bus master device tries to access a peripheral device without authorization. To do.

  Based on the embodiment, the present invention further determines whether or not to interrupt a transaction of a bus master device that attempts to unapproved access to a peripheral device using a safety device connected to the bus. A dummy value is forcibly written to at least one line of the bus in parallel to interrupt at least some transactions.

1 is a block diagram of a secure system in which a plurality of devices communicate via an I ² C bus in an embodiment of the present invention. 4 is a flowchart of a method for protecting access to a peripheral device through an I ² C bus according to an embodiment of the present invention. FIG. 5 is a block diagram of a secure system in which multiple devices communicate over an SPI bus in an alternative embodiment of the present invention. FIG. 5 is a block diagram of a secure system in which multiple devices communicate over an SPI bus in an alternative embodiment of the present invention. FIG. 5 is a block diagram of a secure system in which multiple devices communicate over an SPI bus in an alternative embodiment of the present invention. It is a block diagram of the safety device of the Example of this invention. 4 is a flowchart of a secure booting method used for a host device according to an embodiment of the present invention.

  In order to fully understand the present invention, the following description will be made in detail with reference to examples while showing diagrams.

  Outline

  Embodiments of the present invention provide an improved method and apparatus for how to protect access to peripheral devices via a bus interface. Peripheral devices include cryptographic engines, storage devices that store handling attention data, or any device accessed via a bus.

  In some disclosed embodiments, the safety device monitors bus transactions and further identifies when a host device or other bus master device attempts to access a peripheral device without authorization. Transactions are classified as approved or unapproved according to various appropriate criteria or policies.

  When an unapproved transaction is identified, the safety device forces data or signals to be written to several dummy values in parallel through one or more lines of the bus and interrupts it. For example, the dummy value can be forcibly written in a clock signal, a data signal, and / or a chip-select signal.

Forcibly writing the dummy value is suitable for interrupting a signal on a bus such as an open drain or open collector bus such as an I ² C bus or a push-pull bus such as an SPI bus. In parallel with the transaction on the bus, the dummy value is forcibly written to interrupt the communication with the peripheral device and / or interrupt each clock signal.

This document describes several technical examples used to suspend unapproved transactions on the I ² C and SPI buses, but also describes techniques used to resume normal operation after suspending. To do. In one embodiment, the safety device can interrupt the transaction, but does not need to detect this transaction on the bus in advance, or may not monitor the bus at all. As an example, the safety device can forcibly input a dummy value on the chip select (CS) line of the host device until or until the host device is approved.

In one embodiment, for example, in SPI, the transmission of the bus protected by the safety device is (i) one or more dedicated signals dedicated to the corresponding peripheral devices and (ii) the bus. It includes one or more shared signals that are shared among the serviced peripherals. An example of the shared signal is a data and a clock signal. An example of a dedicated signal is a CS signal. In one embodiment, the safety device maintains the shared signal on the bus and does not interrupt it, but interrupts the transaction by interrupting the dedicated signal associated with the protected peripheral device. It should be noted that not all buses have dedicated signals, for example, all signals are shared signals on an I ² C bus.

  In other embodiments, the secure device does not respond to the protected peripheral device, but suspends the transaction in a manner that responds to an unauthorized host device. In the illustrative embodiment, the peripheral device includes flash memory. The flash memory includes one or more address areas allocated for use in storing handling attention data such as keys, setup data and / or boot codes. The safety device can drive access to data in the flash memory by selectively driving the CS signal of the flash memory. Conversely, the safety device responds to the host device using data stored within the safety device. This type of secure boot process is described here.

  The techniques disclosed herein provide immediate safety selective access to peripheral devices at a transaction-by-transaction level. In most of the techniques described herein, transaction identification and interruption is performed only with existing signals on the bus. Thus, the disclosed technique does not require unspecified pins or interconnections, thereby reducing the overall system size and cost.

Securely access data to peripheral devices via I ² C bus.

FIG. 1 is a block diagram of a safety system 20 according to an embodiment of the present invention. In the preferred embodiment of the present invention, system 20 includes host device 24 and peripheral device 28, all coupled to I ² C bus 32. For brevity, host device 24 and peripheral device 28 are sometimes referred to herein as a host and peripheral, and host device 24 is sometimes referred to as a bus master device.

The safety device 36 protects data access to the peripheral device 28 by monitoring the data exchange on the I ² C bus 32, and the host device 24 or other device having the bus master function accesses the peripheral device 28 without authorization. To avoid. The safety device 36 is also referred to as a control device or a trusted platform module (TPM). In an embodiment of the present invention, the safety device 36 is implemented by an interface 40 used to connect to the I ² C bus 32, a processor 44 installed to implement the techniques of the present invention, and the processor 44. It includes a memory 48 used to store one or more security policies.

  The processor 44 can classify the transaction as unapproved according to any defined or established policy. Typically, an unapproved transaction will overlay the peripheral device 28 data, read the peripheral device 28 data, set or send a command to the peripheral device 28, or otherwise access the peripheral device 28. I often try. The policy enforced by the safety device 36 can be a positive policy (eg, whitelist), a negative policy (eg, blacklist), a policy that depends on the device address or register offset, or any other policy Contains a format policy.

  As an example, the safety device 36 may require the host device to authenticate the identity of the host device 24 before access to the peripheral device 28 is authorized. Transactions attempted by unauthorized host devices can be considered unauthorized. The authentication can be performed by performing a challenge-response process between the host device and the safety device. Additionally or alternatively, the host device can be required to prove its identity in some other suitable manner, or to ensure that the secure boot process is successfully completed.

  In addition, or alternatively, some types of transactions (eg, read transactions) may be considered approved, and other types of transactions (eg, write transactions) may be considered unapproved. In yet another embodiment, access to selected peripheral devices can be considered authorized and access to other addresses can be considered unauthorized. As another example, bit sequences on the bus are displayed as unauthorized transactions.

  Typically, the processor 44 can determine whether the transaction has been approved in any suitable manner. Memory 48 stores one or more policies to determine whether the transaction has been approved.

The I ² C bus 32 includes a serial data line having a serial data (SDA) signal and a serial clock line having a serial clock signal (SCL). The terms “line” and “signal” are used interchangeably herein. By monitoring the SDA and SCL lines, the processor 44 can monitor all transactions on the I ² C bus 32 and identify unauthorized transactions.

When an unapproved transaction is identified, the processor 44 interrupts the transaction by forcing one or more dummy values to be written to the SDA line and / or SCL line on the I ² C bus 32. This mechanism is realized by the I ² C bus having an open drain / open collector structure. Both the SDA line and the SCL line are normally pulled up to a logic “1” state by using a pull-up resistor. Any device can always write a logical “0” value on the SDA or SCL line, regardless of the values that other devices may write simultaneously.

In one embodiment, upon identifying an unapproved transaction, the processor 44 of the safety device 36 passes the interface 40 over the SDA or SCL line of the I ² C bus 32 with a logical “0” ( Forcibly input the preset logical value “1”. In this specification, a “0” value is considered a dummy value. The value “0” forcibly written on the SDA line is a value sent from the host device 24 to the peripheral device 28, a value read from the peripheral device 28 by the host device 24, or a preset logical value “ Overwrite "1". Forcing a "0" value on the SCL line stops the clock signal and interrupts the transaction in any of the above situations.

  In one embodiment, processor 44 continues to force a "0" value until the device is reset. In other embodiments, the processor 44 allows a moderate resumption from interruption, i.e., allows the host device 24 and peripheral device 28 to resume the suspended transaction and resume normal operation. Some host devices and / or peripheral devices cannot resume from a paused timer. Therefore, if it is necessary to properly restart the host device and the peripheral device later, it is preferable to forcibly write the dummy value on the SDA line instead of on the SCL line.

In one embodiment, to return to normal operation after interrupting the transaction, the processor 44 stops the I ^{2 C} at on the bus, or generates a restart condition of I ^{2 C.} As used herein, an I ² C stop or I ² C restart condition includes an arbitrary bus signal value sequence, which indicates that the device bus is idle and a transaction can begin.

The processor 44 can utilize various techniques to allow it to resume properly after the transaction is interrupted. In one embodiment, processor 44 continues to forcibly write a “0” value for the length of the scheduled time. This is considered sufficient to abort an unapproved transaction. Any length of scheduled time can be used. For example, the length of the SM bus pause is defined as 25 mS. Therefore, when applying I ² C on the SM bus, the predefined duration should be set to at least 25 mS to make it easier to pause.

In another embodiment, the processor 44 forces a “0” value on the SDA line for a predetermined time until the SCL line is detected to be a logic high value (ie, not toggling). Continue writing. This condition can instruct the host device to abort or discard the transaction. The processor 44 can release the SDA line and may also generate an I ² C stop condition.

In yet another embodiment, it is useful to interrupt a transaction read from a peripheral device by installing the safety device 36 as an I ² C slave device with the same address as the peripheral device 28. The processor 44 in the safety device 36 responds to any unauthorized read request with a “0” data value. Peripheral device 28 similarly responds to these read requests in parallel to processor 44, but its data value is overlaid with a “0” value transmitted by safety device 36. This process continues until the host device aborts the transaction, for example via a stop condition. Note that, based on the I ² C standard, I ² C slave devices do not drive the ACK / NEGACK bit when transmitting data.

In another embodiment, the processor 44 forces a "0" value on the SDA line as useful for interrupting reading and writing transactions at the same time. Subsequently, if the host device 24 cannot identify this interruption, the transaction is normally terminated via “0” data on the bus, not data transmitted from the peripheral device 28. If the host device 24 detects this interruption (for example, support of I ² C multi-master arbitration) and discards the transaction, the processor 44 typically goes through an additional clock cycle generated on the SCL line. The host device 24 takes over the discarded transaction. The processor 44 aborts this transaction by completing the current byte that was subsequently transmitted and issuing a stop condition.

  The interruption and resumption techniques described above are merely illustrative of the embodiments. In an alternative embodiment, the processor 44 of the safety device 36 can suspend the transaction and / or proceed from suspend to resume by any other technique.

  In the above embodiment, only the existing lines of the bus are used to realize the detection, interruption and resumption after interruption of unauthorized transactions. In an alternative embodiment, the safety device 36 and the host device 24 are also connected by an auxiliary interface external to the bus 32. For example, the safety device 36 and the host device 24 are integrated into the same integrated circuit (IC), and the SDA of the IC This type of mechanism can be implemented when sharing the SCL pin.

  In these embodiments, safety device 36 and host device 24 use an auxiliary interface to validate that no other host device is accessing peripheral device 28. In the exemplary embodiment, when the host device 24 accesses the peripheral device 28, the host device 24 notifies the safety device 36 via the auxiliary interface. In order to respond to the notification, the processor 44 does not forcibly write the dummy value “0” to the bus and permits the execution of the transaction. When accessing a peripheral device 28 but detecting a transaction that has not yet been reported on the auxiliary interface, the processor 44 assumes that the transaction has been issued from some unauthorized host device and forces a "0" value. Interrupt it by writing.

FIG. 2 is a flowchart of a method for protecting an embodiment of the present invention from accessing peripheral device 28 via I ² C bus 32. The method starts at a monitoring step 50 where the processor 44 on the safety device 36 monitors transactions on the I ² C bus 32 via the interface 40.

  In the detect transaction step 54, the processor 44 identifies that the host device 24 is attempting to access the peripheral device 28 transaction. In a check step 58, the processor 44 checks whether the transaction has been approved. As an example, processor 44 may test whether this transaction violates a security policy stored in memory 48.

If the transaction is approved, at permission step 62, processor 44 allows the transaction to proceed normally, and if it detects that the transaction is unapproved, at interruption step 66, processor 44 In order to interrupt the transaction, a dummy value “0” is forcibly written to the SCL and / or SDA line of the I ² C bus 32.

  Access peripheral devices securely via the SPI bus.

  FIG. 3 is a block diagram of a safety system 70 in an alternative embodiment of the present invention. As shown in FIG. 3, system 70 includes host device 74, peripheral device 78, and safety device 86, all coupled to SPI bus 82.

  If the host device 74 attempts to gain unauthorized access to the peripheral device 78, the secure device 86 identifies this transaction and aborts. In an embodiment of the present invention, the safety device 86 includes an interface 90 connected to the SPI bus 82, a processor 94 that sets up techniques for carrying out the present invention, and one or more stored for execution by the processor 94. It includes a memory 98 in which individual security policies are set.

  The security policy for distinguishing between approved and unapproved transactions and the method by which the processor 94 of the safety device 86 identifies unapproved transactions are basically the same as the system 20 described above. The difference between the technology described later and the technology described above is that the safety device 86 forcibly writes a dummy value on the bus 82 and interrupts an unapproved transaction.

  The SPI bus 82 includes a clock (CLK) line and two data transmission lines referred to as a master-out-slave inline (MOSI) and a master-in-slave outline (MISO). The CLK, MISO, and MOSI lines are common to all devices (host devices 74, 78, and 86 in this embodiment). In addition, each slave device is selected by a dedicated chip select line. In this embodiment, the host device 74 uses the CS line labeled CS2 # to select the peripheral device 78 and further selects the safety device 86 using the CS line labeled CS1 #.

  A host device 74 as a master device is connected to all CS lines. On the other hand, since the peripheral device 78 is a slave device, each peripheral device 78 is connected only to its own CS line. Normally, the host device 74 uses the corresponding CS line to select the requesting peripheral device 78 and initiate a transaction. After that, it communicates with the device using the used CLK, MOSI and MISO lines. The MOSI line is used to send a signal from the host device 74 to the peripheral device 78, and the MISO line is used to send a signal from the peripheral device 78 to the host device 74.

  The safety device 86 is defined as a slave device, but is different from a general SIP slave device in that all the CS lines can be driven. As shown in FIG. 3, the interface 90 of the safety device 86 is installed to drive the CS2 # line in parallel with the host device 74. When the system 70 includes a plurality of peripheral devices 78 with corresponding CS lines, the safety device 86 is typically installed to drive any CS line connected to the host device 74 in parallel. .

  In one embodiment, the system 70 allows the logic value driven by the safety device 86 to change the logic value driven by the host device 74 when the host device 74 and the safety device 86 drive the CS line with opposite logic values. Designed to overlay. It can also be said that when the host device 74 and the safety device 86 drive opposite logic values on the CS line, the peripheral device 78 receives and executes the logic value driven by the safety device 86.

  CS line override is another example of interrupting an unacknowledged transaction between a host device and a peripheral device 78 by stopping the transaction on the bus. The above-described override mechanism can be realized in various ways. The following description relates to the CS2 # line for selecting the peripheral device 78, but the same mechanism must be used when using a plurality of peripheral devices 78 and a plurality of opposing CS lines. .

  In one embodiment, the line drive that drives the CS2 # line through the interface 90 of the safety device 86 is stronger than the line drive that the host device 74 drives the CS2 # line. In an alternative embodiment, series resistor 100 can be inserted into the CS2 # line at the output of host device 74. In contrast to the output portion of the CS2 # line drive for the safety device 86, the series resistor 100 weakens the output of the line drive for CS2 # of the host device 74. In addition, the safety device 86 is set to override the signal of the host device 74 that drives the CS2 # line in any other suitable manner.

  The processor 94 of the safety device 86 monitors the CS # line, CLK, MISO and / or MOSI line of the SPI bus 82 and identifies unauthorized transactions in any suitable manner. In one embodiment, upon identifying a host device 74 transaction that attempts to gain unauthorized access to a peripheral device 78, the processor 94 of the safety device 86 invalidates the transaction by invalidating the CS line of the peripheral device 78. Interrupt. Since the safety device 86 is set to overlay the drive of the host device 74 to the CS2 # line, the peripheral device 78 is deselected and the transaction is interrupted. On the other hand, if it is determined that the transaction has been approved, the processor 94 stops its CS2 # drive, thereby preventing access to the peripheral device 78 of the host device from being interrupted.

  FIG. 4 is a block diagram of a safety system 110 in another embodiment of the present invention. System 110 is based on SPI bus 82, similar to system 70 of FIG. However, in the system 110, the safety device 86 destroys unauthorized transactions by forcing a dummy value on the CLK, MISO, and / or MOSI lines and does not overlay the CS line.

  In this embodiment, the system 110 is set to take precedence over the host device 74 when the safety device 86 drives the CLK line, MISO line and / or MOSI line. As shown in the figure, in order to achieve the object, a series resistor 100 is inserted into the CLK line, the MISO line, and the MOSI line. Since the CS2 # line of this embodiment is not overlaid, the series resistor 100 is not inserted into the CS2 # line.

  In an alternative embodiment, the overlay mechanism is implemented by further strengthening the line drive of the CLK line, MISO line and / or MOSI line in the safety device 86.

  In other embodiments, it is also possible to use a mixed scheme in which the CS line is simultaneously overlaid (see FIG. 3) and the CLK line, MISO line and / or MOSI line (see FIG. 4) is overlaid.

  Access to peripheral devices is protected with a P2P signal dedicated to override.

  The signal of the bus (for example, SPI) is divided into a shared signal and a dedicated signal. The shared signal is a signal connected in parallel with a plurality of (for example, all) peripheral devices on the bus. Examples of shared SPI signals are data (MOSI and MISO) and clock (CLK) signals. The dedicated signal is a signal dedicated to a specific peripheral device. An example of a dedicated signal for a part of the bus is a chip-select signal. Alternatively, the bus can be augmented with an out-of-band dedicated signal such as a Write Protect signal (when a peripheral device includes a storage device) as an example. The dedicated signal is also called a P2P (PTP: point to point) line.

  In one embodiment, one or more dedicated signals pass through safety device 86 before reaching the peripheral device. Conversely, shared signals are usually routed to peripheral devices and do not pass through safety devices. This type of interconnection scheme effectively protects peripheral devices with safety devices, as described below.

  FIG. 5 is a block diagram illustrating a safety system 130 according to an alternative embodiment of the present invention. The system is similar to the system 70 of FIG. However, in this embodiment, the CS2 # signal does not directly drive the input of the peripheral device 78. Conversely, the CS2 # line from the host device 74 is input to the safety device 86, which drives a signal labeled CS2_O #, which is connected to the input of the peripheral device 78.

  In the present embodiment, as an example in which the CS2 # signal is used for the dedicated PTP signal, it passes through the safety device on the way and is routed to the protected peripheral device. As can be seen, the shared signals (MOSI, MISO and CLK) are not interrupted between the host device 74 and the peripheral device 78.

  The safety device 86 is set to interrupt the transaction between the host device 74 and the peripheral device 78 by selecting whether the CS2 # signal reaches the peripheral device, or the CS2 # signal does not reach the peripheral device. Is done. In the example of FIG. 5, the selection is performed through whether the control signal indicated as MASK_CS2 # is asserted or deasserted.

  FIG. 6 is a block diagram of the safety device 86 based on the system 130 described in FIG. 5 of the embodiment of the present invention. In this embodiment, the safety device 86 includes an interface 90 connected to the SPI bus 82, a processor 94 installed to implement the disclosed technology, and one or more security enforced by the processor 94. And a memory 98 installed to store the policy. The processor 94 includes slave interface logic (slave interface logic) 91 and interface monitor logic (IML) 92. Communication between the safety device 86 and the host device 74 is handled by the slave interface logic 91. Interface monitor logic 92 monitors, controls, and selectively overrides host device 74 access to peripheral devices 78.

  In one embodiment, the safety device 86 identifies and aborts a host device 74 transaction that attempts to access the peripheral device 78 on the SPI bus 82 without authorization. As can be seen from FIGS. 5 and 6, any safety function possible in the system shown in FIG. 3 can be realized in the system of FIG.

  In the above embodiment, the safety device is set to connect to the bus and add slave equipment. However, in other embodiments, the safety device can be installed as a master device. As an example, this type of implementation applies to bus protocols that support multi-master functionality.

  The safety device responds on behalf of the peripheral device to protect against unauthorized transactions.

  In another embodiment, secure device 86 responds to selected host device transactions on behalf of peripheral device 78. The following description mainly relates to the settings in FIGS. 5 and 6 and gives a simple example. Generally, the disclosed technique is not limited to the specific system settings, and can be applied to any other settings as shown in FIG. 3 or FIG. 4 as an example.

  In the embodiment shown in the settings of FIGS. 5 and 6, when a read command is detected from a certain address area in the address space of the peripheral device 78, the interface monitor logic 92 can forcibly set CS2_O # to “high” and A host device read command (or part of a read command) from within the memory 98. Host device 74 typically does not know that the response is not from a peripheral device. In one embodiment, such a scene applies to the system 110 of FIG. 4, such as when the safety device overrides the MISO signal.

  An example of the use of this type of mechanism is a kind of system. Of these, the peripheral device 78 includes an SPI flash memory device, and the safety device 86 is further configured to override some flash memory address space, and in this manner secure flash memory emulation in the address region. )I will provide a. As an example, the safety device 86 includes a TPM that overrides the flash memory address area (the first activation command derived by the host device at start-up) that includes the initial host boot code in the interface monitor logic 92. The TPM overrides the flash memory address area with the initial boot code that has been self-contained. As an example, authenticate the rest of the code before jumping to the code.

  In one embodiment, safety device 86 further includes a main interface to the SPI flash memory device. Alternatively, the safety device 86 may include a suitable interface and circuitry to keep the host device 74 reset when accessing the SPI flash memory device, which is usually part of the system start process. The safety device 86 may be an embedded controller (EC), Super I / O (SIO), or baseboard management controller (BMC) device, for example.

  FIG. 7 is a flowchart showing an example of a secure boot process in the embodiment of the present invention. The method starts with wakeup, which is to assert system power. In the reset maintaining step 102, the safety device 86 maintains the host device 74 in a reset state, and further selectively activates from the SPI flash memory (peripheral device 78). In the (optional) initial read step 104, the safety device 86 reads the data block from the SPI flash memory, checks the authentication of the data block, and stores it in the memory 98.

  In the override step 108, the safety device 86 sets the interface monitor logic 92 to override access to at least one defined address area (referred to as peripheral device 78 in this embodiment) in the SPI flash memory. The address area in question can include, by way of example, one or more keys, setup data, and / or an initial boot block of the host device 74.

  In the reset release step 112, the safety device 86 releases the reset of the host device. Accordingly, in the startup step 116, the host device 74 starts its startup process. As part of the startup process, in the area access sub-step 120, the safety device 86 services access from the internal memory 98 to the defined address area.

  By such a system, the key, setup data and / or handling attention data of the initial boot codes are safely provided from the safety device. The host device 74 cannot know that the data is provided from the safety device, not from the SPI flash memory.

  The method of FIG. 7 is an example of how the safety device overrides access to a peripheral device's defined address area. In alternative embodiments, any other suitable method can be used for that purpose. As an alternative to impersonating an SPI flash memory device, the safety device protects the flash memory device (or other peripheral device) by overriding and / or aborting any other suitable unapproved transaction.

  In addition, overriding unapproved transactions is not limited to protecting specific defined address areas. As an example, an override is activated based on return data from a protected external facility or an SPI command code. By way of example, a safety device can enforce a security policy, which disables programming, erasing, write activation, status / setting and / or any other command or function for the flash memory device. As a normative example depending on SPI flash memory order and command, on August 24, 2015, “SPI flash memory-SPI / QPI 3V serial flash memory (SPI Flash-3V Serial with dual / quad) by Winbond Electronics Corporation Flash Memory with Dual / Quad SPI and QPI) ”.

  As another example, in the method of FIG. 7, handling attention data is always present in the flash memory device, and further read by the safety device as part of the startup process. In an alternative embodiment, the handling attention data may first be stored in the safety device (other than flash memory or not stored in flash memory). In such an embodiment, the data need not be read from the flash memory device to the safety device.

As another example, the method of FIG. 7 will be described with reference to the SPI bus. In an alternative embodiment, the safety device overrides access to a predefined address area of the peripheral device in other buses and protocols with any dedicated signal (if any) and / or shared signal of the bus. By way of example, the I ² C bus is a pull-up bidirectional bus, which is intended to support multiple slave devices and multiple master devices. Thus, contention between facilities is handled by a protocol with a built-in mechanism. As an example, if an I ² C facility tries to set “1” (pull-up) and detects “0” on the SDA line, it assumes that the device is in contention and releases the bus until the next transaction. To do. In one embodiment, the I ² C safety device (eg, the safety device 36 of FIG. 1) is one of the address spaces of other peripheral slave devices (eg, the peripheral device 28 of FIG. 1). Set to overlap with the part. As an example, the safety device is set to respond to the same data as other peripheral devices. If the safety device detects a data mismatch (for example, “1” is to be pulled up, but “0” is detected on the SDA line), the safety device performs a response operation (for example, the stop As a condition, it is driven to “0” on one or more data lines and endless clock stretching (endless clock stretching) or any other suitable operation is set). The technique uses a conventional I ² C slave unit (no hardware changes in the physical layer) and monitors the equipment to the data level.

  Further, in one embodiment, the safety device 86 further monitors the data phase of the SPI address (using the interface monitor logic 92). Upon identifying a data mismatch, the safety device initiates a response action such as aborting the transaction, resetting the system, locking access to the key, or any other suitable action.

  In the exemplary situation, the safety device 86 stores a signature or digest of a particular code segment stored in the SPI flash memory. The safety device monitors access to the SPI flash memory of the host device 74 when calculating the cache value of the signature or code portion in the background. If an incorrect signature, cache value or SPI acquisition sequence is detected, the safety device 86 initiates an appropriate response operation.

  Further, in one embodiment, the safety device can monitor more than one peripheral device 78 on the bus 82, for example authenticating that the order of access to different facilities is on schedule.

  Further, in one embodiment, the safety device 86 uses one or more signals (other than CS) to restrict access to the peripheral device 78 or to detect an approval transaction to the peripheral device 78. Force the execution of certain system states. Non-limiting examples of this type of signal include:

Any signal described in the system as in FIG.
• Write protect signal in flash memory.
・ Reset control signal.
• Power management control signal.
• One or more devices that control the power supply.
Communication that stops the system (for example, a network stop interface controller).
・ System reset.

  The arrangement of the systems 20, 70, 110 and 130 and the various system components such as the safety devices 36 and 86 and the buses 32 and 82 shown in FIGS. 1 and 3 to 6 are all schematic diagrams for clarity of explanation. However, in one alternative embodiment, any other suitable arrangement may be used.

By way of example, for clarity, the drawing shows only one peripheral device and one host device. In one embodiment, the system can include two or more peripheral devices and / or two or more host devices. The embodiment shown here refers to an embodiment using I ² C and SPI buses. In alternative embodiments, the disclosed technology can be used with other modifications as necessary on any other suitable type of bus.

  The different components of the systems 20, 70, 110 and 130 can be arbitrary, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Can be run on any appropriate hardware. In one embodiment, some parts of safety devices 36 and 86 (eg, processor 44 or processor 94) are implemented in software or a combination of hardware and software parts. The memories 48 and 98 can use any suitable type of storage device, for example, random access memory (RAM) or flash memory.

  In one embodiment, processor 44 and / or processor 94 includes a general purpose programmable processor programmed into software to perform the functions described herein. Software can be downloaded to the processor in electronic form over the network, or can be added to or replaced with non-transitory tangible media such as magnetic, optical, and electronic memory storage.

  In the embodiment described above, the safety device first detects unauthorized transactions by monitoring the bus and then aborts the transaction. In an alternative embodiment, the safety device does not need to detect the transaction first, nor does it need to monitor the bus to abort the transaction. As an example, a security device can overlay a host device's chip select (CS) line until or until the host device is approved. The authorization is performed in any suitable way and does not have to use the same bus.

  By way of non-limiting example, the methods and systems described herein, such as secure memory applications, Internet of Things (IoT) applications, embedded applications, or automotive applications, to name but a few examples are listed here. Can be used for various applications.

  It should be understood that the embodiments described above are cited in the manner of the embodiments, and the present invention is not limited to the specific presentation and details described above. Furthermore, the scope of the present invention includes combinations and subcombinations of the various features described above as well as undisclosed techniques that can be devised after reading the description by those skilled in the art. Documents incorporated in this application are part of this application, and if the definitions of terms in these incorporated documents clearly contradict or imply contradictions herein, For reference.

20 System 24 Host device 28 Peripheral device 32 I ² C bus 36 Safety device 40 Interface 44 Processor 48 Memory 50 Monitoring step 54 Detection step 58 Inspection step 62 Authorization step 66 Interruption step 70 System 74 Host device 78 Peripheral device 82 SPI bus 86 Safety Device 90 Interface 91 Slave interface logic 92 Interface monitor logic 94 Processor 98 Memory 110 System 130 System 100 Series resistance 102 Reset maintenance step 104 Initial read step 108 Override step 112 Reset release step 116 Start step 120 Area access sub step CS1 # Chip select line CS2 # Chip select line CLK clock Line MASK_CS2 # control signal MOSI master out slave-line MISO The Master-In-Slave-outline

Claims (34)

In a safety device for safely accessing peripheral devices via a bus,
Used to connect to a bus that provides service to one or more peripheral devices, of which the transmission on the bus is (i) one or more dedicated signals dedicated to one or more peripheral devices, respectively. And (ii) an interface including one or more shared signals shared between the one or more peripheral devices serviced by the bus;
Connect to the bus, function as an auxiliary device other than one or more of the peripheral devices, and interrupt the dedicated signal that correlates to a specific peripheral device, thereby causing the specific peripheral on the bus A processor that interrupts a transaction of a bus master device attempting to access the device;
A safety device for safely accessing a peripheral device via a bus.   The safety device of claim 1, wherein the processor maintains the shared signal on the bus and does not suspend when suspending the transaction. The interface is
An input unit used to receive the dedicated signal from the bus master device;
An output unit used to output the dedicated signal to the specific peripheral device,
2. The safety device according to claim 1, wherein the processor interrupts the transaction by preventing the dedicated signal received by the input unit from being transmitted from the output unit.   2. The safety device of claim 1, wherein the processor is configured to respond to the bus master device when the dedicated signal is interrupted, but not to the specific peripheral device.   The safety device according to claim 1, wherein the dedicated signal includes a chip select (CS) signal.   The safety device according to claim 1, wherein the processor detects the transaction to be interrupted by monitoring the bus.   The safety device according to claim 1, wherein the processor detects the transaction to be interrupted by communicating with the bus master device via an auxiliary interface external to the bus.   The safety device according to claim 1, wherein the processor is set to continuously interrupt the dedicated signal until a reset signal appears.   The safety device of claim 1, wherein the processor is configured to suspend the dedicated signal within a limited time after detecting the transaction.   The safety device of claim 1, wherein the processor is configured to generate a transaction abort at one or more of the peripheral device locations by interrupting the transaction.   The safety device of claim 1, wherein the processor is configured to restore normal operation of the bus after the transaction is interrupted. In a safety device for safely accessing peripheral devices via a bus,
An interface used to connect to a bus providing service to one or more peripheral devices;
In addition to connecting to one or more peripheral devices, it connects to the bus and responds to the bus master device, but does not respond to one or more peripheral devices. A processor that interrupts a transaction of the bus master device to be accessed;
A safety device for safely accessing a peripheral device via a bus. The bus transmission includes (i) one or more dedicated signals dedicated to one or more peripheral devices corresponding to each other, and (ii) one or more peripheral devices serviced by the bus. One or a plurality of shared signals shared between,
Wherein the processor (i) suspends the dedicated signal associated with the particular peripheral device, and (ii) responds to the bus master device when the dedicated signal is interrupted. 13. The safety device according to claim 12, wherein the transaction is interrupted.   The particular peripheral device includes a storage device, of which the processor identifies a request from the bus master device to read data from the storage device in the transaction and is stored in the safety device. 13. The safety device according to claim 12, wherein the safety device is configured to respond to the request with alternative data.   The processor is configured to suspend the transaction and respond with the alternative data when the bus master device identifies a request to access a defined address area in the storage device. Item 15. The safety device according to Item 14.   The processor is configured to identify a transaction of a bus master device attempting to access a particular peripheral device based on data returned from the particular peripheral device to the bus master device in a transaction. 12. The safety device according to 12.   The safety of claim 12, wherein the processor is configured to identify the transaction of a bus master device attempting to access the particular peripheral device based on a command code used in the transaction. apparatus. In a method for securely accessing a peripheral device via a bus,
Communicating via a bus using a safety device, wherein the safety device is connected to the bus and becomes an accessory device other than one or more peripheral devices, of which transmission on the bus is (i) One or a plurality of dedicated signals respectively dedicated to one or a plurality of peripheral devices corresponding to each other; and (ii) one or a plurality of the peripheral devices serviced by the bus A plurality of shared signals, and
Via a bus characterized in that the safety device interrupts the dedicated signal associated with a specific peripheral device, thereby interrupting a bus master device transaction attempting to access the specific peripheral device on the bus. For secure access to peripheral devices.   The method of claim 18, wherein the step of suspending the transaction includes maintaining and not interrupting the shared signal on the bus. Further comprising using an input used to receive the dedicated signal from the bus master device, and using an output used to output the dedicated signal to the particular peripheral device;
19. The method according to claim 18, wherein the step of interrupting the transaction includes the step of preventing the dedicated signal received at the input unit from being transmitted from the output unit.   19. The method of claim 18, wherein the step of interrupting the transaction includes responding to the bus master device but not responding to the particular peripheral device when the dedicated signal is interrupted.   The method of claim 18, wherein the dedicated signal comprises a chip select (CS) signal.   The method of claim 18, further comprising detecting the transaction to be suspended by monitoring the bus.   The method of claim 18, further comprising detecting the transaction to be aborted by communicating with the bus master device using an auxiliary interface external to the bus.   The method of claim 18, wherein suspending the transaction includes continuing to suspend the dedicated signal until a reset signal appears.   The method of claim 18, wherein the step of suspending the transaction includes suspending the dedicated signal within a finite time after detecting the transaction.   19. The method of claim 18, wherein the step of interrupting the transaction includes generating a transaction abort at one or more of the peripheral device locations.   The method of claim 18, further comprising restoring normal operation of the bus after the transaction is interrupted. In a method for securely accessing a peripheral device via a bus,
Communicating via a bus using a safety device, wherein the safety device is connected to the bus and becomes an attached device other than one or more peripheral devices;
Use the safety device to respond to the bus master device but not to the specific peripheral device, thereby causing the bus master device transaction to access the specific peripheral device on the bus. A method for securely accessing a peripheral device via a bus comprising the step of interrupting. The bus transmission includes (i) one or more dedicated signals dedicated to one or more peripheral devices corresponding to each other, and (ii) one or more peripherals serviced by the bus. Including one or more shared signals shared between devices,
The steps of suspending the transaction include (i) suspending the dedicated signal associated with the particular peripheral device, and (ii) responding to the bus master device when the dedicated signal is interrupted. 30. The method of claim 29.   The particular peripheral device includes a storage device, wherein the step of interrupting the transaction identifies a request from the bus master device to read data from the storage device in the transaction and is stored in the safety device. 30. The method of claim 29, comprising responding to the request with alternative data being stored.   30. The method of claim 29, wherein when the bus master device identifies a request to access a defined address area in the storage device, the transaction is interrupted and responded with the alternative data.   In the transaction, further comprising identifying the transaction of the bus master device attempting to access the specific peripheral device based on data returned from the specific peripheral device to the bus master device. 30. The method of claim 29.   30. The method of claim 29, further comprising identifying the transaction of the bus master device attempting to access the particular peripheral device based on a command code used in the transaction.

Images