JP2019204902A - Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor - Google Patents

Abstract

To provide a multilayer ceramic capacitor in which a crack does not reach an opposing portion even when the crack occurs in a multilayer ceramic capacitor body.SOLUTION: A multilayer ceramic capacitor 10 including a laminate 12 including a plurality of laminated dielectric layers 14 and a plurality of laminated internal electrode layers 16, and external electrode layers 24a and 24b connected to the internal electrode layer 16 and disposed on the end face of the laminate 12 includes an inner layer portion 40 including the internal electrode layer 16b closest to a first main surface 12a to the internal electrode layer 16a closest to a second main surface 12b, and a first outer layer portion 42 and a second outer layer portion 44 sandwiching the inner layer portion 40, and the first outer layer portion 42 includes a first outer layer located closest to the first main surface 12a and a first inner outer layer portion between the first outer layer portion and the inner layer portion 40. A gap 80c (80d) is provided on at least a part of the boundary surface between the first outer layer portion and the first inner outer layer portion.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor.

  In general, in a multilayer ceramic capacitor, an external electrode that covers each end face of a multilayer body is often formed by applying a heat treatment after applying a conductive paste to each end face of the multilayer body. Here, when heat treatment is performed, stress may be accumulated in the external electrode due to the difference between the linear expansion coefficient of the laminate and the linear expansion coefficient of the external electrode. A multilayer ceramic capacitor in which stress is accumulated in the external electrode may cause cracks in the multilayer body due to the stress accumulated in the external electrode or the flexural stress of the substrate when mounted on the mounting substrate.

  As means for solving such a problem, for example, as in Patent Document 1, an effective layer in which an internal electrode is provided between a plurality of first ceramic layers (dielectric layers) and a second plurality of ceramic layers ( In a base body (laminated body) having an ineffective layer provided with a plurality of reinforcing layers arranged between the dielectric layers) at predetermined intervals, the plurality of reinforcing layers provided in the ineffective layer are formed as base bodies (laminated bodies). ), A technology that can suppress the occurrence of cracks or the like in the main body of the chip-type electronic component (multilayer ceramic capacitor) is disclosed.

JP 2002-75780 A

  However, in the technique in which the reinforcing layer is provided in the ineffective layer as in Patent Document 1, there is a problem of cost increase due to the provision of the reinforcing layer, and the capacity forming portion (opposite portion of the internal electrode layer) corresponding to the provision of the reinforcing layer There may be a problem of capacity reduction due to the limitation of the number of stacked layers, and a slight displacement of capacity due to stray capacitance generated between the effective layer and the reinforcing layer.

  Therefore, the present invention provides a multilayer ceramic capacitor in which cracks do not reach the facing portion even if cracks occur in the multilayer ceramic capacitor body, while suppressing the above problems.

  The multilayer ceramic capacitor according to the present invention includes a plurality of dielectric layers stacked and a plurality of stacked internal electrode layers, a first main surface and a second main surface facing the stacking direction, and a stacking direction A laminated body including a first side surface and a second side surface opposite to each other in a width direction orthogonal to the first side surface, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction; A first external electrode layer disposed on the first end surface of the multilayer body; and a second external electrode layer disposed on the second end surface of the multilayer body, wherein the plurality of internal electrode layers are And a first internal electrode layer drawn to the first end face and a second internal electrode layer drawn to the second end face, and the stacked body includes the first internal electrode layer or the second internal electrode layer in the stacking direction. Among the internal electrode layers, the internal electrode layer located closest to the first main surface side to the first internal electrode layer. Is an inner layer portion including the first internal electrode layer or the second internal electrode layer located closest to the second main surface among the second internal electrode layers, and a plurality of dielectrics sandwiching the inner layer portion between each other A first outer layer portion composed of a body layer and a second outer layer portion composed of a plurality of dielectric layers, wherein the first outer layer portion is divided into two regions, and the first outer layer portion is A first outer outer layer portion including a plurality of dielectric layers including a dielectric layer located closest to the first main surface among the plurality of dielectric layers constituting the first outer outer layer portion and the inner layer portion; Including a first inner outer layer portion composed of a plurality of dielectric layers constituting the first outer layer portion positioned between the first outer outer layer portion and at least a part of a boundary surface between the first outer outer layer portion and the first inner outer layer portion. Has a gap portion.

According to the multilayer ceramic capacitor according to the present invention, even if the multilayer ceramic capacitor is cracked due to the deflection of the substrate, stress can be concentrated in the gap and the crack can be extended along the gap. Therefore, it is possible to suppress the crack from reaching the facing portion. Therefore, even if a crack occurs, the characteristics of the capacitor can be maintained.
Since the reinforcing layer is not provided as in Patent Document 1 aiming at the same effect, the problem of the cost increase by providing the reinforcing layer, the problem of the capacity reduction by thickening the ineffective layer by the provision of the reinforcing layer, Further, it is possible to suppress the problem of slight displacement of the capacitance due to the stray capacitance generated between the effective layer and the reinforcing layer.

  According to the present invention, the problem of cost increase due to the provision of the reinforcing layer as in Patent Document 1, the problem of capacity reduction due to the thickening of the ineffective layer, and the effective layer and the reinforcing layer are provided. It is possible to provide a multilayer ceramic capacitor in which cracks do not reach the facing portion even if cracks occur in the multilayer ceramic capacitor body, while suppressing the problem of slight displacement of capacitance due to stray capacitance generated therebetween.

  The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the present invention. It is sectional drawing in the II-II line | wire of FIG. 1 which shows the multilayer ceramic capacitor concerning this invention. It is sectional drawing in the III-III line of FIG. 1 which shows the multilayer ceramic capacitor concerning this invention. It is the A section enlarged view of FIG. 3 which shows the multilayer ceramic capacitor concerning this invention. It is sectional drawing in the VV line | wire of FIG. 3 which shows the multilayer ceramic capacitor concerning this invention. (A) is the schematic in the LT cross section of the multilayer ceramic capacitor concerning this invention. (B) is the schematic in the WT cross section of the multilayer ceramic capacitor concerning this invention. It is a flowchart which shows the manufacturing method of the multilayer ceramic capacitor concerning this invention. It is an external appearance perspective view which shows the modification of the multilayer ceramic capacitor concerning this invention. It is sectional drawing in the IX-IX line of FIG. 8 which shows the modification of the multilayer ceramic capacitor concerning this invention. It is sectional drawing in the XX line of FIG. 8 which shows the modification of the multilayer ceramic capacitor concerning this invention. It is the B section enlarged view of FIG. 10 which shows the modification of the multilayer ceramic capacitor concerning this invention. (A) is LW sectional drawing of the laminated body at the time of permeate | transmitting the location of a clearance gap part. (B) is a WT cross-sectional view of the laminate when the gap portion is transmitted. It is a flowchart which shows the manufacturing method of the modification of the multilayer ceramic capacitor concerning this invention.

1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor 10 according to the present invention will be described with reference to FIGS. FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the present invention. 2 is a cross-sectional view taken along the line II-II of FIG. 1 showing the multilayer ceramic capacitor according to the present invention. 3 is a cross-sectional view of a multilayer ceramic capacitor according to the present invention shown in FIG.
It is sectional drawing in an III line. FIG. 4 is an enlarged view of part A of FIG. 3 showing the multilayer ceramic capacitor according to the present invention. FIG. 5 is a cross-sectional view taken along line VV of FIG. 3 showing the multilayer ceramic capacitor according to the present invention. FIG. 6A is a schematic view of an LT cross section of the multilayer ceramic capacitor according to the present invention. FIG. 6B is a schematic view of a WT cross section of the multilayer ceramic capacitor according to the present invention.

  As shown in FIGS. 1 to 6, the multilayer ceramic capacitor 10 includes a multilayer body 12 having a rectangular parallelepiped shape.

(Laminated body 12)
The multilayer body 12 includes a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 that are stacked, and includes a first main surface 12a and a second main surface 12b that are opposed to the stacking direction x, and a stacking direction x. A first side surface 12c and a second side surface 12d opposite to the orthogonal width direction y; a first end surface 12e and a second end surface 12f opposite to the length direction z orthogonal to the stacking direction x and the width direction y; ,including. Moreover, it is preferable that the laminated body 12 is rounded in the corner | angular part or the ridgeline part. In addition, a corner | angular part is a part where 3 adjacent surfaces of the laminated body 12 cross, and a ridgeline part is a part where 2 adjacent surfaces of the laminated body 12 intersect. Further, unevenness or the like is formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f. May be.

(Dielectric layer 14)
Examples of the ceramic material of the dielectric layer 14 of the multilayer body 12 include a dielectric made of a main component such as BaTiO ₃ , CaTiO ₃ , SrZrO ₃ , CaZrO ₃ or (Ca, Sr, Ba) (Zr, Ti) O _3. Ceramic can be used. Moreover, you may use what added subcomponents, such as a Mn compound, Si compound, Al compound, Re compound (Re is a rare earth element), Fe compound, Cr compound, Co compound, Ni compound, to these main components.

  The thickness of the dielectric layer 14 is preferably 0.3 μm or more and 10 μm or less.

  The dielectric layer 14 of the multilayer body 12 is formed from the internal electrode layer 16 located closest to the first main surface 12a of the first internal electrode layer 16a or the second internal electrode layer 16b in the stacking direction x. A plurality of dielectric layers sandwiching the inner layer portion 40 between the inner layer portion 40 and the inner layer portion 40 including up to the inner electrode layer 16 located closest to the second main surface 12b among the one inner electrode layer 16a or the second inner electrode layer 16b. A first outer layer portion 42 composed of the body layer 14 and a second outer layer portion 44 composed of the plurality of dielectric layers 14. The first outer layer portion 42 includes a plurality of dielectrics positioned between the first main surface 12a and a straight line along the width direction y of the outermost surface of the inner layer portion 40 on the first main surface 12a side. A plurality of dielectric layers positioned between the portion composed of the layer 14 and the first main surface 12a and a straight line along the length direction z of the outermost surface of the inner layer portion 40 on the first main surface 12a side A portion composed of 14 is also included. Similarly, the second outer layer portion 44 includes a plurality of dielectric layers positioned between the second main surface 12b and a straight line along the width direction y of the outermost surface of the inner layer portion 40 on the second main surface 12b side. A plurality of dielectrics positioned between the portion composed of the body layer 14 and the second main surface 12b and a straight line along the length direction z of the outermost surface of the inner layer portion 40 on the second main surface 12b side A portion composed of the layer 14 is also included.

  As shown in FIG. 4, the first outer layer portion 42 is divided into two regions, and is located closest to the first main surface 12 a among the plurality of dielectric layers 14 constituting the first outer layer portion 42. A plurality of first outer outer layer portions 42 a made up of a plurality of dielectric layers 14 including the dielectric layer 14, and a plurality of first outer layer portions 42 positioned between the first outer outer layer portion 42 a and the inner layer portion 40. And a first inner outer layer portion 42b made of the dielectric layer 14. The first outer layer portion 42 is provided on the mounting surface side.

  In addition, as shown in FIG. 4, a gap 80 is provided on at least a part of the boundary surface 42c between the first outer outer layer portion 42a and the first inner outer layer portion 42b. As a result, in the present invention, even if the multilayer ceramic capacitor 10 is cracked due to the deflection of the substrate, the stress can be concentrated in the gap 80 and the crack can be extended along the gap 80. Therefore, it is possible to suppress the crack from reaching the facing portion 18. Therefore, even if a crack occurs, the characteristics of the capacitor can be maintained. Since the reinforcing layer is not provided as in Patent Document 1 aiming at the same effect, the problem of the cost increase by providing the reinforcing layer, the problem of the capacity reduction by thickening the ineffective layer by the provision of the reinforcing layer, Further, it is possible to suppress the problem of slight displacement of the capacitance due to the stray capacitance generated between the effective layer and the reinforcing layer.

  As shown in FIG. 5, the gap 80 is disposed in the vicinity of each end of the first internal electrode layer 16 a and the second internal electrode layer 16 b when viewed from the stacking direction x. Reference numeral 80 denotes a first gap portion 80a arranged on the first side surface 12c side, a second gap portion 80b arranged on the second side surface 12d side, and a lead portion 20a of the first internal electrode layer 16a. It is preferable to have a third gap portion 80c disposed on the opposite side of the second internal electrode layer 16b and a fourth gap portion 80d disposed on the opposite side of the lead portion 20b of the second internal electrode layer 16b. Thereby, the stress can be reliably concentrated in the gap 80 around the internal electrode layer 16 where the stress tends to concentrate. As a result, since the crack can be extended along the gap portion 80, it is possible to suppress the crack from reaching the facing portion 18.

  The first gap 80a is preferably formed on the first side face 12c side so as to extend from the first end face 12e to the second end face 12f, and the second gap 80b The second side surface 12d is preferably formed so as to extend from the first end surface 12e to the second end surface 12f. Thereby, the stress can be reliably concentrated in the gap 80 around the internal electrode layer 16 where the stress tends to concentrate. As a result, since the crack can be extended along the gap portion 80, it is possible to suppress the crack from reaching the facing portion 18.

  More preferably, the first gap portion 80a and the second gap portion 80b are provided so as not to overlap the first internal electrode layer 16a and the second internal electrode layer 16b when viewed from the stacking direction x. The third gap portion 80c is preferably provided so as not to overlap the second internal electrode layer 16b, and the fourth gap portion 80d is provided in the first internal electrode layer 16a. It is preferable that it is provided so that it may not overlap. As a result, stress can be concentrated and cracks can be extended so that the first internal electrode layer 16a and the second internal electrode layer 16b are not applied to the facing portion 18 facing each other, so that the crack reaches the facing portion 18. This can be reliably suppressed.

  Further, the first gap 80a, the second gap 80b, the third gap 80c, and the fourth gap 80d may partially have gaps. In that case, it is preferably provided in the vicinity of the external electrode layer 24 disposed on at least the first main surface 12a and the second main surface 12b, and on the first side surface 12c and the second side surface 12d. More preferably, the first gap 80a, the second gap 80b, the third gap 80c, and the fourth gap 80d are continuously formed along the edge of the internal electrode layer 16. It is preferable. Thereby, the effect of this invention can be acquired more reliably.

  As shown in FIG. 6B, the stacked body 12 is located on the first side surface 12c side, the first side surface 12c, the outermost surface 70a of the inner layer portion 40 on the first side surface 12c side, and the length direction. a first side surface-side outer layer portion 50 formed of a plurality of dielectric layers 14 positioned between the outermost surface 70a and a straight line along z, and the second side surface 12d side, The first dielectric layer 14 is formed by a plurality of dielectric layers 14 positioned between the outermost surface 70b of the inner layer portion 40 on the side surface 12d and the second side surface 12d side and a straight line of the outermost surface 70b along the length direction z. 2 side surface side outer layer portions 52. Note that there is no gap in the first side surface side outer layer portion 50 and the second side surface side outer layer portion 52.

  As shown in FIG. 6A, the laminate 12 includes a second end surface 12f located on the opposite side of the lead portion 20a of the first internal electrode layer, and an inner layer portion 40 on the second end surface 12f side. The first end face side outer layer portion 60 formed from the plurality of dielectric layers 14 located between the first end face 12e and the second inner electrode layer on the opposite side to the lead portion 20b. And a second end face side outer layer part 62 formed from a plurality of dielectric layers 14 positioned between the inner layer part 40 on the first end face 12e side. Note that there is no gap in the first end surface side outer layer portion 60 and the second end surface side outer layer portion 62.

  When the elastic modulus of each pre-fired dielectric sheet constituting the first inner outer layer portion 42b is C2, and the elastic modulus of each pre-fired dielectric sheet constituting the first outer outer layer portion 42a is C1, C2 / C1 is preferably 1.20 or more and 1.80 or less. When C2 / C1 is less than 1.20, the elastic modulus C2 of the first inner outer layer portion 42b is small, and the elastic modulus C1 of the first outer outer layer portion 42a is large. In this case, although the first inner outer layer portion 42b follows the step of the internal electrode layer 16, the first outer outer layer portion 42a hardly follows, and the first outer outer layer portion 42a and the first inner outer layer portion 42b The entire surface of the outer layer is peeled off due to the excessive decrease in the adhesive strength of the laminated ceramic capacitor, and the function as the multilayer ceramic capacitor 10 cannot be maintained. On the other hand, when C2 / C1 is larger than 1.80, the first outer outer layer portion 42a sufficiently follows the two irregularities of the first inner outer layer portion 42b, and the adhesion force is increased. The gap 80 cannot be formed between the first outer outer layer portion 42a and the first inner outer layer portion 42b.

(Internal electrode layer 16)
The plurality of internal electrode layers 16 are disposed on the plurality of dielectric layers 14 and include a first internal electrode layer 16a and a second internal electrode layer 16b. The first internal electrode layers 16a and the second internal electrode layers 16b are alternately stacked.

The first internal electrode layer 16a includes a first facing portion 18a facing each other, and a first lead portion 20a extending from the first facing portion 18a to the first end surface 12e of the stacked body 12.
The second internal electrode layer 16b includes a second facing portion 18b facing each other and a second lead portion 20b extending from the second facing portion 18b to the second end face 12f of the stacked body 12.
The facing portion 18 includes a plurality of first facing portions 18a and a plurality of second facing portions 18b.

  In the present embodiment, the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b face each other with the dielectric layer 14 therebetween, thereby increasing the capacitance. Is formed. Thereby, it functions as the multilayer ceramic capacitor 10.

  The first internal electrode layer 16a and the second internal electrode layer 16b contain, for example, a metal such as Ni, Cu, Ag, Pd, an Ag—Pd alloy, or Au. Of these, Ni is preferable.

  The number of the first internal electrode layers 16a and the second internal electrode layers 16b is not particularly limited.

  The thicknesses of the first internal electrode layer 16a and the second internal electrode layer 16b are preferably 0.2 μm or more and 2.0 μm or less, for example.

(External electrode layer 24)
The external electrode layer 24 includes a first external electrode layer 24a disposed on the first end surface 12e of the multilayer body 12, and a second external electrode layer 24b disposed on the second end surface 12f of the multilayer body 12. And having.

  The first external electrode layer 24 a and the second external electrode layer 24 b include a base electrode layer 26 and a plating layer 28 disposed on the base electrode layer 26.

(1) Base electrode layer 26
The base electrode layer 26 includes a first base electrode layer 26a and a second base electrode layer 26b.

The first base electrode layer 26a covers the first end surface 12e of the multilayer body 12, and reaches the first main surface 12a and the second main surface 12b, and the first side surface 12c and the second side surface 12d. Is provided. However, the first base electrode layer 26a may be disposed only on the first end face 12e.
The second base electrode layer 26b covers the second end surface 12f of the multilayer body 12 and reaches the first main surface 12a and the second main surface 12b, and the first side surface 12c and the second side surface 12d. Is provided. However, the second base electrode layer 26b may be disposed only on the second end face 12f.

  The base electrode layer 26 includes at least one selected from a baking layer, a thin film layer, and the like.

  The baking layer includes glass and metal. The glass contains at least one selected from B, Si, Ba, Mg, Al, Li and the like. Moreover, you may use the same kind of ceramic material as the dielectric material layer 14 instead of glass.

  Examples of the metal of the baking layer include at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

  The baking layer is obtained by applying a conductive paste containing glass and metal to the laminate 12 and baking it. The baking layer may be fired at the same time as the internal electrode layer 16, or may be burned after baking the internal electrode layer 16. . Moreover, you may use the same kind of ceramic material as the dielectric material layer 14 instead of glass.

  The thickness (the thickest part) of the baking layer is preferably 5 μm or more and 150 μm or less. The baking layer may be formed of a plurality of layers.

  The thin film layer is a layer of 1 μm or less formed by a thin film forming method such as a sputtering method or a vapor deposition method and deposited with metal particles.

(2) Plating layer 28
The plating layer 28 includes a first plating layer 28a and a second plating layer 28b.

  A first plating layer 28a is formed on the first base electrode layer 26a. Specifically, the first plating layer 28a is disposed on the first end surface 12e on the first base electrode layer 26a, and the first main surface 12a and the second main surface 12a on the first base electrode layer 26a. The main surface 12b is preferably provided so as to reach the first side surface 12c and the second side surface 12d. However, the first plating layer 28a may be disposed only on the first end face 12e on the first base electrode layer 26a.

  A second plating layer 28b is formed on the second base electrode layer 26b. Specifically, the second plating layer 28b is disposed on the second end face 12f on the second base electrode layer 26b, and the first main surface 12a and the second main surface 12a on the second base electrode layer 26b. The main surface 12b is preferably provided so as to reach the first side surface 12c and the second side surface 12d. However, the second plating layer 28b may be disposed only on the second end face 12f on the second base electrode layer 26b.

  The plating layer 28 preferably includes at least one metal or alloy selected from, for example, Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

  The plating layer 28 may be formed of a plurality of layers. It is preferable to be formed by a two-layer structure of a Ni plating layer and a Sn plating layer. The Ni plating layer can prevent the base electrode layer 26 from being eroded by solder when the multilayer ceramic capacitor 10 is mounted, and the Sn plating layer provides solder wettability when mounting the multilayer ceramic capacitor 10. It can be improved and mounted easily.

  The thickness per layer of the plating layer 28 is preferably 1 μm or more and 15 μm or less.

<When providing the plating layer 28 without providing the base electrode layer 26>
The case where the plating layer 28 is provided without providing the base electrode layer 26 will be described.
Each of the first external electrode layer 24a and the second external electrode layer 24b is directly formed on the surface of the multilayer body 12, and is electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. The structure including the plating layer 28 to be connected may be used.

  In such a case, the plating layer 28 may be formed after disposing the catalyst on the surface of the laminate 12 as a pretreatment.

  The plating layer 28 preferably includes a lower plating layer formed on the surface of the laminate 12 and an upper plating layer formed on the surface of the lower plating layer.

  Each of the lower plating layer and the upper plating layer preferably includes at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing the metal. .

  The lower plating layer is preferably formed using Ni having solder barrier performance, and the upper plating layer is preferably formed using Sn or Au having good solder wettability.

  Further, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, the lower plating layer is preferably formed using Cu having good bonding properties with Ni. . The upper plating layer may be formed as necessary, and each of the first external electrode layer 24a and the second external electrode layer 24b may be formed of only the lower plating layer.

  The upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.

  The thickness of each of the upper plating layer and the lower plating layer is preferably 1 μm or more and 15 μm or less. The upper plating layer and the lower plating layer preferably do not contain glass. The metal ratio per unit volume of the upper plating layer and the lower plating layer is preferably 99% by volume or more.

The dimensions of the length direction z of the laminated ceramic capacitor 10 includes a layered body 12 and the outer electrode layer 24 to L _M dimensions. L _M size is preferably 0.2mm or more 6.0mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode layer 24 is defined as a _TM dimension. T _M size is preferably 0.1mm or more 5.5mm or less. The dimension in the width direction y of the multilayer ceramic capacitor 10 includes a layered body 12 and the outer electrode layer 24 and W _M dimensions. W _M size is preferably 0.1mm or more 3.2mm or less.

(effect)
The multilayer ceramic capacitor 10 according to the present invention has a gap 80 in at least a part of the boundary surface 42c between the first outer outer layer portion 42a and the first inner outer layer portion 42b, so that the substrate is bent. Thus, even if the multilayer ceramic capacitor 10 is cracked, stress can be concentrated in the gap 80 and the crack can be extended along the gap 80, so that the crack reaches the facing portion 18. Can be suppressed. Therefore, even if a crack occurs, the characteristics of the capacitor can be maintained. Since the reinforcing layer is not provided as in Patent Document 1 aiming at the same effect, the problem of the cost increase by providing the reinforcing layer, the problem of the capacity reduction by thickening the ineffective layer by the provision of the reinforcing layer, Further, it is possible to suppress the problem of slight displacement of the capacitance due to the stray capacitance generated between the effective layer and the reinforcing layer.

  Further, the gap 80 of the multilayer ceramic capacitor 10 according to the present invention is disposed in the vicinity of the respective end portions of the first internal electrode layer 16a and the second internal electrode layer 16b when viewed from the stacking direction x. The gap portion 80 includes a first gap portion 80a disposed on the first side surface 12c side, a second gap portion 80b disposed on the second side surface 12d side, and the first internal electrode layer 16a. A third gap portion 80c disposed on the opposite side of the lead portion 20a, and a fourth gap portion 80d disposed on the opposite side of the lead portion 20b of the second internal electrode layer 16b. Is preferred. Thereby, the stress can be reliably concentrated in the gap 80 around the internal electrode layer 16 where the stress tends to concentrate. As a result, since the crack can be extended along the gap portion 80, it is possible to suppress the crack from reaching the facing portion 18.

  In addition, the multilayer ceramic capacitor 10 according to the present invention has the elastic modulus of each pre-firing dielectric sheet constituting the first inner outer layer portion 42b as C2, and each pre-firing dielectric constituting the first outer outer layer portion 42a. When the elastic modulus of the body sheet is C1, C2 / C1 is preferably 1.20 or more and 1.80 or less. When C2 / C1 is less than 1.20, the elastic modulus C2 of the first inner outer layer portion 42b is small, and the elastic modulus C1 of the first outer outer layer portion 42a is large. In this case, although the first inner outer layer portion 42b follows the step of the internal electrode layer 16, the first outer outer layer portion 42a hardly follows, and the first outer outer layer portion 42a and the first inner outer layer portion 42b As a result, the entire outer layer is peeled off due to an excessive decrease in the adhesive strength, and the function as a multilayer ceramic capacitor cannot be maintained. On the other hand, when C2 / C1 is larger than 1.80, the first outer outer layer portion 42a sufficiently follows the two irregularities of the first inner outer layer portion 42b, and the adhesion force is increased. The gap 80 cannot be formed between the first outer outer layer portion 42a and the first inner outer layer portion 42b.

2. Manufacturing Method of Multilayer Ceramic Capacitor Next, a manufacturing method of the multilayer ceramic capacitor 10 according to the present invention will be described with reference to FIG. FIG. 7 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10 according to the present invention.

First, a dielectric sheet and a conductive paste for internal electrode layers are prepared (S01). For example, various subcomponent raw material powders are weighed so as to have a predetermined mixing ratio with respect to main component raw material powders such as BaTiO ₃ and (Ca, Sr) (Zr, Ti) O _3, and the like. Wet mix using Subsequently, the obtained mixture is dried and crushed to obtain a raw material powder.

  Next, for example, a polyvinyl butyral binder and toluene and ethanol as solvents are added to 100 weight of the obtained raw material powder, and wet mixed by a ball mill to prepare a ceramic slurry. The obtained ceramic slurry is formed into a sheet by a lip coater or the like to obtain a ceramic green sheet (S02). The conductive paste for the dielectric sheet and the internal electrode layer contains a binder and a solvent, but a known organic binder or organic solvent can be used. At this time, the first outer outer layer portion 42a and the first inner outer layer portion 42b have different binder specifications. The difference in binder specifications can be obtained, for example, by using polyvinyl butyral having a different degree of polymerization or changing the ratio of the binder and the plasticizer. As the binder, for example, polyvinyl butyral, phthalate, or polyvinyl alcohol binders can be used. As the plasticizer, for example, phthalic acid ester, adipic acid ester, phosphoric acid ester, glycols and the like can be used. Specifically, control is performed as follows.

  Binder / plasticizer ratio, which is the ratio of the binder used for the pre-fired dielectric layer used for the first inner outer layer portion 42b and the plasticizer used for the pre-fired dielectric layer used for the first inner outer layer portion 42b. The ratio is adjusted in the range of 3.1 to 4.2. Binder / plasticizer ratio, which is the ratio of the binder used for the pre-fired dielectric layer used for the first outer outer layer portion 42a and the plasticizer used for the pre-fired dielectric layer used for the first outer outer layer portion 42a. The ratio is adjusted in the range of 2.6 to 3.1. Thereby, the deformation of the first outer outer layer portion 42a does not sufficiently follow the deformation of the first inner outer layer portion 42b at the time of pressing, and between the first inner outer layer portion 42b and the first outer outer layer portion 42a. In addition, the gap 80 can be formed in the first outer outer layer portion 42b, and the deformation of the first outer outer layer portion 42a to the deformation of the first inner outer layer portion 42b is too small to cause peeling of the entire outer layer.

  Next, the conductive paste for the internal electrode layer is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing to form an internal electrode pattern (S03).

  Next, a laminate sheet is obtained by the following method (S04). A predetermined number of outer-layer dielectric sheets prepared as described above, which will be the first outer outer layer portion 42a, on which no internal electrode pattern is printed, are laminated, and the outer layer prepared above as the first inner outer layer portion 42b. A predetermined number of dielectric sheets are laminated. Further, dielectric sheets on which internal electrode patterns are printed are sequentially laminated thereon. Then, a predetermined number of outer layer dielectric sheets to be the second outer layer portion 44 on which the internal electrode pattern is not printed are laminated.

  Next, the laminated sheet is pressed in the laminating direction x by means such as isostatic pressing to produce a laminated block (S05).

  Next, the laminated block is cut into a predetermined size, and the laminated chip is cut out (S06). At this time, the corners and ridges of the multilayer chip may be rounded by barrel polishing or the like.

  Next, the multilayer chip is fired to produce a multilayer body (S07). Although the firing temperature depends on the material of the dielectric layer 14 and the internal electrode layer 16, it is preferably 900 ° C. or higher and 1300 ° C. or lower.

  Next, the external electrode layer 24 is formed on the laminate (S08). A baking layer may be formed, and the plating layer 28 may be formed on the surface of the baking layer. Moreover, you may form the plating layer 28 directly on the surface of a laminated body, without providing a baking layer.

<When providing a baking layer>
A conductive paste for an external electrode layer is applied to both end faces of the laminate 12 and baked to form a baked layer of the external electrode layer 24. The baking temperature is preferably 700 ° C. or higher and 900 ° C. or lower.
If necessary, the surface of the baking layer is plated.

<When providing the plating layer 28 without providing a baking layer>
A plating process is performed on both end faces of the laminate 12 to form a plating layer on the exposed portion of the internal electrode layer 16. In performing the plating treatment, either electrolytic plating or electroless plating may be employed, but it is usually preferable to employ electrolytic plating. As the plating method, barrel plating is preferably used.
When forming the surface conductor, the surface conductor pattern may be printed in advance on the ceramic green sheet of the outermost layer and fired simultaneously with the laminate 12, or the first main body of the laminate after firing may be used. A surface conductor may be printed on the surface 12a and the second main surface 12b and then baked. Then, a plating layer is formed on the surface of the plating layer 28 as necessary.

  As described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

(effect)
Binder / plasticizer ratio, which is the ratio of the binder used for the pre-fired dielectric layer used for the first inner outer layer portion 42b and the plasticizer used for the pre-fired dielectric layer used for the first inner outer layer portion 42b. The binder is used for the pre-fired dielectric layer used for the first outer outer layer part 42a, and the pre-fired dielectric used for the first outer outer layer part 42a, with the ratio adjusted in the range of 3.1 to 4.2. The binder / plasticizer ratio, which is the ratio to the plasticizer used in the layer, is adjusted in the range of 2.6 to 3.1. Thereby, the deformation of the first outer outer layer portion 42a does not sufficiently follow the deformation of the first inner outer layer portion 42b at the time of pressing, and between the first inner outer layer portion 42b and the first outer outer layer portion 42a. In addition, the gap 80 can be formed in the first outer outer layer portion 42b, and the deformation of the first outer outer layer portion 42a to the deformation of the first inner outer layer portion 42b is too small to cause peeling of the entire outer layer.

3. Modified Example A modified example of the present invention will be described with reference to FIGS. As shown in FIG. 9, the multilayer ceramic capacitor 10 </ b> A is provided with a gap 80 in the first outer layer portion 42 and the second outer layer portion 44. Thus, mounting is possible not only on the first main surface 12a but also on the second main surface 12b. The same parts as those of the multilayer ceramic capacitor 10 according to the embodiment of the present invention described above are denoted by the same reference numerals, and the same description will not be repeated.

(Multilayer ceramic capacitor 10A)
A multilayer ceramic capacitor 10A according to the present invention will be described with reference to FIGS. FIG. 8 is an external perspective view showing a modification of the multilayer ceramic capacitor according to the present invention. FIG. 9 is a cross-sectional view taken along the line IX-IX of FIG. 8 showing a modification of the multilayer ceramic capacitor according to the present invention. FIG. 10 is a cross-sectional view taken along line XX of FIG. 8 showing a modification of the multilayer ceramic capacitor according to the present invention. FIG. 11 is an enlarged view of part B of FIG. 10 showing a modification of the multilayer ceramic capacitor according to the present invention. FIG. 12A is an LW cross-sectional view of the stacked body in a case where the location of the gap is transmitted. FIG. 12B is a WT cross-sectional view of the stacked body in the case where the location of the gap is transmitted.

  As shown in FIG. 11, the second outer layer portion 44 is divided into two regions and is located closest to the second main surface 12 b among the plurality of dielectric layers 14 constituting the second outer layer portion 44. A plurality of second outer outer layer portions 44 a made up of a plurality of dielectric layers 14 including the dielectric layer 14 and a plurality of second outer layer portions 44 located between the second outer outer layer portion 44 a and the inner layer portion 40. And a second inner outer layer portion 44b made of the dielectric layer 14.

  As shown in FIG. 11, a gap 80 is provided at least at a part of the boundary surface 44c between the second outer outer layer portion 44a and the second inner outer layer portion 44b. Thereby, not only the effect of the first outer layer portion 42 described above, but also the first outer outer layer portion 42a and the second outer outer layer portion 44a are connected to both the first outer layer portion 42 and the second outer layer portion 44. The first inner outer layer portion 42b and the second inner outer layer portion 44b can be provided, and mounting is possible not only on the first main surface 12a but also on the second main surface 12b.

12A and 12B, the length in the stacking direction x connecting the first main surface 12a and the second main surface 12b of the stacked body 12 is T, The length in the width direction y connecting the first side surface 12c and the second side surface 12d is W, and the length in the length direction z connecting the first end surface 12e and the second end surface 12f of the laminate 12 is L, The width of the first side surface side outer layer portion 50 is W1, the width of the second side surface side outer layer portion 52 is W2, the width of the first end surface side outer layer portion 60 is L1, and the width of the second end surface side outer layer portion 62 is L2, the thickness of the first outer layer portion 42 is T1, the thickness of the second outer layer portion 44 is T2, the width of the first gap portion 80a disposed on the first side surface 12c side is Wd1, and the second side surface The width of the second gap portion 80b arranged on the side is Wd2, and the width of the second gap portion 80b arranged on the side opposite to the lead portion 20a of the first internal electrode layer 16a is The width of the first gap portion 80c is Ld1, the width of the fourth gap portion 80d disposed on the opposite side of the lead portion 20b of the second internal electrode layer 16b is Ld2, and the first gap in the first outer layer portion 42 is Ld2. The thickness of the portion 80a, the second gap portion 80b, the third gap portion 80c, and the fourth gap portion 80d is Td1, and the first gap portion 80a, the second gap portion 80b, and the second gap portion 80b in the second outer layer portion 44 When the thickness of the third gap portion 80c and the fourth gap portion 80d is Td2,
0.05 × W1 or W2 ≦ Wd1 or Wd2 ≦ 0.85 × W1 or W2
0.05 × L1 or L2 ≦ Ld1 or Ld2 ≦ 0.85 × L1 or L2
0.04 × T1 or T2 ≦ Td1 or Td2 ≦ 0.85 × T1 or T2
It is preferable to satisfy. As a result, the effects of the present invention can be obtained more reliably.

  Further, when the elastic modulus of each pre-fired dielectric sheet constituting the second inner outer layer portion 44b is D2, and the elastic modulus of each pre-fired dielectric sheet constituting the second outer outer layer portion 44a is D1. D2 / D1 is preferably 1.20 or more and 1.80 or less. When D2 / D1 is less than 1.20, the elastic modulus D2 of the second inner outer layer portion 44b is small, and the elastic modulus D1 of the second outer outer layer portion 44a is large. In this case, although the second inner outer layer portion 44b follows the step of the internal electrode layer 16, the second outer outer layer portion 44a hardly follows, and the second outer outer layer portion 44a and the second inner outer layer portion 44b As a result, the entire outer layer is peeled off due to an excessive decrease in the adhesive strength, and the function as a multilayer ceramic capacitor cannot be maintained. On the other hand, when D2 / D1 is larger than 1.80, the second outer outer layer portion 44a sufficiently follows the two irregularities of the second inner outer layer portion 44b, and the adhesion force becomes large. The gap 80 cannot be formed between the second outer outer layer portion 44a and the second inner outer layer portion 44b.

(Manufacturing method of multilayer ceramic capacitor 10A)
Next, a manufacturing method of the multilayer ceramic capacitor 10A according to the present invention will be described with reference to FIG. FIG. 13 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10A according to the present invention.

The multilayer ceramic capacitor 10A includes the following steps as step S02 ′ between step S02 and step S03 in FIG.
That is, the binder / plasticity is the ratio of the binder used for the pre-fired dielectric layer used for the second inner outer layer portion 44b and the plasticizer used for the pre-fired dielectric layer used for the second inner outer layer portion 44b. The ratio of the agent is adjusted in the range of 3.1 to 4.2. Binder / plasticizer ratio that is the ratio of the binder used for the pre-fired dielectric layer used for the second outer outer layer portion 44a and the plasticizer used for the pre-fired dielectric layer used for the second outer outer layer portion 44a. The ratio is adjusted in the range of 2.6 to 3.1. Thereby, the deformation of the second outer outer layer portion 44a does not sufficiently follow the deformation of the second inner outer layer portion 44b at the time of pressing, and between the second inner outer layer portion 44b and the second outer outer layer portion 44a. The gap portion 80 can be formed, and the deformation following the second outer outer layer portion 44a to the deformation of the second inner outer layer portion 44b is too small so that the entire outer layer is not peeled off.

Furthermore, the process of obtaining the lamination sheet of process S04 of FIG. 7 is provided with the following processes.
A predetermined number of outer dielectric sheets serving as the first outer outer layer portion 42a without the internal electrode pattern printed thereon are stacked, and a predetermined number of outer dielectric sheets serving as the first inner outer layer portion 42b are formed thereon. Laminate. Further, dielectric sheets on which internal electrode patterns are printed are sequentially laminated thereon. Then, a predetermined number of outer-layer dielectric sheets serving as the second inner outer layer portion 44b on which the internal electrode pattern is not printed are laminated, and further on the outer layer dielectric layer serving as the second outer outer layer portion 44a. A predetermined number of dielectric sheets are laminated. As a result, both the first outer layer portion 42 and the second outer layer portion 44 have the first outer outer layer portion 42a, the second outer outer layer portion 44a, the first inner outer layer portion 42b, and the second inner outer layer portion. 44b and can be mounted not only on the first main surface 12a but also on the second main surface 12b.

4). Experimental Example A multilayer ceramic capacitor 10A was produced according to the method described above. In addition, although the sample used for the experimental example is the multilayer ceramic capacitor 10A, the mounting surface side has the same configuration as the multilayer ceramic capacitor 10.

(1) Multilayer ceramic capacitor used in Examples 1 to 22 (a) Size (design value, including external electrode layer): L _M × W _M × T _M = 2.00 mm × 1.25 mm × 1.25 mm
(B) Ceramic material: CrZrO ₃ system (c) Capacitance: 100 nF
(D) Rated voltage: 50V
(E) Structure of external electrode layer (i) Material of base electrode layer: electrode containing Cu and glass
Base electrode layer thickness: 60 μm (end face center)
(Ii) Plating layer
First plating layer Ni: 3 μm
Second plating layer Sn: 3 μm
(F) Structure of internal electrode layer (i) Material of internal electrode layer: Ni
(Ii) Inner outer layer portion and outer outer layer portion: A polyvinyl butyral binder, toluene, and ethanol were added to the raw material powder, and wet mixed by a ball mill to prepare a ceramic slurry. The first outer outer layer portion 42a and the second outer outer layer portion 44a and the first inner outer layer portion 42b and the second inner outer layer portion 44b have different binder specifications. The difference in binder specifications was obtained by changing the ratio of binder to plasticizer. The elastic modulus of the first outer outer layer part 42a is C1, the elastic modulus of the second outer outer layer part 44a is D1, the elastic modulus of the first inner outer layer part 42b is C2, and the elastic modulus of the second inner outer layer part 44b is The specification was adjusted to satisfy 1.20 ≦ C2 / C1 and D2 / D1 ≦ 1.80 when D2. Specifically, it is shown in Table 1.
(G) Details of the gap: listed in Table 1

(2) Multilayer ceramic capacitor used in Comparative Example 1 (a) Size (design value, including external electrode layer): L _M × W _M × T _M = 2.00 mm × 1.25 mm × 1.25 mm
(B) Ceramic material: CrZrO ₃ system (c) Capacitance: 100 nF
(D) Rated voltage: 50V
(E) Structure of external electrode layer (i) Material of base electrode layer: electrode containing Cu and glass
Base electrode layer thickness: 60 μm (end face center)
(Ii) Plating layer
First plating layer Ni: 3 μm
Second plating layer Sn: 3 μm
(F) Structure of internal electrode layer (i) Material of internal electrode layer: Ni
(Ii) Inner outer layer portion and outer outer layer portion: A polyvinyl butyral binder, toluene, and ethanol were added to the raw material powder, and wet mixed by a ball mill to prepare a ceramic slurry. The outer outer layer portion and the inner outer layer portion have different binder specifications. The difference in binder specifications was obtained by changing the ratio of binder to plasticizer. The elastic modulus of the first outer outer layer part 42a is C1, the elastic modulus of the second outer outer layer part 44a is D1, the elastic modulus of the first inner outer layer part 42b is C2, and the elastic modulus of the second inner outer layer part 44b is The specification was adjusted so that 1.20 ≦ C2 / C1 and D2 / D1 ≦ 1.80 were not satisfied when D2. Specifically, the binder of the first inner outer layer portion 42b and the second inner outer layer portion 44b with respect to the binder / plasticizer ratio 4.2 of the first outer outer layer portion 42a and the second outer outer layer portion 44a. / Adjusted by using a plasticizer ratio of 2.6.
(G) Details of the gap: listed in Table 1

(3) Multilayer ceramic capacitor used in Comparative Example 2 (a) Size (design value, including external electrode layer): L _M × W _M × T _M = 2.00 mm × 1.25 mm × 1.25 mm
(B) Ceramic material: CrZrO ₃ system (c) Capacitance: 100 nF
(D) Rated voltage: 50V
(E) Structure of external electrode layer (i) Material of base electrode layer: electrode containing Cu and glass
Base electrode layer thickness: 60 μm (end face center)
(Ii) Plating layer
First plating layer Ni: 3 μm
Second plating layer Sn: 3 μm
(F) Structure of internal electrode layer (i) Material of internal electrode layer: Ni
(Ii) Inner outer layer portion and outer outer layer portion: A polyvinyl butyral binder, toluene, and ethanol were added to the raw material powder, and wet mixed by a ball mill to prepare a ceramic slurry. The outer outer layer portion and the inner outer layer portion have different binder specifications. The difference in binder specifications was obtained by changing the ratio of binder to plasticizer. The elastic modulus of the first outer outer layer part 42a is C1, the elastic modulus of the second outer outer layer part 44a is D1, the elastic modulus of the first inner outer layer part 42b is C2, and the elastic modulus of the second inner outer layer part 44b is The specification was adjusted so that 1.20 ≦ C2 / C1 and D2 / D1 ≦ 1.80 were not satisfied when D2. Specifically, the binder of the first inner outer layer portion 42b and the second inner outer layer portion 44b with respect to the binder / plasticizer ratio 1.1 of the first outer outer layer portion 42a and the second outer outer layer portion 44a. The ratio was adjusted by using a plasticizer ratio of 4.2.
(G) No gap

  About these obtained samples, the measurement and the test were performed according to the measurement method of the following W void, L void, and T void and the substrate bending test method.

(A) Method for measuring W gap (Wd1 and Wd2) The confirmation of the W gap was performed from the WT surface side using a metal microscope or a scanning electron microscope. The observation surface is a first end surface portion 12e where the first lead portion 20a of the first internal electrode layer 16a is present or a second end face portion where the second lead portion 20b of the second internal electrode layer 16b is present. The measurement was performed at three points, 12f, 1 / 2L, and the end opposite to the first lead 20a of the first internal electrode layer 16a or the second lead 20b of the second internal electrode layer 16b. Two points other than the surface were exposed by precision polishing from the WT surface side.

(B) Measuring method of L space | gap (Ld1 and Ld2) Confirmation of L space | gap was performed using the metal microscope and the scanning electron microscope from the LT surface side. The observation surface was measured at two points, that is, a point where the W end of the internal electrode layer 16 started to appear and a 1 / 2W point. Both points were exposed by precision polishing from the LT surface side.

(C) Method for measuring T gap (Td1 and Td2) The T gap was confirmed from the WT surface side using a metal microscope or a scanning electron microscope. The observation surface is a first end surface portion 12e where the first lead portion 20a of the first internal electrode layer 16a is present or a second end face portion where the second lead portion 20b of the second internal electrode layer 16b is present. The measurement was performed at three points, 12f, 1 / 2L, and the end opposite to the first lead 20a of the first internal electrode layer 16a or the second lead 20b of the second internal electrode layer 16b. Two points other than the surface were exposed by precision polishing from the WT surface side.

(D) Substrate bending test method The produced multilayer ceramic capacitor 10A was reflow mounted on a substrate for substrate bending test made of glass cloth base epoxy resin using Sn-3Ag-0.5Cu lead-free solder. The test conditions were: test head speed: 1.0 mm / s, deflection amount: 10 mm, holding time: 5 ± 1 s, test quantity: 100 pieces. The appearance of cracks was observed by appearance inspection and cross-sectional polishing.

  The values in Table 1 show the results of measurement of the W gap, L gap, and T gap and the substrate bending test.

  As shown in Table 1, the value of W void / W1 or W2 is 0.05 to 0.85, the value of L void / L1 is 0.05 to 0.85, and T void / When the value of T1 was 0.04 or more and 0.85 or less, the ratio of the multilayer ceramic capacitor in which the crack reached the internal electrode layer 16 in the substrate bending test was 0%.

  Further, the value of W void / W1 or W2 is smaller than 0.05 or larger than 0.85, the value of L void / L1 is 0.05 or more and 0.85 or less, and the value of T void / T1 is In the case of 0.04 or more and 0.85 or less, the value of W gap / W1 or W2 is 0.05 or more and 0.85 or less, and the value of L gap / L1 is smaller than 0.05 or larger than 0.85 And, when the value of T gap / T1 or T gap / T2 is 0.04 or more and 0.85 or less, the value of W gap / W1 or W2 is 0.05 or more and 0.85 or less, and L gap / L1 When the value is 0.05 or more and 0.85 or less and the value of T gap / T1 is smaller than 0.04 or larger than 0.85, the multilayer ceramic in which cracks reach the internal electrode layer 16 in the substrate bending test The percentage of capacitors was 5%

  Also, when the elastic modulus of each pre-fired dielectric sheet constituting the first inner outer layer portion 42b is C2, and the elastic modulus of each pre-fired dielectric sheet constituting the first outer outer layer portion 42a is C1. C2 / C1 is 1.20 or more and 1.80 or less, the elastic modulus of each pre-fired dielectric sheet constituting the second inner outer layer portion 44b is D2, and each of the second outer outer layer portions 44a is constituted. When the elastic modulus of the pre-fired dielectric sheet is D1, when D2 / D1 is 1.20 or more and 1.80 or less, the ratio of the multilayer ceramic capacitor in which the crack reaches the internal electrode layer 16 in the substrate bending test is 10 %Met.

  Furthermore, the binder used for the pre-firing dielectric layer used for the first inner outer layer portion 42b and the second inner outer layer portion 44b, and the pre-firing used for the first inner outer layer portion 42b and the second inner outer layer portion 44b. The binder / plasticizer ratio, which is the plasticizer ratio used for the dielectric layer, is adjusted within the range of 3.1 to 4.2, and is used for the first outer outer layer portion 42a and the second outer outer layer portion 44a. The binder / plasticizer ratio, which is the plasticizer ratio used for the binder used for the pre-fired dielectric layer and the pre-fired dielectric layer used for the first outer outer layer portion 42a and the second outer outer layer portion 44a, is 2. When adjusted in the range of 6 or more and 3.1 or less, the ratio of the multilayer ceramic capacitor in which the crack reached the internal electrode layer 16 in the substrate bending test was 5%.

  In Comparative Example 1, the first outer outer layer portion 42a and the second outer outer layer portion 44a cannot be in close contact with the deformation of the first inner outer layer portion 42b and the second inner outer layer portion 44b. Separation of the entire surface occurred between the first inner outer layer portion 42b and the second inner outer layer portion 44b and the first outer outer layer portion 42a and the second outer outer layer portion 44a, and the gap portion 80 was not formed.

  Further, in Comparative Example 2, since there was no gap and no gap 80 was formed, 87 out of 100 cracks reached the internal electrode layer 16.

From the above results, in the present invention, even when the multilayer ceramic capacitor 10A is cracked due to the deflection of the substrate, the stress is concentrated in the gap 80 and the crack is extended along the gap 80. Therefore, it is possible to suppress the crack from reaching the facing portion 18.
Therefore, even if a crack occurs, the characteristics of the capacitor can be maintained.

  In addition, this invention is not limited to the said embodiment, In the range of the summary, it changes variously.

DESCRIPTION OF SYMBOLS 10, 10A Multilayer ceramic capacitor 12 Laminated body 12a 1st main surface 12b 2nd main surface 12c 1st side surface 12d 2nd side surface 12e 1st end surface 12f 2nd end surface 14 Dielectric layer 16 Internal electrode layer 16a 1st internal electrode layer 16b 2nd internal electrode layer 18 Opposition part 18a 1st opposition part 18b 2nd opposition part 20a 1st extraction part 20b 2nd extraction part 24 External electrode layer 24a 1st external electrode Layer 24b second external electrode layer 26 ground electrode layer 26a first ground electrode layer 26b second ground electrode layer 28 plating layer 28a first plating layer 28b second plating layer 40 inner layer portion 42 first outer layer portion 42a First outer outer layer portion 42b First inner outer layer portion 42c Interface between the first outer outer layer portion and the first inner outer layer portion 44 Second outer layer portion 44a Second outer outer layer 44b Second inner outer layer portion 44c Boundary surface between the second outer outer layer portion and the second inner outer layer portion 50 First side surface outer layer portion 52 Second side surface side outer layer portion 60 First end surface side outer layer portion 62 Second end face side outer layer part 70a The outermost surface 70b of the inner layer part on the first side face and the first side face side 70b The outermost surface of the inner layer part on the second side face side and the second side face side 80 gap part 80a first gap part 80b Second gap 80c Third gap 80d Fourth gap C1 Elastic modulus of each pre-fired dielectric sheet constituting the first outer outer layer C2 Each constituting the first inner outer layer Elastic modulus of dielectric sheet before firing D1 Elastic modulus of each dielectric sheet before firing constituting second outer outer layer portion D2 Elastic modulus of each dielectric sheet before firing constituting second inner outer layer portion L Lamination The length connecting the first end face and the second end face of the body Length in length direction L1 Width of first end face side outer layer portion L2 Width of second end face side outer layer portion Ld1 Width of third gap portion Ld2 Width of fourth gap portion T First main surface of laminate The length in the stacking direction connecting the first main surface and the thickness T1 The thickness of the first outer layer portion T2 The thickness of the second outer layer portion Td1 The first gap portion, the second gap portion in the first outer layer portion, the third Td2 Thickness of first gap portion, second gap portion, third gap portion, fourth gap portion in second outer layer portion Wd First thickness of laminate Length in the width direction connecting the side surface and the second side surface W1 Width of the first side surface side outer layer portion W2 Width of the second side surface side outer layer portion Wd1 Width of the first gap portion Wd2 Width of the second gap portion x Stacking direction y Width direction z Length direction

Claims (8)

A plurality of dielectric layers stacked and a plurality of internal electrode layers stacked; a first main surface and a second main surface facing the stacking direction; and a first facing the width direction orthogonal to the stacking direction. A laminated body including one side face and a second side face, and a first end face and a second end face facing in the length direction orthogonal to the laminating direction and the width direction;
A first external electrode layer disposed on a first end surface of the multilayer body; a second external electrode layer disposed on a second end surface of the multilayer body;
Have
The plurality of internal electrode layers have a first internal electrode layer drawn to the first end face and a second internal electrode layer drawn to the second end face,
In the stacking direction, the stacked body includes the first internal electrode layer or the first internal electrode layer or the second internal electrode layer, the internal electrode layer positioned closest to the first main surface of the first internal electrode layer or the second internal electrode layer. An inner layer portion including the first internal electrode layer or the second internal electrode layer located closest to the second main surface among the second internal electrode layers;
A first outer layer portion composed of a plurality of dielectric layers sandwiching the inner layer portion between each other, and a second outer layer portion composed of a plurality of dielectric layers,
The first outer layer portion is divided into two regions, and includes a plurality of dielectric layers including a dielectric layer located closest to the first main surface among the plurality of dielectric layers constituting the first outer layer portion. A first outer outer layer portion made of a plurality of layers, and a first inner outer layer portion made of a plurality of dielectric layers constituting the first outer layer portion located between the first outer outer layer portion and the inner layer portion. Including
A multilayer ceramic capacitor having a gap portion at least at a part of a boundary surface between the first outer outer layer portion and the first inner outer layer portion. The second outer layer part is divided into two regions, and a plurality of dielectrics including a dielectric layer located closest to the second main surface among the plurality of dielectric layers constituting the second outer layer part A second outer outer layer portion made of a plurality of layers, and a second inner outer layer portion made of a plurality of dielectric layers constituting the second outer layer portion located between the second outer outer layer portion and the inner layer portion. Including
2. The multilayer ceramic capacitor according to claim 1, wherein at least a part of a boundary surface between the second outer outer layer portion and the second inner outer layer portion has a gap portion. The first internal electrode layer and the second internal electrode layer extend from a facing portion and a facing portion at which the first internal electrode layer and the second internal electrode layer are opposed to each other. And a drawer portion that is pulled out to the end face of 2.
The gap is disposed in the vicinity of each end of the first internal electrode layer and the second internal electrode layer when viewed from the stacking direction,
The gap portion includes a first gap portion disposed on the first side surface side, a second gap portion disposed on the second side surface side, and a lead portion of the first internal electrode layer. Is a third gap disposed on the opposite side, and a fourth gap disposed on the opposite side to the lead-out portion of the second internal electrode layer,
The multilayer ceramic capacitor according to claim 1, comprising: The laminated body is located on the first side surface side, and includes the outermost surface of the inner layer portion on the first side surface and the first side surface side, and a straight line on the outermost surface along the length direction. A first side-side outer layer portion formed from the plurality of dielectric layers positioned between;
Located on the second side surface side, located between the second side surface and the outermost surface of the inner layer portion on the second side surface side and on the straight line of the outermost surface along the length direction A second side surface side outer layer portion formed of a plurality of dielectric layers;
Located on the first end face side or the second end face side, between the first end face or the second end face and the inner layer portion on the first end face side or the second end face side The first end face side outer layer part or the second end face side outer layer part formed from the plurality of dielectric layers located at
Including
The length in the thickness direction connecting the first main surface and the second main surface of the laminate is T, the length in the width direction connecting the first side surface and the second side surface of the laminate. W, L is the length in the length direction z connecting the first end surface and the second end surface of the laminate,
The width of the first side surface outer layer portion is W1, the width of the second side surface outer layer portion is W2, the width of the first end surface side outer layer portion is L1, and the width of the second end surface side outer layer portion is L2, the thickness of the first outer layer portion is T1, the thickness of the second outer layer portion is T2,
The width of the first gap portion arranged on the first side surface side is Wd1, the width of the second gap portion arranged on the second side surface side is Wd2, and the lead portion of the first internal electrode layer Ld1 is the width of the third gap portion arranged on the opposite side to Ld2, and Ld2 is the width of the fourth gap portion arranged on the side opposite to the lead portion of the second internal electrode layer. The thickness of the first gap part, the second gap part, the third gap part and the fourth gap part in the outer layer part is Td1, the first gap part in the second outer layer part, When the thickness of the second gap, the third gap and the fourth gap is Td2,
0.05 × W1 or W2 ≦ Wd1 or Wd2 ≦ 0.85 × W1 or W2
0.05 × L1 or L2 ≦ Ld1 or Ld2 ≦ 0.85 × L1 or L2
0.04 × T1 or T2 ≦ Td1 or Td2 ≦ 0.85 × T1 or T2
The multilayer ceramic capacitor according to claim 1, wherein:   When the elastic modulus of each pre-fired dielectric sheet constituting the first inner outer layer portion is C2, and the elastic modulus of each pre-fired dielectric sheet constituting the first outer outer layer portion is C1, C2 The multilayer ceramic capacitor according to claim 1, wherein / C1 is 1.20 or more and 1.80 or less.   When the elastic modulus of each pre-fired dielectric sheet constituting the second inner outer layer portion is D2, and the elastic modulus of each pre-fired dielectric sheet constituting the second outer outer layer portion is D1, D2 6. The multilayer ceramic capacitor according to claim 2, wherein / D1 is 1.20 or more and 1.80 or less. A method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 5,
Preparing a dielectric sheet containing a binder and a plasticizer;
A step of forming a portion to be the first outer layer portion by laminating a plurality of the dielectric sheets;
Printing a conductive paste for internal electrodes on the dielectric sheet, and laminating a plurality of dielectric sheets printed with the conductive paste for internal electrodes, thereby forming a portion to be the inner layer portion; and
A step of forming a portion to be the second outer layer portion by laminating a plurality of the dielectric sheets;
Have
In the step of forming a portion to be the first outer layer portion,
The binder included in the dielectric sheet used for the first inner outer layer portion of the first outer layer portion, and the plasticizer included in the dielectric sheet used for the first inner outer layer portion. The ratio is 3.1 or more and 4.2 or less,
The binder contained in the dielectric sheet used for the first outer outer layer part of the first outer layer part, and the plasticizer contained in the dielectric sheet used for the first outer outer layer part. A method for producing a multilayer ceramic capacitor, wherein the ratio is 2.6 or more and 3.1 or less. A method for producing a multilayer ceramic capacitor according to any one of claims 2 to 6,
In the step of forming a portion to be the second outer layer portion,
The binder included in the dielectric sheet used for the second inner outer layer portion of the second outer layer portion, and the plasticizer included in the dielectric sheet used for the second inner outer layer portion. The ratio is 3.1 or more and 4.2 or less,
The binder contained in the dielectric sheet used in the second outer layer part of the second outer layer part, and the plasticizer contained in the dielectric sheet used in the second outer layer part. The method for producing a multilayer ceramic capacitor according to claim 7, wherein the ratio is 2.6 or more and 3.1 or less.

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