JP2019186842A - AD converter - Google Patents

Abstract

To provide an AD converter capable of shortening a period of each step of the successive approximation to be operable speedily.SOLUTION: An AD converter 1A comprises: DA conversion unit 10A; a comparator 20; a control unit 30A; and a charge injection unit 50. The charge injection unit 50 injects a constant charge to a reference potential supply line that gives a first reference potential VREFH or a second reference potential VREFL to the DA conversion unit 10A regardless of history of comparison result by the comparator 20 for each step of the successive approximation in any step of the successive approximation, so as to suppress potential variation of the reference potential supply line in accompany with setting change of switches SW-SWof the DA conversion unit 10A.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a successive approximation AD converter.

  An AD converter (ADC, analog-to-digital converter) can input analog data and output digital data corresponding to the input analog data. Among them, a successive approximation register (SAR) AD converter includes a DA converter, a comparator, and a controller as main components. The DA converter includes a plurality of capacitive elements and a plurality of switches. The successive approximation type AD converter has fewer analog circuits than other types of AD converters, suppresses static current, and is suitable for process miniaturization with low power consumption. Therefore, successive approximation type AD converters have been actively studied in recent years.

  As described in Non-Patent Document 1, the successive approximation type AD converter generally performs the operations of the initialization step and the successive approximation step as follows. In the initialization step, the DA conversion unit initializes the charge of each capacitive element. After this initialization step, each successive comparison step is performed. In each successive comparison step, the DA converter sets each switch based on a control signal given from the controller, and outputs analog data corresponding to the setting to the comparator. The comparison unit evaluates the size of the analog data output from the DA conversion unit based on the input analog data, and outputs the evaluation result to the control unit. Based on the evaluation result output from the comparison unit, the control unit sets each of the DA conversion units in the next step of the successive comparison so that the analog data output from the DA conversion unit approaches a value corresponding to the input analog data. Outputs control signals that control switch settings.

  The control unit determines the value of the most significant bit (MSB) of the digital data to be output in the first step, and sequentially determines the value of the lower bit in each subsequent step. In step, the value of the least significant bit (LSB) is determined. For example, if the digital data to be output is 4-bit data [d3, d2, d1, d0], the control unit determines the value of d3 of the MSB in the first step 1 and the bit d2 in the next step 2. In the next step 3, the value of bit d1 is determined, and in the final step 4, the value of dSB of LSB is determined.

  In the operation of such a successive approximation type AD converter, the DA converter is used when shifting from the initialization step to the first step 1 of the successive approximation and when shifting from each step of the successive approximation to the next step. The setting of the plurality of switches changes, and the amount of charge of each capacitive element of the DA converter changes. The change in the charge amount of the plurality of capacitive elements of the DA converter causes charge transfer via a reference voltage terminal called kickback. By this kickback, the potential of the reference potential supply line that supplies the reference potential to the DA converter varies. In particular, since the kickback is large in the initial step of the successive approximation, the amount of fluctuation in the potential of the reference potential supply line is also large.

  If the comparison unit evaluates the magnitude of the analog data output from the DA conversion unit at a timing when the fluctuation of the reference potential supplied from the reference potential supply line to the DA conversion unit is large, the evaluation result is erroneous and finally obtained. The digital data that is received may be erroneous. Therefore, the comparison unit evaluates the magnitude of the analog data output from the DA conversion unit at a timing after the fluctuation of the reference potential supplied from the reference potential supply line to the DA conversion unit is stabilized and the reference potential is stabilized. It is preferable to do. In this case, the period of each step of the successive comparison must be set longer than the time required for the reference potential to stabilize after the transition to the step. The AD converter is required to increase the speed, but the time required for the reference potential to stabilize after the transition to the step hinders the speed-up of the AD converter.

  Non-patent documents 2 to 4 describe techniques for shortening the period of each step of successive comparison. The technique described in Non-Patent Document 2 speeds up the buffer that outputs the reference potential to the reference potential supply line and adjusts the offset at the time of evaluation by the comparison unit, thereby shortening the period of each step. Plan. The technique described in Non-Patent Document 3 aims at shortening the period of each step by providing a large-capacity decoupling capacitor in the reference potential supply line. In the techniques described in Non-Patent Documents 4 and 5, the period of each step is shortened by injecting charges into the reference potential supply line.

Behzad Razavi, “A Tale of TwoADCs: Pipelined Versus SAR,” IEEE Solid-State Circuits Magazine, Volume: 7, Issue: 3, pp. 38-46, 2015. Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins, “60-dBSNDR 100-MS / s SAR ADCs With Threshold Reconfigurable Reference ErrorCalibration, ”IEEE Journal of Solid-State Circuits, Volume 52, Number 10, pp.2576-2588, October 2017. Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx, “A 70 dB SNDR 200 MS / s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS,” 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp.1-2, June 2014 . Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu, “A 8.2-mW 10-b 1.6-GS / s 4 × TI SAR ADC with fast referencecharge neutralization and background timing-skew calibration in 16 -nm CMOS, ”2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp.1-2, June 2016. Ewout Martens, BenjaminHershberg, Jan Craninckx, “A 16nm 69dB SNDR 300MSps ADC with capacitive referencestabilization,” 2017 Symposium on VLSI Circuits, pp.C92-C93, June 2017.

  The technique described in Non-Patent Document 2 is not preferable because it increases the power consumption by increasing the speed of the buffer.

  The technique described in Non-Patent Document 3 is not preferable when a large-capacity decoupling capacitor is provided on a semiconductor substrate, because it increases the layout area on the semiconductor substrate. When a decoupling capacitor is provided outside the semiconductor substrate, even if a chip capacitor is used as the decoupling capacitor, the self-resonant frequency is as small as about several tens of MHz, which meets the demand for higher speed AD converters. It is difficult.

  The outline of the technology described in Non-Patent Documents 4 and 5 is as follows. The charge transfer amount of the DA conversion unit in each step of the successive comparison is not determined only by the comparison result by the comparison unit of the immediately preceding step, but varies depending on the history of comparison results by the comparison unit from the first step to the immediately preceding step. Therefore, the techniques described in Non-Patent Documents 4 and 5 determine the amount of charge injected into the reference potential supply line for each step based on the history of comparison results from the first step to the previous step. Set to.

  As the number of steps for injecting charges increases, the circuit for determining the amount of charge injection becomes complicated in logic and the time required for processing becomes longer. That is, the result may be contrary to the intention of shortening the period of each step. Although the technique described in Non-Patent Document 4 simplifies the logic for determining the amount of charge injection, it only stops charge injection in the first three steps of the successive comparison. The technique described in Non-Patent Document 5 is provided with a dedicated circuit in order to determine the charge injection amount at high speed and adopts other various characteristic configurations. This is not preferable because it causes an increase in layout area when mounted on the board.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an AD converter that can shorten the period of each step of successive approximation and can easily operate at high speed.

  An AD converter according to a first aspect of the present invention is a successive approximation AD converter that outputs digital data corresponding to input analog data, and is set based on (1) a plurality of capacitive elements and a control signal. By setting all or some of the plurality of switches, (2) the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements is set to the first reference potential. Alternatively, as the second reference potential, a DA converter that outputs data corresponding to the setting of each of the plurality of switches from an output terminal formed by commonly connecting the second terminals of the plurality of capacitive elements, and (3) DA conversion A comparison unit that compares the data output from the unit with the input analog data and outputs a comparison signal representing the comparison result; and (4) a DA conversion unit for each successive comparison step based on the comparison signal. Data output from A control unit that generates and outputs a control signal so that the difference between the input data and the input analog data is reduced, and (5) in any step of the successive approximation, the first reference potential or the second reference potential is supplied to the DA conversion unit. A constant amount of charge is injected into the given reference potential supply line regardless of the comparison result history for each successive comparison step, and potential fluctuations in the reference potential supply line due to setting changes of a plurality of switches of the DA converter are detected. A charge injection portion to be suppressed.

  The AD converter according to the second aspect of the present invention is a successive approximation AD converter that outputs digital data according to input analog data, and is set based on (1) a plurality of capacitive elements and a control signal. A plurality of switches, and after the input analog data is held by the plurality of capacitors, the capacitance corresponding to the switch among the plurality of capacitors is set by setting all or some of the plurality of switches. Using the first end of the element as the first reference potential or the second reference potential, data corresponding to the setting of each of the plurality of switches is output from the output end formed by commonly connecting the second ends of the plurality of capacitive elements. A DA conversion unit; (2) a comparison unit that compares the data output from the DA conversion unit with a reference level and outputs a comparison signal representing the comparison result; and (3) a sequential operation based on the comparison signal. ratio A control unit that generates and outputs a control signal so that the difference between the data output from the DA conversion unit and the reference level is reduced at each step, and (4) in any one of the successive comparison steps, the first reference Setting a plurality of switches of the DA converter by injecting a fixed amount of charge into the reference potential supply line for supplying the potential or the second reference potential to the DA converter regardless of the history of comparison results for each successive comparison step A charge injection unit that suppresses potential fluctuation of the reference potential supply line due to the change.

  An AD converter according to a third aspect of the present invention is a successive approximation type AD converter that outputs digital data corresponding to a difference between first input analog data and second input analog data. A capacitance element and a plurality of switches set based on the first control signal, and after setting the first input analog data by the plurality of capacitance elements, setting of all or some of the plurality of switches By using the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements as the first reference potential or the second reference potential, the first data corresponding to the setting of each of the plurality of switches is received. A first DA converter that outputs from an output terminal in which each second terminal is connected in common; (2) a plurality of capacitive elements; and a plurality of switches set based on a second control signal; 2-input After the log data is held by the plurality of capacitive elements, the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements is set to the first reference by setting all or some of the plurality of switches. A second DA converter that outputs, as a potential or a second reference potential, second data corresponding to the setting of each of the plurality of switches from an output end in which the second ends of the plurality of capacitive elements are connected in common; 3) a comparison unit that compares the first data with the second data and outputs a comparison signal representing the comparison result; and (4) based on the comparison signal, for each successive comparison step, the first data and A control unit that generates and outputs a first control signal and a second control signal so as to reduce a difference from the second data; and (5) a first reference potential or a second reference potential in any step of the successive approximation. Is given to the DA converter A constant amount of charge is injected into the reference potential supply line regardless of the comparison result history for each successive comparison step, and the potential variation of the reference potential supply line due to the setting change of the plurality of switches of the DA converter is reduced. A charge injection portion to be suppressed.

  In the present invention, it is preferable that the charge injection unit injects charges into the reference potential supply line in at least the first step of the successive comparison. It is preferable that the charge injection unit optimizes the amount of charge injected into the reference potential supply line as the successive comparison step proceeds. As the steps progress, the appropriate value tends to decrease. The charge injection unit injects a fixed amount of charge into the reference potential supply line that supplies the first reference potential to the DA conversion unit, and also supplies a fixed amount of charge to the reference potential supply line that supplies the second reference potential to the DA conversion unit. Is preferably injected.

  The charge injection unit includes a capacitor having a first end and a second end, a first switch connecting the first end of the capacitor to the first power supply potential supply line or the reference potential supply line, and a second end of the capacitor Is connected to the second power supply potential supply line or the first power supply potential supply line, the first switch connects the first end of the capacitor to the first power supply potential supply line, and the second switch By connecting the second end of the capacitor portion to the second power supply potential supply line, electric charge is accumulated in the capacitor portion, and the first end of the capacitor portion is connected to the reference potential supply line by the first switch, and by the second switch By connecting the second end of the capacitor portion to the first power supply potential supply line, it is preferable to inject the charge accumulated in the capacitor portion into the reference potential supply line.

  The charge injection unit has (1) a first end and a second end, the first end is connected to the reference potential supply line, and charge accumulation or charge injection to the reference potential supply line is performed according to the level of the second end And (2) an inverter circuit having an output terminal connected to the second end of the capacitor unit and receiving a signal for controlling charge accumulation and charge injection in the capacitor unit, and (3) the capacitor unit It is also preferable to include a current limiting circuit that limits the magnitude of the current flowing between the output terminal of the inverter circuit and the second terminal of the capacitor when charge accumulation is started after the charge injection.

  The charge injection unit includes a capacitor unit having a first end and a second end, a first switch provided between the first end of the capacitor unit and the reference potential supply line, a first end of the capacitor unit, and a power supply potential And a second switch provided between the power supply line, the first switch is turned off, and the second switch is turned on, whereby charges are accumulated in the capacitor portion and the first switch is turned on. It is also preferable to inject the charge stored in the capacitor portion into the reference potential supply line by turning off the second switch.

  Further, it is preferable that the capacitance value of the capacitor portion is variable.

  The AD converter according to the present invention can shorten the period of each step of successive approximation and can easily operate at high speed.

FIG. 1 is a diagram illustrating a configuration of the AD converter 1A. FIG. 2 is a table for explaining a first operation example of the AD converter 1A. FIG. 3 is a table for explaining a second operation example of the AD converter 1A. FIG. 4 is a table for explaining a third operation example of the AD converter 1A. FIG. 5 is a diagram illustrating a configuration of a charge injection unit 51 as a first circuit example of the charge injection unit 50. FIG. 6 is a diagram illustrating a configuration of a charge injection unit 52 as a second circuit example of the charge injection unit 50. FIG. 7 is a diagram illustrating a configuration of a charge injection unit 53 as a third circuit example of the charge injection unit 50. FIG. 8 is a diagram illustrating a configuration of the AD converter 1B. FIG. 9 is a diagram illustrating a circuit example of each switch SW _n of the AD converter 1B. FIG. 10 is a timing chart for explaining the operation of each switch SW _n of the AD converter 1B. FIG. 11 is a diagram illustrating a configuration of the AD converter 1C. FIG. 12 is a table for explaining an operation example of the AD converter 1C. FIG. 12A shows the operation of the first DA converter 11 of the AD converter 1C. FIG. 12B shows the operation of the second DA converter 12 of the AD converter 1C. FIG. 13 is a timing chart for explaining an operation example of the AD converter 1C. FIG. 14 is a diagram illustrating a simulation result of the operation of the AD converter 1C.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. The present invention is not limited to these exemplifications, but is defined by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

(First configuration example)
FIG. 1 is a diagram illustrating a configuration of the AD converter 1A. The AD converter 1A of the first configuration example shown in this figure includes a DA conversion unit 10A, a comparison unit 20, a control unit 30A, and a charge injection unit 50. The AD converter 1A outputs digital data corresponding to the input analog data Ain from the control unit 30A.

The DA conversion unit 10A includes N capacitive elements C _{0 to} C _N−1 , N switches SW _{0 to} SW _N−1 and a switch SW _RST . The N switches SW _{0 to} SW _N-1 are set based on a control signal output from the control unit 30A. The first end of the capacitive element C _n is connected to the corresponding switch SW _n. The first end of the capacitive element C _n is the setting of the switch SW _n, is the second reference potential VREFL the first reference potential VREFH or low potential of the high potential. The second end of the capacitive elements C _n constitute the output terminals are connected in common. The switch SW _RST is provided between the output terminal and the second reference potential supply line. The DA conversion unit 10A outputs data CTOP corresponding to the setting of each of the _N switches SW _{0 to} SW _N−1 from the output terminal to the comparison unit 20.

N is an integer of 2 or more, and n is an integer of 0 or more and (N-1) or less. In addition, the first end of any _one of the _N capacitive elements C _{0 to} C _N-1 may be at a constant potential, and in this case, a switch corresponding to the capacitive element is not necessary. is there.

  The comparison unit 20 compares the data input to each of the two input terminals, and outputs a comparison signal representing the comparison result to the control unit 30A. In the first configuration example, the comparison unit 20 inputs the data CTOP output from the DA conversion unit 10A to one input terminal, and inputs the input analog data Ain to the other input terminal.

  Based on the comparison signal output from the comparison unit 20, the control unit 30A controls the control signal so that the difference between the data CTOP output from the DA conversion unit 10A and the input analog data Ain is reduced at each successive comparison step. And outputs the control signal to the DA converter 10A.

The charge injection unit 50 compares the reference potential supply line for supplying the first reference potential VREFH or the second reference potential VREFL to the DA conversion unit 10A in any step of the successive comparison by the comparison unit 20 for each successive comparison step. Regardless of the history of results, a certain amount of charge is injected to suppress potential fluctuations in the reference potential supply line due to setting changes of the switches SW _{0 to} SW _N-1 of the DA converter 10A.

FIG. 2 is a table for explaining a first operation example of the AD converter 1A. In the first operation example, N = 4, the capacitance value of the capacitive element C ₀ is C, the capacitance value of the capacitive element C ₁ is C, the capacitance value of the capacitive element C ₂ is 2C, and the capacitance of the capacitive element C ₃ The value is 4C. The capacitance value of each capacitive element is indicated by a multiple of the unit capacitance value C. The table has the potential of the first end of the control signals Ccode and the capacitors C _n in each step of the successive approximation is shown. “H” indicates that the first end of the capacitive element is connected to the first reference potential VREFH having a high potential, and “L” indicates that the first end of the capacitive element is connected to the second reference potential VREFL having a low potential. Indicates that Ccode is a 3-bit control signal given from the control unit 30A to the DA conversion unit 10A in order to control the setting of each switch of the DA conversion unit 10A. Setting of the switch SW ₃ is controlled by c2 which is MSB of Ccode [c2, c1, c0] . Setting of the switch SW ₂ is controlled from c1 which is the second bit of Ccode. Setting of the switch SW ₁ is controlled by c0 the LSB of Ccode. Since the capacitive element C ₀ is always connected to the second reference potential VREFL having a low potential, the switch SW ₀ may be omitted.

In the initialization step, both ends of each of the four capacitive elements C _{0 to} C ₃ are set to the second reference potential VREFL by the four switches SW _{0 to} SW ₃ and the switch SW _RST . As a result, the charges of the four capacitive elements C _{0 to} C ₃ are initialized, and the data CTOP output from the DA converter 10A to the comparator 20 is initialized. When the initialization step is completed, the switch SW _RST is turned off.

In a first step 1 the sequential comparison after the initialization step, that is given Ccode [1, 0, 0] to the DA conversion unit 10A from the control unit 30A, the capacitive element C ₃ is connected to a first reference potential VREFH The capacitive elements C ₂ , C ₁ , C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 4C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 4C. The data CTOP output from the DA converter 10A in such a connected state of each capacitive element is (VREFH + VREFL) / 2.

  In step 1, the data CTOP output from the DA converter 10A and the input analog data Ain are compared in magnitude by the comparator 20, and a comparison signal representing the comparison result is output from the comparator 20 to the controller 30A. Then, according to the comparison result of step 1, the control unit 30A determines the Ccode to be given to the DA conversion unit 10A in step 2 next to the successive comparison. Step 2 is divided into Case 1 and Case 2 according to the comparison result of Step 1. If the data CTOP is smaller than the input analog data Ain, the process proceeds to case 1. If the data CTOP is larger than the input analog data Ain, the process proceeds to case 2.

In case 1 of step 2 of the successive approximation, Ccode [1,1,0] is given from the control unit 30A to the DA conversion unit 10A, so that the capacitive elements C ₃ and C ₂ are connected to the first reference potential VREFH. The capacitive elements C ₁ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 6C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 2C. The data CTOP output from the DA converter 10A in such a connected state of each capacitive element is (3VREFH + VREFL) / 4.

  In case 1 of step 2, the data CTOP output from the DA converter 10A and the input analog data Ain are compared in magnitude by the comparator 20, and a comparison signal representing the comparison result is output from the comparator 20 to the controller 30A. . Then, according to the comparison result of case 1 in step 2, the control unit 30A determines the Ccode to be given to the DA conversion unit 10A in step 3 next to the successive comparison. Step 3 after case 1 of step 2 is divided into case 1-1 and case 1-2 according to the comparison result of case 1 of step 2. If the data CTOP is smaller than the input analog data Ain, the process proceeds to case 1-1. If the data CTOP is larger than the input analog data Ain, the process proceeds to case 1-2.

In step 2 of the case 2 of the successive approximation, the DA conversion unit 10A from the control unit 30A that is given Ccode [0,1,0], the capacitor C ₂ is connected to the first reference potential VREFH, the capacitor C ₃ , C ₁ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 2C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 6C. The data CTOP output from the DA converter 10A in such a connected state of each capacitive element is (VREFH + 3VREFL) / 4.

  In case 2 of step 2, the data CTOP output from the DA converter 10A and the input analog data Ain are compared in magnitude by the comparator 20, and a comparison signal representing the comparison result is output from the comparator 20 to the controller 30A. . Then, according to the comparison result of case 2 in step 2, the control unit 30A determines the Ccode to be given to the DA conversion unit 10A in step 3 next to the successive comparison. Step 3 after case 2 of step 2 is divided into case 2-1 and case 2-2 according to the comparison result of case 2 of step 2. When the data CTOP is smaller than the input analog data Ain, the process proceeds to case 2-1, and when the data CTOP is larger than the input analog data Ain, the process proceeds to case 2-2.

In case 1-1 of step 3, Ccode [1,1,1] is given from the control unit 30A to the DA conversion unit 10A, so that the capacitive elements C ₃ , C ₂ , C ₁ are connected to the first reference potential VREFH. is, the capacitor C ₀ is connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 7C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is C. Therefore, the data CTOP output from the DA converter 10A is (7VREFH + VREFL) / 8.

In case 1-2 of step 3, when Ccode [1,0,1] is given from the control unit 30A to the DA conversion unit 10A, the capacitive elements C ₃ and C ₁ are connected to the first reference potential VREFH, and the capacitance The elements C ₂ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 5C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 3C. Therefore, the data CTOP output from the DA converter 10A is (5VREFH + 3VREFL) / 8.

In case 2-1 of step 3, when Ccode [0,1,1] is given from the control unit 30A to the DA conversion unit 10A, the capacitive elements C ₂ and C ₁ are connected to the first reference potential VREFH, and the capacitance The elements C ₃ and C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is 3C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 5C. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + 5VREFL) / 8.

In Case 2-2 Step 3, the DA conversion unit 10A from the control unit 30A that is given Ccode [0,0,1], the capacitive element C ₁ is connected to the first reference potential VREFH, capacitive element C ₃ , C ₂ , C ₀ are connected to the second reference potential VREFL. That is, the sum of the capacitance values of the capacitive elements connected to the first reference potential VREFH is C, and the sum of the capacitance values of the capacitive elements connected to the second reference potential VREFL is 7C. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 7VREFL) / 8.

  Thus, in the first step 1 of the successive approximation, the Ccode given from the control unit 30A to the DA conversion unit 10A is temporarily set to [1,0,0], and the data CTOP output from the DA conversion unit 10A The input analog data Ain is compared in magnitude, and c2 which is the MSB of Ccode is determined based on the comparison result. In the next step 2, the Ccode given from the control unit 30A to the DA conversion unit 10A is temporarily set to [c2,1,0], and the data CTOP output from the DA conversion unit 10A and the input analog data Ain are large or small. Comparison is made, and c1 which is the second bit of Ccode is determined based on the comparison result.

  In the final step 3, the Ccode given from the control unit 30A to the DA conversion unit 10A is temporarily set to [c2, c1,1], and the data CTOP output from the DA conversion unit 10A and the input analog data Ain are large or small. Based on the comparison result, c0 which is the LSB of Ccode is determined. Then, Ccode finally obtained after step 3 (or digital data obtained based on this Ccode) is output from the control unit 30A as digital data corresponding to the input analog data Ain.

FIG. 3 is a table for explaining a second operation example of the AD converter 1A. In the second operation example, N = 8, and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. The sum of the capacitance values of the capacitive elements C ₇ , C ₆ , C ₅ , and C ₄ is 4C, and the sum of the capacitance values of the capacitive elements C ₃ and C ₂ is 2C. Accordingly, the capacitive elements C ₇ , C ₆ , C ₅ , C ₄ provided in parallel with each other are set to the same potential based on c2 of Ccode, and the capacitive elements C ₃ , C ₃ provided in parallel with each other are set. by C ₂ is set to the same potential to each other based on c1 of Ccode, the second operation example will be equivalent to a first operation example.

FIG. 4 is a table for explaining a third operation example of the AD converter 1A. Similarly to the case of the second operation example described above, in this third operation example, N = 8, and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. However, in the above-described second operation example, the connection of each capacitive element is determined based on Ccode [c2, c1, c0] expressed in binary code, but in this third operation example, Ccode [c2, Connection of each capacitive element is determined based on a thermometer code obtained by decoding c1, c0].

In the third operation example, in the first step 1 of the successive approximation, the four capacitive elements C _{0 to} C ₃ are connected to the first reference potential VREFH, and the four capacitive elements C _{4 to} C ₇ are the second reference potential. Connected to potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + VREFL) / 2.

In Case 1 of Step 2, the six capacitive elements C _{0 to} C ₅ are connected to the first reference potential VREFH, and the two capacitive elements C ₆ and C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + VREFL) / 4.

In case 2 of step 2, the two capacitive elements C ₀ and C ₁ are connected to the first reference potential VREFH, and the six capacitive elements C _{2 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 3VREFL) / 4.

In case 1-1 of Step 3, the seven capacitive elements C _{0 to} C ₆ are connected to the first reference potential VREFH, and the one capacitive element C ₇ is connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (7VREFH + VREFL) / 8.

In Step 1-2 of Step 3, the five capacitive elements C _{0 to} C ₄ are connected to the first reference potential VREFH, and the three capacitive elements C _{5 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (5VREFH + 3VREFL) / 8.

In the case 2-1 of Step 3, the three capacitive elements C _{0 to} C ₂ are connected to the first reference potential VREFH, and the five capacitive elements C _{3 to} C ₇ are connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (3VREFH + 5VREFL) / 8.

In Case 2-2 Step 3, one of the capacitor C ₀ is connected to the first reference potential VREFH, 7 pieces of the capacitor C ₁ -C ₇ is connected to the second reference potential VREFL. Therefore, the data CTOP output from the DA converter 10A is (VREFH + 7VREFL) / 8.

  As described above, the data CTOP output from the DA converter 10A of the third operation example in each step and each case is the data output from the DA converter 10A in each of the first and second operation examples described above. The same value as CTOP.

  In any of the first to third operation examples described above, the reference is used when shifting from the initialization step to the first step 1 of the successive approximation and when shifting from one step of the successive comparison to the next step. Charge transfer through the potential supply line occurs. If V = VREFH−VREFL, the amount of charge transfer when shifting from the initialization step to the successive comparison step 1 is 2 CV. The amount of charge transfer when shifting from step 1 to case 1 of the next step 2 is CV / 2. The amount of charge transfer when shifting from step 1 to case 2 of the next step 2 is 3 CV / 2. When transferring from case 1 of step 2 to case 1-1 of the next step 3, when transferring from case 1 of step 2 to case 1-2 of next step 3, from case 2 of step 2 to next step 3 The charge transfer also occurs when the process shifts to case 2-2 and when the process shifts from case 2 of step 2 to case 2-1 of the next step 3.

  The charge transfer amount of the DA conversion unit 10A in each step of the successive comparison is not determined only by the comparison result by the comparison unit 20 of the immediately preceding step, but depends on the history of comparison results by the comparison unit 20 from the first step to the immediately preceding step. Different. On the other hand, the amount of charge transfer of the DA converter 10A in each step of the successive approximation does not depend on the characteristics of the buffer that outputs the reference potential (VREFH, VREFL) to the reference potential supply line.

  Therefore, as described above, the techniques described in Non-Patent Documents 4 and 5 are based on the history of comparison results by the comparison unit from the first step to the previous step, and the charge injected into the reference potential supply line. Set the amount step by step. However, when the number of steps for performing charge injection increases, the logic for determining the amount of charge injection becomes complicated and the time required for processing increases. That is, the result may be contrary to the intention of shortening the period of each step.

  Even if the amount of charge injected into the reference potential supply line can be accurately set for each step in a short time, it is difficult to accurately inject the charge into the DA converter. The reason is as follows. Since the output impedance of the buffer that outputs the reference potential (VREFH, VREFL) to the reference potential supply line is relatively small, not all of the injected charges flow only to the DA converter. If the timing of charge transfer due to kickback is slightly different from the timing of charge injection, the reference potential fluctuates and charge injection from the buffer occurs. Since charge transfer by kickback is fast, it is difficult to match the timing of charge injection with charge transfer by kickback. Even in Non-Patent Document 4, it can be seen that a ripple remains in the time waveform of the reference potential when charge is injected.

  As described above, although the techniques described in Non-Patent Documents 4 and 5 set the charge injection amount for each step based on the history of comparison results by the comparison unit, the logic for that is complicated and the time required is long. In addition, it is difficult to inject an intended amount of charge into the DA converter.

In the present embodiment, the charge injection unit 50 supplies the first reference potential VREFH to the DA conversion unit 10A or the second reference potential VREFL to DA in any step of the successive comparison. A fixed amount of charge is injected into the reference potential supply line (VREFL supply line) to be supplied to the conversion unit 10A regardless of the comparison result history by the comparison unit 20 for each successive comparison step, and the switch SW of the DA conversion unit 10A _It suppresses the potential fluctuation of the reference potential supply line accompanying the setting change of _{0 to} SW _N-1 . Accordingly, since the charge injection unit 50 has a simple logic, charge injection can be performed in many steps of successive approximation. And AD converter 1A of this embodiment can make kickback small, can shorten the period of each step of successive approximation, and high-speed operation becomes easy.

  Kickback tends to be large at the first step of successive approximation and decrease as the step progresses. Therefore, it is preferable that the charge injection unit 50 injects charges into the VREFH supply line or the VREFL supply line in at least the first step of the successive approximation. Further, it is preferable that the charge injection unit 50 optimizes the amount of charge injected into the VREFH supply line or the VREFL supply line as the successive comparison step proceeds.

  The charge injection unit 50 preferably injects a certain amount of charge into the VREFH supply line and injects a certain amount of charge into the VREFL supply line. When the second reference potential VREFL is the same as the ground potential, the charge injection unit 50 may inject a certain amount of charge only to the VREFH supply line. In addition to injecting charges into the reference potential supply line, charges may be extracted from the reference potential supply line. These are collectively referred to as injection.

  The charge injection unit 50 has a configuration including a capacitor unit that accumulates charges, and injects the charge accumulated in the capacitor unit into the VREFH supply line or the VREFL supply line in a predetermined step of successive comparison. When charge injection is performed in a plurality of steps of successive comparison, the charge injection unit 50 has a configuration including a capacitor unit corresponding to each of the plurality of steps. In this case, the capacitance value of the capacitance unit varies from step to step.

  Further, when charge injection is performed on both the VREFH supply line and the VREFL supply line, the charge injection unit 50 has a configuration including a capacitance unit corresponding to each of the VREFH supply line and the VREFL supply line. In this case, the capacitance value of the capacitor corresponding to the VREFH supply line and the capacitance value of the capacitor corresponding to the VREFL supply line may be the same.

  The charge injection unit 50 may use the first power supply potential or the second power supply potential when accumulating charges in the capacitor unit. One of the first power supply potential and the second power supply potential is a high power supply potential (VDD potential), and the other is a low ground potential (VSS potential). Hereinafter, the power supply potential supply line that applies the VDD potential to the DA converter 10A is referred to as a VDD supply line, and the power supply potential supply line that applies the VSS potential to the DA converter 10A is referred to as a VSS supply line.

  The first reference potential VREFH may be the same as the VDD potential. The second reference potential VREFL may be the same as the VSS potential. In general, the first reference potential VREFH and the second reference potential VREFL are generated and output by a buffer driven by the VDD potential and the VSS potential. In general, VDD ≦ VREFL and VREFH ≦ VDD.

  It is preferable that both ends of the capacitor portion of the charge injection portion 50 be in an open state at the time of transition between charge accumulation and charge injection. In this way, unintended charge movement can be suppressed.

  It is preferable that the capacitor portion of the charge injection unit 50 be disconnected from the reference potential supply line during charge accumulation. By doing so, the potential fluctuation of the reference potential supply line due to charge accumulation can be suppressed, so that the degree of freedom of the transition timing between charge accumulation and charge injection is increased. In addition, since the charge accumulation period can be extended, the current flowing through the capacitor portion during charge accumulation can be reduced.

  The capacitance value of the capacitance portion of the charge injection portion 50 is preferably variable. The capacitance value of the capacitor portion is set according to the response characteristics of the buffer that generates the first reference potential VREFH and the second reference potential VREFL, the capacitance value of the decoupling capacitor portion provided in the reference potential supply line, and the like. Is preferred.

  Next, as a circuit example of the charge injection unit 50, each configuration of the charge injection units 51 to 53 will be described. The circuit example shown below has a configuration for one step of successive approximation.

  FIG. 5 is a diagram illustrating a configuration of a charge injection unit 51 as a first circuit example of the charge injection unit 50. The charge injection unit 51 includes capacitance units 101 and 102 and switches 111, 112, 121, and 122. The capacitance values of the capacitance units 101 and 102 may be different from each other, but are preferably equal to each other. Each of switches 111, 112, 121, and 122 is set based on signal NSW given from control unit 30A.

  The first end 101a of the capacitor unit 101 is set to one of a state connected to the VDD supply line, a state connected to the VREFH supply line, and an open state by the switch 111. The second end 101b of the capacitor 101 is set to one of a state connected to the VSS supply line, a state connected to the VDD supply line, and an open state by the switch 121.

  The first end 102a of the capacitor 102 is set to one of a state connected to the VSS supply line, a state connected to the VREFL supply line, and an open state by the switch 112. The second end 102b of the capacitor portion 102 is set to one of a state connected to the VDD supply line, a state connected to the VSS supply line, and an open state by the switch 122.

  During the period when the signal NSW is at a low level, the first end 101a of the capacitor 101 is connected to the VDD supply line by the switch 111, and the second end 101b of the capacitor 101 is connected to the VSS supply line by the switch 121. As a result, charges are accumulated in the capacitor 101. Further, during the period in which the signal NSW is at a low level, the first end 102 a of the capacitor 102 is connected to the VSS supply line by the switch 112, and the second end 102 b of the capacitor 102 is connected to the VDD supply line by the switch 122. As a result, charges are accumulated in the capacitor 102. Since the time required for this charge accumulation may be long, the on-resistance value of each switch during charge accumulation may be large. Further, the power source noise can be reduced by increasing the on-resistance value of each switch during charge accumulation.

  When the signal NSW becomes high level, the first end 101a of the capacitor 101 is connected to the VREFH supply line by the switch 111, and the second end 101b of the capacitor 101 is connected to the VDD supply line by the switch 121. As a result, the charge accumulated in the capacitor 101 so far is injected into the VREFH supply line. When the signal NSW becomes high level, the first end 102a of the capacitor 102 is connected to the VREFL supply line by the switch 112, and the second end 102b of the capacitor 102 is connected to the VSS supply line by the switch 122. As a result, the electric charge accumulated in the capacitor 102 so far is injected into the VREFL supply line. This charge injection is preferably performed in a short time, and therefore, the on-resistance value of each switch during charge injection is preferably small.

  Note that, in order to avoid unintended charge movement, both ends of the capacitor 101 are opened by the switches 111 and 121 at the transition between the charge accumulation period and the charge injection period, and the capacitors 112 and 122 Both ends of the unit 102 are in an open state.

  FIG. 6 is a diagram illustrating a configuration of a charge injection unit 52 as a second circuit example of the charge injection unit 50. The charge injection unit 52 includes capacitance units 201 and 202, PMOS transistors 211 and 212, NMOS transistors 221 and 222, NMOS transistor 231, PMOS transistor 232, resistors 241 and 242, and inverter circuits 261 and 262. The capacitance values of the capacitance units 201 and 202 may be different from each other, but are preferably equal to each other.

  The first end 201a of the capacitor 201 is connected to the VREFH supply line. The capacitor unit 201 performs charge accumulation or charge injection into the VREFH supply line according to the level of the second end 201b. The PMOS transistor 211 and the NMOS transistor 221 constitute an inverter circuit. That is, the source of the PMOS transistor 211 is connected to the VDD supply line. The source of the NMOS transistor 221 is connected to the VSS supply line. The gates of the PMOS transistor 211 and the NMOS transistor 221 are connected to each other and serve as an input terminal. The drains of the PMOS transistor 211 and the NMOS transistor 221 are connected to each other and serve as an output terminal. The output end is connected to the second end 201b of the capacitor unit 201.

  In the inverter circuit including the PMOS transistor 211 and the NMOS transistor 221, an NMOS transistor 231 and a resistor 241 are provided between the input terminal and the gate of the NMOS transistor 221. The drain of the NMOS transistor 231 is connected to the resistor 241 and to the gates of the NMOS transistors 221 and 231. The source of the NMOS transistor 231 is connected to the VSS supply line. The NMOS transistors 221 and 231 constitute a current mirror circuit.

  The NMOS transistor 231 and the resistor 241 limit the magnitude of a current that flows between the output terminal of the inverter circuit and the second end 201b of the capacitor unit 201 when charge accumulation is started after charge injection in the capacitor unit 201. A current limiting circuit 251 is configured. That is, a current having a magnitude corresponding to the resistance value of the resistor 241 flows to the NMOS transistor 231 and a current having a magnitude corresponding to the current flows to the NMOS transistor 221.

  The first end 202a of the capacitor 202 is connected to the VREFL supply line. The capacitor 202 performs charge accumulation or charge injection into the VREFL supply line according to the level of the second end 202b. The PMOS transistor 212 and the NMOS transistor 222 constitute an inverter circuit. That is, the source of the PMOS transistor 212 is connected to the VDD supply line. The source of the NMOS transistor 222 is connected to the VSS supply line. The gates of the PMOS transistor 212 and the NMOS transistor 222 are connected to each other and serve as an input terminal. The drains of the PMOS transistor 212 and the NMOS transistor 222 are connected to each other and serve as an output terminal. This output end is connected to the second end 202b of the capacitor 202.

  In the inverter circuit including the PMOS transistor 212 and the NMOS transistor 222, a PMOS transistor 232 and a resistor 242 are provided between the input terminal and the gate of the PMOS transistor 212. The drain of the PMOS transistor 232 is connected to the resistor 242 and is connected to the gates of the PMOS transistors 212 and 232. The source of the PMOS transistor 232 is connected to the VDD supply line. The PMOS transistors 212 and 232 constitute a current mirror circuit.

  The PMOS transistor 232 and the resistor 242 limit the amount of current that flows between the output terminal of the inverter circuit and the second terminal 202b of the capacitor 202 when charge accumulation is started after charge injection in the capacitor 202. A current limiting circuit 252 is configured. That is, a current having a magnitude corresponding to the resistance value of the resistor 242 flows to the PMOS transistor 232 and a current having a magnitude corresponding to the current flows to the PMOS transistor 212.

  The inverter circuit 261 receives the signal NSW output from the control unit 30A, logically inverts the input signal, and outputs a signal. The inverter circuit composed of the PMOS transistor 211 and the NMOS transistor 221 inputs the signal output from the inverter circuit 261 and performs charge accumulation or charge injection.

  The inverter circuit 262 receives the signal output from the inverter circuit 261 and outputs a signal obtained by logically inverting the input signal. The inverter circuit composed of the PMOS transistor 212 and the NMOS transistor 222 receives the signal output from the inverter circuit 262 and performs charge accumulation or charge injection.

  In this circuit example, charges are accumulated in the capacitor portions 201 and 202 during a period when the signal NSW is at a low level. When the signal NSW becomes high level, the charge accumulated in the capacitor unit 201 so far is injected into the VREFH supply line, and the charge previously accumulated in the capacitor unit 202 is injected into the VREFL supply line. Is done. Further, in this circuit example, since the current limiting circuits 251 and 252 are provided, the potential fluctuation of the reference potential supply line can be suppressed even when the charge storage operation is shifted during the successive approximation process.

  FIG. 7 is a diagram illustrating a configuration of a charge injection unit 53 as a third circuit example of the charge injection unit 50. The charge injection unit 53 includes capacitance units 301 and 302, a PMOS transistor 311, an NMOS transistor 312, a PMOS transistor 321, an NMOS transistor 322, inverter circuits 331 to 335, 341, 342, 351, and 352, NAND gate circuits 361 and 362, and Inverter circuit 363 is included. The capacitance values of the capacitor units 301 and 302 may be different from each other, but are preferably equal to each other.

  The first end 301 a of the capacitor 301 is connected to the VREFH supply line via the PMOS transistor 311 and is connected to the VDD supply line via the PMOS transistor 321. A second end 301 b of the capacitor 301 is connected to the output end of the inverter circuit 351. The PMOS transistor 311 is a first switch provided between the first end 301a of the capacitor unit 301 and the VREFH supply line, and a signal output from the output end of the inverter circuit 341 is input to the gate, and the input On / off is controlled according to the level of the signal. The PMOS transistor 321 is a second switch provided between the first end 301a of the capacitor 301 and the VDD supply line, and inputs a signal output from the output end of the NAND gate circuit 361 to the gate. On / off is controlled according to the level of the input signal.

  The first end 302 a of the capacitor 302 is connected to the VREFL supply line via the NMOS transistor 312 and connected to the VSS supply line via the NMOS transistor 322. A second end 302 b of the capacitor 302 is connected to the output end of the inverter circuit 351. The NMOS transistor 312 is a first switch provided between the first end 302a of the capacitor 302 and the VREFL supply line, and a signal output from the output end of the inverter circuit 342 is input to the gate, and the input On / off is controlled according to the level of the signal. The NMOS transistor 322 is a second switch provided between the first end 302a of the capacitor 302 and the VSS supply line, and outputs a signal that is output from the output end of the NAND gate circuit 362 and logically inverted by the inverter circuit 363. The signal is input to the gate, and on / off is controlled according to the level of the input signal.

  The inverter circuits 331 to 335 are connected in series in this order, and the signal NSW output from the control unit 30A is input to the first stage inverter circuit 331, and the inverter circuit at each stage sequentially receives the signal. The logic is inverted and a predetermined delay is given.

  The inverter circuit 341 receives the signal output from the inverter circuit 332, and outputs a signal obtained by logically inverting the input signal to the gate of the PMOS transistor 311. The inverter circuit 342 receives the signal output from the inverter circuit 333 and outputs a signal obtained by logically inverting the input signal to the gate of the NMOS transistor 312. The inverter circuit 351 receives the signal output from the inverter circuit 333, and outputs a signal obtained by logically inverting the input signal to the second end 301b of the capacitor 301. The inverter circuit 352 receives the signal output from the inverter circuit 334 and outputs a signal obtained by logically inverting the input signal to the second end 302 b of the capacitor 302.

  The NAND gate circuit 361 receives the signals output from the inverter circuits 331 and 335, and outputs a negative logical product of these two signals to the gate of the PMOS transistor 321. NAND gate circuit 362 and inverter circuit 363 receive signals output from inverter circuits 331 and 335, respectively, and output a logical product of these two signals to the gate of NMOS transistor 322.

  In this circuit example, while the signal NSW is at a low level, the PMOS transistor 311 and the NMOS transistor 312 are turned off and the PMOS transistor 321 and the NMOS transistor 322 are turned on. Accumulated. When the signal NSW becomes high level, the PMOS transistor 311 and the NMOS transistor 312 are turned on, and the PMOS transistor 321 and the NMOS transistor 322 are turned off, so that the charge accumulated in the capacitor 301 until now is VREFH The charges that have been injected into the supply line and have been accumulated in the capacitor 302 so far are injected into the VREFL supply line.

  In this circuit example, the PMOS transistor 311 and the PMOS transistor 321 are not simultaneously turned on, and the VREFH supply line and the VDD supply line are not connected to each other. The NMOS transistor 312 and the NMOS transistor 322 are not turned on at the same time, and the VREFL supply line and the VSS supply line are not connected to each other.

(Second configuration example)
FIG. 8 is a diagram illustrating a configuration of the AD converter 1B. The AD converter 1B of the second configuration example shown in this figure includes a DA conversion unit 10B, a comparison unit 20, a control unit 30B, a switch 40, and a charge injection unit 50. The AD converter 1B outputs digital data corresponding to the input analog data Ain from the control unit 30B.

The DA conversion unit 10B includes N capacitive elements C _{0 to} C _N−1 and N switches SW _{0 to} SW _N−1 . The N switches SW _{0 to} SW _N-1 are set based on a control signal output from the control unit 30B. The first end of the capacitive element C _n is connected to the corresponding switch SW _n. The first end of the capacitive element C _n is the setting of the switch SW _n, is the second reference potential VREFL the first reference potential VREFH or low potential of the high potential. The second end of the capacitive elements C _n constitute the output terminals are connected in common. The DA converter 10B holds the input analog data Ain by the N capacitive elements C _{0 to} C _N-1 and then compares the data CTOP corresponding to the setting of each of the _N switches SW _{0 to} SW _N-1. 20 output.

N is an integer of 2 or more, and n is an integer of 0 or more and (N-1) or less. In addition, the first end of any _one of the _N capacitive elements C _{0 to} C _N-1 may be at a constant potential, and in this case, a switch corresponding to the capacitive element is not necessary. is there.

  The comparison unit 20 compares the data input to each of the two input terminals, and outputs a comparison signal representing the comparison result to the control unit 30B. In the second configuration example, the comparison unit 20 inputs the data CTOP output from the DA conversion unit 10B to one input terminal, and inputs the reference level VCM to the other input terminal. The reference level VCM is, for example, an average value of the first reference potential VREFH and the second reference potential VREFL. Alternatively, the reference level VCM may be set to a value at which the comparison unit 20 can operate with the highest performance (for example, high sensitivity and high SN ratio). The switch 40 is provided between the two input terminals of the comparison unit 20.

  Based on the comparison signal output from the comparison unit 20, the control unit 30B controls the control signal so that the difference between the data CTOP output from the DA conversion unit 10B and the input analog data Ain is reduced at each successive comparison step. And outputs the control signal to the DA converter 10B.

The charge injection unit 50 injects a certain amount of charge into the VREFH supply line or the VREFL supply line at any step of the successive comparison regardless of the comparison result history by the comparison unit 20 at each successive comparison step. The potential fluctuation of the reference potential supply line due to the setting change of the switches SW _{0 to} SW _N-1 of the DA converter 10B is suppressed. The charge injection unit 50 is as described above.

In the AD converter 1B, in the initialization step, the switch 40 is turned on to initialize CTOP to VCM, and the input analog data Ain is held in each capacitor element C _n by the setting of each switch SW _n. The The AD converter 1B can perform the same operation as that of the above-described AD converter 1A in each successive comparison step after the initialization step.

FIG. 9 is a diagram illustrating a circuit example of each switch SW _n of the AD converter 1B. Each switch SW _n includes a switch SW _A , a switch SW _H and a switch SW _L. These switches can be constituted by MOS transistors in which conduction / non-conduction between the source and the drain is set according to the magnitude of the gate voltage.

Switch SW _H is provided between the VREFH supply line and the capacitor C _n. The switch SW _H is controlled to be turned on / off based on a signal output from the gate circuit G1. Switch SW _L is provided between the VREFL supply line and the capacitor C _n. The switch SW _L is controlled to be turned on / off based on a signal output from the gate circuit G2. Switch SW _A is provided between the line and the capacitor C _n input analog data Ain is input. The switch SW _A is controlled to be turned on / off based on the signal ASW.

The gate circuit G1 receives the signal Cntl and signal ACT, providing a signal having a value of logical product of the values of these two input signals to the switch SW _H. The gate circuit G2 inputs the logic inversion signal and signal ACT signal Cntl, providing a signal having a value of logical product of the values of these two input signals to the switch SW _L. The gate circuits G1 and G2 are preferably provided in the DA converter 10B.

Cntl is any bit of Ccode that is a binary code or any bit of a thermometer code obtained by decoding Ccode. When ASW is at a high level, the input analog data Ain is held in the capacitor element C _n. When ASW is at a low level and ACT is at a high level, the capacitive element C _n is connected to the first reference potential VREFH or the second reference potential VREFL depending on the value of Cntl.

FIG. 10 is a timing chart for explaining the operation of each switch SW _n of the AD converter 1B. In this figure, RST is a signal for setting on / off of the switch 40. After ACT changes from high level to low level, ASW changes from low level to high level, and RST also changes from low level to high level. After RST changes from high level to low level, ASW changes from high level to low level, and then ACT changes from low level to high level.

After ACT changes from high level to low level, ASW changes from low level to high level, and RST also changes from low level to high level. After RST goes from high to low, ASW goes from high to low. In the initialization step, the duration RST and ASW is at a high level, the switch 40 is turned on, CTOP is initialized to VCM, the input analog data Ain each capacitive element C _n is held.

By such a switching operation, it is possible to avoid a through current from flowing between the line to which the input analog data Ain is input and the reference potential supply line, and the capacitance elements C _n are held. It is possible to prevent the input analog data Ain from leaking.

(Third configuration example)
FIG. 11 is a diagram illustrating a configuration of the AD converter 1C. The AD converter 1C of the third configuration example shown in this figure includes a first DA conversion unit 11, a second DA conversion unit 12, a comparison unit 20, a control unit 30C, a switch 41, a switch 42, and a charge injection unit 50. The AD converter 1C receives differential analog data (Ain1, Ain2), and outputs digital data corresponding to the difference between the first input analog data Ain1 and the second input analog data Ain2 from the control unit 30C.

  The first DA converter 11 and the second DA converter 12 in the third configuration example have the same configuration as the DA converter 10B in the second configuration example described above. The first DA converter 11 receives the first input analog data Ain1. The second DA converter 12 receives the second input analog data Ain2.

The N switches SW _{0 to} SW _N−1 of the _first DA converter 11 are set based on the first control signal output from the controller 30C. The first DA converter 11 holds the first input analog data Ain1 by the N capacitive elements C _{0 to} C _{N-1 and then} sets the first input corresponding to the setting of each of the _N switches SW _{0 to} SW _N-1 . The data CTOP1 is output to the comparison unit 20.

The N switches SW _{0 to} SW _N−1 of the second DA converter 12 are set based on the second control signal output from the controller 30C. The second DA converter 12 holds the second input analog data Ain2 by the N capacitive elements C _{0 to} C _N−1 , and then the second DA corresponding to the setting of each of the _N switches SW _{0 to} SW _N−1 . The data CTOP2 is output to the comparison unit 20.

N is an integer of 2 or more, and n is an integer of 0 or more and (N-1) or less. Further, in each of the first DA converter 11 and the second DA converter 12, the first end of any _one of the _N capacitors C _{0 to} C _N-1 may be set to a constant potential, In some cases, a switch corresponding to the capacitive element is not necessary.

  The comparison unit 20 compares the data input to each of the two input terminals, and outputs a comparison signal representing the comparison result to the control unit 30C. In the third configuration example, the comparison unit 20 inputs the first data CTOP1 output from the first DA conversion unit 11 to one input terminal and the second data CTOP2 output from the second DA conversion unit 12 to the other input. Enter at the end. The switch 41 is provided between one input terminal of the comparison unit 20 and the reference level VCM supply line. The switch 42 is provided between the other input terminal of the comparison unit 20 and the reference level VCM supply line. The reference level VCM is, for example, an average value of the first reference potential VREFH and the second reference potential VREFL. Alternatively, the reference level VCM may be set to a value at which the comparison unit 20 can operate with the highest performance (for example, high sensitivity and high SN ratio).

  Based on the comparison signal output from the comparison unit 20, the control unit 30C performs the first control signal and the second control so that the difference between the first data CTOP1 and the second data CTOP2 is reduced at each successive comparison step. A signal is generated, the first control signal is output to the first DA converter 11, and the second control signal is output to the second DA converter 12.

The charge injection unit 50 injects a certain amount of charge into the VREFH supply line or the VREFL supply line at any step of the successive comparison regardless of the comparison result history by the comparison unit 20 at each successive comparison step. The potential fluctuation of the reference potential supply line accompanying the change in setting of the switches SW _{0 to} SW _N−1 of the _first DA converter 11 and the second DA converter 12 is suppressed. The charge injection unit 50 is as described above.

In the AD converter 1C, in the initialization step, with both both turned on CTOP1, CTOP2 the switches 41 and 42 are initialized to VCM, setting of the switches SW _n In a 1DA converter 11 the first input analog data Ain1 each capacitive element C _n is held, the second input analog data Ain2 is held in the capacitors C _n by the setting of the switches SW _n in a 2DA converter 12 by. The AD converter 1C operates as follows, for example, in each successive comparison step after the initialization step.

FIG. 12 is a table for explaining an operation example of the AD converter 1C. FIG. 12A shows the operation of the first DA converter 11 of the AD converter 1C. FIG. 12B shows the operation of the second DA converter 12 of the AD converter 1C. In this operation example, N = 8, and the capacitance values of the eight capacitive elements C _{0 to} C ₇ are C. In this operation example, the connection of each capacitive element is determined based on a thermometer code obtained by decoding Ccode [c2, c1, c0]. Ccode2 given from the control unit 30C to the second DA conversion unit 12 is obtained by inverting the polarity of each bit of Ccode1 given from the control unit 30C to the first DA conversion unit 11.

In this operation example, in each step of the successive approximation, any of the eight capacitive elements C _{0 to} C ₇ is connected to the first reference potential VREFH or the second reference potential VREFL. The operation of the first DA converter 11 is the same as the operation example of the AD converter 1A described with reference to FIG. The second data CTOP2 output from the second DA converter 12 is a two's complement with respect to the second data CTOP1 output from the first DA converter 11.

  FIG. 13 is a timing chart for explaining an operation example of the AD converter 1C. In this operation example, digital data to be output is 5-bit data, and redundant steps are inserted between steps 3 and 4 in steps 1 to 5 of the successive comparison. In each successive comparison step, a predetermined amount of charge is injected into the VREFH supply line and the VREFL supply line by the charge injection unit 50.

  NSW1 is a signal given from the control unit 30C to inject charges by the charge injection unit 50 in step 1. When ACT goes high, NSW1 also goes high. During the period of step 1, NSW1 is at a high level. NSW2 is a signal given from the control unit 30C to inject charges by the charge injection unit 50 in step 2. During step 2, NSW2 is at a high level. However, the accuracy of the timing of NSW1 and NSW2 is not required. This is because the response of the buffer that generates the first reference potential VREFH and the second reference potential VREFL is slow.

  This figure shows the difference (VREFH−) between the first reference potential VREFH and the second reference potential VREFL for each of the example (when the charge injection unit 50 is operated) and the comparative example (when the charge injection unit 50 is not operated). The time change of VREFL) is schematically shown. Actually, the time waveform of the reference potential difference differs depending on the comparison result history or the like by the comparison unit 20 for each successive comparison step, but the time waveform of the reference potential difference as shown in FIG. In each step, the comparison timing by the comparison unit 20 is indicated by an arrow, and the charge injection timing by the charge injection unit 50 is also indicated by an arrow.

  It is required that the fluctuation of the reference potential is settled by the timing of comparison by the comparison unit 20 in each step (for example, near the center of the period of each step). However, in the comparative example that does not use the charge injection unit, it is becoming more difficult to set the fluctuation of the reference potential by the comparison timing as the AD converter increases in speed and accuracy. The charge injection unit 50 is provided to cope with such a problem.

  In the embodiment shown in this figure, the charge injection by the charge injection unit 50 is overcompensated, the fluctuation range of the reference potential is made as small as possible at the comparison timing by the comparison unit 20 in each step, and the reference in the subsequent step is performed. The fluctuation range of the potential is reduced.

  In the embodiment shown in this figure, NSW1 is set to the high level only during the period of step 1, and NSW1 is changed to the low level at the end of step 1. Similarly, NSW2 is set to the high level only during the period of step 2, and NSW2 is changed to the low level at the end of step 2. By doing so, the charge storage capacitor part of the charge injection part 50 is disconnected from the reference potential supply line at an early stage, and the time available for charge storage can be increased. As a result, the current flowing to the charge storage capacitor portion of the charge injection portion 50 can be reduced, which can contribute to the reduction of power supply noise. If it is difficult to finish the charge injection in one step, the NSW pulse width may be increased. In that case, there is no problem even if an overlap period occurs between NSW1 and NSW2.

  In the example shown in this figure, a redundant step is inserted between steps 3 and 4 in steps 1 to 5 of the successive comparison. It is preferable that the fluctuation of the reference potential is sufficiently settled by this redundant step. In order to do this, it is important to appropriately design the entire AD converter including not only the amount of charge injection but also other constraints.

  FIG. 14 is a diagram illustrating a simulation result of the operation of the AD converter 1C. In this simulation, it is assumed that digital data to be output is 12-bit data, two redundant steps are added to steps 1 to 12 of the successive approximation, and two steps are required for sampling and holding the input analog data. AD conversion processing for one input analog data is performed in a period of a total of 16 steps. Connection of each capacitive element of the DA converter is set based on a thermometer code obtained by decoding 12-bit Ccode and a redundant control signal. In this configuration, the second end of each capacitive element of the DA conversion unit is connected to the input end of the comparison unit, and the input analog data Ain is input to the first end of each capacitive element of the DA conversion unit.

  In each of the successive comparison steps 1, 2, 3, 5, 7, and 8, a predetermined amount of charge is injected into the VREFH supply line and the VREFL supply line by the charge injection unit 50, respectively. The charge injection amount is adjusted so that the fluctuation width remains as close to the center as possible. This is because it is desirable that all the centers of the variation range of each step are aligned since the redundancy correction capability is made symmetrical in the vertical direction.

  This figure shows the results when AD conversion processing is performed on input analog data of various values for each of the example (when the charge injection unit 50 is operated) and the comparative example (when the charge injection unit 50 is not operated). The time change of the difference (VREFH−VREFL) between the first reference potential VREFH and the second reference potential VREFL is shown in an overlapping manner. The fluctuation range of the reference potential at the timing of comparison by the comparison unit 20 in each step (near the center of the period of each step) is smaller in the embodiment than in the comparative example. The effect obtained by charge injection is significant in the first step 1 and step 2 of the successive approximation.

(Modification)
The present invention is not limited to the above embodiment, and various modifications can be made. The concept of the present invention can be applied to all successive approximation AD converters. For example, a redundant step may be inserted during or at the end of the successive approximation step.

  In the AD converters of the second and third configuration examples described above, the second end of each capacitive element of the DA conversion unit is connected to the input end of the comparison unit, and is connected to the first end of each capacitive element of the DA conversion unit. It was a configuration of bottom plate sampling in which input analog data Ain was input. The AD converter may have a configuration of top plate sampling in which input analog data is input to the second end of each capacitive element of the DA conversion unit connected to the input end of the comparison unit.

DESCRIPTION OF SYMBOLS 1A-1C ... AD converter, 10A, 10B ... DA converter, 11 ... 1st DA converter, 12 ... 2nd DA converter, 20 ... Comparison part, 30A-30C ... Control part, 40-42 ... Switch, 50- 53 ... Charge injection unit, 101, 102 ... Capacitor unit, 111, 112, 121, 122 ... Switch, 201, 202 ... Capacitor unit, 211, 212 ... PMOS transistor, 221, 222 ... NMOS transistor, 231 ... NMOS transistor, 232 ... PMOS transistors, 241,242 ... resistors, 251,252 ... current limiting circuits, 261,262 ... inverter circuits, 301,302 ... capacitors, 311 ... PMOS transistors, 312 ... NMOS transistors, 321 ... PMOS transistors, 322 ... NMOS transistor, 331-335, 341, 342 351,352 ... inverter circuit, 361 and 362 ... NAND gate circuit, 363 ... inverter _circuit, C 0 _{~C N-1} ... capacitive _element, SW 0 _{~SW N-1} ... switch.

Claims (10)

A successive approximation AD converter that outputs digital data corresponding to input analog data,
Including a plurality of capacitive elements and a plurality of switches set based on a control signal, by setting all or a part of the plurality of switches,
The first end of the capacitive element corresponding to the switch among the plurality of capacitive elements is used as the first reference potential or the second reference potential, and data corresponding to the setting of each of the plurality of switches is used for A DA converter that outputs from an output end that is commonly connected to the second end of
A comparison unit that compares the data output from the DA conversion unit with the input analog data and outputs a comparison signal representing the comparison result;
Based on the comparison signal, a control unit that generates and outputs the control signal so that the difference between the data output from the DA conversion unit and the input analog data is reduced at each successive comparison step;
In any step of the successive approximation, a constant amount is applied to the reference potential supply line that supplies the first reference potential or the second reference potential to the DA converter, regardless of the history of the comparison results for each successive comparison step. A charge injection unit that injects electric charge and suppresses potential fluctuations of the reference potential supply line due to setting changes of the plurality of switches of the DA conversion unit;
An AD converter comprising: A successive approximation AD converter that outputs digital data corresponding to input analog data,
Including a plurality of capacitive elements and a plurality of switches set based on a control signal, and after holding the input analog data by the plurality of capacitive elements, all or some of the plurality of switches By setting the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements as a first reference potential or a second reference potential, data corresponding to the setting of each of the plurality of switches is obtained. A DA converter that outputs from an output end in which the second ends of the capacitive elements are connected in common;
A comparison unit that compares the data output from the DA conversion unit with a reference level and outputs a comparison signal representing the comparison result;
Based on the comparison signal, a control unit that generates and outputs the control signal so that a difference between the data output from the DA conversion unit and the reference level is reduced at each successive comparison step;
In any step of the successive approximation, a constant amount is applied to the reference potential supply line that supplies the first reference potential or the second reference potential to the DA converter, regardless of the history of the comparison results for each successive comparison step. A charge injection unit that injects electric charge and suppresses potential fluctuations of the reference potential supply line due to setting changes of the plurality of switches of the DA conversion unit;
An AD converter comprising: A successive approximation AD converter that outputs digital data corresponding to a difference between first input analog data and second input analog data,
A plurality of capacitive elements and a plurality of switches set based on a first control signal, and after holding the first input analog data by the plurality of capacitive elements, all or one of the plurality of switches. A first terminal corresponding to the setting of each of the plurality of switches, with the first end of the capacitive element corresponding to the switch among the plurality of capacitive elements being a first reference potential or a second reference potential. A first DA converter that outputs data from an output end formed by connecting a second end of each of the plurality of capacitive elements in common;
A plurality of capacitive elements and a plurality of switches set based on a second control signal, and after holding the second input analog data by the plurality of capacitive elements, all or one of the plurality of switches. A second end corresponding to the setting of each of the plurality of switches, with the first end of the capacitor corresponding to the switch among the plurality of capacitors set as the first reference potential or the second reference potential. A second DA converter that outputs data from an output end formed by connecting a second end of each of the plurality of capacitive elements in common;
A comparison unit that compares the first data with the second data and outputs a comparison signal representing the comparison result;
A control unit that generates and outputs the first control signal and the second control signal based on the comparison signal so that the difference between the first data and the second data is reduced at each successive comparison step. When,
In any step of the successive approximation, a constant amount is applied to the reference potential supply line that supplies the first reference potential or the second reference potential to the DA converter, regardless of the history of the comparison results for each successive comparison step. A charge injection unit that injects electric charge and suppresses potential fluctuations of the reference potential supply line due to setting changes of the plurality of switches of the DA conversion unit;
An AD converter comprising: The charge injection unit injects charges into the reference potential supply line in at least the first step of successive comparison;
The AD converter of any one of Claims 1-3. The charge injection unit optimizes the amount of charge injected into the reference potential supply line as the successive comparison step proceeds.
The AD converter of any one of Claims 1-4. The charge injection unit injects a fixed amount of charge into a reference potential supply line that supplies the first reference potential to the DA conversion unit, and also applies to the reference potential supply line that supplies the second reference potential to the DA conversion unit. Inject a certain amount of electric charge,
The AD converter of any one of Claims 1-5. The charge injection part is
A capacitor having a first end and a second end; a first switch connecting the first end of the capacitor to the first power supply potential supply line or the reference potential supply line; and a second end of the capacitor Two power supply potential supply lines or a second switch connected to the first power supply potential supply line,
The first switch connects the first end of the capacitor to the first power supply potential supply line, and the second switch connects the second end of the capacitor to the second power supply potential supply line. Accumulate charges in the capacitor part,
The first switch connects the first end of the capacitor to the reference potential supply line, and the second switch connects the second end of the capacitor to the first power supply potential supply line. Injecting the charge accumulated in the part into the reference potential supply line,
The AD converter of any one of Claims 1-6. The charge injection part is
A capacitor having a first end and a second end, the first end being connected to the reference potential supply line, and performing charge accumulation or charge injection into the reference potential supply line according to the level of the second end;
An inverter circuit having an output terminal connected to the second end of the capacitor unit, to which a signal for controlling charge accumulation and charge injection in the capacitor unit is input;
A current limiting circuit for limiting a magnitude of a current flowing between an output terminal of the inverter circuit and a second terminal of the capacitor unit when charge accumulation is started after charge injection in the capacitor unit;
including,
The AD converter of any one of Claims 1-6. The charge injection part is
A capacitor having a first end and a second end, a first switch provided between the first end of the capacitor and the reference potential supply line, a first end of the capacitor and a power supply potential supply line A second switch provided between and
By storing the first switch in an off state and the second switch in an on state, electric charge is accumulated in the capacitor unit,
The first switch is turned on and the second switch is turned off to inject the charge accumulated in the capacitor portion into the reference potential supply line.
The AD converter of any one of Claims 1-6. The capacity value of the capacity section is variable.
The AD converter of any one of Claims 7-9.

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