JP2019186819A - Solid-state imaging device - Google Patents

Abstract

To solve a problem in which, in a system in which a driving circuit is arranged on one side of a pixel array, it takes time to charge or discharge a pixel control line to the opposite side of the pixel array, and therefore, a high frame rate cannot be realized.SOLUTION: A first driving unit 200 is disposed adjacent to one end of a pixel array 100 in the row direction, is connected to one end of a plurality of pixel control lines CL1 to CLn, and drives the pixel control line CLi in the selected row i of the pixel array 100. A second driving unit 300 is disposed adjacent to the other end of the pixel array 100 in the row direction, is connected to the other end of each of the plurality of pixel control lines CL1 to CLn, and drives the pixel control line CLi in which a change in the voltage level at the other end is detected from the other end.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state imaging device, for example, a technology for driving pixels of a solid-state imaging device.

  A solid-state imaging device (also referred to as an image sensor) has a pixel array in which a plurality of pixels are arranged in a matrix. A pixel control line is provided in each row of the pixel array. By driving the pixel control line, the pixel connected to the pixel control line can be driven. A driving circuit for driving the pixel control line is disposed on the left side or the right side adjacent to the pixel array (see, for example, Patent Document 1).

JP 2009-89069 A

  However, in the system in which the drive circuit is arranged on one side of the pixel array, it takes time to charge or discharge the pixel control line to the opposite side of the pixel array. As a result, a high frame rate cannot be realized.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

  In one embodiment, the solid-state imaging device is disposed adjacent to one end of the pixel array in the row direction, and is connected to one end of the plurality of pixel control lines, and drives the pixel control line of the selected row of the pixel array. 1 is arranged adjacent to the other end of the pixel array in the row direction and connected to the other end of each of the plurality of pixel control lines, and a pixel control in which a change in the voltage level of the other end is detected. A second drive unit that drives the wire from the other end.

  According to the solid-state imaging device of one embodiment, it is possible to cope with a high frame rate.

It is a figure showing the structure of the solid-state imaging device 500 of 1st Embodiment. It is a figure showing the structure of the solid-state imaging device 110 of 2nd Embodiment. 2 is a diagram illustrating a pixel P (i, j) in the pixel array 10. FIG. It is a figure showing the structure of a part of solid imaging device (reference example 1) of a one side drive system. 7 is a diagram illustrating a configuration for driving reset transistors MR in a plurality of pixels in the first row of the pixel array 10 of Reference Example 1. FIG. 6 is a diagram illustrating an equivalent circuit of a pixel control line R1 and a reset transistor MR in a plurality of pixels in Reference Example 1. FIG. It is a figure showing the operation | movement waveform of each node in FIG. It is a figure showing the structure of a part of solid-state imaging device (reference example 2) of a both-side drive system. It is a figure showing a part of structure of the solid-state imaging device 110 of 2nd Embodiment. It is a figure showing the structure of drive auxiliary circuit CR1 and driver DRR1R of 2nd Embodiment. It is a figure showing an example of the timing waveform of the control signal of 2nd Embodiment. It is a figure showing the structure for driving the reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 2nd Embodiment. FIG. 6 is a diagram illustrating a pixel control line R1 and reset transistors MR in a plurality of pixels in an equivalent circuit according to the second embodiment. FIG. 13 is a diagram illustrating an operation waveform of each node in FIG. 12. It is a figure showing the structure for driving the reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 3rd Embodiment from the right side. It is a figure showing the structure for driving the selection transistor MS in the some pixel of the 1st row of the pixel array 10 of 3rd Embodiment from the right side. It is a figure showing the structure for driving the transfer transistor MT in the some pixel of the 1st row of the pixel array 10 of 3rd Embodiment from the right side. It is a figure showing the structure for driving the reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 4th Embodiment. It is a figure showing the operation waveform of each node in FIG. It is a figure showing the example of the timing waveform of the control signal of 5th Embodiment. It is a figure showing the structure for driving the reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 5th Embodiment from the right side. It is a figure showing the drive of pixel control line R1-Rn by 5th Embodiment. It is a figure showing the timing of the control signal of 6th Embodiment. It is a figure showing the structure for driving the reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 5th Embodiment from the right side. It is a figure showing the drive of pixel control line R1-Rn by 6th Embodiment. It is a figure showing the structure for starting up the reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 7th Embodiment from the right side. It is a figure showing the structure for falling down reset transistor MR in the some pixel of the 1st row of the pixel array 10 of 8th Embodiment from the right side. It is a figure showing the structure for driving the transfer transistor MT in the some pixel of the 1st row of the pixel array 10 of 9th Embodiment from the right side. It is a figure for comparing the rise and fall timing of node # 4 of the third embodiment and the ninth embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram illustrating a configuration of a solid-state imaging device 500 according to the first embodiment.

  The solid-state imaging device 500 includes a pixel array 100, pixel control lines CLi (i = 1 to n), a first driving unit 200, and a second driving unit 300.

  The pixel array 100 includes a plurality of pixels P (i, j) (i = 1 to n, j = 1 to m) that perform photoelectric conversion arranged in a matrix.

  The pixel control line CLi is connected to the pixels P (i, 1) to P (i, m) in the corresponding row in the pixel array 100.

  The first driving unit 200 is disposed adjacent to one end of the pixel array 100 in the row direction, and is connected to one end of the plurality of pixel control lines CL1 to CLn, so that the pixel control of the selected row i of the pixel array 100 is performed. Drive the line CLi.

  The second driving unit 300 is disposed adjacent to the other end of the pixel array 100 in the row direction, and is connected to the other end of each of the plurality of pixel control lines CL1 to CLn, and the voltage level of the other end changes. The pixel control line CLi in which is detected is driven from the other end.

  As described above, according to the present embodiment, it is possible to shorten the time for charging or discharging the pixel control line rather than driving the pixel control line from one side.

[Second Embodiment]
FIG. 2 is a diagram illustrating the configuration of the solid-state imaging device 110 according to the second embodiment.

  The solid-state imaging device 110 includes a pixel array 10, a vertical scanning circuit 111, a pixel signal readout line VEL, a current source circuit group 115, an A / D converter group 116, a horizontal scanning circuit 117, a digital signal processor 114, and a timing generation circuit. 1 and a bias voltage generation circuit 118.

  The pixel array 10 includes (n × m) pixels P (i, j) arranged in a matrix. i = 1 to n and j = 1 to m. The pixel P (i, j) accumulates an amount of charge corresponding to the amount of received light. The pixel signal readout line VEL is wired in the vertical direction and connected to the pixel P (i, j).

  The current source circuit group 115 includes a current source circuit 102 connected to the pixel P (i, j) for each column.

  The timing generation circuit 1 generates various timing signals for controlling the operation timing of the circuits in the pixel array 10 and the current source circuit group 115, and sends them to the pixel array 10 and the current source circuit group 115 via the vertical scanning circuit 111. Output.

  The bias voltage generation circuit 118 generates various bias voltages and supplies them to the current source circuit group 115.

  The voltage signal read from the pixels in the selected row in the pixel array 10 by the vertical scanning circuit 111 is digitally converted by the A / D converter in the A / D converter group 116. The horizontal scanning circuit 117 sequentially selects A / D converters arranged for each column, whereby the digitally converted pixel signals are read out to the digital signal processor 114 and then output from the solid-state imaging device 110. .

FIG. 3 is a diagram illustrating the pixel P (i, j) in the pixel array 10.
The pixel P (i, j) includes a photodiode PD, a transfer transistor MT, a reset transistor MR, an amplification transistor MD, and a selection transistor MS.

  The photodiode PD is a photoelectric conversion element that photoelectrically converts and stores an amount of charge corresponding to the amount of incident light. The floating diffusion FD generates a voltage corresponding to the charge accumulated in the photodiode PD.

  The transfer transistor MT is connected between the photodiode PD and the floating diffusion FD. Transfer transistor MT is formed of an N-channel MOS transistor. The gate of the transfer transistor MT is connected to a pixel control line Ti for transfer transistor control. When the transfer transistor MT is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD.

  Reset transistor MR is formed of an N-channel MOS transistor. The reset transistor MR is connected between the voltage VDD, the power supply, and the floating diffusion FD. The gate of the reset transistor MR is connected to a pixel control line Ri for reset transistor control. When the reset transistor MR is turned on, the voltage of the floating diffusion FD is reset to the power supply voltage VDD.

  The amplification transistor MD is formed of an N channel MOS transistor. The amplification transistor MD has a gate connected to the floating diffusion FD, a drain connected to the power supply VDD, and a source.

  Select transistor MS is formed of an N-channel MOS transistor. The selection transistor MS is connected between the source of the amplification transistor MD and the pixel signal readout line VEL. The gate of the selection transistor MS is connected to a pixel control line Si for selection transistor control. When the selection transistor MS is turned on, the voltage amplified by the amplification transistor MD is output to the pixel signal readout line VEL.

FIG. 4 is a diagram illustrating a partial configuration of a one-sided drive type solid-state imaging device (Reference Example 1).
The timing generation circuit 1 controls activation and deactivation of the reset control signal RST_common, the transfer control signal TX_common, and the selection control signal SEL_common common to all the rows in the pixel array 10.

  The vertical scanning circuit 111 includes a row selection circuit 4, a level shifter group 2, and a driver group 3.

  The row selection circuit 4 selects one row from a plurality of rows in the pixel array 10. When the row selection circuit 4 selects the i-th row, the row selection circuit 4 activates or deactivates the reset control signal RST_i for the i-th row according to the level of the reset control signal RST_common common to all the rows. When the row selection circuit 4 selects the i-th row, the row selection circuit 4 activates or deactivates the transfer control signal TX_i for the i-th row according to the level of the transfer control signal TX_common common to all the rows. When selecting the i-th row, the row selection circuit 4 activates or deactivates the selection control signal SEL_i for the i-th row according to the level of the selection control signal SEL_common common to all the rows.

  The level shifter group 2 includes a level shifter LSRi for reset control, a level shifter LSTi for transfer control, and a level shifter LSSi for selection control corresponding to the i-th row of the pixel array 10. The level shifter LSRi amplifies the level of the reset control signal RST_i to a voltage for driving the reset transistor MR in the pixel. The level shifter LSTi amplifies the level of the transfer control signal TX_i to a voltage for driving the transfer transistor MT in the pixel. The level shifter LSSi amplifies the level of the selection control signal SEL_i to a voltage for driving the selection transistor MS in the pixel.

  The driver group 3 includes a driver DRRiL for reset control, a driver DRTiL for transfer control, and a driver DRSiL for selection control corresponding to the i-th row of the pixel array 10. The driver DRRiL includes an input terminal that receives the voltage amplified by the level shifter LSRi, and an output terminal that is connected to one end of the pixel control line Ri. The driver DRTiL includes an input terminal that receives the voltage amplified by the level shifter LSTi, and an output terminal that is connected to one end of the pixel control line Ti. The driver DRSiL includes an input terminal that receives the voltage amplified by the level shifter LSSi, and an output terminal that is connected to the other end of the pixel control line Si.

  FIG. 5 is a diagram illustrating a configuration for driving the reset transistors MR in the plurality of pixels in the first row of the pixel array 10 of Reference Example 1. FIG. 6 is a diagram showing the pixel control line R1 in Reference Example 1 and the reset transistors MR in a plurality of pixels by an equivalent circuit. FIG. 7 is a diagram showing operation waveforms of each node in FIG.

  The configurations and operations of the reset transistor MR and the pixel control line Ri in the plurality of pixels in the i-th row (i ≠ 1) are the same as these. Further, the configurations and operations of the transfer transistor MT and the pixel control line Tj (j = 1 to n), the selection transistor MS and the pixel control line Sj (j = 1 to n) are the same as these.

  5 to 7, the timing generation circuit 1 raises the reset control signal RST_common at time T0. The row selection circuit 4 raises the reset control signal RST_1 based on the input reset control signal RST_common and outputs it to the node # 1. The level shifter LSR1 amplifies the reset control signal RST_1 and outputs the amplified reset control signal RST_1 ′ to the node # 2. The driver DRR1L drives the pixel control line R1 based on the reset control signal RST_1 ′.

  Since the node # 1 and the node # 2 have almost no load to be driven, the signal is transmitted almost without dullness. As shown in FIG. 6, the CR load caused by the reset transistor MR and the pixel control line R1 in the pixel is charged with the current I1 from the driver DRR1L. Since node # 3 is positioned in the immediate vicinity of the output of driver DRR1L, the voltage at node # 3 has a slightly dull waveform. The node # 4 at the right end of the pixel control line R1 is the farthest from the driver DRR1L, and is affected by the CR load caused by the reset transistors MR and long-distance wiring of all the pixels in one row. Becomes a dull waveform. Time T1 is required to charge node # 4 to voltage VH. Furthermore, since the pixel drive is intended for potential control under the gate, a full swing of the signal is required, and the influence of the CR time constant appears remarkably. For example, an ordinary logic circuit can be sufficiently operated with a voltage amplitude of about 10% to 90%, but in order to drive a pixel, it is not operated with an amplitude of 0% to 100% (ie, If the pixel control line R1 is not charged to VH), a reset failure occurs. Further, when the transfer transistor MT is driven, a charge transfer residue occurs unless it is operated with an amplitude of 0% to 100%.

  When the timing generation circuit 1 falls the reset control signal RST_common at time T1, the node # 1 and the node # 2 have almost no load to be driven, and thus the signal is transmitted almost without dullness. Since node # 3 is positioned in the immediate vicinity of the output of driver DRR1L, the voltage at node # 3 has a slightly dull waveform. The node # 4 at the right end of the pixel control line R1 is the farthest from the driver DRR1L, and is affected by the CR load caused by the reset transistors MR and long-distance wiring of all the pixels in one row. Becomes a dull waveform.

  As described above, in the one-side drive method of Reference Example 1, since it takes time to charge or discharge the rightmost node # 4 of the pixel control line, a high frame rate cannot be realized.

FIG. 8 is a diagram illustrating a partial configuration of a solid-state imaging device (Reference Example 2) of a both-side drive method.
In the reference example 2, the row selection circuit 4, the level shifter group 2, and the driver group 3 are arranged on the left side of the pixel array 10 as in the reference example 1. In Reference Example 2, a row selection circuit 4a, a level shifter group 2a, and a driver group 3a are further arranged on the right side of the pixel array 10.

  Since the reference example 2 is driven from both sides, the supplied current can be increased as compared to the reference example 1, so that the time for driving the pixel control line Ri, the pixel control line Ti, and the pixel control line Si is shortened. Can do. On the other hand, in Reference Example 2, the row selection circuit, the level shifter group, and the driver group are required twice as much as in Reference Example 1. As a result, in Reference Example 2, the chip size increases and the cost increases. In addition, since the logic portion such as the row selection circuit is doubled, the power consumption is nearly doubled.

FIG. 9 is a diagram illustrating a part of the configuration of the solid-state imaging device 110 according to the second embodiment.
The solid-state imaging device 110 includes a pixel array 10, a timing generation circuit 1, and a vertical scanning circuit 111. The vertical scanning circuit 111 includes a first drive unit 81 and a second drive unit 82.

  The first drive unit 81 is disposed adjacent to one end (left end) in the row direction of the pixel array 10 and is connected to one end (left end) of the plurality of pixel control lines R1 to Rn, T1 to Tn, and S1 to Sn. Then, the pixel control lines Ri, Ti, Si of the selected row i of the pixel array 10 are driven. The first drive unit 81 includes the same row selection circuit 4, level shifter group 2, and driver group 3 as those in the first reference example.

  Since pixel array 10, timing generation circuit 1, row selection circuit 4, level shifter group 2, and driver group 3 are the same as in Reference Example 1, description thereof will not be repeated.

  The second driving unit 82 includes a level shifter group 6, a driving auxiliary unit 7, and a driver group 5. The second drive unit 82 is disposed adjacent to the other end (right end) in the row direction of the pixel array 10, and the other end of each of the plurality of pixel control lines R1 to Rn, T1 to Tn, and S1 to Sn ( The pixel control lines Ri, Ti, and Si, which are connected to the right end) and detected the change in voltage level at the other end, are driven from the other end (right end).

  The level shifter group 2 includes a level shifter LSR for reset control, a level shifter LST for transfer control, and a level shifter LSS for selection control that are commonly used for all the rows of the pixel array 10. The level shifter LSR amplifies the level of the reset control signal RST_common common to all rows to a voltage for driving the reset transistor MR in the pixel. The level shifter LST amplifies the level of the transfer control signal TX_common common to all the rows to a voltage for driving the transfer transistor MT in the pixel. The level shifter LSS amplifies the level of the selection control signal SEL_common common to all rows to a voltage for driving the selection transistor MS in the pixel.

  The drive assisting unit 7 corresponds to the i-th row of the pixel array 10, and includes a drive assist circuit CRi for controlling the reset transistor, a drive assist circuit CTi for controlling the transfer transistor, and a drive assist circuit CSi for controlling the selection transistor. Is provided.

  The driver group 5 includes a reset transistor control driver DRRiR, a transfer transistor control driver DRTiR, and a selection transistor control driver DRSiR corresponding to the i-th row of the pixel array 10.

  The drive assist circuit CRi controls the output of the driver DRRiR based on the voltage of the level shifter LSR and the voltage of the pixel control line Ri. The driver DRRiR is connected to the right end of the pixel control line Ri, and drives the pixel control line Ri from the right end in accordance with the driving assistance of the driving assistance circuit CRi. The drive assist circuit CTi controls the output of the driver DRTiR based on the voltage of the level shifter LST and the voltage of the pixel control line Ti. The driver DRTiR is connected to the right end of the pixel control line Ti, and drives the pixel control line Ti from the right end in accordance with the driving assistance of the driving assistance circuit CTi. The drive assist circuit CSi controls the output of the driver DRSiR based on the voltage of the level shifter LSS and the voltage of the pixel control line Si. The driver DRSiR is connected to the right end of the pixel control line Si, and drives the pixel control line Si from the right end in accordance with the driving assistance of the driving assistance circuit CSi.

  FIG. 10 is a diagram illustrating the configuration of the drive assist circuit CR1 and the driver DRR1R according to the second embodiment. The configurations of the drive assist circuit CRi (i ≠ 1) and the driver DRRiR are the same as this. Further, the configurations of the drive assist circuit CTj and the driver DRTjR and the configurations of the drive assist circuit CSj and the driver DRSjR are the same. Here, j = 1 to n.

  The driver DRR1R includes a PMOS transistor P1 and an NMOS transistor P1 connected in series between the power supply of the voltage VH and the power supply of the voltage VL.

  The drive assist circuit CR1 includes a NAND circuit 91 and a NOR circuit 92. The input terminal A of the NAND circuit 91 receives the output of the level shifter LSR. The input terminal B of the NAND circuit 91 is connected to the right end of the pixel control line R1. The output terminal C of the NAND circuit 91 is connected to the gate of the PMOS transistor P1. The input terminal A of the NOR circuit 92 receives the output of the level shifter LSR. The input terminal B of the NOR circuit 92 is connected to the right end of the pixel control line R1. The output terminal C of the NOR circuit 92 is connected to the gate of the NOS transistor N1.

FIG. 11 is a diagram illustrating an example of a timing waveform of a control signal according to the second embodiment.
The common reset control signal RST_common, the transfer control signal TX_common, and the selection control signal SEL_common are activated by the timing generation circuit 1 at a periodically determined timing.

  The row selection circuit 4 selects a first row from a plurality of rows in the pixel array 10 in the first period. The row selection circuit 4 selects the reset control signal RST_1, the transfer control signal TX_1, and the transfer control signal TX_1 of the first row selected according to the levels of the reset control signal RST_common, the transfer control signal TX_common, and the selection control signal SEL_common received from the timing generation circuit 1. The selection control signal SEL_1 is activated or deactivated.

  The row selection circuit 4 selects the i-th row from a plurality of rows in the pixel array 10 for the i-th cycle. The row selection circuit 4 receives the reset control signal RST_i, the transfer control signal TX_i, and the selection control for the i-th row according to the levels of the reset control signal RST_common, the transfer control signal TX_common, and the selection control signal SEL_common received from the timing generation circuit 1. The signal SEL_i is activated or deactivated.

  The above timing example is for the case where each row of the pixel array 10 is selected one by one in order. However, a plurality of rows of the pixel array 10 may be selected simultaneously, and a plurality of rows of the pixel array may be selected. It is good also as what selects one line at a random order.

  Next, an operation when the voltage of the pixel control line R1 is raised from the right end will be described. The operation when raising other pixel control lines from the right end is the same as this.

  First, the high-level reset control signal RST_common amplified by the timing generation circuit 1 and the level shifter LSR is input to the input terminal A of the NAND circuit 91 and the input terminal A of the NOR circuit 92. Since the voltage at the input terminal B connected to the pixel control line R1 is low level, the output of the NAND circuit 91 is high level. Therefore, the PMOS transistor P1 is off. Since a high level voltage is input to the input terminal A of the NOR circuit 92, the output of the NOR circuit 92 is at a low level. Therefore, the NMOS transistor N1 is off.

  Next, the voltage at the right end of the pixel control line R1 rises gently by the level shifter LSR1 and the driver DRR1L on the left side of the pixel array 10, and the right end of the pixel control line R1 connected to the input terminal B of the NAND circuit 91 is increased. When the voltage rises to the threshold value VTN of the NAND circuit 91, the output of the NAND circuit 91 becomes low level. As a result, the PMOS transistor P1 is turned on. On the other hand, the output of the NOR circuit 92 maintains the low level regardless of the increase in the voltage at the right end of the pixel control line R1. Therefore, the NMOS transistor N1 is kept off.

  Next, the driver DRR1R connects the right end of the pixel control line R1 to the power source of the voltage VH, and the right end of the pixel control line R1 is also charged by the current from the driver DRR1R. As a result, the voltage at the right end of the pixel control line R1 rises steeply to the voltage VH.

  Next, an operation when the voltage of the pixel control line R1 falls from the right side will be described. The operation when the other pixel control lines are lowered from the right end is the same as this.

  First, the low-level reset control signal RST_common is input to the input terminal A of the NAND circuit 91 and the input terminal A of the NOR circuit 92 by the timing generation circuit 1 and the level shifter LSR. Since the voltage at the input terminal A is low, the output of the NAND circuit 91 is high. Therefore, the PMOS transistor P1 is off. Since the voltage at the input terminal B connected to the right end of the pixel control line R1 is at low level, the output of the NOR circuit 92 is at low level. Therefore, the NMOS transistor N1 is off.

  Next, the voltage at the right end of the pixel control line R1 in the first row gradually decreases by the left level shifter LSR1 and the driver DRR1L of the pixel array 10. When the voltage at the right end of the pixel control line R1 drops to (VH−VTP), the output of the NOR circuit 92 becomes high level. As a result, the NMOS transistor N1 is turned on. Here, VTP is a threshold voltage of the NOR circuit 92. On the other hand, the output of the NAND circuit 91 is maintained at a high level regardless of the decrease in the voltage at the right end of the pixel control line R1. Therefore, the PMOS transistor P1 is kept off.

  Next, the driver DRR1R connects the right end of the pixel control line R1 and the power supply of the voltage VL, and the pixel control line R1 is also discharged by the driver DRR1R. As a result, the right end voltage of the pixel control line R1 falls steeply to the voltage VL.

  FIG. 12 is a diagram illustrating a configuration for driving the reset transistors MR in a plurality of pixels in the first row of the pixel array 10 of the second embodiment. FIG. 13 is a diagram showing the pixel control line R1 and the reset transistors MR in a plurality of pixels in an equivalent circuit in the second embodiment. FIG. 14 is a diagram illustrating operation waveforms of the respective nodes in FIG.

The operation when the pixel control line R1 is started up will be described with reference to FIGS.
The timing generation circuit 1 raises the reset control signal RST_common at time T0. In response to the rise of the reset control signal RST_common, the row selection circuit 4 raises the reset control signal RST_1 and outputs it to the node # 1. The level shifter LSR1 amplifies the reset control signal RST_1 and outputs the amplified reset control signal RST_1 ′ to the node # 2. The driver DRR1L drives the pixel control line R1 based on the reset control signal RST_1 ′.

  Since the node # 1 and the node # 2 have almost no load to be driven, the signal is transmitted almost without dullness. As shown in FIG. 13, the CR load caused by the reset transistor MR and the pixel control line R1 in the pixel is charged with the current I1 from the driver DRR1L. Since node # 3 is positioned in the immediate vicinity of the output of driver DRR1L, the voltage at node # 3 has a slightly dull waveform. The rightmost node # 4 of the pixel control line R1 has the longest distance from the driver DRR1L and is affected by the CR load caused by the reset transistors MR and long-distance wiring of all the pixels in one row. The voltage at the right end gradually rises.

  On the other hand, at time T2, the voltage at the rightmost node # 4 of the pixel control line R1 rises to the threshold voltage VTN of the NAND circuit 91. As a result, after time T2, the CR load caused by the reset transistor MR and the pixel control line R1 in the pixel is charged with the current I2 from the driver DRR1R on the right side of the pixel array 10. As a result, the voltage at the node # 4 rises sharply. Here, for example, the voltage VH is 4 to 5V, while the threshold voltage VTN can be less than 1V. In such a case, the time until the voltage at the rightmost node # 4 of the pixel control line R1 reaches the threshold voltage VTN can be shortened.

The operation when the pixel control line R1 is lowered will be described with reference to FIGS.
The timing generation circuit 1 causes the reset control signal RST_common to fall at time T1. In response to the fall of the reset control signal RST_common, the row selection circuit 4 falls the reset control signal RST_1 and outputs it to the node # 1. The level shifter LSR1 amplifies the reset control signal RST_1 and outputs the amplified reset control signal RST_1 ′ to the node # 2. The driver DRR1L drives the pixel control line R1 based on the reset control signal RST_1 ′.

  Since the node # 1 and the node # 2 have almost no load to be driven, the signal is transmitted almost without dullness. Since node # 3 is positioned in the immediate vicinity of the output of driver DRR1L, the voltage at node # 3 has a slightly dull waveform. The rightmost node # 4 of the pixel control line R1 has the longest distance from the driver DRR1L and is affected by the CR load caused by the reset transistors MR and long-distance wiring of all the pixels in one row. The voltage at the right end gradually falls.

  On the other hand, at time T3, the voltage at the rightmost node # 4 of the pixel control line R1 falls to the threshold voltage (VH−VTP). As a result, after time T3, the charge accumulated by the reset transistor MR in the pixel and the CR load caused by the pixel control line R1 is discharged through the driver DRR1R on the right side of the pixel array 10. As a result, the voltage at the node # 4 falls sharply. Here, for example, the voltage VH is 4 to 5V, while the threshold voltage VTP can be less than 1V. In such a case, the time until the voltage at the rightmost node # 4 of the pixel control line R1 reaches the threshold voltage (VH−VTP) can be shortened.

  In this embodiment, the drive assist circuit detects the direction of change in potential at the right end of the pixel control line for reset transistor control, the pixel control line for transfer transistor control, and the pixel control line for control of the select transistor. Assist in changing quickly in the detected direction. In addition, since the power consumption and circuit scale of the row selection circuit are large, the power consumption and circuit scale are large in the double-side drive method of Reference Example 2, but in this embodiment, row selection is performed on both sides as in the double-side drive method. Since it is not necessary to provide a circuit, the power consumption and the circuit scale can be greatly reduced as compared with the double-side drive method. In this embodiment, a drive assist circuit is added, but since the number of transistors constituting the drive assist circuit is small, the increase in area due to the provision of the drive assist circuit is small.

[Third Embodiment]
FIG. 15 is a diagram illustrating a configuration for driving the reset transistors MR in the plurality of pixels in the first row of the pixel array 10 of the third embodiment from the right side. The configuration for driving the reset transistors MR in the pixels in the i-th row (i ≠ 1) from the right side is the same as this.

  The driver DRR1R includes a PMOS transistor P1 and an NMOS transistor P1 connected in series between the power supply of the voltage VH and the power supply of the voltage VL.

  The level shifter LSR includes PMOS transistors PT4 and PT5, NMOS transistors NT4 and NT5, and an inverter IV3.

  A PMOS transistor PT4 and an NMOS transistor NT4 are connected in series between the power supply of the voltage VH and the power supply of the voltage VL. A PMOS transistor PT5 and an NMOS transistor NT5 are connected in series between the power supply of the voltage VH and the power supply of the voltage VL.

  The gate of the PMOS transistor PT5 is connected to a node NDX between the PMOS transistor PT4 and the NMOS transistor NT4. The gate of the PMOS transistor PT4 is connected to a node between the PMOS transistor PT5 and the NMOS transistor NT5. The gate of NMOS transistor NT5 receives reset control signal RST_common. Inverter IV3 receives reset control signal RST_common. The gate of NMOS transistor NT4 receives the output of inverter IV3.

  The drive assist circuit CR1 includes an inverter IV1 including a PMOS transistor PT2 and an NMOS transistor NT2, an inverter IV2 including a PMOS transistor PT3 and an NMOS transistor NT3, an NMOS transistor NT1, and a PMOS transistor PT1.

  A PMOS transistor PT2, an NMOS transistor NT2, and an NMOS transistor NT1 are connected in series between the power supply of the voltage VH and the power supply of the voltage VL. A PMOS transistor PT1, a PMOS transistor PT3, and an NMOS transistor NT3 are connected in series between the power supply of the voltage VH and the power supply of the voltage VL. The input of inverter IV1 is connected to node NDX. The output of inverter IV1 is connected to the gate of PMOS transistor P1 in driver DRR1R. The input of inverter IV2 is connected to node NDX. The output of inverter IV2 is connected to the gate of NMOS transistor N1 in driver DRR1R. The gate of the NMOS transistor NT1 is connected to the pixel control line R1. The gate of the PMOS transistor PT1 is connected to the pixel control line R1.

In the above, for example, VH = 4.9V and VL = 0V can be set.
FIG. 16 is a diagram illustrating a configuration for driving select transistors MS in a plurality of pixels in the first row of the pixel array 10 of the third embodiment from the right side. The configuration for driving the selection transistors MS in a plurality of pixels in the i-th row (i ≠ 1) from the right side is the same as this.

  Driver DRS1R has the same configuration as driver DRR1R. However, the output of the driver DRS1R is connected to the pixel control line S1. The level shifter LSS has the same configuration as the level shifter LSR. However, the level shifter LSS receives the selection control signal SEL_common. The drive assist circuit CS1 has the same configuration as the drive assist circuit CR1. However, the gate of the NMOS transistor NT1 and the gate of the PMOS transistor PT1 of the drive assist circuit CS1 are connected to the pixel control line S1.

  FIG. 17 is a diagram illustrating a configuration for driving the transfer transistors MT in the plurality of pixels in the first row of the pixel array 10 of the third embodiment from the right side. The configuration for driving the transfer transistors MT in the pixels in the i-th row (i ≠ 1) from the right side is the same as this.

  The level shifter LTR includes PMOS transistors PT4 and PT5, NMOS transistors NT4 and NT5, and an inverter IV3. The level shifter LTR further includes PMOS transistors PT6 and PT7 and NMOS transistors NT6 and NT7.

  A PMOS transistor PT4 and an NMOS transistor NT4 are connected in series between the power supply of the voltage VH_H and the power supply of the voltage VH_L. A PMOS transistor PT5 and an NMOS transistor NT5 are connected in series between the power supply of the voltage VH_H and the power supply of the voltage VH_L. The gate of the PMOS transistor PT5 is connected to a node NDX1 between the PMOS transistor PT4 and the NMOS transistor NT4. The gate of the PMOS transistor PT4 is connected to a node between the PMOS transistor PT5 and the NMOS transistor NT5. The gate of NMOS transistor NT5 receives transfer control signal TX_common. Inverter IV3 receives transfer control signal TX_common. The gate of NMOS transistor NT4 receives the output of inverter IV3.

  A PMOS transistor PT6 and an NMOS transistor NT6 are connected in series between the power supply of the voltage VL_H and the power supply of the voltage VL_L. A PMOS transistor PT7 and an NMOS transistor NT7 are connected in series between the power supply of the voltage VL_H and the power supply of the voltage VL_L. The gate of the NMOS transistor NT7 is connected to a node NDX2 between the PMOS transistor PT6 and the NMOS transistor NT6. NMOS transistor NT6 has its gate connected to a node between PMOS transistor PT7 and NMOS transistor NT7. The gate of the PMOS transistor PT7 receives the transfer control signal TX_common. The gate of PMOS transistor PT6 receives the output of inverter IV3.

  The driver DRT1R includes a PMOS transistor P1 and an NMOS transistor N1 connected in series between a power source having a voltage VH_H and a power source having a voltage VL_L.

  The drive assist circuit CT1 includes an inverter IV1 composed of a PMOS transistor PT2 and an NMOS transistor NT2, an inverter IV2 composed of a PMOS transistor PT3 and an NMOS transistor NT3, an NMOS transistor NT1, and a PMOS transistor PT1.

  A PMOS transistor PT2, an NMOS transistor NT2, and an NMOS transistor NT1 are connected in series between the power supply of the voltage VH_H and the power supply of the voltage VH_L. A PMOS transistor PT1, a PMOS transistor PT3, and an NMOS transistor NT3 are connected in series between the power supply of the voltage VL_H and the power supply of the voltage VL_L. The input of inverter IV1 is connected to node NDX1. The output of inverter IV1 is connected to the gate of PMOS transistor P1 in driver DRT1R. The input of inverter IV2 is connected to node NDX2. The output of inverter IV2 is connected to the gate of NMOS transistor N1 in driver DRT1R. The gate of the NMOS transistor NT1 is connected to the pixel control line T1. The gate of the PMOS transistor PT1 is connected to the pixel control line T1.

  In the above, for example, VH_H = 3.6V, VL_H = 1.8V, VH_L = 0V, VL_L = −1.3V, and the pixel control line T1 varies in the range of −1.3V to 3.6V. can do.

  According to the present embodiment, it is possible to realize a level shifter and a driving auxiliary circuit corresponding to the amplitude range of the pixel control line.

[Fourth Embodiment]
The present embodiment includes a third drive unit 83 in addition to the first drive unit 81 and the second drive unit 82.

  FIG. 18 is a diagram illustrating a configuration for driving the reset transistors MR in a plurality of pixels in the first row of the pixel array 10 of the fourth embodiment.

  The configuration of the present embodiment in FIG. 18 is different from the configuration in FIG. 12 of the second embodiment as follows. In the present embodiment, a level shifter LSRM, a driving auxiliary circuit CR1M, and a driver DRR1M are provided. The level shifter LSRM, the drive assist circuit CR1M, and the driver DRR1M constitute a third sub drive unit 83_R1 included in the third drive unit 83. The third drive unit 83 is disposed above or below the pixel array 10 in the stacking direction. The third driving unit 83 is connected to the central node between the right end and the left end of each of the plurality of pixel control lines, and the pixel control line in which the change in the voltage level of the central node is detected is connected to the central node. Drive from.

  The third sub drive unit 83_R1 drives the pixel control line R1 in the first row of the pixel array 10 from the central node M between the right end and the left end. Although not shown, the third sub-driving unit 83_Ri (i ≠ 1) drives the pixel control line Ri in the i-th row of the pixel array 10 from the central node M between the right end and the left end. The third sub drive unit 83_Tj (j = 1 to N) drives the pixel control line Tj in the j-th row of the pixel array 10 from the central node M between the right end and the left end. The third sub drive unit 83_Sj (j = 1 to N) drives the pixel control line Sj in the j-th row of the pixel array 10 from a central node M between the right end and the left end.

The level shifter LSRM has the same configuration as the level shifter LSR.
Driver DRR1M has the same configuration as driver DRR1R. However, the driver DRR1R is connected to the right end of the pixel control line R1, whereas the output of the driver DRR1M is connected to the center node M of the pixel control line R1.

  The drive assist circuit CR1M has the same configuration as the drive assist circuit CR1. However, in the drive assist circuit CR1, the input terminal B of the NAND circuit 91 and the input terminal B of the NOR circuit 92 are connected to the right end of the pixel control line R1, whereas in the drive assist circuit CR1M, the input terminal B of the NAND circuit 91 The input terminal B and the input terminal B of the NOR circuit 92 are connected to the central node M of the pixel control line R1.

FIG. 19 is a diagram illustrating operation waveforms of the respective nodes in FIG.
With reference to FIGS. 18 and 19, the operation at the time of starting up the pixel control line R1 will be described.

  The timing generation circuit 1 raises the reset control signal RST_common at time T0. The row selection circuit 4 raises the reset control signal RST_1 in response to the rise of the reset control signal RST_common and outputs it to the node # 1. The level shifter LSR1 amplifies the reset control signal RST_1 and outputs the amplified reset control signal RST_1 ′ to the node # 2. The driver DRR1L drives the pixel control line R1 based on the reset control signal RST_1 ′.

  Since the node # 1 and the node # 2 have almost no load to be driven, the signal is transmitted almost without dullness. The CR load caused by the reset transistor MR and the pixel control line R1 in the pixel is charged with the current I1 from the driver DRR1L. Since node # 3 is positioned in the immediate vicinity of the output of driver DRR1L, the voltage at node # 3 has a slightly dull waveform. Since the node M and the node # 4 are far from the driver DRR1L and are affected by the CR load caused by the reset transistors MR and the long-distance wiring of all the pixels in one row, the voltages of the node M and the node # 4 are gradually increased. Stand up to.

  On the other hand, at time T5, the voltage at the node M of the pixel control line R1 rises to the threshold voltage VTN. As a result, after time T5, the CR load caused by the reset transistor MR and the pixel control line R1 in the pixel is charged with the current I2 from the driver DRR1M connected to the node M. As a result, the voltage at the node M rises sharply.

  At time T6, the voltage at the rightmost node # 4 of the pixel control line R1 rises to the threshold voltage VTN. As a result, after time T6, the CR load caused by the reset transistor MR and the pixel control line R1 in the pixel is charged with the current I3 from the driver DRR1R connected to the node # 4. As a result, the voltage at the node # 4 rises sharply. Here, time T5 <T6 <T2 (FIG. 14).

With reference to FIGS. 18 and 19, the operation when the pixel control line R1 is lowered will be described.
The timing generation circuit 1 causes the reset control signal RST_common to fall at time T1. In response to the fall of the reset control signal RST_common, the row selection circuit 4 falls the reset control signal RST_1 and outputs it to the node # 1. The level shifter LSR1 amplifies the reset control signal RST_1 and outputs the amplified reset control signal RST_1 ′ to the node # 2. The driver DRR1L drives the pixel control line R1 based on the reset control signal RST_1 ′.

  Since the node # 1 and the node # 2 have almost no load to be driven, the signal is transmitted almost without dullness. Since node # 3 is positioned in the immediate vicinity of the output of driver DRR1L, the voltage at node # 3 has a slightly dull waveform.

  Since the node M and the node # 4 are far from the driver DRR1L and are affected by the CR load caused by the reset transistors MR and the long-distance wiring of all the pixels in one row, the node M and the node # of the pixel control line R1 The voltage of 4 falls gradually.

  On the other hand, at time T7, the voltage at the node M of the pixel control line R1 drops to the threshold voltage (VH−VTP). As a result, after time T7, electric charges accumulated by the reset transistor MR in the pixel and the CR load caused by the pixel control line R1 are discharged through the driver DRR1M connected to the node M of the pixel array 10. As a result, the voltage at the node M falls sharply.

  At time T8, the voltage at the rightmost node # 4 of the pixel control line R1 falls to the threshold voltage (VH−VTP). As a result, after time T8, the charges accumulated by the reset transistor MR in the pixel and the CR load caused by the pixel control line R1 are discharged through the driver DRR1R connected to the node # 4 of the pixel array 10. As a result, the voltage at the node # 4 falls sharply. Here, time T7 <T8 <T3 (FIG. 14).

  According to the present embodiment, the drive unit for assisting the drive of the pixel control line is not only mounted on the peripheral part of the pixel array, but also using, for example, back side illumination (Back Side Illuminati: BSI) or a stacked structure, By providing above or below the pixel array in the stacking direction, it is possible to enhance the function of assisting driving of the pixel control lines.

  In the present embodiment, the first driving unit 81 is on the right side of the pixel array 10, the second driving unit 82 is on the left side of the pixel array 10, and the third driving unit 83 is on the pixel array 10 in the stacking direction. However, the present invention is not limited to this. For example, the first drive unit 81 may be disposed on the right side of the pixel array 10 and the second drive unit 82 may be disposed above or below the pixel array 10 in the stacking direction. Alternatively, the first driving unit 81 is disposed above or below the pixel array 10 in the stacking direction, the second driving unit 82 is disposed on the left side of the pixel array 10, and the third driving unit 83 is disposed on the right side of the pixel array 10. Also good.

[Fifth Embodiment]
In this embodiment, the reset transistor MR and the transfer transistor MT included in the pixel are normally-off transistors.

FIG. 20 is a diagram illustrating an example of a timing waveform of a control signal according to the fifth embodiment.
Outside the period during which the selection control signal SEL_k is at a high level (range of operation sequence in which a pixel is selected), the reset control signal RST_k and the transfer control signal TX_k are fixed at a low level. Here, k = 1 to n.

  FIG. 21 is a diagram illustrating a configuration for driving the reset transistors MR in a plurality of pixels in the first row of the pixel array 10 of the fifth embodiment from the right side. The configuration for driving the reset transistors MR of the pixels in the i-th row (i ≠ 1) and the transfer transistors MT of the pixels in the j-th row (j = 1 to n) from the right side is the same as this. is there.

  The timing generation circuit 1, the level shifter LSR, and the driver DRR1R are the same as those in the second embodiment.

The drive assist circuit CR1 includes a NAND circuit 91 and an inverter 93.
The input terminal A of the NAND circuit 91 receives the output of the level shifter LSR. The input terminal B of the NAND circuit 91 is connected to the right end of the pixel control line R1. The output terminal C of the NAND circuit 91 is connected to the PMOS transistor P1 in the driver DRR1R.

  The input terminal A of the inverter 93 receives the output of the level shifter LSR. The output terminal C of the inverter 93 is connected to the NMOS transistor N1 in the driver DRR1R.

  The operation when the voltage of the pixel control line R1 rises from the right side is the same as that in the second embodiment.

An operation when the voltage of the pixel control line R1 falls from the right side will be described.
First, the timing generation circuit 1 causes the reset control signal RST_common to fall.

Next, the level shifter LSR boosts the reset control signal RST_common.
Next, a low level voltage is input to the input terminal A of the NAND circuit 91. Since the voltage at the input terminal A is low, the output of the NAND circuit 91 is high. Therefore, the PMOS transistor P1 remains off.

  A low level voltage is input to the input terminal A of the inverter 93. As a result, the NMOS transistor N1 is turned on regardless of the level of the voltage at the right end of the pixel control line R1. The driver DRR1R connects the right end of the pixel control line R1 and the power supply of the voltage VL, and the pixel control line R1 is also discharged by the driver DRR1R. As a result, the right end voltage of the pixel control line R1 falls steeply to the voltage VL.

FIG. 22 is a diagram illustrating driving of pixel control lines R1 to Rn according to the fifth embodiment.
Assume that the xth row in the pixel array 10 is selected.

  An operation when the pixel control line Rx is activated will be described. This operation is the same as the operation of the second embodiment.

  The pixel control line Rx rises by the left level shifter LSRx and the driver DRRxL corresponding to the xth row of the row selection circuit 4 and the pixel array 10. Further, the rise of the pixel control line Rx is assisted by the level shifter LSR, the drive assist circuit CRx, and the driver DRRxR located on the right side of the pixel array 10.

  On the other hand, the pixel control line Ri is not raised by the row selection circuit 4, the left level shifter LSRi corresponding to the i-th row of the pixel array 10 and the driver DRRiL. The i-th row is all rows other than the x-th row. Therefore, the rise of the pixel control line Ri is not assisted by the level shifter LSR, the drive assist circuit CRi, and the driver DRRiR located on the right side of the pixel array 10.

  In other words, only the pixel control line that has been selected and started from the left side is assisted by the NAND circuit 91 to start from the right side. The unselected pixel control lines are not assisted by the NAND circuit 91 to start up from the right side.

An operation when the pixel control line Rx is lowered will be described.
The pixel control line Rx falls by the left side level shifter LSRx and the driver DRRxL corresponding to the xth row of the row selection circuit 4 and the pixel array 10. The fall of the pixel control line Rx is assisted by the level shifter LSR, the drive assist circuit CRx, and the driver DRRxR located on the right side of the pixel array 10. Here, the pixel control line Rx is lowered by the operation of the inverter 93 regardless of the voltage level of the node of the pixel control line Rx.

  Similarly, the pixel control line Ri is driven to a low level by the row selection circuit 4, the right level shifter LSRi corresponding to the i-th row of the pixel array 10 and the driver DRRiL regardless of the level of the pixel control line Ri. In the reset transistor MR of the pixel in the i-th row in the pixel array 10, since the period in which the x-th row is selected is not an operation sequence period, it is fixed at the low level, so the pixel control line Ri is driven to the low level. However, no problem occurs.

  That is, at the time of falling, all the pixel control lines R1 to Rn are lowered from the right side regardless of whether the inverter 93 is selected and lowered from the left side.

  In the solid-state imaging device according to the present embodiment, the portion that assists the falling of the pixel control lines Ri and Ti in the driving auxiliary circuit is configured by only an inverter, so that when the pixel control lines Ri and Ti are lowered, The row pixel control lines R1 to Rn and T1 to Tn are simultaneously lowered. With such a configuration, for example, when the normally-off type reset transistor MR and the transfer transistor MT are changed from on to off by lowering the pixel control lines Ri and Ti, a delay of (VH−VTP) occurs. You can avoid it.

[Sixth Embodiment]
In this embodiment, the reset transistor MR and the transfer transistor MT included in the pixel are normally-on transistors.

FIG. 23 is a diagram illustrating the timing of control signals according to the sixth embodiment.
Outside the period during which the selection control signal SEL_k is at the high level (the range of the operation sequence in which the pixels are selected), the reset control signal RST_k and the transfer control signal TX_k are fixed at the high level. Here, k = 1 to n.

  FIG. 24 is a diagram illustrating a configuration for driving the reset transistors MR in the plurality of pixels in the first row of the pixel array 10 of the fifth embodiment from the right side. The configuration for driving the reset transistors MR of the pixels in the i-th row (i ≠ 1) and the transfer transistors MT of the pixels in the j-th row (j = 1 to n) from the right side is the same as this. is there.

  The timing generation circuit 1, the level shifter LSR, and the driver DRR1R are the same as those in the second embodiment.

The drive assist circuit CR1 includes an inverter 94 and a NOR circuit 92.
The input terminal A of the NOR circuit 92 receives the output of the level shifter LSR. The input terminal B of the NOR circuit 92 is connected to the right end of the pixel control line R1. The output terminal C of the NOR circuit 92 is connected to the NMOS transistor N1 in the driver DRR1R.

  The input terminal A of the inverter 94 receives the output of the level shifter LSR. The output terminal C of the inverter 94 is connected to the PMOS transistor P1 in the driver DRR1R.

  The operation when the voltage of the pixel control line R1 falls from the right side is the same as in the second embodiment.

An operation when the voltage of the pixel control line R1 is raised from the right side will be described.
First, the timing generation circuit 1 raises the reset control signal RST_common.

Next, the level shifter LSR boosts the reset control signal RST_common.
Next, a high level voltage is input to the input terminal A of the NOR circuit 92. Since the voltage at the input terminal A is at a high level, the output of the NOR circuit 92 is at a low level. Therefore, the NMOS transistor N1 remains off.

  A high level voltage is input to the input terminal A of the inverter 94. As a result, the PMOS transistor P1 is turned on regardless of the level of the voltage at the right end of the pixel control line R1. The driver DRR1R connects the right end of the pixel control line R1 and the power supply of the voltage VH, and the pixel control line R1 is charged by the driver DRR1R. As a result, the voltage at the right end of the pixel control line R1 rises steeply to the voltage VH.

FIG. 25 is a diagram illustrating driving of pixel control lines R1 to Rn according to the sixth embodiment.
Assume that the xth row in the pixel array 10 is selected.

  An operation when the pixel control line Rx is lowered will be described. This operation is the same as the operation of the second embodiment.

  The pixel control line Rx falls by the left side level shifter LSRx and the driver DRRxL corresponding to the xth row of the row selection circuit 4 and the pixel array 10. The fall of the pixel control line Rx is assisted by the level shifter LSR, the drive assist circuit CRx, and the driver DRRxR located on the right side of the pixel array 10.

  On the other hand, the pixel control line Ri is not lowered by the row selection circuit 4, the left level shifter LSRi corresponding to the i-th row of the pixel array 10 and the driver DRRiL. i is a number other than x. Therefore, the falling of the pixel control line Ri is not assisted by the level shifter LSR, the drive assist circuit CRi, and the driver DRRiR located on the right side of the pixel array 10.

An operation when the pixel control line Rx is activated will be described.
The pixel control line Rx rises by the left level shifter LSRx and the driver DRRxL corresponding to the xth row of the row selection circuit 4 and the pixel array 10. The rise of the pixel control line Rx is assisted by the level shifter LSR, the drive assist circuit CRx, and the driver DRRxR located on the right side of the pixel array 10.

  Similarly, the pixel control line Ri is driven to a high level by the row selection circuit 4, the right level shifter LSRi corresponding to the i-th row of the pixel array 10 and the driver DRRiL regardless of the level of the pixel control line Ri. i is a number other than x.

  In the reset transistor MR of the pixel in the i-th row in the pixel array 10, since the period during which the x-th row is selected is not an operation sequence period and is fixed at a high level, the pixel control line Ri is set to a high level. There is no problem even if it is driven.

  In the solid-state imaging device according to the present embodiment, the portion that assists the start-up of the pixel control lines Ri and Ti in the drive assist circuit is configured by only an inverter, so that all the control lines Ri and Ti are The row pixel control lines R1 to Rn and T1 to Tn are simultaneously activated. With such a configuration, for example, when the normally-on type reset transistor MR and the transfer transistor MT are changed from OFF to ON by raising the pixel control lines Ri and Ti, a delay in VTN time does not occur. Can be.

[Seventh Embodiment]
The present embodiment relates to a configuration for assisting the start-up of the pixel control line Ri, the pixel control line Ti, and the pixel control line Si from the right side.

  FIG. 26 is a diagram illustrating a configuration for raising the reset transistors MR in the plurality of pixels in the first row of the pixel array 10 of the seventh embodiment from the right side. The configuration for raising the reset transistors MR in a plurality of pixels in the i-th row (i ≠ 1) from the right side is the same as this. Furthermore, the configuration for raising the transfer transistors MT in the pixels in the j-th row (j = 1 to n) from the right side is also the selection transistor MS in the pixels in the j-th row (j = 1 to n). The configuration for starting up from the right side is the same as this.

The level shifter LSR is the same as that of the second embodiment.
The driver DRR1R includes a PMOS transistor P1 connected between the power supply of the voltage VH_H and the pixel control line R1.

  The drive assist circuit CR1 includes a NAND circuit 91. The input terminal A of the NAND circuit 91 is connected to the output of the level shifter LSR, and the input terminal B of the NAND circuit 91 is connected to the pixel control line R1. The output of the NAND circuit 91 is connected to the gate of the PMOS transistor P1.

  According to the present embodiment, since the drive assist circuit CR1 includes only the NAND circuit 91 and the driver DRR1R includes only the PMOS transistor P1, only the start-up assist of the pixel control line R1 is executed.

  According to the solid-state imaging device of the present embodiment, the area can be reduced by executing only the start-up of the pixel control line.

[Eighth Embodiment]
The present embodiment relates to a configuration for assisting the falling of the pixel control line Ri, the pixel control line Ti, and the pixel control line Si from the right side.

  FIG. 27 is a diagram illustrating a configuration for causing the reset transistors MR in the plurality of pixels in the first row of the pixel array 10 of the eighth embodiment to fall from the right side. The configuration for causing the reset transistors MR in the plurality of pixels in the i-th row (i ≠ 1) to fall from the right side is the same as this. Further, the configuration for dropping the transfer transistors MT in the plurality of pixels in the jth row (j = 1 to n) from the right side is also the selection transistor MS in the plurality of pixels in the jth row (j = 1 to n). The configuration for lowering from the right side is the same as this.

The level shifter LSR is the same as that of the second embodiment.
The driver DRR1R includes an NMOS transistor N1 connected between the pixel control line R1 and the power supply of the voltage VL_L.

    The drive assist circuit CR1 includes a NOR circuit 92. The input terminal A of the NOR circuit 92 is connected to the output of the level shifter LSR, and the input terminal B of the NOR circuit 92 is connected to the pixel control line R1. The output of the NOR circuit 92 is connected to the gate of the NMOS transistor N1.

  According to the present embodiment, since the drive assist circuit CR1 includes only the NOR circuit 92 and the driver DRR1R includes only the NMOS transistor N1, only the fall assist of the pixel control line R1 is executed.

  According to the solid-state imaging device of the present embodiment, the area can be reduced by performing only the falling of the pixel control line.

[Ninth Embodiment]
FIG. 28 is a diagram illustrating a configuration for driving the transfer transistors MT in the plurality of pixels in the first row of the pixel array 10 of the ninth embodiment from the right side. The configuration for driving the transfer transistors MT in the pixels in the i-th row (i ≠ 1) from the right side is the same as this. Furthermore, the configuration for driving the reset transistors MR in the pixels in the j-th row (j = 1 to n) from the right side is also the selection transistor MS in the pixels in the j-th row (j = 1 to n). The configuration for driving the motor from the right side is the same as this.

The configuration of FIG. 38 is different from the configuration of the third embodiment of FIG. 17 as follows.
In the present embodiment, an NMOS transistor LNT1 having a threshold voltage VTN2 lower than VTN is used as a transistor connected in series with the inverter IV1. As a transistor connected in series to the inverter IV2, a PMOS transistor LPT1 having a threshold voltage VTP2 lower than VTP is used.

  Here, the threshold voltage VTN2 can be lower than the threshold voltage of the NMOS transistor included in the circuits other than the driving auxiliary circuits CT1 to CTn, CR1 to CRn, and CS1 to CSn in the second driving unit 82. . The threshold voltage VTP2 can be lower than the threshold voltage of the PMOS transistor included in circuits other than the drive auxiliary circuits CT1 to CTn, CR1 to CRn, and CS1 to CSn in the second drive unit 82.

  FIG. 29 is a diagram for comparing the rise and fall timings of the node # 4 of the third embodiment and the ninth embodiment.

  In the third embodiment, since the threshold value of the NMOS transistor NT1 is VTN, the voltage of the node # 4 rapidly rises at time T2. On the other hand, in the present embodiment, since the threshold value of the NMOS transistor LNT1 is VTN2, the voltage of the node # 4 rises rapidly at the time TS. Here, VTN> VTN2 and T2> TS.

  In the third embodiment, since the threshold value of the PMOS transistor PT1 is VTP, the voltage of the node # 4 falls sharply at time T3. On the other hand, in the present embodiment, since the threshold value of the PMOS transistor LPT1 is VTP2, the voltage at the node # 4 falls sharply at the time TE. Here, VTP> VTP2 and T3> TE.

  According to the solid-state imaging device of the present embodiment, by providing the low threshold NMOS transistor LNT1 and the PMOS transistor LPT1, the rise and fall of the pixel control line can be speeded up.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Timing generation circuit, 2, 2a, 6 level shifter group, 3, 3a, 5 driver group, 4, 4a row selection circuit, 7 drive auxiliary | assistant part, 10,100 pixel array, 81,200 1st drive part, 82, 300 second driving unit, 83 third driving unit, 83_R1 third sub driving unit, 91 NAND circuit, 92 NOR circuit, 93, 94, IV1, IV2, IV3 inverter, 102 current source circuit, 110, 500 solid Imaging device, 111 vertical scanning circuit, 114 digital signal processor, 115 current source circuit group, 116 A / D converter group, 117 horizontal scanning circuit, 118 bias voltage generation circuit, CR1 to CRn, CT1 to CTn, CS1 to CSn , CR1M Drive auxiliary circuit, DRR1L to DRRnL, DRT1L to DRTnL, DRS1L to DRSnL, DRR1R to DRR nR, DRT1R to DRTnR, DRS1R to DRSnR, DRR1M driver, LSR1 to LSRn, LST1 to LSTn, LSS1 to LSSn, LSR1R to LSRnR, LST1R to LSTnR, LSS1R to LSSnR, LSR, LST, LSS, LSRM level transistor, MD MR reset transistor, MS selection transistor, MT transfer transistor, P pixel, PD photodiode, FD floating diffusion.

Claims (17)

A pixel array including a plurality of pixels that perform photoelectric conversion arranged in a matrix;
A plurality of pixel control lines each connected to a corresponding row of pixels in the pixel array;
A first driving unit disposed adjacent to one end of the pixel array in the row direction and connected to one end of the plurality of pixel control lines, and driving the pixel control line in a selected row of the pixel array; ,
The pixel control line disposed adjacent to the other end in the row direction of the pixel array and connected to the other end of each of the plurality of pixel control lines, the change in the voltage level of the other end being detected. A solid-state imaging device comprising: a second drive unit that is driven from the other end. The first driving unit receives a control signal common to all the rows in the pixel array, and drives the pixel control lines of the selected row based on the common control signal.
The second driving unit receives the common control signal, and the plurality of pixels according to a level of the common control signal and a voltage level of the other end of each of the plurality of pixel control lines. The solid-state imaging device according to claim 1, wherein each control line is driven from the other end. A timing generation circuit for controlling activation and deactivation of a control signal common to all the rows in the pixel array;
The first driving unit includes:
A row selection circuit for selecting a row in the pixel array and activating or deactivating a control signal of the selected row according to a level of the common control signal;
A plurality of first level shifters each amplifying the level of the control signal in the corresponding row;
A plurality of first drivers each having an input terminal for receiving the amplified control signal in a corresponding row and an output terminal connected to one end of the pixel control line in the corresponding row;
The second driving unit includes:
A second level shifter for amplifying the level of the common control signal;
A plurality of second drivers each having an output terminal connected to the other end of the pixel control line of the corresponding row;
A plurality of driving auxiliary circuits each controlling the output of the corresponding second driver according to the voltage at the other end of the pixel control line in the corresponding row and the level of the amplified common control signal; The solid-state imaging device according to claim 1, comprising: The second driver includes a PMOS transistor and an NMOS transistor connected in series,
The drive assist circuit includes:
A first input terminal connected to the output node of the second level shifter; a second input terminal connected to the other end of the pixel control line; and an output terminal connected to the gate of the PMOS transistor. A NAND circuit having
A first input terminal connected to the output node of the second level shifter; a second input terminal connected to the other end of the pixel control line; and an output terminal connected to the gate of the NMOS transistor. The solid-state imaging device according to claim 3, comprising a NOR circuit having the same. The second level shifter outputs a first voltage or a second voltage according to a level of an input signal,
The second driver includes a first PMOS transistor connected to the power source of the first voltage connected in series and a first NMOS transistor connected to the power source of the second voltage;
The drive assist circuit includes:
An input terminal connected to the output node of the second level shifter; and an output terminal connected to the gate of the first PMOS transistor; connected to the second NMOS transistor and the power supply of the first voltage. A first inverter configured with a second PMOS transistor to be
An input terminal connected to an output node of the second level shifter; and an output terminal connected to a gate of the first NMOS transistor; connected to a third PMOS transistor and a power supply of the second voltage A second inverter constituted by a third NMOS transistor to be operated;
A fourth NMOS transistor disposed between the second NMOS transistor and the power supply of the second voltage;
A fourth PMOS transistor disposed between the third PMOS transistor and the power supply of the first voltage;
The solid-state imaging device according to claim 3, wherein a gate of the fourth NMOS transistor and a gate of the fourth NMOS transistor are connected to the other end of the pixel control line. The second level shifter outputs a first output node that outputs a first voltage or a second voltage according to a level of an input signal, and a second output that outputs a third voltage or a fourth voltage. And an output node of
The second driver includes a first PMOS transistor connected to the power source of the first voltage connected in series and a first NMOS transistor connected to the power source of the fourth voltage,
The drive assist circuit includes:
An input terminal connected to the first output node of the second level shifter; and an output terminal connected to a gate of the first PMOS transistor, the second NMOS transistor and the first voltage A first inverter constituted by a second PMOS transistor connected to the power source of
An input terminal connected to the second output node of the second level shifter; and an output terminal connected to a gate of the first NMOS transistor. The third PMOS transistor and the fourth voltage A second inverter constituted by a third NMOS transistor connected to the power source of
A fourth NMOS transistor disposed between the second NMOS transistor and the power supply of the second voltage;
A fourth PMOS transistor disposed between the third PMOS transistor and a power supply of the third voltage;
The solid-state imaging device according to claim 3, wherein a gate of the fourth NMOS transistor and a gate of the fourth NMOS transistor are connected to the other end of the pixel control line.   In the stacking direction, disposed on or below the pixel array, connected to a node between the one end and the other end of each of the plurality of pixel control lines, and a change in voltage level of the node is detected. The solid-state imaging device according to claim 1, further comprising a third driving unit that drives a pixel control line from the node. The pixel includes a normally-off type transistor connected to the pixel control line,
The second driver includes a PMOS transistor and an NMOS transistor,
The drive assist circuit includes:
A first input terminal connected to the output node of the second level shifter; a second input terminal connected to the other end of the pixel control line; and an output terminal connected to the gate of the PMOS transistor. A NAND circuit having
The solid-state imaging device according to claim 3, further comprising: an inverter having an input terminal connected to the output node of the second level shifter and an output terminal connected to the gate of the NMOS transistor. The pixel includes a normally-on type transistor connected to the pixel control line,
The second driver includes a PMOS transistor and an NMOS transistor,
The drive assist circuit includes:
An inverter having an input terminal connected to the output node of the second level shifter and an output terminal connected to the gate of the PMOS transistor;
A first input terminal connected to the output node of the second level shifter; a second input terminal connected to the other end of the pixel control line; and an output terminal connected to the gate of the NMOS transistor. The solid-state imaging device according to claim 3, further comprising a NOR circuit having the same. The second driver includes a PMOS transistor;
The drive assist circuit includes:
A first input terminal connected to the output node of the second level shifter; a second input terminal connected to the other end of the pixel control line; and an output terminal connected to the gate of the PMOS transistor. The solid-state imaging device according to claim 3, comprising a NAND circuit having the same. The second driver includes an NMOS transistor;
The drive auxiliary circuit is connected to a first input terminal connected to the output node of the second level shifter, a second input terminal connected to the other end of the pixel control line, and a gate of the NMOS transistor. The solid-state imaging device according to claim 3, further comprising a NOR circuit having an output terminal to be operated. The threshold voltage of the fourth NMOS transistor in the drive assist circuit is smaller than the threshold voltage of an NMOS transistor included in a circuit other than the drive assist circuit included in the second driver,
The threshold voltage of the fourth PMOS transistor in the drive assist circuit is smaller than a threshold voltage of a PMOS transistor included in a circuit other than the drive assist circuit included in the second driver. Solid-state imaging device. The pixel includes a transfer transistor;
The solid-state imaging device according to claim 1, wherein the pixel control line is connected to a gate of the transfer transistor in the pixel. The pixel includes a selection transistor,
The solid-state imaging device according to claim 1, wherein the pixel control line is connected to a gate of the selection transistor in the pixel. The pixel includes a reset transistor,
The solid-state imaging device according to claim 1, wherein the pixel control line is connected to a gate of the reset transistor in the pixel. The pixel includes a transfer transistor, a selection transistor, and a reset transistor,
The pixel control line includes a first pixel control line connected to a gate of the transfer transistor in the pixel, a second pixel control line connected to a gate of the selection transistor in the pixel, and the pixel The solid-state imaging device according to claim 1, further comprising: a third pixel control line connected to a gate of the reset transistor within. A pixel array in which a plurality of pixels that perform photoelectric conversion are arranged in a matrix;
A plurality of pixel control lines each connected to a corresponding row of pixels in the pixel array;
A timing generation circuit that controls activation and deactivation of control signals common to all rows in the pixel array;
A row selection circuit for selecting a row in the pixel array and activating or deactivating a control signal of the selected row according to a level of the common control signal;
A plurality of first level shifters each amplifying the level of the control signal in the corresponding row;
A plurality of first drivers each having an input terminal for receiving the amplified control signal in a corresponding row and an output terminal connected to one end of the pixel control line in the corresponding row;
A second level shifter for amplifying the level of the common control signal;
A plurality of second drivers each having an output terminal connected to the other end of the pixel control line of the corresponding row;
A plurality of driving auxiliary circuits each controlling the output of the corresponding second driver according to the voltage at the other end of the pixel control line in the corresponding row and the level of the amplified common control signal; Including
The timing generation circuit, the row selection circuit, the plurality of first level shifters, and the plurality of first drivers are arranged on one side in the row direction of the pixel array rather than the pixel array,
The solid-state imaging device, wherein the second level shifter, the plurality of second drivers, and the plurality of driving auxiliary circuits are arranged on the other side in the row direction of the pixel array with respect to the pixel array.

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