JP2019169943A - Current drive circuit - Google Patents

Abstract

To maintain an output current with high accuracy, even when an output voltage fluctuates.SOLUTION: A current drive circuit includes a first transistor that outputs a current, a second transistor that is cascode-connected to the first transistor, a third transistor that is cascode-connected to the second transistor, a first current source for supplying the current to the third transistor and the second transistor, a fourth transistor for causing the third transistor and a gate to be common, a fifth transistor for causing the second transistor and a gate to be common and that is cascode-connected to the fourth transistor, a second current source for supplying the current to the fourth transistor and the fifth transistor, a sixth transistor for causing the third transistor, the fourth transistor, and the gate to be common and for controlling a gate voltage of the first transistor, and a third current source for supplying a drain current of the sixth transistor.SELECTED DRAWING: Figure 1A

Description

  Embodiments described herein relate generally to a current driving circuit.

  An LED (Light Emitting Device) used for a backlight of a liquid crystal panel changes in color rendering depending on the magnitude of an energization current. Therefore, in order to emit light with an assumed color rendering, it is necessary to control the current applied to the LED with high accuracy. . Dimming of the LED that emits light with the controlled current is performed by controlling the pulse width of the current applied to the LED. If the frequency of the pulse current is in the human audible range, it may cause an unpleasant sound in the power circuit, etc., and as a countermeasure, the frequency in the ultrasonic range is often much higher than the frequency of the commercial power supply. . Moreover, in order to obtain a required luminous intensity, it is necessary to drive a plurality of LEDs in series, and the output voltage of the drive power supply may be several tens of volts or more.

  When an LED is driven on / off by pulse width control, the voltage at the LED connection terminal of the current drive circuit that supplies current to the LED fluctuates greatly, but even if the output voltage fluctuates greatly so as not to affect color rendering and dimming It is desirable to maintain the accuracy of the output current of the current driving circuit.

JP 2011-249760 A

  One embodiment of the present invention provides a current driving circuit capable of maintaining an output current with high accuracy even when an output voltage fluctuates.

According to this embodiment, a first transistor that outputs current, a second transistor that is cascode-connected to the first transistor,
A third transistor cascode-connected to the second transistor;
A first current source for supplying current to the third transistor and the second transistor;
A fourth transistor sharing a gate with the third transistor;
A fifth transistor having a common gate to the second transistor and cascode-connected to the fourth transistor;
A second current source for supplying current to the fourth transistor and the fifth transistor;
A sixth transistor for controlling a gate voltage of the first transistor by sharing a gate with the third transistor and the fourth transistor;
And a third current source for supplying a drain current of the sixth transistor.

The circuit diagram of the current drive circuit by a 1st embodiment. The graph which shows the electrical property in the current drive circuit of FIG. 1A. The circuit diagram which shows the modification of the circuit of FIG. 1A. The figure which shows the voltage waveform of N4 and N8 in the circuit of FIG. 1A and FIG. 1C. The circuit diagram which shows another modification of the circuit of FIG. 1A. The circuit diagram which shows another modification of the circuit of FIG. 1A. The circuit diagram of the modification of the current drive circuit by a 1st embodiment. The graph which shows the electrical property in the current drive circuit of FIG. 2A. The circuit diagram which shows the modification of the circuit of FIG. 2A. FIG. 2B is a circuit diagram showing another modification of the circuit of FIG. 2A. FIG. 2B is a circuit diagram showing another modification of the circuit of FIG. 2A. The graph which shows another modification of the circuit of FIG. 2A. FIG. 2B is a circuit diagram showing another modification of the circuit of FIG. 2A. FIG. 2B is a circuit diagram showing another modification of the circuit of FIG. 2A. The equivalent circuit schematic of the principal part of the current drive circuit by 1st Embodiment. The circuit diagram of the current drive circuit of the 1st example provided with the starting auxiliary circuit by a 1st embodiment. The circuit diagram of the current drive circuit of the 2nd example provided with the starting auxiliary circuit by a 1st embodiment. The circuit diagram of the current drive circuit of the 3rd example provided with the starting auxiliary circuit by a 1st embodiment. The circuit diagram of the modification of the 3rd example provided with the starting auxiliary circuit by a 1st embodiment. FIG. 7 is an operation waveform diagram of each part in the current drive circuit shown in FIG. 5 or FIG. 6. The circuit diagram which shows the example which inserted the buffer in the starting auxiliary circuit. FIG. 9B is a circuit diagram showing a modification of FIG. 9A. FIG. 10 is a circuit diagram in which a pulse generation circuit is further added to the startup auxiliary circuit of FIG. FIG. 10B is a circuit diagram showing a modification of FIG. 10A. The circuit diagram of the current drive circuit by a 2nd embodiment. The circuit diagram of the modification of the current drive circuit by a 2nd embodiment. The circuit diagram which added the 13th transistor to the current drive circuit by a 2nd embodiment. Another circuit diagram which added the 13th transistor to the current drive circuit by a 2nd embodiment. The figure explaining the operation | movement of the OFF state of the 2nd transistor which concerns on 1st, 2nd embodiment, and an ON state. FIG. 16 is a circuit diagram of a modification of FIG. 15. FIG. 16 is another circuit diagram of a modification of FIG. 15. The equivalent circuit diagram in the case of dividing the 2nd transistor which concerns on 1st, 2nd embodiment into 1 time part and N time part. The equivalent circuit diagram which added the starting auxiliary circuit to the current drive device by an embodiment. FIG. 20 is a circuit diagram of a current drive circuit 100 in which a sixth switch is interposed between the output node of the startup assist circuit of FIG. 19 and the gate of the second transistor. FIG. 20 is a circuit diagram of a current drive circuit in which a sixth switch is interposed between the output node of the startup assist circuit of FIG. 19 and the gate of the second transistor. FIG. 20 is a circuit diagram of a current drive circuit 100 in which a sixth switch is interposed between the output node of the startup assist circuit of FIG. 19 and the gate of the second transistor. The circuit diagram of the current drive circuit 100 which drives the gate of a 2nd transistor only by a starting auxiliary circuit at the time of starting. The circuit diagram of the current drive circuit 100 which drives the gate of a 2nd transistor only by a starting auxiliary circuit at the time of starting. The circuit diagram of the current drive circuit 100 which drives the gate of a 2nd transistor only by a starting auxiliary circuit at the time of starting. FIG. 6 is a circuit diagram of a current driving circuit that drives the gate of the second transistor by using both the auxiliary start circuit and the potential of the node N3 at the time of startup when the second transistor M2 is not divided into a 1-fold portion and an N-fold portion. FIG. 6 is a circuit diagram of a current driving circuit that drives the gate of the second transistor by using both the auxiliary start circuit and the potential of the node N3 at the time of startup when the second transistor M2 is not divided into a 1-fold portion and an N-fold portion. FIG. 6 is a circuit diagram of a current driving circuit that drives the gate of the second transistor by using both the auxiliary start circuit and the potential of the node N3 at the time of startup when the second transistor M2 is not divided into a 1-fold portion and an N-fold portion. FIG. 5 is a circuit diagram of a current driving circuit 100 that drives the gate of the second transistor by using both of the auxiliary start circuit and the potential of the node N3 at the time of startup when the second transistor is not divided into a 1 × portion and an N × portion. FIG. 5 is a circuit diagram of a current driving circuit 100 that drives the gate of the second transistor by using both of the auxiliary start circuit and the potential of the node N3 at the time of startup when the second transistor is not divided into a 1 × portion and an N × portion. FIG. 5 is a circuit diagram of a current driving circuit 100 that drives the gate of the second transistor by using both of the auxiliary start circuit and the potential of the node N3 at the time of startup when the second transistor is not divided into a 1 × portion and an N × portion. The circuit diagram of the current drive circuit 100 by one comparative example. The figure which shows the curve which shows the correspondence of the output voltage output from the OUT terminal connected to the drain of a 1st transistor, and the output current which flows from OUT terminal. (A) And (b) is a figure which shows the responsiveness of the output current of the current drive circuit 100 by this embodiment and one comparative example.

  Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. In the drawings attached to the present specification, for the sake of illustration and ease of understanding, the scale, the vertical / horizontal dimension ratio, and the like are appropriately changed and exaggerated from those of the actual product.

  Furthermore, as used in this specification, the shape and geometric conditions and the degree thereof are specified. For example, terms such as “parallel”, “orthogonal”, “identical”, length and angle values, etc. Without being bound by meaning, it should be interpreted including the extent to which similar functions can be expected.

(First embodiment)
FIG. 1A is a circuit diagram of a current driving circuit 100 according to the first embodiment. The current drive circuit 100 of FIG. 1A is built in, for example, an LED driver, but its application is not limited to driving LEDs. FIG. 1B is a graph (graph1 to graph6) showing electrical characteristics in the current driving circuit 100 of FIG. 1A. The horizontal axis of graph1 to graph6 is the output voltage (V). The vertical axis of graph1 is the drain current of the first transistor M1, and the vertical axes of graph2 to graph6 are the voltages (V) of N1, N2, N4, N8, and N3.

  A current driving circuit 100 in FIG. 1A is a circuit for driving a first transistor M1 having a high withstand voltage and having a current output. The current drive circuit 100 in FIG. 1A includes second to sixth transistors M2 to M6 having a lower withstand voltage than the first transistor M1, and first to third current sources 1 to 3. Although FIG. 1A shows an example in which the first to sixth transistors M1 to M6 are n-type MOS (Metal-Oxide-Silicon) transistors, they may be formed of p-type MOS transistors. When the first to sixth transistors M1 to M6 are p-type MOS transistors, the connection relationship of each transistor between the power supply voltage node VDD and the ground node is opposite to that in FIG. 1A. The drain of the first transistor M1 is connected to the output terminal OUT, and a constant current is output from the output terminal OUT. In this specification, an example in which the first to sixth transistors M1 to M6 are n-type MOS transistors will be described. The first transistor M1 does not necessarily have a high breakdown voltage, and may have the same breakdown voltage or low breakdown voltage as the second to sixth transistors M2 to M6.

  The second transistor M2 is cascode-connected to the first transistor M1. The third transistor M3 is cascode-connected to the second transistor M2. 1 supplies current to the third transistor M3 and the second transistor M2. The first current source 1 is interposed between the power supply voltage node VDD and the drain of the third transistor M3. The source of the third transistor M3 is connected to the drain of the second transistor M2, and the source of the second transistor M2 is connected to the ground node. The gate and drain of the third transistor M3 are connected.

  The fourth transistor M4 has a common gate with the third transistor M3. The fifth transistor M5 is cascode-connected to the fourth transistor M4. The second current source 2 supplies current to the fourth transistor M4 and the fifth transistor M5. The second current source 2 is interposed between the power supply voltage node VDD and the drain of the fourth transistor M4. The source of the fourth transistor M4 is connected to the drain of the fifth transistor M5, and the source of the fifth transistor M5 is connected to the ground node. The gate of the fifth transistor M5 and the drain of the fourth transistor M4 are connected.

  The sixth transistor M6 has a common gate with the third transistor M3 and the fourth transistor M4. The sixth transistor M6 controls the gate voltage of the first transistor M1. The third current source supplies current to the sixth transistor M6. The third current source 3 is interposed between the power supply voltage node VDD and the drain of the sixth transistor M6. The drain of the sixth transistor M6 is connected to the gate of the first transistor M1. For example, a resistance element R1 is connected between the source of the sixth transistor M6 and the ground node.

  The second transistor M2 has a size (N + 1) times larger than the third to sixth transistors M3 to M6. N is a value of several tens to several thousand, for example. The size of the first transistor M1 is also sufficiently large. In FIG. 1A, the size of the first transistor M1 is described as “× N”, but the size of the first transistor M1 may be larger than that of the second transistor M2.

  In FIG. 1A, the connection node between the source of the first transistor M1 and the drain of the second transistor M2 is N1, the common gate of the third transistor M3, the fourth transistor M4, and the sixth transistor M6 is N2, and the second transistor M2 and the second transistor M2 are connected to each other. The common gate of the five transistors M5 is N3, the gate of the first transistor M1 is N4, and the source of the sixth transistor M6 is N8.

  Since the third transistor M3 and the fourth transistor M4 form a current mirror circuit, the value of M3 (gate width W / gate length L) per unit current of the current I1 from the first current source 1 is set as the second current. The current I2 from the source 2 is equal to the value of (gate width W / gate length L) of M4 per unit current. The current I1 flows to the node N2 connected to the gate of the third transistor M3, and the current I2 flows to the node N3 connected to the gate of the second transistor M2.

  Further, the value of (gate width W / gate length L) of M6 per unit current of the current I3 from the third current source 3 is set to (gate width of M3 per unit current of the current I1 from the first current source 1). When the value is W / gate length L), the saturation potential of N1 can be set by the product of the resistance R1 and the current I3 of the saturation potential of N8, as shown in graph 1 of FIG. 1B.

  The saturation potentials of N1 and N8 are substantially the same due to the feedback of the loop rp2, but for this purpose, it is necessary to set the interlocking N2 and N4 so as not to be saturated near the power supply voltage VDD.

  FIG. 1C is a circuit diagram showing a modification of the circuit of FIG. 1A. FIG. 1C is an example of a circuit that shortens the time required for N4 to rise by feedback of the loop rp2 when N4 is restarted or N8 immediately after activation of the current source is lifted by the source follower circuit 70. The source follower circuit 70 is connected between the transistors M15 and M16 constituting the current mirror circuit, the resistor R8 connected between the source of the transistor M15 and the ground node, and between the source and ground node of the transistor M16. The resistor R9 and the current source 71 connected between the drain of the transistor M16 and the power supply voltage VDD are provided. The source of the transistor M15 is connected to the source of the transistor M6.

  FIG. 1D is a diagram showing voltage waveforms of N4 and N8 in the circuits of FIGS. 1A and 1C. As shown in FIG. 1D, when N4 is 0V in the initial state, in the circuit of FIG. 1A, N8 stays near 0.1V until N4 exceeds the threshold voltage, but in the circuit of FIG. 1C, the source follower circuit 70 Since N8 is immediately raised to 0.4 V or higher, the settling time is shortened by about 30%.

  FIG. 1E is a circuit diagram showing another modification of the circuit of FIG. 1A. FIG. 1E is a circuit diagram illustrating an example in which N4 is pulled down by a resistor R10 so that an LED current is not generated when the power supply VDD is insufficient. In FIG. 1E, the drain current of the sixth transistor M6 decreases from I3 to the I3-N4 potential / R10.

  FIG. 1F is a circuit diagram showing another modification of the circuit of FIG. 1A. FIG. 1F is a circuit example in which the buffer amplifier A1 compensates for the decrease in the N4 potential due to the resistor R10 of FIG. 1E. That is, in the circuit of FIG. 1E, since the N4 potential is too low, the buffer amplifier A1 operates to raise the N4 potential. A resistor R11 is connected between the output node of the buffer amplifier A1 and N4, and a resistor R12 is connected between the output node of the buffer amplifier A1 and the ground node. Resistance R12 = R10−R11 is set.

  2A is a circuit diagram of a modification of the current drive circuit 100 of FIG. 1A, and FIG. 2B is a graph (graph7 to graph12) showing electrical characteristics in the current drive circuit 100 of FIG. 2A. The horizontal axis of graph7 to graph12 is the output voltage (V). The vertical axis of graph7 is the drain current of the first transistor M1, and the vertical axes of graphs 8 to 12 are the voltages (V) of N1, N2, N4, N8, and N3. By changing the size of the seventh transistor M7 from x1 to xA, the voltages at N1, N2, N4, N8, and N3 can be changed, but the change in the OUT terminal current due to this is small.

  The current drive circuit 100 in FIG. 2A includes a seventh transistor M7 instead of the resistance element R1. The seventh transistor M7 has a common gate with the third transistor M3, the fourth transistor M4, and the sixth transistor M6. The drain of the seventh transistor M7 is connected to the source of the sixth transistor M6, and the source of the seventh transistor M7 is connected to the ground node. The seventh transistor M7 has the same size as the third to sixth transistors M3 to M6. Similarly to the second to sixth transistors M2 to M6, the seventh transistor M7 has a low breakdown voltage, and is an NMOS transistor, for example.

  The seventh transistor M7 in FIG. 2A is provided to generate the gate voltage of the first transistor M1, similarly to the resistance element R1 in FIG. As shown in FIG. 2B, the saturation potential of N1 can be set by the overdrive voltage of the seventh transistor M7 at the drain current I3 of the saturation potential of N8. As in FIG. 1B, the saturation potentials of N1 and N8 are substantially the same due to the feedback of the loop rp2. To that end, it is necessary to set the interlocking N2 and N4 so that they are not saturated near the power supply voltage VDD potential. is there.

  FIG. 2C is a circuit diagram showing a modification of the circuit of FIG. 2A. FIG. 2C is a circuit diagram showing a circuit example in which the sixth transistor M6 and the seventh transistor M7 of FIG. 2A are combined into one sixth transistor M6. The sum of the overdrive voltage and the threshold voltage at the time of the drain current I3 of the sixth transistor M6 is the overdrive voltage of the drain current I3 of the seventh transistor M7 and the overdrive voltage of the drain current I3 of the sixth transistor M6 in FIG. The size (gate width W / gate length L) is set to be the same as the sum of the threshold voltages.

  FIG. 2D is a circuit diagram showing another modification of the circuit of FIG. 2A. FIG. 2D is a circuit diagram illustrating a circuit example in which N8 is set by both the size setting of the seventh transistor M7 and I3 × R1.

  FIG. 2E is a circuit diagram showing another modification of the circuit of FIG. 2A. FIG. 2E is a circuit diagram showing a circuit example for shortening the time until N4 is settled by the feedback of the loop rp2 by lifting N8 immediately after the start of the current source or N8 immediately after the activation of the current source by the source follower circuit 70. is there. The circuit configuration of the source follower circuit 70 in FIG. 2E is the same as that of the source follower circuit 70 in FIG. 1C except that the resistors R8 and R9 are replaced with transistors M17 and M11.

  FIG. 2F is a graph showing another modification of the circuit of FIG. 2A. As shown in FIG. 2F, when N4 is 0V in the initial state, in the circuit of FIG. 2A, N8 stays near 0.1V until N4 exceeds the threshold voltage, but in the circuit of FIG. 2E, the source follower circuit 70 Since N8 is immediately raised above 0.2V, the settling time is shortened by about 20%.

  FIG. 2G is a circuit diagram showing another modification of the circuit of FIG. 2A. FIG. 2G is a circuit diagram illustrating an example of pulling down N4 so that LED current is not generated when the power supply VDD is insufficient. In the circuit of FIG. 2G, the drain current of the sixth transistor M6 decreases from I3 to I3-N4 potential / R10.

  FIG. 2H is a circuit diagram showing another modification of the circuit of FIG. 2A. FIG. 2H is a circuit example in which the buffer amplifier A1 compensates for the decrease in the N4 potential due to the resistor R10 in FIG. 2G. The relationship between the buffer amplifier A1 in FIG. 2H and the resistors R11 and R12 connected to the buffer amplifier A1 is the same as that in FIG. 1F.

  FIG. 3 is an equivalent circuit diagram of the main part of the current driving circuit 100 of FIGS. 1A and 2A. The equivalent circuit of FIG. 3 includes a first transistor M1, a second transistor M2, a fifth transistor M5, a second current source 2, an OTA (Operational Trans-conductance Amplifier) 4, a differential amplifier 5, 1 to third voltage sources 6 to 8.

The OTA 4 outputs a current proportional to the difference between the two input voltages. The non-inverting input terminal of the OTA 4 is connected to the first voltage source 6 and the inverting input terminal of the differential amplifier 5 and corresponds to the node N2. The inverting input terminal of the OTA 4 is connected to the second voltage source 7 that outputs the voltage V2. Two current output terminals of the OTA 4 are inserted on a current path from the second current source 2.
On the current path, the second current source 2 and the fifth transistor M5 are connected. A non-inverting input terminal of the differential amplifier 5 is connected to a third voltage source 8 that outputs a voltage V3. A first voltage source 6 that outputs a voltage V <b> 1 is connected to the inverting input terminal of the differential amplifier 5. The gate of the first transistor M1 is connected to the output terminal of the differential amplifier 5 via the node N4.

  The equivalent circuit of FIG. 3 includes a first control loop rp1 that passes through the second transistor M2, OTA4, and the fifth transistor M5, and a second control loop that passes through the differential amplifier 5, the first transistor M1, and the first voltage source 6. rp2.

  In the first control loop rp1, the potential of the node N3 is determined by the potential of the node N1. In the first control loop rp1, the drain current of the second transistor M2 is controlled to be I2 × (1 + N) ≈I2 × N. In the second control loop rp2, the potential of the node N4 is controlled so that the node N1 has the same potential as the node N8 in FIGS. 1A and 2A. When the output voltage VOUT is higher than the target voltage of the node N1 (the potential of the node N8 = V3−V1), the node N1 is maintained at the target voltage in the second control loop rp2, so that the potential fluctuation of the node N4 becomes small. . When the output voltage VOUT becomes lower than the target voltage, the second control loop rp2 raises the potential of the node N4 and feeds back so as to prevent the potential of the node N1 from decreasing. Even with such feedback control, when the potential of the node N1 decreases, the first control loop rp1 raises the potential of the node N3 so as to maintain the drain currents of the first transistor M1 and the second transistor M2. Perform feedback control.

  In the circuit of FIGS. 1A and 2A, the first control loop rp1 is a path that passes through the fourth transistor M4, the fifth transistor M5, the second transistor M2, and the third transistor M3. The second control loop rp2 is a path that passes through the first transistor M1, the third transistor M3, and the sixth transistor M6.

  In the circuits of FIGS. 1A and 2A, since the size of the first transistor M1 and the second transistor M2 is much larger than the sizes of the third to seventh transistors M3 to M7, the power-on activation signal is input. It takes time for the first transistor M1 to start outputting current. There are a plurality of circuit configurations of the auxiliary start circuit for shortening this time. Hereinafter, typical first to fifth specific examples of the activation assist circuit will be described.

(First specific example of the startup auxiliary circuit)
The first specific example of the activation assist circuit is to temporarily increase the charging current of the node N3 connected to the gate of the second transistor M2. “Temporary” means, for example, a predetermined time after an activation signal is input.

  FIG. 4 is a circuit diagram of the current driving circuit 100 including the activation auxiliary circuit 25 according to the first specific example. 4 includes, for example, an eighth transistor M8, a ninth transistor M9, a fourth current source 9, and a first start switch 10 in addition to the circuit configuration of the current drive circuit 100 of FIG. 2A. And a second start switch 11.

  The eighth transistor M8 has a common gate to the third transistor M3, the fourth transistor M4, and the sixth transistor M6. The ninth transistor M9 has a common gate to the second transistor M2 and the fifth transistor M5. The source of the eighth transistor M8 is connected to the drain of the ninth transistor M9, and the source of the ninth transistor M9 is connected to the ground node. The first start switch 10 is interposed between the fourth current source 9 and the drain of the eighth transistor M8. The second activation switch 11 is interposed between the drain of the eighth transistor M8 and the drain of the fourth transistor M4.

  Since the eighth transistor M8 and the ninth transistor M9 have a size (M−1) times that of the fourth transistor M4 and the fifth transistor M5, the fourth current source 9 is equal to (M−1) of the second current source 2. ) Can pass twice as much current.

  FIG. 4A shows a state before the start assist circuit 25 performs start assist. In the case of FIG. 4A, both the first activation switch 10 and the second activation switch 11 block the connection path. As a result, the eighth transistor M8 and the ninth transistor M9 are turned off.

FIG. 4B shows a state in which the start assist circuit 25 performs start assist within a predetermined period after the start signal is input. In the case of FIG.4 (b), both the 1st starting switch 10 and the 2nd starting switch 11 conduct | electrically_connect a connection path | route. As a result, M times the current flows in the node N3 as compared with the case where the eighth and ninth transistors M9 and the second current source 2 are not provided, and the activation time can be shortened to 1 / M.
When the predetermined period elapses, as shown in FIG. 4A, the first start switch 10 and the second start switch 11 cut off the connection path, so that the eighth and ninth transistors M9 and the second current source 2 Stops working.

(Second specific example of the startup auxiliary circuit 25)
The second specific example of the activation auxiliary circuit 25 performs control to increase the potential of the node N3 for a predetermined period after the activation input signal is input.

  FIG. 5 is a circuit diagram of a current driving circuit 100 including the activation auxiliary circuit 25 according to the second specific example. 5 includes, for example, eighth to tenth transistors M8 to M10 and a fourth current source 9. The connection configuration of the eighth transistor M8, the ninth transistor M9, and the fourth current source 9 is the same as that in FIG. The gate of the tenth transistor M10 is connected to the drain of the eighth transistor M8, the drain of the tenth transistor M10 is connected to the power supply voltage node VDD, and the sources of the tenth transistor M10 are the second transistor M2 and the fifth transistor M5. And the common gate of the ninth transistor M9. The start assist circuit 25 has an eighth current per unit current of I4 so that when N3 becomes a predetermined voltage, the potential of N5 surely falls below (the potential of N3) + (the threshold voltage of M10). The (gate width W / gate length L) of the transistor M8 is set to be equal to or greater than (gate width W / gate length L) of the fourth transistor M4 per unit current of the current due to I2. The size of the tenth transistor M10 is 1 to Ma times (Ma> 1).

  For a predetermined period after the activation signal is input, the gate of the tenth transistor M10 becomes high level, and the potential of the node N3 connected to the gates of the second, fifth, and ninth transistors M2, M5, and M9 increases. When the drain current of the second transistor M2 becomes a times the drain current of the second transistor M2 in a steady state (a <1, for example, a = 0.5), the node N5 connected to the gate of the tenth transistor M10 is The tenth transistor M10 is turned off, and the startup assist operation ends.

  Here, the points of “a predetermined period after the activation signal is input” and “a times (drain current)” will be supplemented. First, “a predetermined period after the activation signal is input” means “in the initial state in which the potentials of the node N2 and the node N3 are in the initial state and the eighth transistor M8 and the ninth transistor M9 in series are not energized. From the time when power supply to the nodes N2 to N5 of the first to fourth current sources 1 to 3 and 9 is started (when the activation signal is input), the power supply causes the nodes N2 to N5 to approach a steady state and Period until the drain currents of the transistor M8 and the ninth transistor M9 reach a times (gate width W / gate length L of M8) / (gate width W / gate length L of M4) times the current of the second current source 2 (Predetermined period) ". Note that the activation signal may be input by an on signal of a current source.

  Next, the point “a times the drain current” will be described. The current of the fourth current source 9 is a × (gate width W of M8 / gate length L) / (gate width W of M4 / gate length L) times the current of the second current source 2 (provided that a <1 For example, a = 0.5). During the predetermined period, the power supply capability of the fourth current source 9 exceeds the drain currents of the eighth transistor M8 and the ninth transistor M9 in series, so that the gate of the tenth transistor M10 becomes high level, and the second, fifth, and Power is supplied so that the potential of the node N3 connected to the gates of the ninth transistors M2, M5, and M9 approaches a steady state. After a predetermined period, the drain current in the saturation region of the eighth transistor M8 and the ninth transistor M9 in series exceeds the current supply capability of the fourth current source 9, so that the node N5 connected to the gate of the tenth transistor M10 is at the low level. Thus, the tenth transistor M10 is turned off, and the start assist operation is finished. The timing is when the drain current of the second transistor M2 exceeds a times the drain current of the second transistor M2 in the steady state.

(Third specific example of the startup auxiliary circuit 25)
The third specific example of the activation auxiliary circuit 25 performs control to increase the potential of the node N4 connected to the gate of the first transistor M1 for a predetermined period after the activation input signal is input.

  FIG. 6 is a circuit diagram of a current driving circuit 100 including the activation auxiliary circuit 25 according to the third specific example. The activation assist circuit 25 in FIG. 6 includes, for example, eighth to twelfth transistors M8 to M12 and a fourth current source 9. The connection form of the eighth to tenth transistors M8 to M10 and the fourth current source 9 is the same as in FIG.

  The twelfth transistor M12 is different in conductivity type from the first to tenth transistors M1 to M10. The twelfth transistor M12 controls the gate voltage of the first transistor M1. The eleventh transistor M11 has a common gate with the tenth transistor M10. The gate of the twelfth transistor M12 is connected to the drain of the eleventh transistor M11. The source of the eleventh transistor M11 is connected to the ground node. A resistance element R12 is connected between the gate of the twelfth transistor M12 and the power supply voltage node VDD. The size of the twelfth transistor M12 is 1 to Mb times (Mb> 1).

  For a predetermined period after the activation signal is input, the gate of the tenth transistor M10 becomes high level, and the potential of the node N3 connected to the gates of the second, fifth, and ninth transistors M2, M5, and M9 increases. Further, since the gate potential of the eleventh transistor M11 is also increased, the gate potential of the twelfth transistor M12 is decreased and the potential of the node N4 connected to the gate of the first transistor M1 is increased. When the predetermined period ends, the potential of the node N3 connected to the gate of the second transistor M2 approaches a steady state, and the drain current of the second transistor M2 is a times the steady state (a <1, for example, a = 0.5). ) Exceeds the node N5 connected to the gate of the tenth transistor M10, the tenth transistor M10 and the eleventh transistor M11 are turned off. As a result, the twelfth transistor M12 is also turned off.

  As a modification of FIG. 6, as shown in FIG. 7, a fourteenth transistor M <b> 14 and a resistance element R <b> 13 that are Darlington-connected to the twelfth transistor M <b> 12 may be provided.

  In the first specific example and the second specific example of the reference auxiliary circuit described above, a current of a × I2 (a <1) is supplied to the eighth transistor M8 and the ninth transistor M9 within a predetermined period after the activation signal is input. , The drain current of the second transistor M2 rises earlier, but the potential at the node N5 connected to the drain of the eighth transistor M8 is high immediately after the start signal is input, and then rapidly decreases. To do. By monitoring the potential of the node N5, it is possible to determine whether or not to end the activation assistance of the second transistor M2, that is, the end timing of the predetermined period.

  FIG. 8 is an operation waveform of each part in the current driving circuit 100 of FIG. 5 or FIG. When the activation signal is input at time t0, the a × I2 current flows through the eighth and ninth transistors M8 and M9 to assist activation, so that the potential (waveform) of the node N3 connected to the gate of the second transistor M2 w1) increases linearly. After the time point (time t1) when the node N3 exceeds the threshold voltage, the drain current (waveform w2) of the second transistor M2 increases rapidly. Further, although the potential of the node N5 (waveform w3) connected to the drain of the eighth transistor M8 rapidly decreases, the point in time when the potential of the node N5 becomes a predetermined potential may be set as the end time of activation assistance.

(Fourth specific example of the startup auxiliary circuit 25)
In the fourth specific example of the activation auxiliary circuit 25, a buffer is inserted on at least one of the node N4 connected to the gate of the first transistor M1 and the node N3 connected to the gate of the second transistor M2.

  FIG. 9A and FIG. 9B are circuit diagrams of the activation auxiliary circuit 25 showing an example in which a buffer is inserted on the node N3 connected to the node of the second transistor M2. 9A and 9B includes a first buffer 11, a second buffer 12, and an analog switch 13. Pulse signals XEN and EN are input to the first buffer 11 and the second buffer 12 in synchronization with the input timing of the start signal. The pulse signals XEN and EN are signals in which the rising (falling) edge at the time of input is steep and the falling (rising) at the end changes slowly. The reason for gently changing the trailing edge (rising edge) at the end is to prevent the occurrence of overshoot and undershoot and to gently end the start assist operation.

  The first buffer 11 shown in FIG. 9A includes a PMOS transistor 14 that is connected to the power supply voltage node VDD and functions as a current source, and a PMOS transistor 15 and an NMOS that are cascode-connected between the drain of the PMOS transistor 14 and the ground node. The transistor 16 has a PMOS transistor 17 and an NMOS transistor 18 that are also cascode-connected between the drain of the PMOS transistor 14 and the ground node.

  The first buffer 11 shown in FIG. 9B is obtained by adding transistors 72 to 76 in order to make the drain voltages of the transistor 16 and the transistor 18 in FIG. 9A uniform, and the input / output offset of the first buffer 11 can be reduced. it can.

  The second buffer 12 shown in FIG. 9A includes an NMOS transistor 19 that is connected to the ground node and functions as a current source, and a PMOS transistor 20 and an NMOS transistor that are cascode-connected between the power supply voltage node VDD and the drain of the NMOS transistor 19. 21, and a PMOS transistor 22 and an NMOS transistor 23 that are also cascode-connected between the power supply voltage node VDD and the drain of the NMOS transistor 19.

  The second buffer 12 shown in FIG. 9B is obtained by adding transistors 77 to 81 in order to make the drain voltages of the transistor 20 and the transistor 22 in FIG. 9A uniform, and the input / output offset of the second buffer 12 can be reduced. it can.

  The gate of the PMOS transistor 15 and the gate of the NMOS transistor 21 are connected to the input terminal of the auxiliary start circuit 25 together with the input node of the analog switch 13. The gate of the PMOS transistor 17 and the gate of the NMOS transistor 23 are connected to the gate of the second transistor M2.

  When the pulse signals XEN and EN are input, the analog switch 13 blocks the connection path between the node N3 and the gate of the second transistor M2. When the pulse signals XEN and EN are not input, the analog switch 13 conducts the node N3 and the gate of the second transistor M2.

  During the period in which the pulse signals XEN and EN are input, the signal on the node N3 is buffered by the first buffer 11 and the second buffer 12 and then input to the gate of the second transistor M2. By buffering with the first buffer 11 and the second buffer 12, the rise of the gate voltage of the second transistor M2 becomes steep, and the startup time of the second transistor M2 can be shortened. When the pulse signals XEN and EN are not input, the first buffer 11 and the second buffer 12 do not perform the buffering operation, the node N3 and the gate of the second transistor M2 are conducted through the analog switch 13, and the normal operation is performed. Is called.

  The pulse signals XEN and EN can be generated in synchronization with the rising edge of the activation signal, for example. FIG. 10A is a circuit diagram in which a pulse generation circuit 30 is added to the start-up auxiliary circuit 25 in FIG. 9A, and FIG. 10B is a circuit diagram in which the pulse generation circuit 30 is added to the start-up auxiliary circuit 25 in FIG. 9B. 10A and 10B includes a one-shot pulse generator 31, a first waveform adjustment circuit 32, and a second waveform adjustment circuit 33.

  The one-shot pulse generator 31 includes a buffer 34, a resistance element R2, a capacitor C1, an inverter 35, and a logic gate 36. An activation signal is input to the buffer 34. When the activation signal rises, the rising waveform of the activation signal is smoothed by the resistor element R2 and the capacitor C1. The logic gate receives a start signal and a signal obtained by smoothing the start signal, and generates a one-shot pulse signal. This one-shot pulse signal is a signal whose rising edge is slightly gentle and the falling edge is trailing.

  The first waveform adjustment circuit 32 includes a circuit in which two cascode-connected PMOS transistors 37 and 38, a resistor element R3, and a capacitor C2 are connected in parallel, and a resistor element R4 and an NMOS transistor connected in series to this circuit. 39.

  The second waveform adjustment circuit 33 includes a circuit in which two cascode-connected NMOS transistors 40 and 41, a resistor element R5 and a capacitor C3 are connected in parallel, a resistor element R6 and a PMOS transistor connected in series to this circuit. 42.

  A pulse signal XEN similar to that in FIG. 9A is output from the drain of the NMOS transistor 39. Further, the same pulse signal EN as in FIG. 9A is output from the drain of the PMOS transistor 42.

  10A has a high-speed start-up circuit 43 that starts up the gate of the first transistor M1 at high speed. The fast start circuit 43 includes a PMOS transistor 44, an NMOS transistor 45, and a resistance element R7. The source of the PMOS transistor 44 is connected to the power supply voltage node VDD, and the drain of the PMOS transistor 44 is connected to the gate of the NMOS transistor 45 and one end of the resistance element R7. The drain of the NMOS transistor 45 is connected to the power supply voltage node VDD, and the source of the NMOS transistor 45 is connected to a node N4 connected to the gate of the first transistor M1.

  As described above, the current driving circuit 100 according to the first embodiment shown in FIG. 1A has been described using some modified examples and specific examples. However, these current driving circuits 100 have at least a large size and a high breakdown voltage. In order to drive the large-sized low-breakdown-voltage second transistor M2 that is cascode-connected to the first transistor M1, the third to sixth transistors M3 to M6 are provided. The second to fifth transistors M2 to M5 form a first control loop rp1 that determines the potential of the node N3 based on the potential of the node N1 and controls the drain current of the second transistor M2 to be about I2 × N. To do. The third transistor M3 and the sixth transistor M6 are controlled so that the node N1 where the source of the first transistor M1 and the drain of the second transistor M2 are connected has the same potential as the node N6 where the source of the sixth transistor M6 is connected. A second control loop rp2 is configured. By providing the first control loop rp1 and the second control loop rp2 as described above, a constant current can be output from the output terminal OUT even if the output voltage VOUT varies greatly.

  Further, as described with reference to FIGS. 9A and 10A, in the current driving circuit 100 according to the first embodiment, the start-up auxiliary circuit 25 can be additionally provided inside the circuit. By providing the start-up auxiliary circuit 25, the time until the first transistor M1 starts to output current can be shortened. The activation assist circuit 25 operates only for a predetermined period after the activation signal is input, and stops operating when the predetermined period elapses, so there is no possibility that the power consumption increases.

(Second Embodiment)
In the second embodiment, a circuit for increasing the speed is added to the current driving circuit 100 of FIG. 1A.

  FIG. 11 is a circuit diagram of the current driving circuit 100 according to the second embodiment. The current drive circuit 100 of FIG. 11 includes eighth to twelfth transistors M8 to M12, a fourth current source 9, and a resistance element R1 in addition to the circuit configuration of the current drive circuit 100 of FIG. 1A. The connection relationship among the eighth to twelfth transistors M8 to M12, the fourth current source 9, and the resistance element R1 is the same as that in FIG.

  The resistance value of the resistance element R1 is set to a value obtained by dividing the static potential of the node N1 by the current I3 output from the third current source 3. The current ratio between the current I2 output from the second current source 2 and the current I3 output from the third current source 3 is set to the current mirror ratio of the fourth transistor M4 and the sixth transistor M6.

  The third transistor M3, the fourth transistor M4, and the fifth transistor M5 in FIG. 11 constitute a gate voltage generation circuit of the second transistor M2. Further, the sixth transistor M6, the seventh transistor M7, and the third current source 3 constitute a gate voltage generation circuit of the first transistor M1.

FIG. 12 is a circuit diagram of a current driving circuit 100 according to a modification of FIG. The current drive circuit 100 in FIG. 12 includes a seventh transistor M7 instead of the resistance element R1 in FIG.
The connection relationship of the seventh transistor M7 is the same as that in FIG. 2A.

The ratio between the current I2 output from the second current source 2 and the current I3 output from the third current source 3 is set by the ratio of the gate width W / gate length L of the fourth transistor M4 and the sixth transistor M6. Similarly, the W / L of the fifth transistor M5 and the seventh transistor M7 is also set to the same ratio. By adjusting this ratio, the gate voltage of the first transistor M1 can be adjusted, and the drain current of the first transistor M1 (the output current of the current driving circuit 100) can be adjusted. As shown in the following equation (1), the output current Iout is the current mirror ratio (W2 / L2) / (W5 / of the fifth transistor M5 and the second transistor M2) to the current I2 output from the second current source 2. A value obtained by subtracting the current I1 output from the first current source 1 from the value multiplied by L5).
Iout = I2 × (W2 / L2) / (W5 / L5) −I1 (1)

  The eighth to tenth transistors M8 to M10 in FIGS. 11 and 12 constitute a part of the startup auxiliary circuit 25, and start up the gate voltage of the second transistor M2 at high speed. 11 and 12 is basically the same in configuration as the circuit shown in FIG. 6, for example, the eighth to twelfth transistors M8 to M12 and the fourth current source. 9. The gate of the tenth transistor M10 is connected to the node N5, and the drain is connected to the node N3. Thus, the node N3 is a source follower output, and the node N3 is set to a predetermined potential by the tenth transistor M10 only at the time of activation.

  The current mirror ratio between the current I4 output from the fourth current source 9 and the current I2 output from the second current source 2 is the W / L ratio between the eighth transistor M8 and the fourth transistor M4, the ninth transistor M9, The W / L ratio of each of the five transistors M5 is set to the same value.

  FIGS. 13 and 14 are circuit diagrams in which a thirteenth transistor M13 is added to the current driving circuit 100 of FIGS. 11 and 12, respectively. The thirteenth transistor M13 has a common gate with the second transistor M2. The drain of the thirteenth transistor M13 is connected to the node N5, and the source is connected to the ground node.

  By providing the thirteenth transistor M13, it is possible to clamp the potential of the node N5 so as not to rise above 2Vth, and to suppress the function of the tenth transistor M10.

  The eleventh transistor M11 shown in FIGS. 11 to 14 constitutes a part of the auxiliary start circuit 25 for starting the gate voltage of the first transistor M1 at high speed. The eleventh transistor M11 has a gate connected to the node N5, a source connected to the ground node, and a drain connected to the gate of the twelfth transistor M12. The twelfth transistor M12 is a MOS transistor having a polarity opposite to that of the first to eleventh transistors M1 to M11 (for example, p-type). The source of the twelfth transistor M12 is connected to the power supply voltage node VDD, and the drain is connected to the node N4.

  A circuit for turning on the twelfth transistor M12 may be provided separately. For example, a pulse signal output from the pulse generation circuit 30 in FIG. 10A or a pulse signal using the potential of the node N5 may be applied to the gate of the twelfth transistor M12.

(Operation of the second transistor M2 in the off state)
When the drain voltage of the first transistor M1 decreases, it is necessary to prevent the current I1 from the first current source 1 from flowing from the drain of the first transistor M1 to the OUT terminal. In order to prevent this, as shown in FIG. 15, a first switch 51 may be connected between a node N3 connected to the gate of the second transistor M2 and the ground node. FIG. 15A shows a case where the second transistor M2 is in an off state, and FIG. 15B shows a case where the second transistor M2 is in an on state. The first switch 51 makes the node N3 conductive to the ground node as shown in FIG. 15A when the second transistor M2 is in the OFF state. When the second transistor M2 is on, the connection between the node N3 and the ground node is cut off as shown in FIG. 15 (b).

  To reliably prevent the current I1 from the first current source 1 from flowing from the drain of the first transistor M1 to the OUT terminal when the drain voltage of the first transistor M1 decreases, as shown in FIG. A simple circuit may be adopted. In FIG. 16, in addition to the first switch 51 of FIG. 15, a second switch 52 is inserted between the source of the third transistor M3 and the node N1. FIG. 16A shows a case where the second transistor M2 is in an off state, and FIG. 16B shows a case where the second transistor M2 is in an on state.

  When the second transistor M2 is in the ON state, as shown in FIG. 16B, the second switch 52 makes the drain of the second transistor M2 conductive to the node N1. On the other hand, when the second transistor M2 is in the off state, the second switch 52 cuts off the connection between the source of the third transistor M3 and the node N1. Thereby, when the second transistor M2 is in the OFF state, it is possible to prevent the current I1 from the first current source 1 from flowing out to the OUT terminal through the node N1.

  The current drive circuit 100 in FIG. 17 includes a third switch 53 and a fourth switch 54 instead of the second switch 52 in FIG. The third switch 53 is interposed between the node N4 connected to the gate of the first transistor M1 and the ground node. The fourth switch 54 is interposed between the node N2 connected to the gate of the third transistor M3 and the ground node. FIG. 17A shows a case where the second transistor M2 is in an off state, and FIG. 17B shows a case where the second transistor M2 is in an on state.

  When the second transistor M2 is on, the third switch 53 cuts off the connection between the node N4 connected to the gate of the first transistor M1 and the ground node. The fourth switch 54 cuts off the connection between the node N2 connected to the gate of the third transistor M3 and the ground node. On the other hand, when the second transistor M2 is off, the third switch 53 makes the node N4 connected to the gate of the first transistor M1 conductive to the ground node. The fourth switch 54 makes the node N2 connected to the gate of the third transistor M3 conductive to the ground node. Thereby, the second transistor M2 and the third transistor M3 are surely turned off, and there is no possibility that the current I1 from the first current source 1 flows into the OUT terminal through the node N1.

  In the current drive circuit 100 of FIGS. 11 to 14, the second transistor M2 has a size (1 + N) times that of the third to thirteenth transistors M3 to M13 having the same low breakdown voltage. The second transistor M2 can be divided into a 1-times size 1-times portion M2-1 and N-times-size N-times portion M2-N that are the same as the 3rd to 13th transistors M3 to M13. . FIG. 18A and FIG. 18B are equivalent circuit diagrams in the case where the second transistor M2 is divided into a 1 × portion M2-1 and an N × portion M2-N. FIG. 18A is an equivalent circuit diagram in which the second transistor M2 is in an OFF state, and FIG. 18B is an equivalent circuit diagram in which the second transistor M2 is in an ON state. This equivalent circuit includes a first switch 51 interposed between the gate of the N-fold portion M2-N and the ground node, and between the gate of the 1-fold portion M2-1 and the gate of the N-fold portion M2-N. And a fifth switching device 55 inserted in the.

  When the second transistor M2 is in the off state, as shown in FIG. 18A, the fifth switch 55 is off and the gate of the 1 × portion M2-1 is connected to the node N3. The gate of -N is cut off from the node N3. Further, the first switch 51 is turned on to connect the gate of the N-fold portion M2-N to the ground node. As a result, the gate voltage of the N-fold portion M2-N is completely discharged, and the N-fold portion M2-N is turned off. Since the 1 × portion M2-1 operates, the current I1 flowing from the first current source 1 to the node N1 flows through the 1 × portion M2-1 to the ground node.

  When the second transistor M2 is on, the fifth switch 55 is turned on and the first switch 51 is turned off as shown in FIG. Therefore, the drain current of the first transistor M1 flows through the N-fold portion M2-N. Further, the current flowing from the first current source 1 to the node N1 flows to the 1 × portion M2-1.

  As described above, when the startup auxiliary circuit 25 is connected to the node N3 connected to the gate of the second transistor M2, the 1 × portion M2-1 is arranged on the input side of the startup auxiliary circuit 25, and the N × portion M2-N is It is desirable to arrange on the output side of the start-up auxiliary circuit 25.

  19 (a) and 19 (b) are equivalent circuit diagrams in which a startup auxiliary circuit 25 is added to FIGS. 18 (a) and 18 (b). FIG. 19A is an equivalent circuit diagram in which the second transistor M2 is in an off state, and FIG. 19B is an equivalent circuit diagram in which the second transistor M2 is in an on state. As shown in FIGS. 19A and 19B, the potential of the connection node between the node N3 and the 1 × portion M2-1 is input to the activation assist circuit 25. The output signal of the start assist circuit 25 is input to the gate of the N-times portion M2-N at the input terminal of the start assist circuit 25. The start assist circuit 25 performs start assist according to the signal cnt. The signal cnt is a signal that becomes, for example, a high level only for a predetermined period after the activation signal is input.

20A, 20B, and 20C are circuit diagrams of the current drive circuit 100 in which the sixth switch 56 is interposed between the output node of the auxiliary start circuit 25 of FIG. 19 and the gate of the second transistor M2. In the circuits of FIGS. 20A to 20C, at the time of startup, the gate of the second transistor M2 is driven using both the startup auxiliary circuit 25 and the potential of the node N3. FIG. 20A shows a case where the second transistor M2 is in an off state, FIG. 20B shows a case where the second transistor M2 is activated, and FIG. 20C shows a case where the second transistor M2 is in an on state after activation. 20A to 20C includes a first switch 51 and a fifth switch 55 similar to those in FIG. The sixth switch 56 in FIGS. 20A to 20C switches whether the output node of the auxiliary start-up circuit 25 and the gate of the second transistor M2 are conducted. When the second transistor M2 is off, the first switch 51 causes the gate of the second transistor M2 to conduct to the ground node as shown in FIG. 20A. Further, the fifth switch 55 and the sixth switch 56 are in an open state, and the second transistor M2 is completely turned off. When the second transistor M2 is activated, as shown in FIG. 20B, the first switch 51 cuts off the connection between the gate of the second transistor M2 and the ground node. The fifth switch 55 connects the node N3 and the gate of the second transistor M2. The sixth switch 56 connects the output node of the activation assist circuit 25 to the gate of the second transistor M2.
As a result, the second transistor M2 is activated at high speed. When the second transistor M2 is in an on state after startup, as shown in FIG. 20C, the first switch 51 and the sixth switch 56 are in an open state, and the fifth switch 55 is connected to the node N3 and the second transistor M2. Connect to the gate.
As a result, the auxiliary activation circuit is disconnected, and the second transistor M2 operates based on the potential of the node N3.

  21A, FIG. 21B, and FIG. 21C are circuit diagrams of the current driving circuit 100 that drives the gate of the second transistor M2 only by the auxiliary starting circuit 25 at the time of starting, unlike FIGS. 20A to 20C. 21A to 21C are configured by adding a sixth switch 56 to the circuit of FIG. 21A shows a case where the second transistor M2 is in an off state, FIG. 21B shows a case where the second transistor M2 is activated, and FIG. 21C shows a case where the second transistor M2 is in an on state. The circuits of FIGS. 21A to 21C are different from the circuits of FIGS. 20A to 20C in that the fifth switch 55 is in an open state at the time of startup. At the time of start-up, the output node of the start-up auxiliary circuit 25 is connected to the gate of the N-fold portion M2-N, and the output node of the start-up auxiliary circuit 25 is not connected to the gate of the one-time portion M2-1.

22A, 22B, and 22C show that both the auxiliary auxiliary circuit 25 and the potential of the node N3 are used at the time of startup when the second transistor M2 is not divided into the 1-fold portion M2-1 and the N-fold portion M2-N. FIG. 5 is a circuit diagram of a current driving circuit 100 that drives the gate of the second transistor M2.
22A shows a case where the second transistor M2 is in an off state, FIG. 22B shows a case where the second transistor M2 is activated, and FIG. 22C shows a case where the second transistor M2 is in an on state. The switching states of the first, second and sixth switchers 56 in FIG. 22 are the same as those in FIG.

FIG. 23A, FIG. 23B, and FIG. 23C show the case where both the auxiliary auxiliary circuit 25 and the potential of the node N3 are used at the time of startup when the second transistor M2 is not divided into the 1-fold portion M2-1 and the N-fold portion M2-N. FIG. 5 is a circuit diagram of a current driving circuit 100 that drives the gate of the second transistor M2.
23A shows a case where the second transistor M2 is in an off state, FIG. 23B shows a case where the second transistor M2 is activated, and FIG. 23C shows a case where the second transistor M2 is in an on state. The switching states of the first, second, and sixth switchers 56 in FIG. 23 are the same as those in FIG.

(Difference from the circuit of one comparative example)
FIG. 24 is a circuit diagram of a current driving circuit 100 according to a comparative example. The current drive circuit 100 of FIG. 24 includes a low breakdown voltage second transistor M2, cascode-connected to a high breakdown voltage first transistor M1, a third transistor M3, a first current source 1, a first differential amplifier 61, and the like. The second differential amplifier 62 is provided. The non-inverting input terminal of the first differential amplifier 61 is connected to a connection node between the first current source 1 and the drain of the third transistor M3. The inverting input terminal of the first differential amplifier 61 is connected to a connection node between the source of the first transistor M1 and the drain of the second transistor M2. The output node of the first differential amplifier 61 is connected to the gate of the first transistor M1. A non-inverting input terminal of the second differential amplifier 62 is connected to a connection node between the first current source 1 and the drain of the third transistor M3. A voltage source 63 that outputs a predetermined voltage is connected to the inverting input terminal of the second differential amplifier 62. The output node of the second differential amplifier 62 is connected to the gate of the second transistor M2.

  FIG. 25 is a diagram illustrating a curve indicating a correspondence relationship between the output voltage output from the OUT terminal connected to the drain of the first transistor M1 and the output current flowing from the OUT terminal. A curve w4 shows the current drive circuit 100 according to the present embodiment, and a curve w5 shows the current drive circuit 100 according to one comparative example of FIG. It can be seen that the curve w4 has a sharper rise than the curve w5, and is superior in constant current characteristics.

  FIG. 26A and FIG. 26B are diagrams showing the response of the output current of the current drive circuit 100 according to this embodiment and a comparative example. In FIGS. 26A and 26B, the horizontal axis represents time, and the vertical axis represents output current. 26 (a) and 26 (b) show the responsiveness when the current driving circuit 100 according to the present embodiment and one comparative example is pulse-driven for a period of 200 ns, 400 ns, 600 ns, 800 ns, and 1000 ns. The output current waveform of 200 ns to 1000 ns is represented by w6 to w10. As illustrated, in the present embodiment, the output current becomes constant immediately after startup, whereas in one comparative example, the time until the output current becomes constant is long. Thereby, it turns out that starting time is short in this embodiment.

  Thus, in the second embodiment, since the seventh transistor M7 or the resistor element R1 is provided in the current driving circuit 100, the first transistor is set so that a desired output current is output from the drain of the first transistor M1. The gate voltage of M1 can be adjusted. In the second embodiment, since the eighth to twelfth transistors M8 to M12 are provided in the current driving circuit 100, the start-up of the second transistor M2 can be speeded up. Furthermore, in the second embodiment, since the eleventh transistor M11 is provided in the current driving circuit 100, the start-up of the first transistor M1 can be speeded up.

  In the first and second embodiments described above, the first transistor M1 may be incorporated in the current driving circuit 100, or the first transistor M1 may be externally attached.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 first current source, 2 second current source, 3 third current source, 4 OTA, 5 differential amplifier, 6
1st voltage source, 7 2nd voltage source, 8 3rd voltage source, 9 4th current source, 10 1st starting switch, 11 2nd starting switch, 25 starting auxiliary circuit, 100 current drive circuit,

Claims (10)

A first transistor that outputs current;
A second transistor cascode-connected to the first transistor;
A third transistor cascode-connected to the second transistor;
A first current source for supplying current to the third transistor and the second transistor;
A fourth transistor sharing a gate with the third transistor;
A fifth transistor having a common gate to the second transistor and cascode-connected to the fourth transistor;
A second current source for supplying current to the fourth transistor and the fifth transistor;
A sixth transistor for controlling a gate voltage of the first transistor by sharing a gate with the third transistor and the fourth transistor;
And a third current source for supplying a drain current of the sixth transistor. The second transistor is larger in size than the third to sixth transistors, and
2. The current drive circuit according to claim 1, further comprising a start assist circuit that speeds up an operation of at least one of the first transistor and the second transistor for a predetermined period after the start signal is input.   3. The current drive circuit according to claim 2, wherein the activation assist circuit increases a gate current of at least one of the first transistor and the second transistor for the predetermined period after the activation signal is input. The starting auxiliary circuit is
A buffer interposed in at least one of a path connected to the gate of the first transistor and a path connected to the gate of the second transistor;
The current drive circuit according to claim 2, further comprising: a switching circuit that operates the buffer within the predetermined period and bypasses the buffer after the predetermined period has elapsed.   5. The current drive circuit according to claim 2, wherein the predetermined period is a period from when the activation signal is input to when a drain current of the second transistor becomes a predetermined current. 6.   6. The current drive circuit according to claim 1, further comprising a seventh transistor that is cascode-connected to the sixth transistor and has a gate common to the sixth transistor.   6. The current drive circuit according to claim 1, further comprising a resistance element interposed on a path through which a drain current of the sixth transistor flows. An eighth transistor sharing a gate with the third transistor, the fourth transistor, and the sixth transistor;
A ninth transistor having a common gate to the second transistor and the fifth transistor and cascode-connected to the eighth transistor;
A fourth current source for supplying drain currents of the eighth transistor and the ninth transistor;
10. A tenth transistor that controls gate voltages of the second transistor, the fifth transistor, and the ninth transistor based on a voltage at a connection node between the fourth current source and the eighth transistor. The current drive circuit according to any one of 1 to 7. An eleventh transistor having a common gate with the tenth transistor;
The current drive according to claim 8, further comprising: a twelfth transistor having a conductivity type different from that of the second to eleventh transistors and controlling a gate voltage of the first transistor in accordance with a drain voltage of the eleventh transistor. circuit.   10. The current drive circuit according to claim 8, further comprising a thirteenth transistor having a gate shared with the second transistor, the fifth transistor, and the ninth transistor and supplied with a drain current from the fourth current source. 11. .

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