JP2019165396A - Terminal device - Google Patents

Abstract

To obtain a terminal device with which it is possible to prevent an unnecessary rise of the voltage of an internal power supply generated on the basis of a voltage pulse.SOLUTION: Provided is a terminal device of a signal transmission system in which, while a central processing device feeds power to the terminal device using two transmission lines sa, sb, a control signal is transmitted from the central processing device to the terminal device while inverting the voltage polarities of transmission lines sa, sb. The terminal device comprises: a rectification circuit 21 for rectifying a voltage pulse transmitted from the central processing device via two transmission lines sa, sb before outputting; a peak voltage suppression circuit 23 for accepting a DC voltage outputted from the rectification circuit 21 as input, and when the inputted DC voltage exceeds a predetermined value, suppressing the DC voltage to or below the predetermined value before outputting; and a smoothing circuit 26 for smoothing the DC voltage outputted from the peak voltage suppression circuit 23.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a terminal device that communicates with a central processing unit while receiving power from the central processing unit via two transmission lines.

  In a signal transmission system in which the central processing unit uses two transmission lines to supply power to the terminal and transmit control signals, signal transmission from the central processing unit to the terminal is performed in a voltage mode in which the voltage is changed. The signal transmission from the terminal unit to the central processing unit is performed in a current mode in which the current is changed (for example, Patent Document 1).

Japanese Patent Laid-Open No. 2-200095

  In the above signal transmission system, the terminal rectifies the voltage pulse output from the central processing unit to the transmission line, and stores it in a capacitor provided in the circuit to obtain an internal power source. However, when the frequency component included in the edge of the voltage pulse resonates with the transmission line, high-frequency ringing occurs, and an inrush current flows into the capacitor provided in the terminal device. For this reason, terminal devices that consume a small amount of current and cannot consume surplus power from the inrush current due to the first voltage pulse after the occurrence of one voltage pulse until the next voltage pulse is There is a problem that the parts may be damaged.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a terminal device that can prevent an internal power supply voltage generated based on a voltage pulse from rising more than necessary.

  In order to solve the above-described problems and achieve the object, the present invention provides a transmission line from the central processing unit to the terminal device while the central processing unit supplies power to the terminal device using two transmission lines. This is a terminal device of a signal transmission system that transmits a control signal while reversing the voltage polarity. The terminal device receives a rectification circuit that rectifies and outputs a voltage pulse transmitted from the central processing unit via two transmission lines, and a DC voltage output from the rectification circuit. A peak voltage suppression circuit that suppresses and outputs a DC voltage so as to be equal to or less than a predetermined value when a predetermined value is exceeded, a smoothing circuit that smoothes the DC voltage output from the peak voltage suppression circuit, Is provided.

  The terminal device according to the present invention has an effect that the voltage of the internal power source generated based on the voltage pulse can be prevented from rising more than necessary.

The figure which shows an example of the signal transmission system comprised including the terminal device concerning Embodiment 1. FIG. The figure which shows an example of the signal of the voltage mode which the central processing unit concerning Embodiment 1 outputs to a transmission line The figure which shows the structural example of the terminal device concerning Embodiment 1. FIG. The figure which shows an example of the voltage mode signal input into the terminal device concerning Embodiment 1. The figure which shows an example of the voltage waveform produced | generated inside the terminal device concerning Embodiment 1. The figure which shows the structural example of the terminal device concerning Embodiment 2. FIG. The figure which shows an example of the voltage waveform produced | generated inside the terminal device concerning Embodiment 2.

  Below, the terminal device concerning an embodiment of the invention is explained in detail based on a drawing. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating an example of a signal transmission system including the terminal device according to the first embodiment of the present invention.

  A signal transmission system 100 according to the present embodiment includes a central processing unit 1 and a terminal device 2, and the central processing unit 1 and each terminal device 2 have two transmission lines, a transmission line sa and a transmission line sb. Connected through. The central processing unit 1 is supplied with AC power from an AC power source 3.

  The central processing unit 1 supplies power to the terminal device 2 via the transmission line sa and the transmission line sb, and controls the terminal device 2 by transmitting a control signal. The terminal device 2 operates according to the content of the control signal received from the central processing unit 1. For example, the terminal device 2 is connected to another device (not shown), and controls the other connected device according to the control information included in the control signal received from the central processing unit 1. An example of another device is a lighting device, but is not limited thereto.

  FIG. 2 is a diagram illustrating an example of a voltage mode signal output to the transmission line sa and the transmission line sb by the central processing unit 1 according to the first embodiment.

  The central processing unit 1 switches between positive and negative polarities at intervals (at [sec], bt [sec] in the example of FIG. 2) based on the content of the control signal to be transmitted with a voltage pulse of ± ΔV as shown in FIG. Thus, a control signal is transmitted to the terminal device 2. Note that the width bt of the voltage pulse of −ΔV and the width at of the voltage pulse of + ΔV correspond to the state of the bit included in the control signal. For example, if the bit state is “1”, the central processing unit 1 sets the voltage pulse width to “at”, and if it is “0”, sets the voltage pulse width to “bt”. In this case, if the control signal includes a bit string in which 1 and 0 are alternately repeated, a voltage pulse having a width of at and a voltage pulse having a width of bt are alternately repeated in a section where 1 and 0 are alternately repeated. become. On the other hand, the terminal device 2 responds to the central processing unit 1 by generating a current pulse having a pulse width of Δt by short-circuiting the transmission line sa and the transmission line sb over a predetermined time. Note that Δt is a constant value.

  FIG. 3 is a diagram of a configuration example of the terminal device 2 according to the first embodiment. The terminal device 2 includes a control circuit 20, a rectifier circuit 21, a current pulse output circuit 22, a peak voltage suppression circuit 23, a backflow prevention circuit 24, a current limiting circuit 25, a smoothing circuit 26, and a load 30. The rectifier circuit 21 is connected to the transmission line sa and the transmission line sb. A voltage pulse of ± ΔV of a voltage mode signal generated by the central processing unit 1 and output to the transmission line sa and the transmission line sb is input to the rectifier circuit 21. A load 30 is connected to both ends of the smoothing circuit 26. The rectifier circuit 21, the peak voltage suppression circuit 23, the current limiting circuit 25, and the smoothing circuit 26 are circuits that generate an internal power source based on voltage pulses output from the central processing unit 1. In addition, the circuit element which comprises each circuit with which the terminal device 2 is provided, and the connection relation of each circuit element are not limited to what was shown in FIG. As long as the operation of each circuit described below can be realized, the types, number, and connection relationships of circuit elements constituting the circuit may be different.

  The control circuit 20 controls the transistor Q1 of the current pulse output circuit 22. The control circuit 20 is realized by a microcontroller, for example. The rectifier circuit 21 includes a diode bridge DB, and rectifies ± ΔV voltage pulses input from the transmission line sa and the transmission line sb into a DC voltage. The current pulse output circuit 22 includes a transistor Q1 and a resistor R1. The current pulse output circuit 22 is controlled by the control circuit 20, and generates a current pulse that is a signal to be transmitted to the central processing unit 1 by short-circuiting the transmission line sa and the transmission line sb. The peak voltage suppression circuit 23 includes a Zener diode ZD1. When the DC voltage generated by the rectifier circuit 21 exceeds a predetermined constant value, the peak voltage suppression circuit 23 suppresses the voltage to be equal to or lower than the predetermined value and outputs it. The backflow prevention circuit 24 includes a diode D1. The backflow prevention circuit 24 prevents a current from flowing back from the smoothing circuit 26 to the rectifying circuit 21 when the DC voltage generated by the rectifying circuit 21 is lower than the voltage across the smoothing circuit 26. The current limiting circuit 25 includes a limiting resistor R2 and suppresses an inrush current that flows into the smoothing circuit 26. The smoothing circuit 26 includes a storage capacitor C1. The smoothing circuit 26 performs smoothing by accumulating the current output from the rectifier circuit 21 in the storage capacitor C1. The charge accumulated in the storage capacitor C1 is consumed by the load 30.

  The rectifier circuit 21 is assumed to be realized by the diode bridge DB, but any circuit or element that can rectify an AC (Alternating Current) input waveform into a DC (Direct Current) waveform may be used. . The current pulse output circuit 22 is assumed to be a switching circuit composed of a transistor Q1 which is a bipolar transistor and a resistor R1, but a switching circuit using an FET (Field Effect Transistor) instead of the bipolar transistor, etc. Any circuit or element that can short-circuit the transmission line may be used. Further, the peak voltage suppression circuit 23 is assumed to be a voltage limiter circuit constituted by a Zener diode ZD1, but a circuit capable of suppressing voltage peaks, such as a voltage limiter circuit using a varistor or a triac instead of a Zener diode, Alternatively, any element may be used. In addition, the diode D1 of the backflow prevention circuit 24 is assumed to be a unidirectional rectifier element formed of a switching diode, but a current does not flow in the reverse direction, such as a unidirectional rectifier element using a Schottky barrier diode. Any circuit or element that can be controlled may be used.

  Hereinafter, the operation of the terminal device 2 according to the present embodiment, specifically, the operation of suppressing the inrush current to the storage capacitor C1 constituting the smoothing circuit 26 will be described with reference to FIGS. FIG. 4 is a diagram of an example of a voltage mode signal input to the terminal device according to the first embodiment. FIG. 5 is a diagram illustrating an example of a voltage waveform generated inside the terminal device 2 according to the first embodiment.

  The voltage of the waveform shown in FIG. 4, that is, the voltage in which the ringing waveform generated by the resonance of the high frequency component included in the edge of the voltage pulse on the transmission lines sa and sb is superimposed on the rectifier circuit 21 of the terminal device 2. A pulse is input. When this voltage pulse passes through the rectifier circuit 21, it is rectified to a DC voltage of + ΔV as shown in FIG. 5, but the DC voltage after rectification also has a ringing waveform superimposed thereon. Therefore, the DC voltage having the waveform shown in FIG. 5 is output from the rectifier circuit 21 and reaches the peak voltage suppression circuit 23 via the current pulse output circuit 22.

  When the peak voltage + Vp of the ringing waveform included in the DC voltage input from the rectifier circuit 21 is larger than the voltage + Vcl to be suppressed by the peak voltage suppression circuit 23, a current flows through the Zener diode ZD1. As a result, the peak voltage is lowered by the difference voltage between + Vp and + Vcl, that is, “Vp−Vcl”, and the peak voltage is suppressed to + Vcl as shown in FIG. In FIG. 5, the solid line is the waveform of the voltage output from the rectifier circuit 21 and corresponds to the waveform of the voltage input to the peak voltage suppression circuit 23. A broken line indicates a waveform of a voltage output from the peak voltage suppression circuit 23. The DC voltage after the peak voltage suppression output from the peak voltage suppression circuit 23 reaches the current limiting circuit 25 via the backflow prevention circuit 24.

  When the voltage input to the limiting resistor R2 of the current limiting circuit 25 is larger than the voltage Vcc required by the internal power supply, the limiting resistor R2 calculates the difference between the input voltage and the voltage Vcc, that is, the voltage Vcc from the input voltage. The current flowing through the backflow prevention circuit 24 is consumed so that the input voltage is stepped down by the subtracted voltage. Thereby, the current limiting circuit 25 suppresses the inrush current flowing into the storage capacitor C1 of the smoothing circuit 26 so as to become the current Irl consumed by the load 30. The resistance value of the limiting resistor R2 is sufficient for the time constant of the circuit formed by the limiting resistor R2 and the storage capacitor C1 to suppress the inrush current with respect to the value and frequency of the inrush current to the storage capacitor C1. It is determined to be a value. The value sufficient to suppress the inrush current is a value at which the power accumulated excessively in the storage capacitor C1 due to the inrush current is equal to or lower than the power consumed by the load 30, that is, the voltage across the storage capacitor C1 is constant. It is a value that is less than or equal to the value. The time constant of the circuit configured by the limiting resistor R2 and the storage capacitor C1 is determined based on the frequency of the inrush current to the storage capacitor C1 and the average value of the power consumed by the load 30.

  In general, the smaller the peak value + Vcl of the voltage after passing through the peak voltage suppression circuit 23, the higher the peak voltage suppression effect of the ringing waveform. However, if the amount of suppression by the peak voltage suppression circuit 23 is increased and the value of + Vcl is decreased, the differential voltage Vp−Vcl increases, so that the current that flows through the Zener diode ZD1 during the operation of the peak voltage suppression circuit 23 increases. Circuit or element is required. Further, the larger the resistance value of the limiting resistor R2, the more the inrush current can be suppressed, but the voltage loss due to the limiting resistor R2 increases.

  Since the peak voltage suppression circuit 23 and the current limiting circuit 25 are each effective for suppressing the inrush current flowing into the storage capacitor C1, the voltage mode signal can be obtained even when the circuit is provided with either one of the circuits. It is possible to prevent the internal power supply voltage generated from the excessive rise in voltage and damage to the components. However, by combining the peak voltage suppression circuit 23 and the current limiting circuit 25, the peak voltage suppression circuit 23 can be reduced in size, and the resistance value of the limiting resistor R2 of the current limiting circuit 25 can be decreased. Since the resistance value of the limiting resistor R2 can be reduced, voltage loss due to the limiting resistor R2 can be reduced. In this case, the time constant of the circuit constituted by the limiting resistor R2 and the storage capacitor C1 is based on the power consumption of the load 30, and the peak of the inrush current determined by the peak voltage + Vcl after the peak is suppressed by the peak voltage suppression circuit 23 It is determined to be a sufficient value for the value and the frequency of the inrush current.

  As described above, the terminal device 2 according to this embodiment includes the peak voltage suppression circuit 23 that suppresses the peak value of the DC voltage obtained by rectifying the voltage pulse output from the central processing unit 1, and the DC voltage is smoothed. And a current limiting circuit 25 for limiting the inrush current to the smoothing circuit 26 to be converted. Thereby, the peak value of the voltage applied to the storage capacitor C1 constituting the smoothing circuit 26 can be suppressed, and the voltage of the internal power supply can be prevented from rising more than necessary. Moreover, since the terminal device 2 suppresses the peak value of the voltage applied to the storage capacitor C1 by the peak voltage suppression circuit 23 and the current limiting circuit 25, it can prevent the respective circuits from becoming large. Further, the voltage loss in the limiting resistor R2 of the current limiting circuit 25 can be reduced.

Embodiment 2. FIG.
FIG. 6 is a diagram of an example of a circuit configuration of the terminal device according to the second embodiment. In the terminal device 2a according to the second embodiment, the peak voltage suppression circuit 23 of the terminal device 2 according to the first embodiment is deleted, and a peak voltage suppression circuit 27 is provided in the previous stage of the rectifier circuit 21. Since the configuration of the terminal device 2a other than the peak voltage suppression circuit 27 is the same as that of the terminal device 2, the description of the configuration other than the peak voltage suppression circuit 27 is omitted.

  The peak voltage suppression circuit 27 includes a bidirectional Zener diode ZD2. When the voltage value of the voltage pulse of ± ΔV inputted from the transmission line sa and the transmission line sb exceeds a predetermined value, the peak voltage suppression circuit 27 becomes a voltage (± ΔVcl) that is equal to or lower than the predetermined value. Suppress and output.

  The rectifier circuit 21 of the terminal device 2a receives a voltage pulse in a state where the peak voltage suppression circuit 27 suppresses the voltage value in the range of −ΔVcl to + ΔVcl. The rectifier circuit 21 rectifies ± ΔVcl voltage pulses input via the peak voltage suppression circuit 27 into a DC voltage. When the waveform of the input voltage mode signal input to the terminal device 2a is as shown in FIG. 4, the waveform of the voltage output from the rectifier circuit 21 is as shown in FIG. In the terminal device 2a, the peak voltage suppression circuit 27 suppresses the voltage peak in the previous stage of the rectifier circuit 21, so that the peak of the voltage waveform shown in FIG. Becomes smaller than the peak of the voltage waveform shown by the solid line in FIG.

  The terminal device 2a according to the present embodiment can achieve the same effects as the terminal device 2 according to the first embodiment.

  The configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.

  DESCRIPTION OF SYMBOLS 1 Central processing unit, 2 Terminal device, 3 AC power supply, 20 Control circuit, 21 Rectifier circuit, 22 Current pulse output circuit, 23 Peak voltage suppression circuit, 24 Backflow prevention circuit, 25 Current limiting circuit, 26 Smoothing circuit, 30 Load, 100 Signal transmission system.

Claims (4)

Signal transmission in which the central processing unit uses two transmission lines to feed power to the terminal device and transmits a control signal from the central processing unit to the terminal device while inverting the voltage polarity of the transmission line. The terminal device of the system,
A rectifying circuit that rectifies and outputs voltage pulses transmitted from the central processing unit via the two transmission lines;
DC voltage output from the rectifier circuit is input, and when the input DC voltage exceeds a predetermined value, the DC voltage is suppressed and output so as to be equal to or less than the predetermined value. Circuit,
A smoothing circuit for smoothing a DC voltage output from the peak voltage suppression circuit;
A terminal device comprising: Signal transmission in which the central processing unit uses two transmission lines to feed power to the terminal device and transmits a control signal from the central processing unit to the terminal device while inverting the voltage polarity of the transmission line. The terminal device of the system,
When the voltage of the voltage pulse transmitted from the central processing unit via the two transmission lines exceeds a predetermined value, the voltage of the voltage pulse is suppressed to be equal to or less than the predetermined value. Output peak voltage suppression circuit,
A rectifying circuit that rectifies and outputs a voltage pulse output from the peak voltage suppressing circuit;
A smoothing circuit for smoothing a DC voltage output from the rectifier circuit;
A terminal device comprising: A current limiting circuit for suppressing an inrush current to the smoothing circuit;
The terminal device according to claim 1, comprising: The smoothing circuit is a capacitor,
The current limiting circuit is a resistor,
The time constant of the circuit composed of the capacitor and the resistor is determined based on the frequency of the inrush current and the power consumption of the load that consumes the power stored in the capacitor.
The terminal device according to claim 3.

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