JP2019149609A - Imaging apparatus and signal processing method in the same - Google Patents

Abstract

To reliably detect a synchronization code even when transfer data is scrambled.SOLUTION: The imaging apparatus includes: an oscillator that generates a reference clock; synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in synchronization with a reference clock; image signal readout means for reading out an image signal in synchronization with the horizontal synchronization signal and the vertical synchronization signal; synchronization code adding means for adding a synchronization code to the image signal in synchronization with the horizontal synchronization signal; synchronization code detecting means for detecting the synchronization code; an effective period generation circuit that determines a first effective period that is started in synchronization with the vertical synchronization signal and ends by detecting the synchronization code as a period for validating a detection result of the synchronization code detecting means and a second effective period that is started after a predetermined time has elapsed since the detection of the synchronization code detected within the first effective period and ends when the synchronization code is detected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technique for detecting a horizontal synchronization signal included in an image signal output from an image sensor (image sensor).

With the recent increase in image quality and frame rate of image sensors, high-speed readout of pixel data from image sensors is required.
As a sensor capable of handling such high-speed pixel data reading, a method of serially converting digital data obtained by A / D converting analog data by parallel-serial conversion and transferring the data at high speed is known.

  In such pixel data transfer, in order to obtain horizontal and vertical synchronization timing of pixel data, a plurality of code strings called synchronization codes are embedded and transferred in serial data. In order to process pixel data, it is important to correctly detect this synchronization code.

  Patent Document 1 describes a method for preventing erroneous detection of this synchronization code. In data transfer, there is a possibility that a data error occurs in the transmission path on the way. In Patent Document 1, as a result of an error in data, the code string of the synchronization code is unintentionally present in the transferred data, and the synchronization code is erroneously detected and the data cannot be processed correctly. It is listed as an issue.

  In order to avoid this, it is described that the synchronization code detected only when the level of the clock component extracted from the received data is high is determined as the target synchronization code, and other than that is not determined as the synchronization code. .

JP 2000-307540 A

  In recent high-speed pixel data transfer, a transfer method called a clock data recovery method in which a clock signal is embedded in transfer data and a clock signal is extracted from the received transfer data is often used.

  When data is transferred by AC coupling in the clock data recovery method, encoding is performed so that the numbers of 0 and 1 in the transfer data are as uniform as possible in order to extract the clock normally.

  There is a method of scrambling data as one means of encoding. As a result of scrambling the transfer data, the code string of the synchronization code is unintentionally present in the transfer data, and the synchronization code is erroneously detected. Data may not be processed correctly.

  In Patent Document 1, it is assumed that the clock component is large at the position of the correct synchronization code in the received data, and that the clock component is small at the position of the synchronization code that was unintentionally present due to an error or the like, but a scramble method is used for data encoding. If it is adopted, there is a possibility that the clock component of the data resulting from the scrambling becomes large and erroneous detection occurs even at the position of the synchronization code that was not intended.

  The present invention has been made in view of the above-described problems, and an object thereof is to reliably detect a synchronization code even when transfer data is scrambled.

In order to achieve the above object, the imaging apparatus of the present invention provides:
An oscillator that generates a reference clock; and
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in synchronization with the reference clock;
Image signal readout means for reading out an image signal in synchronization with the horizontal synchronization signal and the vertical synchronization signal;
Synchronization code adding means for adding a synchronization code to the image signal in synchronization with the horizontal synchronization signal;
Transmitting means for transmitting the synchronization code and the image signal;
Receiving means for receiving the synchronization code and the image signal;
Synchronization code detection means for detecting the synchronization code;
A first validity period that is started in synchronization with the vertical synchronization signal and ends by detection of a synchronization code as a period for validating the detection result of the synchronization code detection means;
A second validity period that starts after a predetermined time has elapsed since detection of the synchronization code detected within the first validity period and ends by detection of the synchronization code;
An effective period generation circuit for determining

  According to the present invention, it is possible to reliably detect a synchronization code even when transfer data is scrambled.

It is a block diagram of the imaging device in this embodiment. It is a block diagram which shows the structure of the transmission data processing circuit in this embodiment. It is a block diagram which shows the structure of the window generation circuit in this embodiment. It is a timing chart which shows operation | movement of the window generation circuit in this embodiment. It is a block diagram which shows the structure of the synchronous code detection circuit in this embodiment. It is a block diagram of the imaging device in 2nd this embodiment. It is a block diagram which shows the structure of the window generation circuit in 2nd this embodiment. It is a timing chart which shows operation | movement of the window generation circuit in 2nd this embodiment. It is a block diagram which shows the structure of the synchronous code detection circuit in 2nd this embodiment. It is a block diagram which shows the structure of the window generation circuit in 3rd this embodiment. It is a timing chart which shows operation | movement of the window generation circuit in 3rd this embodiment. It is a table | surface explaining switching of the threshold value of the window generation circuit in 3rd this embodiment. It is a block diagram which shows the structure of the transmission data processing circuit in 4th Embodiment. 14 is a timing chart illustrating an operation of the window generation circuit according to the fourth embodiment.

[Example 1]
Hereinafter, the first embodiment of the present invention will be described in detail.

  FIG. 1 is a block diagram illustrating a configuration of an imaging apparatus according to an embodiment of the present invention. In FIG. 1, an oscillator 101 outputs a reference clock that is a reference for operation. Based on the reference clock output from the oscillator 101, each unit described later operates.

  The synchronization signal generator (SSG) 110 outputs a horizontal synchronization signal HD and a vertical synchronization signal VD in synchronization with the reference clock. The timing signal generator (TG) 102 generates a driving pulse signal for driving the image sensor (sensor) 120 based on the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) supplied from the SSG 110. .

  The sensor 120 is an image pickup device configured by, for example, a CCD or a CMOS. The sensor 120 sequentially outputs a pixel unit 103 such as a photodiode that performs photoelectric conversion and a pixel signal obtained by the pixel unit 103 in accordance with a drive pulse signal (drive signal) supplied from the TG 102. It includes a transfer path, an amplifier that amplifies the pixel signal, an A / D converter that converts the pixel signal into a digital signal, and the like.

  The transmission data processing circuit 104 generates transmission data according to a predetermined protocol from the pixel signal from the pixel unit 103 and the timing signal from the TG 102 and outputs it as parallel data.

  Specifically, a synchronization code corresponding to the horizontal synchronization signal HD is added to the pixel data. The configuration of the transmission data processing circuit 104 is shown in FIG. The state machine circuit (FSM) 202 generates an instruction signal for switching the output of the output selector 206 to data according to a predetermined protocol according to the count value from the counter 201 that counts processing cycles and the timing signal from the TG 102. Output.

  Specifically, the fixed pattern data output by the fixed pattern generation unit 203 is output for a predetermined time at the head of the data synchronized with the vertical synchronization signal VD. The fixed pattern repeatedly includes a predetermined specific control code, and is used for data processing in the image processing unit 130 described later. The synchronization code generation unit 204 adds a synchronization code corresponding to the horizontal synchronization signal HD to each horizontal line of the pixel signal.

  The synchronization code refers to a specific pattern of data (symbols) having a predetermined word length. For example, if the synchronization code is composed of 4 symbols, {synchronization code 1, synchronization code 2, synchronization code 3, Synchronization code 4} = {ALL0 symbol, ALL0 symbol, ALL1 symbol, ALL1 symbol}.

  The receiving side detects these data patterns as synchronization codes by pattern matching and takes the timing of horizontal synchronization. The synchronization code is controlled by the FSM 202 so as to be output immediately after the fixed pattern or at the head of data synchronized with the horizontal synchronization signal HD. The pixel data from the pixel unit 103 is scrambled by the scramble circuit 205.

  For the scramble processing, for example, the data to be actually transmitted is generated by taking the exclusive OR of the random number generated by the linear feedback shift register and the pixel data. The parallel-serial converter 106 converts the parallel data output from the transmission data processing circuit 104 into serial data.

  The converted serial data is supplied to the reception driver 111 through the transmission driver 107 via the board and the cable. The PLL 105 supplies a serial clock that matches the conversion rate from the reference clock to the serial data of the parallel-serial converter 106 to the parallel-serial converter 106.

  Here, an example in which output data from the transmission data processing circuit 104 is output via one transmission driver is shown, but data may be distributed and sent to a plurality of drivers according to the data rate to be realized. Reference numeral 130 denotes an image processing unit. The serial / parallel converter 112 inputs serial data from the reception driver 111 and stores it in an internal shift register.

  The stored serial data is output as, for example, 8-bit parallel data. In addition, a clock recovered from the serial data is also output. The word align circuit 113 is a circuit that extracts data having a predetermined word length from the parallel data output from the serial / parallel converter 112.

  For example, if the parallel data from the serial / parallel converter 112 is 8 bits and the pixel data has a word length of 12 bits per pixel, the 12-bit boundary of each pixel is searched from the 8-bit input, and 12 bits. Is taken out and output.

  Such word synchronization (word alignment) operation is performed when the above-described fixed pattern is received. The fixed pattern is a predetermined specific control code, and the word align circuit 113 obtains the word synchronization by searching for the pattern of the specific control code by pattern matching. The fixed pattern data is, for example, an array of data such as {fixed pattern 1, fixed pattern 2, fixed pattern 3, fixed pattern 4} = {ALL1 symbol, ALL0 symbol, ALL1 symbol, ALL1 symbol}.

  The word alignment circuit 113 takes word synchronization and outputs a fixed pattern detection signal to the window generation circuit 114 while the fixed pattern detection signal is High while a specific control code in the fixed pattern is detected. When a specific control code cannot be detected continuously for several symbols, the fixed pattern detection signal is set to Low and output to the window generation circuit 114. Further, the data signal having the word synchronization is output to the synchronization code detection circuit 115 and the reception data processing circuit 116. The window generation circuit 114 generates a signal indicating a period for validating the detection result of the synchronization code.

  In this embodiment, a signal indicating this period is called a window signal. By taking the logical product of the window signal and the synchronization code detection signal, it is determined that the synchronization code detected when the window signal is High is valid and the synchronization code detected when the window signal is Low is invalid. A signal obtained by taking the logical product is called a data head notification signal.

  The configuration of the window generation circuit 114 is shown in FIG. An operation timing chart of the window generation circuit 114 is shown in FIG. In response to the VD signal from the SSG 110, the VD reception flag generation unit 301 sets the flag signal indicating that the VD signal has been received to High. The flag signal becomes Low when the data head notification signal is received. The window 1 signal is the logical product of this flag signal and the fixed pattern detection signal from the word align circuit 113.

  When only the fixed pattern detection signal is the window 1 signal, there is a possibility that the window 1 signal becomes high in an unintended period when a specific control code in the fixed pattern appears in the transfer data. However, the possibility can be lowered by making the logical product with the flag signal.

  Since VD is a vertical synchronization signal and the fixed pattern is attached to the head of data in synchronization with the vertical synchronization signal, the window 1 signal indicates a period in which the detection of the first synchronization code of the transfer data is valid. become.

  When the counter 302 receives the data head notification signal, it is reset and starts counting up. The comparator 304 compares the value with a predetermined value, and outputs High as a window 2 signal from the comparator 304 when the count value is larger and Low when the count value is smaller. For the predetermined value, a plurality of horizontal count setting values are held in advance in a plurality of setting registers in the image processing unit 130.

  In this embodiment, it is assumed that the horizontal count setting value 1 and the horizontal count setting value 2 are provided. These set values are switched by the selector 303 according to a data type notification signal from the received data processing circuit 116 described later and used by the comparator 304.

  In this embodiment, it is assumed that the transfer data amount for each horizontal synchronization signal is not constant, and each transfer data amount is determined for each data type. For example, it is assumed that there are two types of data, type A and type B, the data of type A is the amount of data that can be processed with 100 cycles and the data of type B is 50 cycles.

  In this case, the horizontal count setting value 1 corresponding to the type A is set to 100, and the horizontal count setting value 2 corresponding to the type B is set to 50. When the data type notification signal indicates type A, the selector 303 selects and outputs the horizontal count setting value 1, and when the count value of the counter 302 exceeds 100, the window 2 signal becomes High. When the synchronization code is detected while the window 2 signal is high, the data head notification signal is input and the counter 302 is reset, so that the window 2 signal becomes low.

  When the data type notification signal indicates type B, the selector 303 selects and outputs the horizontal count setting value 2, and when the count value of the counter 302 exceeds 50, the window 2 signal becomes High. When the synchronization code is detected while the window 2 signal is high, the data head notification signal is input and the counter 302 is reset, so that the window 2 signal becomes low.

  By repeating this operation, the window 2 signal indicates a period in which detection of the synchronous code periodically transferred is valid. The window generation circuit 114 outputs a logical sum of the window 1 signal and the window 2 signal as a window signal.

  In this embodiment, the operation of the window generation circuit 114 is described so that the setting value is switched by the selector 303 in accordance with the data type notification signal from the reception data processing circuit 116. However, the present invention is not limited to this configuration. For example, the window 2 signal may be generated by receiving the number of cycles necessary for processing the data to be processed from the reception data processing circuit 116 and comparing the number of cycles with the count value of the counter 302.

  The synchronization code detection circuit 115 receives the data signal from the word alignment circuit 113, detects the synchronization code, and outputs it as a synchronization code detection signal. The configuration of the synchronization code detection circuit 115 is shown in FIG. Here, an example is shown in which the synchronization code is composed of four symbols. Reference numerals 501 to 504 denote delay elements for delaying input data. The outputs of the delay elements 501 to 504 are compared with the expected values of the four symbols of the synchronization code by the comparators 505 to 508, respectively. Each comparator outputs 1 if it matches the expected value, and 0 if it does not match. The outputs from the comparators are added by an adder 509. The value is compared with a preset threshold value by a comparator 510, and when the value is equal to or greater than the threshold value, a synchronization code detection signal is output.

  In this way, when the synchronization code is composed of multiple symbols and the evaluation result is compared with the expected value of each symbol, a bit error occurs in a certain cycle and a part of the synchronization code is broken. Error tolerance. The reception data processing circuit 116 analyzes and processes the contents of data defined in a predetermined format with the timing at which the data head notification signal is received from the data signal from the word align circuit 113 as the head of the data. .

  The content of the data in a predetermined format includes an identification signal indicating the data type. By notifying the window generation circuit 114 of this identification signal as a data type notification signal, the window generation circuit 114 switches the window 2 signal period according to the content of the identification information. The information notified from the reception data processing circuit 116 to the window generation circuit 114 is not limited to the identification information as described above. The data length may be included in the data of a predetermined format, and the number of cycles required to process the data length in the horizontal period may be notified.

  As described above, according to the present embodiment, the detection result of the synchronization code is validated only during the period when the window signal is High, so that the code string of the synchronization code is not intended in the transfer data as a result of scrambling the transfer data. Even if it exists, false detection can be prevented. In this embodiment, the transfer data is scrambled. However, the embodiment is not limited to scramble the transfer data. Even if the transfer data is not scrambled and an error occurs in the transfer data, and the code string of the synchronization code exists unintentionally, erroneous detection can be prevented.

[Example 2]
Hereinafter, the second embodiment of the present invention will be described in detail. The same parts as those in the first embodiment are denoted by the same symbols, and the description thereof is omitted. In the first embodiment, the data transferred during the period in which the window 1 signal is High is a fixed pattern data and a synchronization code. Data transferred during a period when the window 2 signal is High is data obtained by performing scramble processing on pixel data and a synchronization code.

  As described above, since the type of data transferred in each period is different, the tolerance for errors in each period in the detection of the synchronization code is different.

  For example, in the period when the window 1 signal is High, if the error is equal to or less than a predetermined number, by setting the fixed pattern that is not determined as the synchronization code on the sensor 120 side, the tolerance to the error in the detection of the synchronization code can be increased. . On the other hand, during a period in which the window 2 signal is high, data obtained by subjecting the pixel data to scramble processing is less resistant to errors in detecting the synchronization code than the fixed pattern.

  Therefore, there is a problem that the synchronization code cannot be detected correctly if the same threshold value is used for detecting the synchronization code during the period when the window 1 signal is high and the window 2 signal is high. The second embodiment differs from the first embodiment in that the threshold used for synchronization code detection is switched depending on the state of the window 1 signal and the window 2 signal of the window generation circuit.

  FIG. 6 is a block diagram illustrating the configuration of the imaging apparatus according to the second embodiment of the present invention. Reference numeral 630 denotes an image processing unit. The window generation circuit 614 differs from FIG. 1 in that it generates a signal indicating a period during which the detection result of the synchronization code is valid and a signal for switching a threshold used for detection of the synchronization code. The configuration of the window generation circuit 614 is shown in FIG. An operation timing chart of the window generation circuit 614 is shown in FIG.

  The threshold switching unit 701 receives the window 1 signal and the window 2 signal and outputs a threshold switching signal. When the window 1 signal is high and the window 2 signal is low, a threshold value switching signal is output in which the threshold value 1 is used as the threshold value used for detecting the synchronization code. When the window 2 signal is high and the window 1 signal is low, a threshold value switching signal is output that the threshold value 2 is used as the threshold value used for detecting the synchronization code.

  In cases other than the above, a threshold value switching signal that uses the threshold value 3 as the threshold value used for detection of the synchronization code is output.

  The synchronization code detection circuit 615 receives the threshold value switching signal from the window generation circuit 614 and the data signal from the word alignment circuit 113, detects the synchronization code from the data signal based on the threshold value switching signal, and outputs it as a synchronization code detection signal. The configuration of the synchronization code detection circuit 615 is shown in FIG. In response to the threshold switching signal, the threshold is selected from threshold 1, threshold 2, and threshold 3, and the threshold used for detecting the synchronization code is output.

  The value added by the adder 509 is compared with the selected threshold value by the comparator 510, and when the value is equal to or greater than the selected threshold value, a synchronization code detection signal is output.

  As described above, during the period when the window 1 signal is high, the tolerance to the error in detecting the synchronization code is higher than when the window 2 signal is high. Therefore, the threshold value 1 used for detecting the synchronization code is set to a value lower than the threshold value 2.

  For example, if the synchronization code is composed of 4 symbols, the threshold value 1 is set to a threshold value for determining a synchronization code when two symbols in four symbols match. The threshold 2 is set to a threshold for determining a synchronization code when 3 symbols coincide in 4 symbols. Note that threshold 3 is set to a threshold at which no synchronization code is detected.

  As described above, according to the present embodiment, the synchronization code can be correctly detected by switching the threshold used for the synchronization code detection according to the state of the window 1 signal and the window 2 signal of the window generation circuit. In this embodiment, the transfer data is scrambled. However, the embodiment is not limited to scramble the transfer data. Even if the transfer data is not scrambled and an error occurs in the transfer data, and the code string of the synchronization code exists unintentionally, erroneous detection can be prevented.

[Example 3]
Hereinafter, the third embodiment of the present invention will be described in detail. Portions similar to those in the first embodiment and the second embodiment are denoted by the same symbols, and description thereof is omitted. In the first embodiment and the second embodiment, the window 2 signal becomes High when the count value of the counter 302 exceeds a predetermined horizontal count set value. Since the timing at which the synchronization code is added on the sensor 120 side may vary for each horizontal synchronization signal HD, the horizontal count setting value for setting the window 2 signal to High is a value including a specific margin in consideration of the variation amount. Need to be set.

  Specifically, a predetermined horizontal count setting is set so that the timing at which the high period of the window 2 signal starts is advanced in comparison with the case where the timing of adding the synchronization code on the sensor 120 side does not vary for each horizontal synchronization signal HD Set by subtracting a specific margin value from the value.

  As described above, since the High period of the window 2 signal includes a specific margin, the data transferred during the period includes both the data obtained by performing the scramble processing on the pixel data and the synchronization code. Since the predetermined period from the start of the High period of the window 2 signal is a period including a specific margin, there is a high possibility that the data in that period is data obtained by performing scramble processing on the pixel data. For this reason, the code string of the synchronization code is unintentionally present in the transfer data during that period, and there is a high possibility that the synchronization code is erroneously detected and data processing cannot be performed correctly.

  In addition, there is a high possibility that the transfer data after a predetermined period from the start of the High period of the window 2 signal includes a synchronization code.

  In other words, since it is highly possible that the predetermined period after the start of the high period of the window 2 signal is scrambled data, the data is higher than the predetermined period after the high period of the window 2 signal starts. The tolerance for errors in the detection of the synchronization code is low. Therefore, there is a problem that the synchronization code cannot be correctly detected if the same threshold value is used for detecting the synchronization code during the period when the window 2 signal is High.

  In the third embodiment, the threshold value used for synchronous code detection is determined depending on the state of the window 1 signal and window 2 signal of the window generation circuit and whether or not the high period of the window 2 signal is within a predetermined period. The point of switching is different from the second embodiment. The configuration of the window generation circuit 614 of the third embodiment is shown in FIG. An operation timing chart of the window generation circuit 614 is shown in FIG. FIG. 12 shows a table for explaining the threshold value switching of the window generation circuit 614.

  The counter 1001 starts counting up when the window 2 signal becomes High. The count value of the counter 1001 is reset when the window 2 signal becomes low. The threshold switching unit 1002 receives the window 1 signal, the window 2 signal, and the count value of the counter 1001, and outputs a threshold switching signal.

  When the window 1 signal is high and the window 2 signal is low, a threshold value switching signal is output in which the threshold value 1 is used as the threshold value used for detecting the synchronization code. When the window 1 signal is low and the window 2 signal is high and the count value of the count 1001 is equal to or smaller than the predetermined count value, a threshold value switching signal is output that the threshold value 2 is used as the threshold value used for detecting the synchronization code. In FIG. 11, the predetermined count value is “1”.

  When the window 1 signal is low and the window 2 signal is high and the count value of the count 1001 is larger than a predetermined count value, a threshold value switching signal is output that the threshold value 1 is used as the threshold value used for detecting the synchronization code.

  In cases other than the above, a threshold value switching signal that uses the threshold value 3 as the threshold value used for detection of the synchronization code is output.

  For example, if the synchronization code is composed of 4 symbols, the threshold value 1 is set to a threshold value for determining a synchronization code when two symbols in four symbols match. The threshold 2 is set to a threshold for determining a synchronization code when 3 symbols coincide in 4 symbols. Note that threshold 3 is set to a threshold at which no synchronization code is detected.

  Thus, there is a possibility that the code string of the synchronization code is unintentionally present in the transfer data during the period when the window 2 signal is High. Therefore, it is possible to prevent erroneous detection of the synchronization code by switching the synchronization code detection threshold within the period in which the window 2 signal is High.

  As described above, according to the present embodiment, the synchronization code can be correctly detected by switching the threshold used for the synchronization code detection according to the state of the window 1 signal and the window 2 signal of the window generation circuit and the count value of the counter 1001. . In this embodiment, the transfer data is scrambled. However, the embodiment is not limited to scramble the transfer data.

  Even when the transfer data is not scrambled and an error occurs in the transfer data and the code string of the synchronization code unintentionally exists, erroneous detection can be prevented with the same configuration.

[Example 4]
Hereinafter, the fourth embodiment of the present invention will be described in detail. The same parts as those in the first embodiment are denoted by the same symbols, and the description thereof is omitted.

  In the first embodiment, when the count value of the counter 302 exceeds a predetermined horizontal count setting value, the window 2 signal becomes High. Since the timing at which the synchronization code is added on the sensor 120 side may vary for each horizontal synchronization signal HD, the horizontal count setting value for setting the window 2 signal to High is a value including a specific margin in consideration of the variation amount. Need to be set.

  Specifically, a predetermined horizontal count setting is set so that the timing at which the high period of the window 2 signal starts is advanced in comparison with the case where the timing of adding the synchronization code on the sensor 120 side does not vary for each horizontal synchronization signal HD. Set by subtracting a specific margin value from the value.

  As described above, since the High period of the window 2 signal includes a specific margin, the data transferred during the period includes both the data obtained by performing the scramble processing on the pixel data and the synchronization code.

  Since the predetermined period from the start of the High period of the window 2 signal is a period including a specific margin, there is a high possibility that the data in that period is data obtained by performing scramble processing on the pixel data. Therefore, there is a problem in that the code string of the synchronization code is unintentionally present in the transfer data during that period, and the synchronization code is erroneously detected and data processing cannot be performed correctly.

  The fourth embodiment is different from the first embodiment in that an end code formed by a predetermined number of unscrambled symbols different from the synchronization code is added to the transfer data. FIG. 13 shows the configuration of the transmission data processing circuit 104 according to the fourth embodiment. An operation timing chart of the window generation circuit 114 is shown in FIG.

  The transmission data processing circuit 104 generates an end code formed by a predetermined number of unscrambled symbols different from the synchronization code in addition to the fixed pattern data, the synchronization code, and the scrambled pixel data. And different.

  The end code generation unit 1301 generates an end code. The end code is formed of a predetermined number of symbols which are formed of symbols different from the predetermined symbols forming the synchronization code and are not scrambled.

  For example, it is assumed that the end code is composed of 4 symbols as with the fixed pattern data and the synchronization code. In this case, the end code may be an array of data such as {end code 1, end code 2, end code 3, end code 4} = {ALL1 symbol, ALL1 symbol, ALL0 symbol, ALL0 symbol}. .

  The state machine circuit (FSM) 1302 outputs an instruction signal for switching the output of the output selector 206 to data according to a predetermined protocol in accordance with the count value from the counter 201 that counts processing cycles and the timing signal from the TG 102. To do.

  Specifically, the fixed pattern data output by the fixed pattern generation unit 203 is output for a predetermined time at the head of the data synchronized with the vertical synchronization signal VD. The synchronization code output by the synchronization code generation unit 204 is output immediately after the fixed pattern data or at the beginning of data synchronized with the horizontal synchronization signal HD. The pixel data scrambled by the scramble circuit 205 is output immediately after the synchronization code. The end code output from the end code generation unit 1301 is output immediately after the scrambled pixel data.

  The output timing of the end code is controlled by the FSM 1302 so that the pixel data is not included in the High period of the window 2 signal. As a result, the High period of the window 2 signal can be started when the end code is transferred on the image processing unit 130 side.

  Thus, there is a possibility that the code string of the synchronization code is unintentionally present in the transfer data during the period when the window 2 signal is High. Therefore, it is possible to prevent erroneous detection of the synchronization code by adding the end code so as not to include the data subjected to the scramble processing on the pixel data during the High period of the window 2 signal.

  As described above, according to the present embodiment, the end code is added immediately after the transfer data, and as a result of scrambled the transfer data while the window signal is High, the code string of the synchronization code is intended in the transfer data. Even if it does exist, false detection can be prevented. In this embodiment, the transfer data is scrambled. However, the embodiment is not limited to scramble the transfer data. Even if the transfer data is not scrambled and an error occurs in the transfer data, and the code string of the synchronization code exists unintentionally, erroneous detection can be prevented.

101 Transmitter 104 Transmission Data Processing Circuit 120 Sensor (Imaging Device)

Claims (16)

An oscillator that generates a reference clock; and
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in synchronization with the reference clock;
Image signal readout means for reading out an image signal in synchronization with the horizontal synchronization signal and the vertical synchronization signal;
Synchronization code adding means for adding a synchronization code to the image signal in synchronization with the horizontal synchronization signal;
Transmitting means for transmitting the synchronization code and the image signal;
Receiving means for receiving the synchronization code and the image signal;
Synchronization code detection means for detecting the synchronization code;
A first validity period that is started in synchronization with the vertical synchronization signal and ends by detection of a synchronization code as a period for validating the detection result of the synchronization code detection means;
A second validity period that starts after a predetermined time has elapsed since detection of the synchronization code detected within the first validity period and ends by detection of the synchronization code;
An imaging device comprising an effective period generation circuit for determining An identification signal adding means for adding an identification signal indicating the type of the image signal to the image signal; and an identification signal detecting means for detecting the identification signal;
The imaging apparatus according to claim 1, wherein the predetermined time for starting the second effective period is changed according to a detection result of the identification signal detection unit. Data length information adding means for adding information on the data length of the image signal to the image signal, and data length information detecting means for detecting the data length information,
The imaging apparatus according to claim 1, wherein the predetermined time for starting the second effective period is set according to data length information from the data length information detection unit. 4. The apparatus according to claim 1, further comprising: an encoding unit that scrambles the image signal with a predetermined coefficient; and a decoding unit that restores the data scrambled by the encoding unit. 5. Imaging device. 5. The synchronization code detection unit according to claim 1, wherein the synchronization code detection unit determines that a synchronization code has been detected when a symbol equal to or greater than a threshold value is received among a predetermined number of symbols forming the synchronization code. The imaging apparatus according to item 1. An oscillator that generates a reference clock; and
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in synchronization with the reference clock;
Image signal readout means for reading out an image signal in synchronization with the horizontal synchronization signal and the vertical synchronization signal;
Synchronization code adding means for adding a synchronization code to the image signal in synchronization with the horizontal synchronization signal;
Transmitting means for transmitting the synchronization code and the image signal;
Receiving means for receiving the synchronization code and the image signal;
Synchronization code detection means for detecting the synchronization code;
A first validity period that is started in synchronization with the vertical synchronization signal and ends by detection of a synchronization code as a period for validating the detection result of the synchronization code detection means;
An effective period generation circuit that determines a second effective period that is started after a predetermined time has elapsed from the detection of the synchronization code detected within the first effective period and ends by detection of the synchronization code;
A threshold value switching means for switching a threshold value of synchronization code detection in each of the periods defined by the effective period generation circuit;
The synchronization code detection means in the previous period is
An imaging apparatus, wherein a synchronization code is determined to be detected when a symbol equal to or greater than the threshold is received among a predetermined number of symbols forming the synchronization code. The imaging apparatus according to claim 6, wherein the threshold value switching unit sets a threshold value for detecting a synchronization code to be low during a first effective period determined by the effective period generation circuit. The imaging apparatus according to claim 6, wherein the threshold value switching unit sets a detection threshold value of the synchronization code high in a second effective period determined by the effective period generation circuit. An oscillator that generates a reference clock; and
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in synchronization with the reference clock;
Image signal readout means for reading out an image signal in synchronization with the horizontal synchronization signal and the vertical synchronization signal;
Synchronization code adding means for adding a synchronization code to the image signal in synchronization with the horizontal synchronization signal;
Transmitting means for transmitting the synchronization code and the image signal;
Receiving means for receiving the synchronization code and the image signal;
Synchronization code detection means for detecting the synchronization code;
A first validity period that is started in synchronization with the vertical synchronization signal and ends by detection of a synchronization code as a period for validating the detection result of the synchronization code detection means;
An effective period generation circuit that determines a second effective period that is started after a predetermined time has elapsed from the detection of the synchronization code detected within the first effective period and ends by detection of the synchronization code;
Counting means for starting counting when the second effective period starts and resetting the count when the second effective period ends;
A threshold value switching means for switching a threshold value for detecting a synchronization code according to information about whether each period is determined by the effective period generation circuit and information about whether the count value of the count means is a predetermined count value or less;
The synchronization code detection means in the previous period is
An imaging apparatus, wherein a synchronization code is determined to be detected when a symbol equal to or greater than the threshold is received among a predetermined number of symbols forming the synchronization code. The imaging apparatus according to claim 9, wherein the threshold value switching unit sets a threshold value for detecting a synchronization code to be low during a first effective period determined by the effective period generation circuit. The threshold value switching means sets a synchronization code detection threshold value high when the count value of the counter means is equal to or less than a predetermined count value within a second effective period determined by the effective period generation circuit. The imaging device according to claim 9 or 10. The threshold value switching means sets a low threshold value for detecting a synchronization code when the count value of the counter means is larger than a predetermined count value within a second effective period determined by the effective period generation circuit. The imaging device according to any one of claims 9 to 11. An oscillator that generates a reference clock; and
Synchronization signal generating means for generating a horizontal synchronization signal and a vertical synchronization signal in synchronization with the reference clock;
Image signal readout means for reading out an image signal in synchronization with the horizontal synchronization signal and the vertical synchronization signal;
Encoding means for scrambling the image signal with a predetermined coefficient;
Synchronization code adding means for adding a synchronization code formed by a predetermined number of symbols not scrambled to the image signal in synchronization with the horizontal synchronization signal;
An end code adding means for adding an end code formed of a predetermined number of unscrambled symbols to the image signal;
Transmitting means for transmitting the synchronization code and the image signal;
Receiving means for receiving the synchronization code and the image signal;
Synchronization code detection means for detecting the synchronization code;
A first validity period that is started in synchronization with the vertical synchronization signal and ends by detection of a synchronization code as a period for validating the detection result of the synchronization code detection means;
An effective period generation circuit that determines a second effective period that is started after a predetermined time has elapsed from the detection of the synchronization code detected within the first effective period and ends by detection of the synchronization code;
An imaging apparatus comprising: decoding means for restoring data scrambled by the encoding means, wherein the end code adding means changes a position where the end code is added according to a data length of the image signal. The imaging apparatus according to claim 13, wherein the end code is formed of a symbol different from the predetermined symbol forming the synchronization code. 15. The imaging apparatus according to claim 1, wherein a specific pattern is repeatedly transmitted at the head of the image signal in synchronization with the vertical synchronization signal. 16. The imaging apparatus according to claim 15, wherein the specific pattern is data that is not determined as a synchronization code if an error is equal to or less than a predetermined number.