JP2019149508A - Wiring board and electronic apparatus - Google Patents

Abstract

To provide a wiring board capable of more effectively supplying stable electric power, and an electronic apparatus.SOLUTION: A wiring board includes: a core insulation layer; insulation layers above and below the core insulation layer; first connection terminals on the uppermost surface; second connection terminals on the lowermost surface; and a wiring conductor and a voltage regulator. The first connection terminal connected to the voltage regulator is located in a first region, and the other first connection terminals are located in a second region separated from the first region. A wiring conductor for a signal related to signal transmission is located so as to avoid the first region and a region between the first region and the second region in plan view, a wiring 252 is located between and across an expansion region R228 located on an outer edge side of the insulation layer with respect to the positions of the first connection terminals and the second connection terminals and the second region in plan view between insulation layers higher than the core insulation layer, and the wiring is located between and across the expansion region R228 and the arrangement region of the second connection terminal in plan view between insulation layers lower than the core insulation layer.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to a wiring board and an electronic device.

  There is a wiring board for connecting an electronic component such as a semiconductor element to a board of an electronic device. Electric power is supplied to the electronic component via a through conductor of the wiring board, and signals are transmitted and received. When there are fluctuations in the power consumption of electronic components, the supplied power may not be kept stable due to the influence of the impedance and inductance of the through conductor.

  In Patent Document 1, a semiconductor element and a voltage regulator are provided on the upper surface of a wiring board, a voltage surface having a mesh-like conductor portion is provided near the upper surface, and power is supplied to the semiconductor element through the voltage surface with low impedance and low inductance. A configuration for supplying the power is disclosed.

US Patent No. 7085143

  However, a large number of signal transmission paths connecting the lower surface connected to the substrate of the electronic device and the upper surface connected to the electronic component extend on the wiring board. Since these signal transmission paths hinder the flow of current at each voltage plane, there is a problem that power cannot be effectively and stably supplied to the electronic component from the voltage regulator.

  An object of the present disclosure is to provide a wiring board and an electronic device that can supply power more effectively and stably.

  In order to achieve the above object, one aspect of the present disclosure includes a core insulating layer, a plurality of insulating layers positioned in a stacked state on the upper side and the lower side of the core insulating layer, and an uppermost surface of the upper insulating layer. Among the first connection terminal, the second connection terminal located on the lowermost surface of the lower insulating layer, the ground conductors for power, signal and signal, and the first connection terminal for grounding A voltage regulator connected to a part of the plurality of ground terminals connected to the wiring conductor and a part of the plurality of power supply terminals connected to the wiring conductor for power. The connected ground terminal and power supply terminal are located in the first region, and the first connection terminal outside the first region is located in the second region separated from the first region. The signal wiring conductor for signal transmission between the connection terminal and the second connection terminal is: It is located in a state avoiding the first region and the region between the first region and the second region in plan view, and a part of the signal wiring conductor is between the upper insulating layers. In FIG. 3, the first and second connection terminals to which the signal wiring conductor is connected in plan view are positioned between the development region and the second region located on the outer edge side of the insulating layer with respect to the positions of the first connection terminal and the second connection terminal. The wiring board is located between the lower insulating layers and between the development region and the second connection terminal arrangement region in a plan view.

  Another aspect of the present disclosure is an electronic device including the above-described wiring board and an electronic component connected to a first connection terminal located in the second region.

  According to the contents of the present disclosure, there is an effect that stable power can be supplied more effectively in the wiring board.

It is a whole block diagram of the electronic module containing a wiring board. It is a figure which illustrates a part of sectional structure of an electronic device typically. It is the top view which looked at a part among wiring layers of the uppermost surface from the upper surface side. FIG. 5 is a plan view of a part of a wiring layer of a buildup layer above a core substrate and a part of a through conductor penetrating an insulating layer on the wiring layer as viewed from the upper surface side. FIG. 5 is a plan view of a part of a wiring layer of a buildup layer above a core substrate and a part of a through conductor penetrating an insulating layer on the wiring layer as viewed from the upper surface side. FIG. 5 is a plan view of a part of an upper conductor layer and a part of a penetrating conductor penetrating an insulating layer on a part of the upper conductor layer as viewed from the upper surface side. FIG. 5 is a plan view of a part of a lower conductor layer and a part of a core through conductor that penetrates a core insulating layer on the lower conductor layer as viewed from the upper surface side. FIG. 3 is a plan view of a part of a wiring layer of a build-up layer below a core substrate and a through conductor penetrating an insulating layer on the wiring layer as viewed from above. FIG. 3 is a plan view of a part of a wiring layer of a build-up layer below a core substrate and a through conductor penetrating an insulating layer on the wiring layer as viewed from above. It is the top view which looked at the through conductor which penetrates an insulating layer on a part and wiring layer of the lowermost layer from the upper surface side.

Hereinafter, embodiments according to the present disclosure will be described with reference to the drawings.
FIG. 1 is an overall configuration diagram of an electronic module 1 including a wiring board 100 of the present embodiment.

  The electronic module 1 includes a module substrate 200 and an electronic device 2 located on the module substrate 200. The electronic device 2 includes a wiring board 100 and electronic components. The wiring board 100 is square or rectangular in plan view, and has two voltage regulators 60 (Voltage Regulator Modules; VRM) symmetrically on the upper surface side (the side opposite to the connection surface with the module substrate 200). In addition, a semiconductor element 70 such as an IC chip or LSI is connected as an electronic component to the central portion on the upper surface side. A plurality of other electronic components and wiring boards may be connected to the wiring on the module board 200.

FIG. 2 is a diagram schematically illustrating a part of the cross-sectional structure of the electronic device 2 of the present embodiment.
2A is a cross section cut along a cross-sectional line XX in FIG. 1, and FIG. 2B is a cross section cut along a cross-sectional line YY in FIG.

  The wiring substrate 100 includes a core substrate 30, build-up layers 20 and 40 sandwiching the core substrate 30 above and below, and a solder resist layer that covers the opposite side of the build-up layers 20 and 40 from the side in contact with the core substrate 30. 10 and 50, and a voltage regulator 60 (Voltage Regulator Module; VRM) positioned on the upper surface side of the buildup layer 20 (on the side opposite to the contact surface with the core substrate 30). This is well known in the art for maintaining the voltage of the power supplied to the semiconductor element 70 at a predetermined operating voltage according to the operation of the semiconductor element 70.

  With respect to the stacking direction of the wiring substrate 100, the buildup layer 20 positioned on the upper side of the core substrate 30 includes a plurality of (three) insulating layers I21, I22, I23 in a stacked state and the upper surfaces of the insulating layers I21 to I23. Wiring layers L21, L22, and L23 located on the side (surface). The insulating layers I21 to I23 have through conductors 231, 232, and 233 that penetrate the inside in the stacking direction (vertical direction), and electrically connect the wiring layers L21 to L23 and the upper conductor layer L31.

  The core substrate 30 has an upper conductor layer L31 on the upper surface side and a lower conductor layer L32 on the lower surface side with respect to the core insulating layer I31. A through hole 320 passes through the core insulating layer I31, and the surface of the through hole 320 is covered with a conductive core through conductor 331 so that the core through conductor 331 and the upper conductor layer L31 are connected to the core insulating layer I31. The side conductor layer L32 is electrically connected.

  With respect to the stacking direction of the wiring substrate 100, the buildup layer 40 located below the core substrate 30 includes a plurality of (three) insulating layers I44, I45, I46 in a stacked state, and the insulating layers I44 to I46. Wiring layers L44, L45, and L46 located on the lower surface side are included. The insulating layers I44 to I46 have through conductors 434, 435, and 436 penetrating inside in the stacking direction (vertical direction), and electrically connect the wiring layers L44 to L46 and the lower conductor layer L32. .

  On the upper surface side (uppermost surface) of the buildup layer 20, a plurality of electrode pads 211 (see FIG. 3, first connection terminals, here, power supply pads 211 b and ground pads 211 c) are located. The solder resist layer 10 has openings so as to expose the range of these electrode pads 211. Some of the power supply pads 211b (power supply terminals connected to power wiring conductors for power supply) and the ground pads 211c (ground terminals connected to ground wiring conductors) are made of solder or the like. The remaining electrode pad 211 is connected to the semiconductor element 70 via the connection conductor 71 and is connected to the voltage regulator 60 via the connection conductor 61.

On the lower surface side (lowermost surface) of the buildup layer 40, a plurality of external connection pads 416 (see FIG. 10, see FIG. 10) for connection to an external device or the like in an array pattern corresponding to the array of through conductors that penetrate the insulating layer I46. 2 connection terminals, where a power supply pad 416b and a ground pad 416c) are located. The solder resist layer 50 has openings so as to expose the range of these external connection pads 416.
Wiring layers L21 to L23, L44 to L46, upper conductor layer L31, lower conductor layer L32, through conductors 231 to 233 and 434 to 436, core through conductor 331 and lands 262c, 263b, 361c, 362b, 464c and 465b described later Are the wiring conductors that perform grounding, power supply, and signal transmission on the wiring board 100 of the present embodiment.

  The distance between the electrode pads 211 connected to the voltage regulator 60 and the distance between the external connection pads 416 are equal, and the electrode pad 211 and the external connection pad 416 are connected in a straight line through the through conductor. The distance between the electrode pads 211 connected to the semiconductor element 70 is narrower than the distance between the external connection pads 416, and the position of the through conductor is adjusted by the wiring layers L22, L23, L44, L45 and the like.

  As the insulating layers I21 to I23, I44 to I46 and the core insulating layer I31, for example, various insulating resin materials are used, but various other organic compounds and inorganic materials (ceramics) may be used. As the through conductor, a suitable combination of tungsten and copper according to the material of the insulating layer is used.

  It should be noted that the insulating layers I21 to I23, I44 to I46, the core insulating layer I31 and the wiring layers L21 to L23, L44 to L46, the thickness ratio of the upper conductor layer L31, the lower conductor layer L32, the through conductor, and the electrode pad 211 In addition, the shape and size of the external connection pads 416 are emphasized or simplified for the sake of explanation, and do not reflect specific values or shapes. The upper and lower parts here are for convenience of explanation and are not fixed. The direction during storage or use may be changed as appropriate.

  FIG. 3 is a plan view of a part of the wiring layer L21 of the buildup layer 20 as viewed from the upper surface side. Here, ¼ corresponding to a partial region RUL including the upper left corner in the wiring substrate 100 of FIG. 1 is shown in plan view, but the remaining portions are also arranged in substantially the same manner.

  The wiring layer L21 has a ground plane 241. Inside the ground plane 241, large and small electrode pads 211 are positioned in a two-dimensional array. Among these, the small electrode pads 211 arranged in the center of the wiring layer L <b> 21 (lower right part of the drawing) are connected to the semiconductor element 70. A large electrode pad 211 arranged near the outer edge of the wiring layer L <b> 21 (lower left part of the drawing) is connected to the voltage regulator 60. The planar view position of the large electrode pad 211 is the same as the planar view position of the external connection pad 416 (see FIG. 10).

  A connection region R216 (first region) in which the power supply pad 211b and the ground pad 211c connected to the voltage regulator 60 are arranged is a rectangular region, and the long side thereof is connected to the semiconductor element 70. It faces away from the connection region R217 (second region) where the electrode pads 211 are arranged. Here, the long side of the connection region R216 is slightly shorter than the length of the opposite side of the connection region R217, but is not limited thereto. The shapes and sizes of the connection region R216 and the connection region R217 may be determined according to the relationship between the size of the voltage regulator 60 and the semiconductor element 70, the number of connection terminals thereof, and the like.

  The connection region R217 to the semiconductor element 70 has a rectangular shape or a square shape (rectangular region). In the connection region R217, the signal pads 211a connected to the wiring (signal wiring conductor) used for signal transmission are arranged in a plurality of rows along the side not facing the connection region R216. The signal pad 211a does not exist in the portion along the side facing the connection region R216 or the inside of the connection region R217 (within a predetermined range from the center position in the direction along the side facing the connection region R216). Only the pad 211b and the ground pad 211c are located (that is, the signal pad 211a is located outside this predetermined range). The size of the predetermined range may be set as large as possible according to the number of signal pads 211a.

  The signal pad 211a and the power supply pad 211b are located on the lattice points of the two-dimensional lattice, and the ground pad 211c is located at the center of a square formed by the four points of the adjacent signal pad 211a or power supply pad 211b. As a whole, electrode pads 211 are arranged on lattice points of a square lattice (two-dimensional lattice) inclined by 45 degrees with respect to each side of the wiring board 100, for example, a signal pad 211a or a power supply pad 211b and a ground pad 211c. Are located alternately.

  4 shows the above-described part of the wiring layer L22 of the buildup layer 20 (the same applies to FIG. 10 below) and a part of the through conductor 231 penetrating the insulating layer I21 above the wiring layer L22. FIG.

  The wiring layer L22 between the insulating layer I21 and the insulating layer I22 (a plurality of insulating layers above the core insulating layer I31) has a ground plane 242c and a power supply plane 242b. Here, the ground plane 242c occupies a range that is about the upper half (the end side of the wiring layer L22) in FIG. 4 and does not include the connection region R216 in plan view. The power supply surface 242b occupies the lower half of FIG. 4 (the center side of the wiring layer L22 in the vertical direction) and includes the connection region R216 in plan view. The ground plane 242c is connected to the ground plane 241 by a through conductor 231 in the development region R228. The ground plane 242c is grounded and becomes a ground voltage. The power supply surface 242b becomes the above-described predetermined operating voltage by the power supplied from the outside and the voltage regulator 60.

  Each of the signal pads 211a is connected to the wiring layer L22 by a through conductor 231 that penetrates the insulating layer I21 at the same position as the signal pad 211a in plan view. The wiring layer L22 includes a wiring 252 that connects the lower end of the through conductor 231 connected to the signal pad 211a to the outside of the connection region R217. The wirings 252 are all outside the power supply surface 242b and are located in a state avoiding the power supply surface 242b. The wiring 252 is separated from the ground plane 242c by an insulating portion. That is, the wiring 252 is between the insulating layers I21 and I22 between the connection region R216 and the development region R228 in a plan view, and the region R218 (in the connection region R216 and between the connection region R216 and the connection region R217). It is located in a state avoiding the range in which the outer frame of each region is connected by a straight line (not located in the connection region R216 and the region R218).

  Further, the power supply surface 242b is not positioned on either side of an arbitrary point on the wiring 252. A part of the other end of the wiring 252 opposite to the one connected to the through conductor 231 is on a lattice point of a predetermined two-dimensional lattice and is located at the same position as the signal pad 416a (see FIG. 10) in plan view. The other part is located in the development region R228 at the upper end of the ground contact surface 242c. The development region R228 is located on the outer edge side of the wiring substrate 100 (that is, the insulating layers I21, I22, etc.) with respect to the corresponding signal pads 211a, 416a (which are connected to the wiring 252 and become both ends).

  The power supply pads 211b and the ground pads 211c in the connection region R216 are connected to five through conductors 231 arranged in a cross shape (four points at the tip of the cross and intersections), respectively. These through conductors 231 penetrate through the insulating layer I21 and are connected to the wiring layer L22. Of the electrode pads 211 in the connection region R217, all of the power supply pads 211b are connected to the wiring layer L22 by through conductors 231 at the same position in plan view. A part of the ground pad 211c in the connection region R217 is connected to the wiring layer L22 by a through conductor 231 at the same position in plan view.

  The lower ends of the through conductors 231 connected to all the power supply pads 211b in the connection region R216 and the connection region R217 are inside the power supply surface 242b and are electrically connected to the power supply surface 242b. That is, the power supply surface 242 b is included in a connection path between the power supply pad 211 b in the connection region R 216 connected to the voltage regulator 60 and the power supply pad 211 b in the connection region R 217 connected to the semiconductor element 70. The power supply surface 242 b has a shape in which the wiring 252 does not block between the through conductor 232 related to power supply at a predetermined voltage from the voltage regulator 60 and the through conductor 232 related to power supply to the semiconductor element 70 ( That is, the positional relationship with the wiring 252 is established.

  Of the through conductors 231 connected to the ground pad 211c, the five through conductors 231 connected to one ground pad 211c in the connection region R216 are conductors connecting the lower ends of the five through conductors 231 in the wiring layer L22. It is connected to a land 262c which is a pattern. The through conductors 231 connected to the ground pad 211c in the connection region R217 are connected to isolated ground portions in the wiring layer L22. The through conductor 231 is not connected to the ground pad 211c inside the connection region R217 in a plan view at a position corresponding to the power supply pad 416b (see FIG. 10) in the plan view. The through conductors 231 arranged in the ground plane 242c connect the ground plane 242c and the ground plane 241 of the wiring layer L21, respectively.

  FIG. 5 is a plan view of a part of the wiring layer L23 of the buildup layer 20 and a through conductor 232 penetrating the insulating layer I22 above the part of the wiring layer L23 as viewed from above.

  The wiring layer L23 has a ground plane 243. The through conductor 232 located immediately below the other end of the wiring 252 in the wiring layer L22 and connected to the wiring 252 is connected to the through conductor 233 that penetrates the insulating layer I23 at the same position in plan view. Of the signal paths formed by the through conductor 232 and the through conductor 233, those that should not pass through the immediate vicinity of the ground plane 243, for example, a set of two signal paths related to differential signals, are appropriately spaced in the wiring layer L23. The shape and positional relationship can be collectively surrounded by the insulating portion.

  On the lower surface side of the power supply surface 242b, in the same position range as each power supply pad 416b in a plan view, the five through conductors 232 having a cross-like positional relationship (four tips and intersections of the cross) respectively pass through the insulating layer I22. It penetrates. The five through conductors connected to the same power supply pad 416b are connected to the same land 263b in the wiring layer L23, similarly to the land 262c in the wiring layer L22.

  Of the through conductors 232 connected to the inner side surrounded by the power supply surface 242b, the through conductors 232 pass through the insulating layer I22 at the same position in plan view but connected to the ground surface 241 and the lower ends thereof are connected to the ground surface 243, respectively. Has been. Of the same position as the planar view position of the grounding pad 416c inside the grounding surface 242c, at portions that do not overlap with the wiring 252 and surrounding insulating portions, five or a part of through conductors 232 arranged in a cross shape are respectively provided. Passes through the insulating layer I22 and is connected to the ground plane 243. In addition, the outside conductor pad 416 is located outside the range where the external connection pad 416 is located in plan view, between the peripheral portion of the ground plane 243 and the signal path in the development region R228. A through conductor 232 connected to connect the ground plane 242c and the ground plane 243 passes through the insulating layer I22.

  FIG. 6 is a plan view in which a part of the upper conductor layer L31 on the upper surface of the core substrate 30 and a part of the through conductor 233 penetrating the insulating layer I23 above the part of the upper conductor layer L31 are viewed from the upper surface side. It is. 7 shows a part of the lower conductor layer L32 on the lower surface of the core substrate 30 and a part of the core through conductor 331 penetrating the core insulating layer I31 above the lower conductor layer L32 from the upper surface side. FIG.

  The upper conductor layer L31 has a power supply surface 341b and a ground surface 341c. The power supply surface 341b extends in a range obtained by adding a range where the signal pad 211a is located to the range of the power supply surface 242b in plan view. The ground plane 341c is a range in the upper conductor layer L31 other than the power supply plane 341b except for an insulating portion that forms a boundary with the power supply plane 341b. Generally corresponds to the range including the range where is located.

  The through conductor 233 related to the power supply and signal path penetrates the insulating layer I23 at the same position as the through conductor 232 in plan view, and connects the wiring layer L23 and the upper conductor layer L31. The through conductors 233 for grounding are arranged in a cross shape at the same position as the ground pad 416c in a plan view, and on the inner side surrounded by the power supply surface 341b, the lower ends of the five through conductors 233 have a common land. 361c, respectively. Further, through conductors 233 for grounding are arranged one by one in the deployment region R228 and in the peripheral portion of the grounding surface 341c in plan view.

  The lower conductor layer L32 has a ground plane 342. The core through conductor 331 relating to power supply and grounding has a common one connecting the upper conductor layer L31 and the lower conductor layer L32 to the five through conductors 233 arranged in a cross shape. In the lower conductor layer L32, the core through conductor 331 related to power supply is connected to the land 362b. For each of the through conductors 233 related to the signal path, which are independent one by one, the upper conductor layer L31 and the lower conductor layer L32 are respectively separated by the core through conductor 331 penetrating the core insulating layer I31 at the same position in plan view. Is connected.

  FIG. 8 is a plan view of a part of the wiring layer L44 and a through conductor 434 penetrating the insulating layer I44 above the wiring layer L44 as viewed from the upper surface side.

  The wiring layer L44 between the insulating layers I44 and I45 on the lower side of the core insulating layer I31 includes a power supply surface 444b, a ground surface 444c, and a wiring 454. The wiring 454 is a wiring located between the development region R228 and the arrangement region of the signal pad 416a in order to return the signal path drawn to the development region R228 in plan view by the wiring 252 to the planar view position of the signal pad 416a. Yes, connected to the core through conductor 331 related to the signal path, and further connected to the through conductor 434 penetrating the insulating layer I44. The planar view position of the signal pad 416a returned by the wiring 454 is difficult to be pulled out from the planar view position of the signal pad 211a directly by the wiring layer L22 by the numerous wirings 252. The wiring 454 is not located in the connection region R216 in the plan view and in the region R218 between the connection region R216 and the connection region R217. The planar view positions of the through conductors 434 related to other signal paths are the same as the planar view positions of the signal pad 416a and the core through conductor 331.

  The through conductor 434 related to the ground is in the same position as the plan view of the majority of the through conductor 233 related to the ground. That is, the five penetrating conductors 233 having a cross-like positional relationship and the five penetrating conductors 434 at the same position in plan view as the penetrating conductor 233 are respectively connected to the common core through the upper conductor layer L31 and the lower conductor layer L32. The conductor 331 is connected. The grounding through conductors 434 connected to the power supply surface 444b of the wiring layer L44 are connected by five common lands 464c.

  Most of the planar view position of the through conductor 434 related to power supply is the same as the planar view position of the through conductor 233 related to power supply. In the insulating layer I23, the through conductor 233 for supplying power does not exist in the range where the signal pads 211a are arranged in a plan view position. Therefore, the insulating layer I44 is cross-shaped with the planar view position of the core through conductor 331 related to the power supply within the range where the signal pads 211a are arranged in the center with respect to the planar view position of the through conductor 233 related to the power supply. Five through conductors 434 that are in a positional relationship are added.

  FIG. 9 is a plan view of a part of the wiring layer L45 and the through conductor 435 penetrating the insulating layer I45 above the wiring layer L45 as viewed from the upper surface side.

  The wiring layer L45 has a ground plane 445. The through conductor 435 penetrates the insulating layer I45 at the same position as the through conductor 434 in plan view. The wiring layer L45 includes a wiring 455 for adjusting the planar view position of each set of through conductors related to the differential signal among the through conductors related to the signal to the planar view position of the signal pad 416a. The through conductors 435 relating to the power supply connected in the ground plane 445 of the wiring layer L45 are connected to the land 465b by five.

  FIG. 10 is a plan view of a part of the wiring layer L46 and a penetrating conductor 436 penetrating the insulating layer I46 above the wiring layer L46 as viewed from the upper surface side.

  The wiring layer L46 has a power supply surface 446b and a ground surface 446c. On the lower surface of the wiring layer L 46, that is, on the bottom surface side of the wiring substrate 100, the external connection pads 416 are located on the lattice points of a square lattice-like two-dimensional array. The through conductor 436 related to the signal path among the through conductors 436 penetrating the insulating layer I46 is located at the center of each external connection pad 416 in plan view. Five through conductors 436 related to power supply and grounding are arranged in a cross-like positional relationship around the center of each external connection pad 416 in plan view. As described above, these position ranges coincide with the opening positions of the solder resist layer 50, respectively.

  As described above, in the wiring substrate 100, in the entire range from the upper surface of the buildup layer 20 to the lower surface of the buildup layer 40, the inside of the connection region R216 and between the connection region R216 and the connection region R217 in plan view. In the region R218, there is no wiring conductor for signals related to signal transmission, that is, there is no wiring or through conductor (the wiring and the through conductor are located in a state avoiding the connection region R216 and the region R218).

  As described above, the wiring substrate 100 according to the present embodiment includes the core insulating layer I31 and the plurality of insulating layers I21 to I23 and I44 to I46 that are positioned in a stacked state on the upper and lower sides of the core insulating layer I31. The electrode pad 211 located on the top surface of the insulating layer above the core insulating layer I31, the external connection pad 416 located on the bottom surface of the insulating layer below the core insulating layer I31, and for grounding and power Among the electrode pads 211, a part of the plurality of ground pads 211c connected to the ground wiring conductor and the plurality of power supply pads 211b connected to the power supply wiring conductor. And a voltage regulator 60 connected to a part of the voltage regulator 60.

  The ground pad 211c and the power supply pad 211b connected to the voltage regulator 60 are located in the connection region R216, and the electrode pad 211 outside the connection region R216 is located in the connection region R217 separated from the connection region R216.

  Among the wiring conductors, a signal wiring conductor related to signal transmission between the electrode pad 211 and the external connection pad 416 is a connection region R216 and a region R218 between the connection region R216 and the connection region R217 in plan view. Is located in a state to avoid.

  Some of the signal wiring conductors are electrode pads 211 and external connection pads that are connected to the signal wiring conductors in plan view between the plurality of insulating layers I21 and I22 above the core insulating layer I31. The plurality of insulating layers I <b> 44 and I <b> 45 located between the development region R <b> 228 and the connection region R <b> 217 located on the outer edge side of the plurality of insulating layers I <b> 21 from the respective positions of 416 and below the core insulating layer I <b> 31. Between the expansion region R228 and the region where the external connection pad 416 (signal pad 416a) is disposed in plan view.

  As described above, the wiring 252 is positioned so as not to disturb the current between the through conductors 232 on the power supply surface 242b included in the power supply path between the voltage regulator 60 and the semiconductor element 70. In the wiring board 100, voltage drop can be suppressed without increasing the load related to power supply such as impedance. Accordingly, the wiring board 100 has wiring that is once drawn from the position of the signal pad 211a to the vicinity of the outer edge of the insulating layer in plan view and wiring that returns from the vicinity of the outer edge to the position of the signal pad 416a in plan view. Thus, a signal path that connects the signal pads 211a and 416a without difficulty can be obtained, and an increase in cost and labor associated with miniaturization and complexity of wiring can be suppressed. Accordingly, the wiring board 100 can supply sufficient power to the semiconductor element 70 stably and more effectively.

Further, the wiring substrate 100 has a power supply pad 211b of the connection region R216 and a power supply pad 211b of the connection region R217 on the surface of the insulating layer I22 where the wiring 252 is located between the connection region R217 and the development region R228 in plan view. And a power supply surface 242b included in the connection path. The wiring 252 is positioned so as to avoid the power supply surface 242b.
That is, since there is no isolated part or narrowly intricate part on the power supply surface 242b, the electrical conductivity of the power supply path can be stably improved.

  In addition, the connection region R217 has a rectangular shape (rectangular region), and the electrode pads 211 of the connection region R217 are respectively located on lattice points of a square lattice. The signal pad 211a is not located within a predetermined range from the center position in the direction along the side of the connection region R217 that faces the connection region R216 (the vertical direction in FIG. 3).

  Due to the arrangement of the signal pads 211a, the wiring 252 is more efficiently connected from the connection region R217 to the arrangement region and the development region R228 of the planar view signal pad 416a, that is, the connection region R216 or between the connection region R216 and the connection region R217. Can be pulled out in a direction that does not overlap the region R218 (vertical direction in FIG. 3). In addition, the length of the wiring 252 that crosses the power supply path in the power supply surface 242b is shortened also inside the connection region R217, and stable and sufficient power supply can be performed more effectively.

  In addition, the electronic device 2 of the present embodiment includes the above-described wiring board 100 and an electronic component (semiconductor element 70) connected to the electrode pad 211 located in the connection region R217. In such an electronic device 2, it is possible to stably supply sufficient power in accordance with an increase or fluctuation in power consumption of the semiconductor element 70, and to maintain a stable operation of the semiconductor element 70.

Various modifications can be made to the above-described embodiment according to the present disclosure.
For example, in the above-described embodiment, the case where the two voltage regulators 60 are positioned at symmetrical positions on the uppermost surface of the wiring board 100 has been described as an example. However, the necessary supply power, the size of the wiring board, and the signal Depending on the number of transmission paths and the like, the number (for example, one or four) of voltage regulators 60 and the position (for example, near the diagonal) may be different.

  Further, the shapes of the connection regions R216 and R217 and the number and arrangement of the internal electrode pads 211 are determined by the voltage regulator 60 and the semiconductor element 70, and are not limited to those shown in the above embodiment.

  In the above embodiment, the electrode pad 211 and the external connection pad 416 related to signal transmission are connected via the wiring 252 of the wiring layer L22 and the wiring 454 of the wiring layer L44. However, when the number of pads is large, etc. The buildup layers 20 and 40 may be connected by wiring of a plurality of wiring layers.

  Further, the positional relationship between the ground plane and the power supply plane of each of the wiring layers L21 to L23, L44 to L46, the upper conductor layer L31, and the lower conductor layer L32 is not limited to that of the above embodiment.

  In addition, specific details such as the configuration, structure, arrangement, and positional relationship described in the above embodiments can be changed as appropriate without departing from the spirit of the present disclosure.

DESCRIPTION OF SYMBOLS 1 Electronic module 2 Electronic device 10 Solder resist layer 20 Buildup layer 211 Electrode pad 211a Signal pad 211b Power supply pad 211c Grounding pads 231 to 233 Through conductors 241, 242c, 243 Grounding surface 242b Power supply surface 252 Wiring 262c, 263b Land 30 Core substrate 320 Through hole 331 Core through conductor 341b Power supply surface 341c, 342 Ground surface 361c, 362b Land 40 Build-up layer 416 External connection pad 416a Signal pad 416b Power supply pad 416c Ground pads 434-436 Through conductor 444b Power supply surface 444c 445, 446c Ground plane 446b Power supply plane 454, 455 Wiring 464c, 465b Land 50 Solder resist layer 60 Voltage regulator 61 Connection conductor 70 Semiconductor element 71 Connecting conductor 100 Wiring board 200 Module board I21-I23 Insulating layer I31 Core insulating layers I44-I46 Insulating layers L21-L23 Wiring layer L31 Upper conductor layer L32 Lower conductor layers L44-L46 Wiring layers R216, R217 Connection area R218 region R228 expanded region RUL partial region

Claims (4)

A core insulation layer;
A plurality of insulating layers positioned in a state of being laminated on the upper side and the lower side of the core insulating layer;
A first connection terminal located on the uppermost surface of the upper insulating layer;
A second connection terminal located on the lowermost surface of the lower insulating layer;
Wiring conductors for grounding, power and signals;
Of the first connection terminals, connected to a part of the plurality of ground terminals connected to the ground wiring conductor and a part of the plurality of power supply terminals connected to the power wiring conductor A voltage regulator that
With
The ground terminal and the power supply terminal connected to the voltage regulator are located in a first region,
The first connection terminal outside the first region is located in a second region separated from the first region,
The signal wiring conductor related to signal transmission between the first connection terminal and the second connection terminal includes the first region, the first region, and the second region in plan view. Located in a state avoiding the area between the areas,
Part of the signal wiring conductor is located between the upper insulating layers from the positions of the first connection terminal and the second connection terminal to which the signal wiring conductor is connected in a plan view. Is also located between the development region located on the outer edge side of the insulating layer and the second region, and between the lower insulation layers, the development region and the second region in plan view. A wiring board characterized in that the wiring board is located between the connection terminal area and the area. The power supply terminal of the first region and the power supply of the second region are formed on the surface of the insulating layer where the signal wiring conductor is located between the second region and the development region in plan view. A power supply surface included in the connection path with the terminal,
The wiring board according to claim 1, wherein the signal wiring conductor is positioned so as to avoid the power supply surface. The second region is a rectangular region;
The first connection terminals of the second region are located on lattice points of a two-dimensional lattice,
The first connection terminal connected to the signal wiring conductor is not located within a predetermined range from a center position in a direction along a side facing the first region in the second region. The wiring board according to claim 1 or 2, characterized in that: The wiring board according to any one of claims 1 to 3,
An electronic component connected to the first connection terminal located in the second region;
An electronic device comprising:

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