JP2019149220A - Semiconductor memory device and memory system - Google Patents

Abstract

To provide a semiconductor memory device and a memory system capable of improving reliability.SOLUTION: According to the embodiment, a semiconductor memory device includes: a first memory unit SU0 including first to third memory cells MT; a second memory unit SU1 including fourth to sixth memory cells MT; and a third memory unit SU2 including seventh to ninth memory cells MT. When performing a second write operation on any of the first, fourth, and seventh memory cells connected to a first word line, the first memory cell is selected first, when performing the second write operation on any of the second, fifth, and eighth memory cells connected to a second word line, the fifth memory cell is selected first, and when performing the second write operation on any of the third, sixth, and ninth memory cells connected to a third word line, the ninth memory cell is selected first.SELECTED DRAWING: Figure 11

Description

  Embodiments described herein relate generally to a semiconductor memory device and a memory system.

  A NAND flash memory is known as a semiconductor memory device.

JP 2012-048791 A

  A semiconductor memory device and a memory system capable of improving reliability are provided.

  The semiconductor memory device according to the embodiment includes a first memory unit including a first memory string having first to third memory cells and a first selection transistor, and fourth to sixth memory cells and a second selection transistor. A second memory unit including two memory strings; a third memory unit including a third memory string having seventh to ninth memory cells and a third select transistor; and gates of the first, fourth, and seventh memory cells. A first word line connected to the second word line, a second word line connected to the gates of the second, fifth and eighth memory cells, and a gate of the third, sixth and ninth memory cells. Connected to the third word line, the first to third selection gate lines connected to the first to third selection transistors, respectively, the first to third word lines, and the first to third selection gate lines. The including a row decoder. The first to ninth memory cells can each hold a plurality of bits of data, and the writing operation of the plurality of bits of data includes a first writing operation and a second writing operation. In the write operation, when the second write operation is performed on any of the first, fourth, and seventh memory cells connected to the first word line, the first memory cell is selected first, and the second word line When the second write operation is performed on any one of the second, fifth, and eighth memory cells connected to the fifth memory cell, the fifth memory cell is selected first, and the third, second, and third memory cells connected to the third word line are selected. When performing the second write operation on any of the sixth and ninth memory cells, the ninth memory cell is selected first.

FIG. 1 is a block diagram of a memory system according to the first embodiment. FIG. 2 is a block diagram of a RAM included in the memory system according to the first embodiment. FIG. 3 is a circuit diagram of a memory cell array included in the semiconductor memory device according to the first embodiment. FIG. 4 is a diagram showing data allocation, threshold distribution, and read level of the memory cell transistor in the semiconductor memory device according to the first embodiment. FIG. 5 is a diagram showing a change in the threshold distribution of the memory cell transistor due to the first write operation in the semiconductor memory device according to the first embodiment. FIG. 6 is a diagram showing a change in the threshold distribution of the memory cell transistor due to the second write operation in the semiconductor memory device according to the first embodiment. FIG. 7 is a diagram showing a command sequence of the first write operation in the memory system according to the first embodiment. FIG. 8 is a diagram showing a command sequence of the second write operation in the memory system according to the first embodiment. FIG. 9 is a flowchart of the write operation in the semiconductor memory device according to the first embodiment. FIG. 10 is a flowchart showing the shift operation of the selected string unit in the write operation in the semiconductor memory device according to the first embodiment. FIG. 11 is a diagram showing a data write order of blocks in the semiconductor memory device according to the first embodiment. FIG. 12 is a diagram showing the order of the second write operation of the word line group in the semiconductor memory device according to the first embodiment. FIG. 13 is a timing chart showing the voltage of each wiring during the program operation in the semiconductor memory device according to the first embodiment. FIG. 14 is a diagram showing the voltages of the selection gate line and the word line during the program operation in the first to 28th operations in the semiconductor memory device according to the first embodiment. FIG. 15 is a timing chart showing the voltage of the selected word line during the first and second write operations in the semiconductor memory device according to the first embodiment. FIG. 16 is an example showing the number of disturbances received by the second write operation of another string unit. FIG. 17 is an example showing the number of disturbances received by the second write operation of another string unit for each memory cell group. FIG. 18 is a diagram illustrating the order of the second write operation of the word line group in the semiconductor memory device according to the first example of the second embodiment. FIG. 19 is a diagram illustrating the order of the second write operation of the word line group in the semiconductor memory device according to the second example of the second embodiment. FIG. 20 is a diagram illustrating the order of the second write operation of the word line group in the semiconductor memory device according to the third example of the second embodiment. FIG. 21 is a diagram showing a data write order of blocks in the semiconductor memory device according to the third embodiment. FIG. 22 is a diagram showing data allocation, threshold distribution, and read level of the memory cell transistor in the semiconductor memory device according to the fourth embodiment. FIG. 23 is a view showing a change in the threshold distribution of the memory cell transistor due to the first write operation in the semiconductor memory device according to the fourth embodiment. FIG. 24 is a diagram illustrating changes in the threshold distribution of the memory cell transistor due to the second write operation in the semiconductor memory device according to the fourth embodiment. FIG. 25 is a diagram showing a change in the threshold distribution of the memory cell transistor due to the first write operation in the semiconductor memory device according to the fifth embodiment. FIG. 26 is a diagram showing changes in the threshold distribution of the memory cell transistor due to the second write operation in the semiconductor memory device according to the fifth embodiment. FIG. 27 is a diagram showing a change in the threshold distribution of the memory cell transistor due to the third write operation in the semiconductor memory device according to the fifth embodiment. FIG. 28 is a diagram showing a block data write order in the semiconductor memory device according to the fifth embodiment. FIG. 29 is a diagram showing a data write order of blocks in the semiconductor memory device according to the sixth embodiment. FIG. 30 is a diagram showing a data write order of blocks in the semiconductor memory device according to the seventh embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In this description, components having substantially the same functions and configurations are denoted by the same reference numerals. In addition, each embodiment shown below exemplifies an apparatus and a method for embodying the technical idea of this embodiment, and the technical idea of the embodiment is the material, shape, and structure of component parts. The arrangement is not specified below. Various changes can be added to the technical idea of the embodiments within the scope of the claims.

1. First Embodiment A semiconductor memory device according to a first embodiment will be described. Hereinafter, as a semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked above a semiconductor substrate will be described as an example.

1.1 Configuration 1.1.1 Configuration of Memory System First, the overall configuration of the memory system 1 will be described with reference to FIG. In addition, in the example of FIG. 1, although a part of connection of each block is shown by the arrow line, the connection between each block is not limited to this.

As shown in FIG. 1, the memory system 1 includes a semiconductor memory device 10 and a controller 20 and is connected to an external host device 30. The controller 20 and the semiconductor memory device 10 may constitute one semiconductor memory device by a combination thereof, for example, a memory card such as an SD ^TM card, an SSD (solid state drive), or the like. .

  In response to a command from the host device 30, the controller 20 commands the semiconductor memory device 10 to perform a data read operation, a write operation, an erase operation, and the like. Further, the controller 20 manages the memory space of the semiconductor memory device 10.

  The controller 20 includes a host interface circuit 21, a built-in memory (RAM) 22, a processor (CPU) 23, a buffer memory 24, an ECC circuit 25, and a NAND interface circuit 26.

  The host interface circuit 21 is connected to the host device 30 via a host bus and manages communication with the host device 30. For example, the host interface circuit 21 transfers commands and data received from the host device 30 to the CPU 23 and the buffer memory 24, respectively. The host interface circuit 21 transfers data in the buffer memory 24 to the host device 30 in response to a command from the CPU 23.

  The RAM 22 is a semiconductor memory such as a DRAM, for example, and holds firmware for managing the semiconductor storage device 10, various management tables, and the like. The RAM 22 is used as a work area for the CPU 23.

  The CPU 23 controls the operation of the entire controller 20. For example, the CPU 23 issues a write command to the NAND interface circuit 26 in response to a write command received from the host device 30. This operation is the same for the read command and the erase command. Further, the CPU 23 executes various processes for managing the memory space of the semiconductor memory device 10 such as wear leveling.

  The buffer memory 24 temporarily stores read data received from the semiconductor memory device 10 by the controller 20, write data received from the host device 30, and the like.

  The ECC circuit 25 performs data error correction (ECC: Error Checking and Correcting) processing. Specifically, the ECC circuit 25 generates parity based on the write data when writing data. Then, the ECC circuit 25 generates a syndrome from the parity when reading data, detects an error, and corrects the detected error.

  The NAND interface circuit 26 is connected to the semiconductor memory device 10 via a NAND bus and manages communication with the semiconductor memory device 10. Signals transmitted and received between the semiconductor memory device 10 and the controller 20 follow the NAND interface. For example, the NAND interface circuit 26 transmits a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn to the semiconductor memory device 10 based on an instruction received from the CPU 23, and a ready / busy signal RBn. Are received from the semiconductor memory device 10 and input / output signals I / O are transmitted to and received from the semiconductor memory device 10.

  The signals CLE and ALE are signals for notifying the semiconductor memory device 10 that the input signal I / O to the semiconductor memory device 10 is the command CMD and the address information ADD, respectively. The signal WEn is asserted at the “L” level, and is a signal for causing the semiconductor memory device 10 to capture the input signal I / O. The signal REn is asserted at the “L” level, and is a signal for reading the output signal I / O from the semiconductor memory device 10.

  The ready / busy signal RBn is a signal for notifying whether or not the semiconductor memory device 10 can receive an instruction from the controller 20. For example, the ready / busy signal RBn is set to “H” level when the semiconductor memory device 10 is in a ready state in which an instruction from the controller 20 can be received, and is set to “L” level when the semiconductor memory device 10 is in a busy state where reception is impossible.

  The input / output signal I / O is an 8-bit signal, for example, and includes a command CMD, address information ADD, data DAT, and the like. For example, during a write operation, the input / output signal I / O transferred to the semiconductor memory device 10 includes a write command CMD issued by the CPU 23, address information ADD, and write data DAT in the buffer memory 24. In the read operation, the input / output signal I / O transferred to the semiconductor memory device 10 includes a read command CMD and address information ADD, and the input / output signal I / O transferred to the controller 20 receives the read data DAT. Including.

  Examples of the host device 30 that uses the memory system 1 described above include a digital camera and a personal computer.

  Next, the configuration of the semiconductor memory device 10 will be described. The semiconductor memory device 10 includes a memory cell array 11, a command register 12, an address register 13, a sequencer 14, a driver circuit 15, a row decoder 16, a data register 17, and a sense amplifier 18.

  The memory cell array 11 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The block BLK is a set of a plurality of nonvolatile memory cell transistors associated with the bit line and the word line, and is, for example, a data erasing unit.

  The command register 12 holds the command CMD received from the controller 20. The address register 13 holds address information ADD received from the controller 20. This address information ADD includes a column address CA, a page address PA, and a block address BA.

  The sequencer 14 controls the operation of the entire semiconductor memory device 10 based on the command CMD held in the command register 12. Specifically, the sequencer 14 controls the driver circuit 15, the row decoder 16, the data register 17, the sense amplifier 18, and the like based on the command CMD, and executes a data write operation, a read operation, and the like.

The driver circuit 15 generates a necessary voltage based on an instruction from the sequencer 14. Based on the page address PA held in the address register 13, the driver circuit 15
The generated voltage is supplied to the row decoder 16.

  The row decoder 16 selects one of the blocks BLK0 to BLKn based on the block address BA held in the address register 13. Further, the row decoder 16 selects the row direction in the selected block BLK, and applies the voltage supplied from the driver circuit 15 to the selected word line.

  The data register 17 includes a plurality of latch circuits. The latch circuit temporarily holds data. For example, in a write operation, the data register 17 temporarily holds write data received via an input / output circuit (not shown) and transmits the data to the sense amplifier 18. Further, for example, in the read operation, the data register 17 temporarily holds the read data received from the sense amplifier 18 and transmits it to the controller 20 via the input / output circuit.

  The sense amplifier 18 senses data read from the memory cell array 11 during a read operation. Then, the sense amplifier 18 transmits the read data to the data register 17. The sense amplifier 18 transmits write data to the memory cell array 11 during a write operation.

1.1.2 Configuration of RAM Next, the configuration of the RAM 22 will be described with reference to FIG.

  As shown in FIG. 2, the RAM 22 includes page clusters CL0 to CL4. Each page cluster CL includes regions PG0 to PG3. Each region PG can hold one page of data. The definition of this “page” will be described later. That is, each of the page clusters CL0 to CL4 can hold four pages of data. Note that the storage capacity of the page cluster CL is not limited to four pages, and may be two pages, three pages, or five pages or more.

1.1.3 Configuration of Memory Cell Array Next, the configuration of the memory cell array 11 will be described with reference to FIG. The example of FIG. 3 shows the block BLK0, but the configuration of the other blocks BLK is the same.

  As shown in FIG. 3, the block BLK0 includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, 96 memory cell transistors MT0 to MT95 and select transistors ST1 and ST2. Hereinafter, when the memory cell transistors MT0 to MT95 are not limited, they are expressed as memory cell transistors MT. The memory cell transistor MT includes a control gate and a charge storage layer, and holds data in a nonvolatile manner.

  The number of string units SU is not limited to four. The memory cell transistor MT may be a MONOS type using an insulating film as a charge storage layer or an FG type using a conductive layer as a charge storage layer. Hereinafter, in the present embodiment, a MONOS type will be described as an example. The number of memory cell transistors MT is not limited to 96, and may be 8, 16, 32, 64, 128, etc., and the number is not limited. Furthermore, the number of selection transistors ST1 and ST2 is arbitrary, and it is sufficient that each is one or more.

  The memory cell transistor MT is connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. More specifically, the current paths of the memory cell transistors MT0 to MT95 are connected in series. The drain of the memory cell transistor MT95 is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT0 is connected to the drain of the selection transistor ST2.

  The gates of the select transistors ST1 in each of the string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. Similarly, the gates of the selection transistors ST2 in each of the string units SU0 to SU3 are connected to selection gate lines SGS0 to SGS3, respectively. Hereinafter, when the selection gate lines SGD0 to SGD3 are not limited, they are expressed as selection gate lines SGD. When the selection gate lines SGS0 to SGS3 are not limited, they are expressed as selection gate lines SGS. Note that the select gate lines SGS0 to SGS3 of the string units SU may be connected in common.

  Control gates of the memory cell transistors MT0 to MT95 in the block BLK are commonly connected to word lines WL0 to WL95, respectively. Hereinafter, when the word lines WL0 to WL95 are not limited, they are expressed as a word line WL or WLi (i is an integer of 0 to 95).

  The drain of the selection transistor ST1 of each NAND string NS in the string unit SU is connected to different bit lines BL0 to BL (m−1) (m is an integer of 2 or more). Hereinafter, when the bit lines BL0 to BL (m−1) are not limited, they are expressed as bit lines BL. Each bit line BL commonly connects one NAND string NS in each string unit SU among a plurality of blocks BLK. Further, the sources of the plurality of selection transistors ST2 are commonly connected to the source line SL. That is, the string unit SU is an aggregate of NAND strings NS connected to different bit lines BL and connected to the same selection gate lines SGD and SGS. The block BLK is an aggregate of a plurality of string units SU that share the word line WL. The memory cell array 11 is an aggregate of a plurality of blocks BLK that share the bit line BL.

  Data writing and reading are collectively performed on the memory cell transistors MT connected to any one of the word lines WL in any of the string units SU. Hereinafter, a group of memory cell transistors MT that are collectively selected during a data write operation and a data read operation will be referred to as a “memory cell group MCG”. A collection of 1-bit data written to or read from each memory cell transistor MT in one memory cell group MCG is called a “page”. Therefore, when 4-bit data is stored in one memory cell transistor MT, four pages of data are stored in the memory cell group MCG connected to one word line WL.

  In the present embodiment, one memory cell transistor MT can hold 4-bit data. That is, the memory cell transistor MT in the present embodiment is a QLC (quad level cell) that holds 4-bit data. The 4-bit data held by a QLC (quad level cell) memory cell transistor is referred to as a lower bit, a middle bit, an upper bit, and a top bit in order from the lower bit. A set of lower bits held by the memory cell transistors MT connected to the same word line WL is called a “lower page”, a set of middle bits is called a “middle page”, and a set of upper bits is called an “upper page”. And a set of Top bits is called a “Top page”.

  Note that the number of bits of data that can be held by the memory cell transistor MT is not limited to 4 bits, and the present embodiment can be applied to any number of bits, that is, 2 bits or more. For example, the memory cell transistor MT may be an MLC (multi level cell) that holds 2-bit data or a TLC (three level cell) that holds 3-bit data.

  The configuration of the memory cell array 11 may be other configurations. The configuration of the memory cell array 11 is described in, for example, US patent application Ser. No. 12 / 407,403 filed on Mar. 19, 2009, “THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY”. ing. Also, US patent application Ser. No. 12 / 406,524 filed Mar. 18, 2009 entitled “Three DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY”, “Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof” (NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME), US patent application Ser. No. 12 / 679,991, filed Mar. 25, 2010 “SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME” In US patent application Ser. No. 12 / 532,030 filed Mar. 23, 2009. These patent applications are hereby incorporated by reference in their entirety.

1.2 Threshold Distribution of Memory Cell Transistor MT Next, the threshold distribution of the memory cell transistor MT will be described with reference to FIG. FIG. 4 shows data that can be taken by each memory cell transistor MT, threshold distribution, and voltages used in the read operation.

  As shown in FIG. 4, when the memory cell transistor MT holds 4-bit data, the threshold voltage distribution is divided into 16 pieces. The 16 threshold distributions are divided into “0” level, “1” level, “2” level, “3” level, “4” level, “5” level, “6” level in order from the lowest threshold voltage. They are referred to as “7” level, “8” level, “9” level, “A” level, “B” level, “C” level, “D” level, “E” level, and “F” level.

  Further, the voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF shown in FIG. “1” level, “2” level, “3” level, “4” level, “5” level, “6” level, “7” level, “8” level, “9” level, “A” level, “A” level, It is used for verifying the B level, the C level, the D level, the E level, and the F level. The voltage VREAD is a voltage applied to the non-selected word line during the read operation. When the voltage VREAD is applied to the gate, the memory cell transistor MT is turned on regardless of the data held. The relationship between these voltage values is V1 <V2 <V3 <V4 <V5 <V6 <V7 <V8 <V9 <VA <VB <VC <VD <VE <VF <VREAD.

  The “0” level in the above threshold distribution corresponds to the erased state of the memory cell transistor MT. The threshold voltage at the “0” level is less than the voltage V1. The threshold voltage at the “1” level is not less than the voltage V1 and less than the voltage V2. The threshold voltage at the “2” level is not less than the voltage V2 and less than the voltage V3. The threshold voltage at the “3” level is equal to or higher than the voltage V3 and lower than the voltage V4. The threshold voltage at the “4” level is not less than the voltage V4 and less than the voltage V5. The threshold voltage at the “5” level is not less than the voltage V5 and less than the voltage V6. The threshold voltage at the “6” level is not less than the voltage V6 and less than the voltage V7. The threshold voltage at the “7” level is not less than the voltage V7 and less than the voltage V8. The threshold voltage at the “8” level is not less than the voltage V8 and less than the voltage V9. The threshold voltage at the “9” level is equal to or higher than the voltage V9 and lower than the voltage VA. The threshold voltage at the “A” level is equal to or higher than the voltage VA and lower than the voltage VB. The threshold voltage at the “B” level is equal to or higher than the voltage VB and lower than the voltage VC. The threshold voltage at the “C” level is equal to or higher than the voltage VC and lower than the voltage VD. The threshold voltage at the “D” level is equal to or higher than the voltage VD and lower than VE. The threshold voltage at the “E” level is equal to or higher than the voltage VE and lower than VF. The threshold voltage at the “F” level is equal to or higher than the voltage VE and lower than the voltage VREAD.

  In the read operation in this example, a case where the verify voltage is used as the read voltage will be described as an example for the sake of simplicity. Hereinafter, the read operations using the voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF are respectively read operations 1R, 2R, They are called 3R, 4R, 5R, 6R, 7R, 8R, 9R, AR, BR, CR, DR, ER, and FR. In the read operation 1R, it is determined whether or not the threshold voltage of the memory cell transistor MT is less than the voltage V1. In the read operation 2R, it is determined whether or not the threshold voltage of the memory cell transistor MT is less than the voltage V2. In the read operation 3R, it is determined whether or not the threshold voltage of the memory cell transistor MT is less than the voltage V3. The same applies hereinafter.

  The 16 threshold distributions described above are formed by writing 4-bit (4 pages) data consisting of a lower bit, a middle bit, an upper bit, and a top bit. The 16 threshold distributions correspond to different 4-bit data. In the present embodiment, data is allocated to the “Lower bit / Middle bit / Upper bit / Top bit” as shown below for the memory cell transistors MT included in each level.

  The memory cell transistor MT included in the “0” level holds “1111” data. The memory cell transistor MT included in the “1” level holds “0111” data. The memory cell transistor MT included in the “2” level holds “0101” data. The memory cell transistor MT included in the “3” level holds “0001” data. The memory cell transistor MT included in the “4” level holds “1001” data. The memory cell transistor MT included in the “5” level holds “1000” data. The memory cell transistor MT included in the “6” level holds “0000” data. The memory cell transistor MT included in the “7” level holds “0100” data. The memory cell transistor MT included in the “8” level holds “0110” data. The memory cell transistor MT included in the “9” level holds “0010” data. The memory cell transistor MT included in the “A” level holds “0011” data. The memory cell transistor MT included in the “B” level holds “1011” data. The memory cell transistor MT included in the “C” level holds “1010” data. The memory cell transistor MT included in the “D” level holds “1110” data. The memory cell transistor MT included in the “E” level holds “1100” data. The memory cell transistor MT included in the “F” level holds “1101” data.

  When reading data allocated in this way, the Lower bit is determined by the read operations 1R, 4R, 6R, and BR. The Middle bit is determined by the read operations 3R, 7R, 9R, and DR. The upper bit is determined by read operations 2R, 8R, and ER. The Top bit is determined by read operations 5R, AR, CR, and FR. That is, the values of the Lower bit, the Middle bit, the Upper bit, and the Top bit are determined by four, four, three, and four read operations, respectively. Hereinafter, this data allocation is referred to as “4-4-3-4 code”.

1.3 Write Operation Next, the write operation will be described. The write operation roughly includes a program operation and a verify operation. Then, by repeating the combination of the program operation and the verify operation (hereinafter referred to as “program loop”), the threshold voltage of the memory cell transistor MT is raised to the target level.

  The program operation is an operation of increasing the threshold voltage by injecting electrons into the charge storage layer (or maintaining the threshold voltage by prohibiting the injection). Hereinafter, the operation for increasing the threshold voltage is referred to as a ““ 0 ”program”. For example, raising the threshold value of the memory cell transistor MT included in the “0” level threshold distribution so as to be included in the “1” level threshold distribution is called a “0” program. A voltage for programming “0” (for example, voltage VSS) is applied from the sense amplifier 18 to the bit line BL to be programmed “0”. On the other hand, the operation of maintaining the threshold voltage is called ““ 1 ”program” or “write prohibition”, and the voltage for the “1” program is supplied from the sense amplifier 18 to the bit line BL targeted for the “1” program. (Hereinafter referred to as “voltage VBL”). Hereinafter, the bit line corresponding to the “0” program is expressed as BL (“0”), and the bit line corresponding to the “1” program is expressed as BL (“1”).

  The verify operation is an operation of reading data after the program operation and determining whether or not the threshold voltage of the memory cell transistor MT has reached a target level. Hereinafter, the case where the threshold voltage of the memory cell transistor MT has reached the target level is referred to as “passed verification”, and the case where the threshold voltage has not reached the target level is referred to as “failed verification”.

1.3.1 First and Second Write Operations Next, the write operation of this embodiment will be described in detail. In the present embodiment, the 4-page data write operation is executed in two steps of the first write operation and the second write operation. Hereinafter, the first write operation performed on a certain memory cell group MCG is referred to as a “first write operation”, and the second (nth) write operation is referred to as a “second write operation” ( This is called the nth write operation). Each of the first and second write operations is executed based on four pages of write data. In the present embodiment, 4 page data is written roughly in the first write operation, and the 4 page data is written precisely in the second write operation. Note that the write operation may be divided into three or more times. For example, four page data may be written in three times, or may be written in four times for each page data.

  First, the first write operation will be described with reference to FIG. FIG. 5 shows a change in the threshold distribution of the memory cell transistor MT due to the first write operation.

  As shown in FIG. 5, the sequencer 14 performs the first write operation based on the 4-page data input from the controller 20.

  The threshold voltage of the memory cell transistor MT before executing the first write operation is distributed to the “ER” level. The threshold voltage at the “ER” level is less than the voltage V1, and corresponds to the erased state of the memory cell transistor MT.

  In the first write operation, the sequencer 14 uses the voltages VM1, VM2, VM3, VM4, VM5, VM6, VM7, VM8, VM9, VMA, VMB, VMC, VMD, VME, and VMF as verify voltages. The voltages VM1, VM2, VM3, VM4, VM5, VM6, VM7, VM8, VM9, VMA, VMB, VMC, VMD, VME, and VMF are “1111” (“Lower bit / Middle bit / Upper bit / Top bit”, respectively. “) Data,“ 0111 ”data,“ 0101 ”data,“ 0001 ”data,“ 1001 ”data,“ 1000 ”data,“ 0000 ”data,“ 0100 ”data,“ 0110 ”data,“ 0010 ”data,“ This is used when writing “0011” data, “1011” data, “1010” data, “1110” data, “1100” data, and “1101” data. The voltage VM1 is less than the voltage V1. The voltage VM2 is not less than the voltage V1 and less than the voltage V2. The voltage VM3 is not less than the voltage V2 and less than the voltage V3. The voltage VM4 is not less than the voltage V3 and less than the voltage V4. The voltage VM5 is not less than the voltage V4 and less than the voltage V5. The voltage VM6 is not less than the voltage V5 and less than the voltage V6. The voltage VM7 is not less than the voltage V6 and less than the voltage V7. The voltage VM8 is not less than the voltage V7 and less than the voltage V8. The voltage VM9 is not less than the voltage V8 and less than the voltage V9. The voltage VMA is not less than the voltage V9 and less than the voltage VA. The voltage VMB is equal to or higher than the voltage VA and lower than the voltage VB. Voltage VMC is equal to or higher than voltage VB and lower than voltage VC. The voltage VMD is equal to or higher than the voltage VC and lower than the voltage VD. The voltage VME is equal to or higher than the voltage VD and lower than the voltage VE. The voltage VMF is equal to or higher than the voltage VE and lower than the voltage VF.

  When the first write operation is executed, the threshold voltage of the memory cell transistor MT rises based on the data to be written, and 16 threshold distributions are formed. In the first write operation, as shown in FIG. 5, the 16 threshold distributions may overlap with adjacent threshold distributions. The “M0” level shown in FIG. 5 is formed by a plurality of memory cell transistors MT into which “1111” data is written. The “M1” level is formed by a plurality of memory cell transistors MT into which “0111” data is written. The “M2” level is formed by a plurality of memory cell transistors MT into which “0101” data is written. The same applies hereinafter.

  The threshold voltage at the “M0” level is less than the voltage V1 and corresponds to the erased state of the memory cell transistor MT, similarly to the “0” level and the “ER” level described above. That is, in the memory cell transistor MT that writes 1111 ”data in the first write operation, an increase in threshold voltage is suppressed. However, the“ M0 ”level is also changed to the“ 1 ”level by the first write operation. However, the threshold voltage rises slightly: the threshold voltage at the “M1” level is equal to or higher than the voltage VM1 and lower than the voltage V2. The threshold voltage at the “M2” level is equal to or higher than the voltage VM2 and lower than the voltage V3. The same.

  As described above, the voltages VM1, VM2, VM3, VM4, VM5, VM6, VM7, VM8, VM9, VMA, VMB, VMC, VMD, VME, and VMF used for the verify in the first write operation are verified. The threshold voltage of the passed memory cell transistor MT is set so as not to exceed the voltages V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, VF, and VREAD.

  Next, the second write operation will be described with reference to FIG. FIG. 6 shows a change in the threshold distribution of the memory cell transistor MT due to the second write operation.

  As shown in FIG. 6, the sequencer 14 executes the second write operation based on the 4-page data input from the controller 20.

  In the second write operation, the sequencer 14 uses voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF as verify voltages. When the second write operation is executed, the threshold voltage of the memory cell transistor MT rises based on the data to be written, and 16 narrow threshold distributions are formed from the 16 wide threshold distributions. For example, a threshold distribution of “0” level is formed from the threshold distribution of “M0” level, a threshold distribution of “1” level is formed from the threshold distribution of “M1” level, and “2” from the threshold distribution of “M2” level. A “level threshold distribution is formed. The same applies hereinafter.

1.3.2 Command Sequence Next, a command sequence transmitted from the controller 20 to the semiconductor memory device will be described with reference to FIGS. 7 and 8 show command sequences in the first write operation and the second write operation, and show the input / output signal I / O input to the semiconductor memory device 10. The command CMD input to the semiconductor memory device 10 is stored in the command register 12, the address information ADD is stored in the address register 13, and the data DAT is stored in a latch circuit (not shown) of the data register 17. In the following description, a command combination corresponding to the first write operation is referred to as a first command set, and a command combination corresponding to the second write operation is referred to as a second command set.

  First, a command sequence in the first write operation will be described.

  As shown in FIG. 7, the controller 20 first transmits a command “xzh” to the semiconductor memory device 10. The command “xzh” is a command for instructing the semiconductor memory device 10 to perform the first write operation.

  Next, the controller 20 issues a command “01h” and transmits it to the semiconductor memory device 10. The command “01h” is a command indicating that the subsequently received data DAT is write data for the first page.

  Next, the controller 20 issues a command “80h” and transmits it to the semiconductor memory device 10. The command “80h” is a command for instructing the semiconductor memory device 10 to perform a write operation.

  Next, the controller 20 continuously transmits the address information ADD and the lower page data DAT1 to the semiconductor memory device 10. The semiconductor memory device 10 holds the received data DAT 1 in the latch circuit of the data register 17.

  Next, the controller 20 issues a command “xyh” and transmits it to the semiconductor memory device 10. When the command “xyh” is stored in the command register 12, the sequencer 14 sets the ready / busy signal RBn to a low (“L”) level indicating a busy state, and the data DAT 1 held in the data register 17 is sense amplifier 18. To be transferred. When the transfer of the data DAT1 to the sense amplifier 18 is completed, the sequencer 14 sets the ready / busy signal RBn to a high (“H”) level indicating a ready state. This operation is indicated as “Dummy Busy” in FIG.

  Next, when the controller 20 receives the “H” level ready busy signal RBn, the command “xzh”, the command “02h”, the command “80h”, the address information ADD, the data DAT2 of the Middle page, and the command “Xyh” is sequentially transmitted to the semiconductor memory device 10. The command “02h” is a command indicating that the subsequently received data DAT2 is write data for the second page. When the command “xyh” is stored in the command register 12, the sequencer 14 sets the ready / busy signal RBn to “L” level and transfers the data DAT 2 held in the data register 17 to the sense amplifier 18.

  Next, when the controller 20 receives the “H” level ready busy signal RBn, the command “xzh”, the command “03h”, the command “80h”, the address information ADD, the upper page data DAT3, the command “Xyh” is sequentially transmitted to the semiconductor memory device 10. When the command “xyh” is stored in the command register 12, the sequencer 14 sets the ready / busy signal RBn to “L” level and transfers the data DAT 3 held in the data register 17 to the sense amplifier 18.

  Next, when the controller 20 receives the “H” level ready busy signal RBn, the command “xzh”, the command “04h”, the command “80h”, the address information ADD, the Top page data DAT4, the command “10h” is sequentially transmitted to the semiconductor memory device 10.

  When the command “10h” is stored in the command register 12, the sequencer 14 sets the ready / busy signal RBn to the “L” level and transfers the data DAT 4 held in the data register 17 to the sense amplifier 18. Then, the sequencer 14 performs the first write operation based on the data DAT1 to DAT4 stored in the sense amplifier 18. Hereinafter, the execution period of the first write operation is tProg1.

  Next, a command sequence in the second write operation will be described.

  As shown in FIG. 8, the command sequence in the second write operation is the same as that except for the command “xzh” given at the beginning of the command sequence in the first write operation described with reference to FIG.

  When the command “10h” as the last command shown in FIG. 8 is stored in the command register 12, the sequencer 14 sets the ready / busy signal RBn to the “L” level and executes the second write operation. Hereinafter, the execution period of the second write operation is tProg2.

1.3.3 Overall Flow of Write Operation Next, the overall flow of the write operation will be described with reference to FIGS. FIG. 9 is a flowchart of the entire write operation. FIG. 10 is a flowchart showing the shift operation of the selected string unit in the write operation. In the following description, for simplicity of explanation, the variable i is used as the number of the word line WL, and the variable j is used as the number of the string unit SU. The variables i and j are variables held by a counter provided in the controller 20, for example, and are incremented by the control of the controller 20.

  The sequencer 14 performs a write operation based on the address information ADD and data DAT transmitted from the controller 20.

  As shown in FIG. 9, first, the controller 20 selects i = j = 0, that is, selects the word line WL0 and the string unit SU0 (step S10), and transmits the first command set to the sequencer 14.

  Next, the sequencer 14 executes a first write operation based on a command from the controller 20 (step S11).

  Next, the controller 20 shifts the selected string unit SU, that is, the variable j (step S12). More specifically, the controller 20 increments the variable j to j = j + 1 when the variable j is 0 to 2, and sets j = 0 when the variable j is 3. Then, the controller 20 confirms whether or not the first write operation of the memory cell group MCG connected to the word line WLi (i = 0) is completed in the string units SU0 to SU3 (step S13).

  In the string units SU0 to SU3, when the first write operation corresponding to the word line WLi is not completed (step S13_No), that is, when the variable j after the shift is 1 to 3, the controller 20 sets the word line WLi to The corresponding first command set is transmitted to the sequencer 14. Returning to step S11, the sequencer 14 executes the first write operation corresponding to the word line WLi.

  In the string units SU0 to SU3, when the first write operation corresponding to the word line WLi is finished (step S13_Yes), that is, when the variable j after the shift is 0, the controller 20 sends the variable i = The first command set corresponding to i + 1, that is, the word line WL (i + 1) is transmitted.

  Next, the sequencer 14 performs a first write operation corresponding to the word line WL (i + 1) based on the command from the controller 20 (step S14).

  When the first write operation is finished, the controller 20 transmits the variable i, that is, the second command set corresponding to the word line WLi, to the sequencer 14. The sequencer 14 executes the second write operation corresponding to the word line WLi based on the command from the controller 20 (step S15).

  Next, similarly to step S12, the controller 20 shifts the selected string unit SU, that is, the variable j (step S16). Then, the controller 20 confirms whether or not the second write operation of the memory cell group MCG connected to the word line WLi is completed in the string units SU0 to SU3 (step S17).

  In the string units SU0 to SU3, when the second write operation corresponding to the word line WLi is not completed (step S17_No), the controller 20 transmits the first command set corresponding to the word line WL (i + 1) to the sequencer 14. To do. Returning to step S14, the sequencer 14 executes the first write operation corresponding to the word line WL (i + 1).

  In the string units SU0 to SU3, when the second write operation corresponding to the word line WLi is finished (step S17_Yes), the controller 20 increments the variable i to make the variable i = i + 1. Further, the controller 20 shifts the selected string unit SU, that is, the variable j, similarly to step S12 (step S18). Next, the controller 20 checks whether the variable i of the word line WLi is i = 95 (step S19). That is, the controller 20 confirms whether the word line WLi corresponding to the incremented variable i is the terminal word line WL95.

  When i = 95 is not satisfied (step S19_No), the controller 20 transmits the first command set corresponding to the word line WL (i + 1) to the sequencer 14. Returning to step S14, the sequencer 14 executes the first write operation corresponding to the word line WL (i + 1).

  When i = 95 (step S19_Yes), the controller 20 transmits the second command set corresponding to the word line WLi to the sequencer 14. The sequencer 14 executes the second write operation corresponding to the word line WLi based on the command from the controller 20 (step S20).

  After executing the second write operation corresponding to the word line WLi in step S20, the controller 20 shifts the selected string unit SU, that is, the variable j, similarly to step S12 (step S21). Then, the controller 20 confirms whether the second write operation of the memory cell group MCG connected to the word line WLi is completed in the string units SU0 to SU3 (step S22).

  In the string units SU0 to SU3, when the second write operation corresponding to the word line WLi is not completed (step S22_No), the controller 20 transmits the second command set corresponding to the word line WLi to the sequencer 14. Returning to step S20, the sequencer 14 executes the second write operation corresponding to the word line WLi.

  In the string units SU0 to SU3, when the second write operation corresponding to the word line WLi has ended (step S22_Yes), the controller 20 ends the write operation in the block BLK.

  Next, the shift operation of the selected string unit SU will be described.

  As shown in FIG. 10, first, the controller 20 increments the variable j to j = j + 1 (step S30).

  Next, when the variable j = 4 (step S31_Yes), the controller 20 sets the variable j = 0 (step S32).

  On the other hand, when the variable j is not 4 = 4 (step S31_No), the controller 20 does not change the variable j. That is, the variable j = j + 1 obtained in step S30 is maintained.

1.3.4 Data Write Order Next, the data write order will be described with reference to FIG. FIG. 11 shows the selection order of the string units SU in one block BLK. A solid square frame divided into two upper and lower lines by a broken line corresponding to the word line WL and the string unit SU indicates one memory cell group MCG, and an upper stage of the square frame indicates a second write operation (reference numeral). “WRT2”), and the lower part of the square frame indicates the first write operation (reference numeral “WRT1”).

  As shown in FIG. 11, first, the sequencer 14 executes a first write operation that selects the word line WL0 and sequentially selects the string units SU0 to SU3 as the first to fourth operations.

  Next, the sequencer 14 selects the string unit SU0 as the fifth and sixth operations, and executes the first write operation that selects the word line WL1 and the second write operation that selects the word line WL0. To do. In addition, the sequencer 14 sequentially selects the string units SU1 to SU3 as the seventh to twelfth operations, and selects the word line WL1 in the same procedure as the fifth and sixth operations. And the second write operation with the word line WL0 selected are executed alternately.

  Next, the sequencer 14 selects, as the 13th to 20th operations, the first write operation that selects the word line WL2 for each string unit SU and the word line WL1 as in the 5th to 12th operations. The second write operation is executed alternately. In the thirteenth to twentieth operations, the string units SU1, SU2, SU3, and SU0 are selected in order. That is, the string unit SU selected first is shifted from SU0 to SU1.

  Next, the sequencer 14 executes the 21st to 28th operations in which the word lines WL3 and WL2 are selected, similarly to the 5th to 12th operations. In the 21st to 28th operations, the string units SU2, SU3, SU0, and SU1 are selected in order. That is, the string unit SU selected first is shifted from SU1 to SU2.

  Next, the sequencer 14 executes the 29th to 36th operations in which the word lines WL4 and WL3 are selected, similarly to the 5th to 12th operations. In the 29th to 36th operations, the string units SU3, SU0, SU1, and SU2 are selected in order. That is, the string unit SU selected first is shifted from SU2 to SU3.

  Similarly, in the 37th to 44th operations in which the word lines WL5 and WL4 are selected, the sequencer 14 first selects the string unit SU0, and in the 45th to 52nd operations in which the word lines WL6 and WL5 are selected, In the 53rd to 60th operations in which the string unit SU1 is first selected and the word lines WL7 and WL6 are selected, the string unit SU2 is first selected. The same applies to the subsequent processing.

  As described above, the sequencer 14 performs a write operation based on the address information ADD and data DAT transmitted from the controller 20.

  That is, when the controller 20 causes the sequencer 14 to perform a write operation, the string unit SU that is first subjected to the second write operation is moved from the word line WL0 toward the word line WL95, and the string units SU0, SU1, SU2, SU3. The page address PA is designated so as to repeatedly shift in the order of. In other words, when the controller 20 causes the sequencer 14 to perform a write operation, the string unit SU that is first subjected to the first write operation is moved from the word line WL1 toward the word line WL95, and the string units SU0, SU1, SU2. , The page address PA is designated so as to repeatedly shift in the order of SU3.

  Accordingly, the cycle of the selected string unit SU is repeated for every four word lines WL corresponding to the four string units SU. Hereinafter, a group of four word lines WL corresponding to this cycle is referred to as a word line group WG. In the example of FIG. 11, paying attention to the order of the string units SU in which the second write operation is first performed, the four word lines WL0 to WL3 are set as the word line group WG0, and the four word lines WL4 to WL7 are set. The word line group WG1 is used. The same applies to the subsequent word lines WL.

  Next, the order of the second write operation in one word line group WG will be described with reference to FIG.

  As shown in FIG. 12, it is assumed that a certain word line group WG includes word lines WLi to WL (i + 3). Then, in the case of the word line WLi, the second writing is executed in the order of the string units SU0, SU1, SU2, SU3. In the case of the word line WL (i + 1), the first string unit SU is shifted from the string unit SU0 to the string unit SU1, and the second write is executed in the order of the string units SU1, SU2, SU3, SU0. In the case of the word line WL (i + 2), the first string unit SU is shifted from the string unit SU1 to the string unit SU2, and the second write is executed in the order of the string units SU2, SU3, SU0, SU1. In the case of the word line WL (i + 3), the first string unit SU is shifted from the string unit SU2 to the string unit SU3, and the second write is executed in the order of the string units SU3, SU0, SU1, and SU2.

1.3.5 Voltage of Each Wiring During Program Operation Next, an example of the voltage of each wiring during the program operation will be described with reference to FIGS. The example of FIG. 13 shows the program operation in the first program loop. The example of FIG. 14 shows the data write order (first to 28th operations) and the corresponding voltages of the select gate lines SGD0 to SGD3 and word lines WL0 to WL4. In the example of FIG. 14, the first program operation of each write operation is shown to simplify the description.

  As shown in FIG. 13, at time t1, the sense amplifier 18 applies the voltage VBL to the bit line BL (“1”) and starts BL precharge. The row decoder 16 applies the voltage VSD1 to the selection gate line SGD (reference numeral “selection SGD”) of the selection string unit SU in the selection block BLK. The voltage VSD1 is a voltage that turns on the selection transistor ST1. On the other hand, the row decoder 16 applies the voltage VSS to the selection gate line SGD (reference numeral “non-selection SGD”) of the non-selection string unit SU to turn off the corresponding selection transistor ST1. In addition, the row decoder 16 applies the voltage VSS to the selection gate line SGS of the selected string unit SU and the unselected string unit SU, thereby turning off the selection transistor ST2. A voltage VCELSRC (> VSS) is applied to the source line SL.

  At time t2, the row decoder 16 applies the voltage VSD2 to the selection gate line SGD of the selected string unit SU. The voltage VSD2 is a voltage lower than the voltage VSD1 and the voltage VBL, and the selection transistor ST1 to which the voltage VSS is applied is turned on, but the selection transistor ST1 to which the voltage VBL is applied is cut off. As a result, the channel of the NAND string NS corresponding to the bit line BL (“1”) is in a floating state.

  At time t3, the row decoder 16 applies the voltage VPASS to each word line WL of the selected string unit SU. The voltage VPASS is a voltage that turns on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT.

  At time t4, the row decoder 16 applies the voltage VPGM to the selected word line WL of the selected string unit SU. The voltage VPGM is a high voltage for injecting electrons into the charge storage layer.

  In the NAND string NS corresponding to the bit line BL (“0”), since the selection transistor ST1 is in the on state, the channel potential of the memory cell transistor MT connected to the selected word line WL is VSS. Therefore, the potential difference (VPGM-VSS) between the control gate and the channel is increased. As a result, electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT corresponding to the bit line BL (“0”) is increased.

  In the NAND string NS corresponding to the bit line BL (“1”), the selection transistor ST1 is cut off, so that the channel of the memory cell transistor MT connected to the selection word line WL is electrically floating. . Then, the channel potential rises due to capacitive coupling with the word line WL or the like. Therefore, the potential difference between the control gate and the channel is smaller than that of the memory cell transistor MT corresponding to the bit line BL (“0”). As a result, almost no electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT corresponding to the bit line BL (“1”) is maintained (the threshold voltage distribution level is changed to a higher distribution) The threshold voltage does not fluctuate).

  At time t5, the row decoder 16 applies the voltage VSS to the word line WL.

  At time t6, the recovery process is executed and the program operation ends.

  Next, the data write order and the corresponding voltages of the select gate lines SGD0 to SGD3 and the word lines WL0 to WL4 will be described.

  As shown in FIG. 14, in the first program operation, the selection gate line SGD0 and the word line WL0 are selected. A voltage VSD (voltages VSD1 and VSD2) is applied to the selected gate line SGD0, a voltage VPGM (and voltage VPASS) is applied to the selected word line WL0, and a voltage VPASS is applied to the unselected word lines WL1 to WL3. .

  Similarly, in the second to fourth operations, the word line WL0 is selected, and the selection gate lines SGD1 to SGD3 are sequentially selected. More specifically, the voltage VSD is applied to the selection gate line SGD1 in the second operation, the voltage VSD is applied to the selection gate line SGD2 in the third operation, and the selection is performed in the fourth operation. The voltage VSD is applied to the gate line SGD3. In the second to fourth operations, the voltage VPGM is applied to the selected word line WL0, and the voltage VPASS is applied to the non-selected word lines WL1 to WL3.

  Next, in the fifth and sixth operations, the selection gate line SGD0 is selected, and the word lines WL1 and WL0 are sequentially selected. More specifically, in the fifth operation, the voltage VSD is applied to the selected gate line SGD0, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. Is done. In the sixth operation, the voltage VSD is applied to the selected gate line SGD0, the voltage VPGM is applied to the selected word line WL0, and the voltage VPASS is applied to the unselected word lines WL1 to WL3.

  Next, in the seventh to twelfth operations, the selection gate lines SGD1 to SGD3 are sequentially selected in the same procedure as the fifth and sixth write operations. More specifically, in the seventh operation, the voltage VSD is applied to the selected gate line SGD1, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. Is done. In the eighth operation, the voltage VSD is applied to the selected gate line SGD1, the voltage VPGM is applied to the selected word line WL0, and the voltage VPASS is applied to the unselected word lines WL1 to WL3. In the ninth operation, the voltage VSD is applied to the selected gate line SGD2, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. In the tenth operation, the voltage VSD is applied to the selected gate line SGD2, the voltage VPGM is applied to the selected word line WL0, and the voltage VPASS is applied to the unselected word lines WL1 to WL3. In the eleventh operation, the voltage VSD is applied to the selected gate line SGD3, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. In the twelfth operation, the voltage VSD is applied to the selected gate line SGD3, the voltage VPGM is applied to the selected word line WL0, and the voltage VPASS is applied to the unselected word lines WL1 to WL3.

  In the thirteenth to twentieth operations, the selection gate line SGD1 is selected in the thirteenth and fourteenth operations, the selection gate line SGD2 is selected in the fifteenth and sixteenth operations, and the seventeenth and eighteenth operations. The selection gate line SGD3 is selected by the operation, and the selection gate line SGD0 is selected by the nineteenth and twentieth operations. In the thirteenth, fifteenth, seventeenth, and nineteenth operations, the word line WL2 is selected, and in the fourteenth, sixteenth, eighteenth, and twentieth operations, the word line WL1 is selected. . More specifically, in the thirteenth operation, the voltage VSD is applied to the selected gate line SGD1, the voltage VPGM is applied to the selected word line WL2, and the voltage VPASS is applied to the unselected word lines WL0, WL1, and WL3. Is done. In the fourteenth operation, the voltage VSD is applied to the selected gate line SGD1, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. In the fifteenth operation, the voltage VSD is applied to the selected gate line SGD2, the voltage VPGM is applied to the selected word line WL2, and the voltage VPASS is applied to the unselected word lines WL0, WL1, and WL3. In the sixteenth operation, the voltage VSD is applied to the selected gate line SGD2, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. In the seventeenth operation, the voltage VSD is applied to the selected gate line SGD3, the voltage VPGM is applied to the selected word line WL2, and the voltage VPASS is applied to the unselected word lines WL0, WL1, and WL3. In the eighteenth operation, the voltage VSD is applied to the selected gate line SGD3, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3. In the nineteenth operation, the voltage VSD is applied to the selected gate line SGD0, the voltage VPGM is applied to the selected word line WL2, and the voltage VPASS is applied to the unselected word lines WL0, WL1, and WL3. In the twentieth operation, the voltage VSD is applied to the selected gate line SGD0, the voltage VPGM is applied to the selected word line WL1, and the voltage VPASS is applied to the unselected word lines WL0, WL2, and WL3.

  In the 21st to 28th operations, the selection gate line SGD2 is selected in the 21st and 22nd operations, the selection gate line SGD3 is selected in the 23rd and 24th operations, and the 25th and 26th operations are selected. The selection gate line SGD0 is selected by the operation, and the selection gate line SGD1 is selected by the 27th and 28th operations. In the twenty-first, twenty-second, twenty-third, and twenty-fifth operations, the word line WL3 is selected, and in the twenty-second, twenty-fourth, twenty-sixth, and twenty-eighth operations, the word line WL2 is selected. More specifically, in the 21st operation, the voltage VSD is applied to the selected gate line SGD2, the voltage VPGM is applied to the selected word line WL3, and the voltage VPASS is applied to the unselected word lines WL0 to WL2. In the twenty-second operation, the voltage VSD is applied to the selected gate line SGD2, the voltage VPGM is applied to the selected word line WL2, and the voltage VPASS is applied to the unselected word lines WL0, WL1, and WL3. Thereafter, in the same procedure, the voltage VSD is applied to the selected selection gate line SGD, the voltage VPGM is applied to the selected word line WL, and the voltage VPASS is applied to the unselected word line WL.

1.3.6 Voltage of Selected Word Line in First and Second Write Operations Next, an example of the voltage of the selected word line WL in the first and second write operations will be described. FIG. 15 shows voltages applied to the selected word line WL in the first and second write operations.

  As shown in FIG. 15, after receiving the first command set, in the first write period tProg1, first, the row decoder 16 applies the voltage Vpgm1 to the selected word line WL. The voltage Vpgm1 is the program voltage VPGM in the first write operation. When the voltage Vpgm1 is applied to the selected word line WL, the threshold voltage of the “0” programmed memory cell transistor MT connected to the selected word line WL rises, and the “1” programmed memory cell transistor MT threshold The voltage hardly rises. Next, the row decoder 16 applies the voltage Vvfy. The voltage Vvfy is a verify voltage, for example, the voltage VM1 shown in FIG.

  The above-described operation of applying the program voltage and the verify voltage corresponds to one program loop. Such a program loop is repeated by increasing the value of the program voltage by ΔVpgm1. The value of the voltage Vvfy applied in each program loop is changed to, for example, the voltage VM2 or VM3 with the progress of the first write operation. A plurality of types of verify voltages may be used in one program loop. For example, when the sequencer 14 passes verification by the voltage VMF, the sequencer 14 ends the first write operation and sets the ready / busy signal RBn to the “H” level.

  Next, after receiving the second command set, in the second write period tProg2, the row decoder 16 applies the voltage Vpgm2 to the selected word line WL as in the first write period tProg1. The voltage Vpgm2 is the program voltage VPGM in the second write operation. Next, the row decoder 16 applies the voltage Vvfy. For example, the row decoder 16 applies the voltage V1 shown in FIG. 6 to the selected word line WL as the voltage Vvfy. Such a program loop is repeated by increasing the value of the program voltage by ΔVpgm2 until the verify is passed. The voltage Vpgm2 is smaller than the voltage Vpgm1, and ΔVpgm2 is smaller than ΔVpgm1. As described above, in the second write operation, the threshold voltage of the memory cell transistor MT is finely controlled by using a program voltage smaller than the first write operation and ΔVpgm. For this reason, the second writing period tProg2 tends to be longer than the first writing period tProg1.

1.4 Effects According to this Embodiment With the configuration according to this embodiment, the reliability of the semiconductor memory device can be improved. This effect will be described in detail.

  The threshold voltage of the memory cell transistor MT to which data has been written may vary due to disturbance during a write operation to an adjacent memory cell transistor MT or a write operation to another string unit SU.

  On the other hand, in the configuration according to the present embodiment, the multi-bit write operation is divided into two times, and first, the first write operation is performed on the memory cell transistors MT connected to the word line WLi. After the first write operation is performed on the memory cell transistor MT connected to WL (i + 1), the second write operation can be performed on the memory cell transistor MT connected to the word line WLi. As a result, even if the memory cell transistor MT connected to the word line WLi receives a disturbance due to the first write operation to the memory cell transistor MT connected to the adjacent word line WL (i + 1), the subsequent second write Since the operation is precisely written, the influence of disturbance can be suppressed.

  Focusing on the threshold voltage of “0” level (erase level) data, the threshold voltage of “M0” level data of the memory cell transistor MT on which the first write operation has been executed is influenced by the “1” program. The threshold voltage of the “ER” level data of the memory cell transistor MT that has not reached the “1” level but is not performing the first write operation is slightly increased. For this reason, the memory cell transistor MT in which the first write operation is performed has a fail bit of “0” level due to disturbance from other string units SU than the memory cell transistor MT in which the first write operation is not performed. That is, a shift from the “0” level to the “1” level is likely to occur. FIG. 16 shows the relationship between the data write order and the disturbance from the second write operation of the other string unit SU. FIG. 16 shows the selection order of the string units SU on the word lines WL0 and WL1, and the selection order is the same as FIG.

  As shown in FIG. 16, when focusing on the memory cell group MCG connected to the word line WL1 of the string unit SU0, after the first write operation is executed (fifth), the first word line WL1 is selected. The write operation and the second write operation in which the word line WL0 is selected are executed in the order of the string units SU1, SU2, and SU3. Accordingly, the memory cell group MCG connected to the word line WL1 of the string unit SU0 is affected three times by the disturb by the second write operation of the other string unit SU that has selected the word line WL0. Similarly, the memory cell group MCG connected to the word line WL1 of the string unit SU1 is affected twice by the disturbance. The memory cell group MCG connected to the word line WL1 of the string unit SU2 is affected once by the disturb. The memory cell group MCG connected to the word line WL1 of the string unit SU3 is affected zero times by the disturbance. Thus, according to the selection order of the string units SU that perform the first write operation on the word line WL (i + 1), in other words, according to the selection order of the string units SU that execute the second write operation on the word line WLi. The amount of fluctuation of the threshold voltage due to disturbance is different. As the number of times of disturbance is increased, the threshold voltage rises, and therefore the number of fail bits tends to increase.

  For example, in each word line WL, when the string unit SU that performs the first write operation and the second write operation is selected in the order of the string units SU0, SU1, SU2, and SU3, the string unit SU0 has a “0” level. Fail bits are concentrated. If the number of fail bits increases to such an extent that it cannot be relieved by the ECC processing, erroneous reading occurs, and the reliability of data reading deteriorates.

  On the other hand, with the configuration according to the present embodiment, the selection order of the string units SU that execute the first and second write operations can be shifted for each word line WL. As a result, the number of disturbances received from other string units SU can be leveled. A specific example is shown in FIG. FIG. 17 shows the second write operation in the memory cell group MCG of another string unit SU to which the next lower word line WL is connected for each memory cell group MCG in the data write sequence described in FIG. Indicates the number of disturbances received.

  As shown in FIG. 17, focusing on the word lines WL1 to WL4, by shifting the selection order of the string units SU that execute the first and second write operations, the number of times of disturbance is not affected by the string units SU. 6 times, it can be seen that the influence of disturbance is leveled. The same applies to the other word lines WL.

  Thus, the number of fail bits of “0” level data in each string unit SU can be leveled. Accordingly, there is a high possibility that the fail bit can be relieved by the ECC processing, and erroneous reading can be suppressed. Therefore, the reliability of the semiconductor memory device can be improved.

2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, three examples of the selection order of string units SU different from the first embodiment will be described. Only differences from the first embodiment will be described below.

2.1 First Example First, a first example of the second embodiment will be described with reference to FIG.

  As shown in FIG. 18, it is assumed that a certain word line group WG includes word lines WLi to WL (i + 3). Then, in the case of the word line WLi, the second writing is executed in the order of the string units SU0, SU1, SU2, SU3. In the case of the word line WL (i + 1), the first string unit SU is shifted from the string unit SU0 to the string unit SU3, and the second write is executed in the order of the string units SU3, SU0, SU1, SU2. In the case of the word line WL (i + 2), the first string unit SU is shifted from the string unit SU3 to the string unit SU2, and the second write is executed in the order of the string units SU2, SU3, SU0, SU1. In the case of the word line WL (i + 3), the first string unit SU is shifted from the string unit SU2 to the string unit SU1, and the second write is executed in the order of the string units SU1, SU2, SU3, SU0.

2.2 Second Example Next, a second example of the second embodiment will be described with reference to FIG.

  As shown in FIG. 19, it is assumed that a certain word line group WG includes word lines WLi to WL (i + 3). Then, in the case of the word line WLi, the second writing is executed in the order of the string units SU0, SU1, SU2, SU3. In the case of the word line WL (i + 1), the first string unit SU is shifted from the string unit SU0 to the string unit SU2, and the second writing is executed in the order of the string units SU2, SU3, SU0, SU1. In the case of the word line WL (i + 2), the first string unit SU is shifted from the string unit SU2 to the string unit SU3, and the second writing is executed in the order of the string units SU3, SU0, SU1, and SU2. In the case of the word line WL (i + 3), the first string unit SU is shifted from the string unit SU3 to the string unit SU1, and the second write is executed in the order of the string units SU1, SU2, SU3, SU0.

2.3 Third Example Next, a third example of the second embodiment will be described with reference to FIG. In the third example, a case where a combination of selection orders of a plurality of string units SU is used will be described.

  As shown in FIG. 20, the selection order of the string units SU described in the first example is applied to a certain word line group WGj (j is an arbitrary integer), and the second order is applied to the word line group WG (j + 1). The selection order of the string units SU described in the example is applied.

  The combination of the selection order of the plurality of string units SU can be arbitrarily changed. For example, the selection order of the string units SU described in the first embodiment may be combined with the selection order of the string units SU described in the first example.

2.4 Effects according to the present embodiment The configuration according to the present embodiment provides the same effects as those of the first embodiment.

  Note that the selection order of the string units SU is not limited to the first and second embodiments. In one word line group WG, any string unit SU can be arbitrarily set as long as it is selected in the order of the first, second, third and fourth times.

  Further, the selection order of each string unit SU is not changed in units of word line groups WG, but the number of times each string unit SU is selected through writing to all word lines (for example, word lines WL0 to WL95) is equalized. It may be made to be.

3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a data reading order when one block BLK is divided into a lower block BLK and an upper block BLK for use will be described. Only differences from the first and second embodiments will be described below.

3.1 Data Write Order The data write order will be described with reference to FIG. In the present embodiment, a group of memory cell transistors MT connected to the word lines WL0 to WL47 is referred to as a lower block BLK, and a group of memory cell transistors MT connected to the word lines WL48 to 95 is referred to as an upper block BLK. The controller 20 independently manages data write operations in the lower block BLK and the upper block BLK.

  As shown in FIG. 21, when writing data to the lower block BLK, the sequencer 14 writes data from the word line WL47 toward the word line WL0.

  More specifically, the sequencer 14 executes a first write operation in which the word line WL47 is selected and the string units SU0 to SU3 are sequentially selected as the first to fourth operations in the lower block BLK.

  Next, the sequencer 14 selects the string unit SU0 as the fifth and sixth operations, and executes the first write operation that selects the word line WL46 and the second write operation that selects the word line WL47. To do. The sequencer 14 selects the string units SU1 to SU3 in order as the seventh to twelfth operations, and selects the word line WL46 in the same procedure as the fifth and sixth operations. And the second write operation in which the word line WL47 is selected are executed alternately.

  Next, the sequencer 14 selects the first write operation and the word line WL46 that select the word line WL45 for each string unit SU as the 13th to 20th operations, as in the 5th to 12th operations. The second write operation is executed alternately. In the thirteenth to twentieth operations, the string units SU1, SU2, SU3, and SU0 are selected in order. That is, the string unit SU selected first is shifted from SU0 to SU1.

  Next, the sequencer 14 executes the 21st to 28th operations in which the word lines WL44 and WL45 are selected, similarly to the 5th to 12th operations. In the 21st to 28th operations, the string units SU2, SU3, SU0, and SU1 are selected in order. That is, the string unit SU selected first is shifted from SU1 to SU2.

  Next, the sequencer 14 executes the 29th to 36th operations in which the word lines WL43 and WL43 are selected, similarly to the 5th to 12th operations. In the 29th to 36th operations, the string units SU3, SU0, SU1, and SU2 are selected in order. That is, the string unit SU selected first is shifted from SU2 to SU3.

  Similarly, in the 37th to 44th operations in which the word lines WL42 and WL43 are selected, the sequencer 14 first selects the string unit SU0, and in the 45th to 52nd operations in which the word lines WL41 and WL42 are selected, First, the string unit SU1 is selected. The same applies to the subsequent processing.

  As described above, the sequencer 14 performs a write operation based on the address information ADD and data DAT transmitted from the controller 20.

  That is, when the controller 20 causes the sequencer 14 to perform a write operation, the string unit SU that is first subjected to the second write operation is moved from the word line WL47 toward the word line WL0, and the string units SU0, SU1, SU2, SU3. The page address PA is designated so as to repeatedly shift in the order of. In other words, when the controller 20 causes the sequencer 14 to perform a write operation, the string unit SU that is first subjected to the first write operation is the string units SU0, SU1, SU2 from the word line WL46 toward the word line WL0. , The page address PA is designated so as to repeatedly shift in the order of SU3.

  Further, when writing data to the upper block BLK, the sequencer 14 writes data from the word line WL48 toward the word line WL95. The data writing order is the same as in FIG. 11 of the first embodiment, and the word line WL48 in FIG. 21 corresponds to the word line WL0 in FIG.

3.2 Effects according to the present embodiment The configuration according to the present embodiment can provide the same effects as those of the first embodiment.

  Note that the selection order of the string units SU described in the second embodiment may be applied to the lower block BLK and the upper block BLK.

4). Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, first and second write operations different from the first embodiment will be described. Only differences from the first to third embodiments will be described below.

4.1 Threshold Distribution of Memory Cell Transistor MT First, the threshold distribution of the memory cell transistor MT will be described with reference to FIG. In the present embodiment, a case where coding different from that of the first embodiment is applied will be described.

  As shown in FIG. 22, data is allocated to “Lower bit / Middle bit / Upper bit / Top bit” as shown below for the memory cell transistors MT included in each level.

  The memory cell transistor MT included in the “0” level holds “1111” data. The memory cell transistor MT included in the “1” level holds “1110” data. The memory cell transistor MT included in the “2” level holds “1100” data. The memory cell transistor MT included in the “3” level holds “1101” data. The memory cell transistor MT included in the “4” level holds “1001” data. The memory cell transistor MT included in the “5” level holds “1000” data. The memory cell transistor MT included in the “6” level holds “1010” data. The memory cell transistor MT included in the “7” level holds “1011” data. The memory cell transistor MT included in the “8” level holds “0011” data. The memory cell transistor MT included in the “9” level holds “0010” data. The memory cell transistor MT included in the “A” level holds “0000” data. The memory cell transistor MT included in the “B” level holds “0001” data. The memory cell transistor MT included in the “C” level holds “0101” data. The memory cell transistor MT included in the “D” level holds “0100” data. The memory cell transistor MT included in the “E” level holds “0110” data. The memory cell transistor MT included in the “F” level holds “0111” data.

  When reading the data allocated in this way, the Lower bit is determined by the read operation 8R. The Middle bit is determined by the read operation 4R and CR. The Upper bit is determined by the read operations 2R, 6R, AR, and ER. The Top bit is determined by the read operations 1R, 3R, 5R, 7R, 9R, BR, DR, and FR. That is, the values of the Lower bit, the Middle bit, the Upper bit, and the Top bit are determined by the read operation once, twice, four times, and eight times, respectively. Hereinafter, this data allocation is referred to as “1-2-4-8 code”.

4.2 First and Second Write Operations Next, the write operation of this embodiment will be described. In the present embodiment, the 4-page data write operation is executed in two steps: a first write operation for writing a Lower page and a Middle page, and a second write operation for writing an Upper page and a Top page.

  First, the first write operation will be described with reference to FIG.

  As shown in FIG. 23, first, the sequencer 14 executes a first write operation based on the Lower page data and the Middle page data input from the controller 20.

  More specifically, the sequencer 14 uses the voltages VM1, VM2, and VM3 as verify voltages. The voltage VM1 is used when writing “10” (“Lower bit / Upper bit”) data, and is equal to or higher than the voltage V1 and lower than the voltage V5. The voltage VM2 is a verify voltage used when writing “00” data, and is equal to or higher than the voltage V5 and lower than the voltage V9. The voltage VM3 is a verify voltage used when writing “01” data, and is equal to or higher than the voltage V9 and lower than the voltage VD.

  When the first write operation is executed, the threshold voltage of the memory cell transistor MT rises based on the write data, and four threshold distributions are formed. The “M0” level shown in FIG. 23 is formed by a plurality of memory cell transistors MT into which “11” data is written. The “M1” level is formed by a plurality of memory cell transistors MT into which “10” data is written. The “M2” level is formed by a plurality of memory cell transistors MT into which “00” data is written. The “M3” level is formed by a plurality of memory cell transistors MT into which “01” data is written.

  The threshold voltage at the “M0” level is less than the voltage V1. The threshold voltage at the “M1” level is equal to or higher than the voltage VM1 and lower than the voltage V5. The threshold voltage at the “M2” level is equal to or higher than the voltage VM2 and lower than the voltage V9. The threshold voltage at the “M3” level is equal to or higher than the voltage VM3 and lower than the voltage VD.

  Next, the second write operation will be described with reference to FIG.

  As shown in FIG. 24, first, the sequencer 14 reads data of Lower page data and Middle page data read from the memory cell array 11, that is, “11” data, “10” data, “00” data, and “01”. The second write operation is executed based on the data and the upper page data and top page data input from the controller 20.

  In the second write operation, for example, “0” level, “1” level, “2” level, and “3” level threshold distributions are formed from the “M0” level threshold distribution. A threshold distribution of “4” level, “5” level, “6” level, and “7” level is formed from the threshold distribution of “M1” level. A threshold distribution of “8” level, “9” level, “A” level, and “B” level is formed from the threshold distribution of “M2” level. The threshold distribution of “C” level, “D” level, “E” level, and “F” level is formed from the threshold distribution of “M3” level.

4.3 Effects according to the present embodiment The configuration according to the present embodiment provides the same effects as those of the first embodiment.

5. Fifth Embodiment Next, a fifth embodiment will be described. In the fifth embodiment, a case where 4-page data is written by three writing operations will be described. Only differences from the first to fourth embodiments will be described below.

5.1 First to Third Write Operations First, the write operation of this embodiment will be described. In the present embodiment, four page data is written by “8” level, “9” level, “A” level, “B” level, “C” level, “D” level, “E” level, and “F”. The first write operation for temporarily writing to a level lower than the “8” level and the rough write operation (first write operation in the first embodiment) described in the first embodiment for the memory cell transistor MT to be written to the “level”. The second write operation to be performed and the third write operation to perform the precise write operation described in the first embodiment (the second write operation in the first embodiment) are divided into three times.

  First, the first write operation will be described with reference to FIG. FIG. 25 shows changes in the threshold distribution of the memory cell transistor MT due to the first write operation.

  As shown in FIG. 25, the sequencer 14 executes the first write operation based on the LM data input from the controller 20.

  More specifically, the controller 20 includes “1111” data, “0111” data, “0101” data, “0001” data, “1001” data, “1000” data, “0000” data, and “0100” data. Is “0” data, and “0110” data, “0010” data, “0011” data, “1011” data, “1010” data, “1110” data, “1100” data, and “1101” data are “1”. “LM data as data is created and transmitted to the semiconductor memory device 10. Note that when the 4-page data is a 1-2-4-8 code, the controller 20 may transmit the Lower page data.

  In the first write operation, the sequencer 14 uses the voltage VLM as the verify voltage. The voltage VLM is, for example, not less than the voltage V5 and less than the voltage VM8.

  When the first write operation is executed, the threshold voltage of the memory cell transistor MT rises based on the write data, and two threshold distributions are formed. The “LM0” level shown in FIG. 26 is formed by a plurality of memory cell transistors MT corresponding to “1” data. The “LM1” level is formed by a plurality of memory cell transistors MT corresponding to “0” data.

  The threshold voltage at the “LM0” level is less than the voltage V1. The threshold voltage at the “LM1” level is equal to or higher than the voltage VLM and lower than the voltage V8.

  Next, the second write operation will be described with reference to FIG. FIG. 26 shows a change in the threshold distribution of the memory cell transistor MT due to the second write operation.

  As shown in FIG. 26, the second write operation is the same as the coarse write operation described in the first embodiment (the first write operation of the first embodiment). The difference from the first embodiment is that in the first embodiment, the threshold distribution of each level is formed from the threshold distribution of the “ER” level. On the other hand, in the present embodiment, for example, from the threshold distribution of “LM0” level, “M0” level, “M1” level, “M2” level, “M3” level, “M4” level, “M5” level, “M6” level and “M7” level threshold distributions are formed. From the “LM1” level threshold distribution, “M8” level, “M9” level, “MA” level, “MB” level, “MC” level, Threshold distributions of “MD” level, “ME” level, and “MF” level are formed.

  Next, the third write operation will be described with reference to FIG. FIG. 27 shows changes in the threshold distribution of the memory cell transistor MT due to the third write operation.

  As shown in FIG. 27, the third write operation is the same as the precise write operation (second write operation of the first embodiment) described in the first embodiment.

5.2 Data Write Order Next, the data write order will be described with reference to FIG. FIG. 28 shows the selection order of string units SU in one block BLK. The solid square boxes in the upper, middle, and lower three levels separated by the broken line corresponding to the word line WL and the string unit SU indicate one memory cell group MCG, and the upper stage of the square frame indicates the third write operation (see Symbol “WRT3”) indicates that the interruption of the square frame indicates the second writing operation (reference symbol “WRT2”), and the lower part of the square frame indicates the first writing operation (reference symbol “WRT1”).

  As shown in FIG. 28, the sequencer 14 performs the first write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected as the first to fourth operations.

  Next, as the fifth to ninth operations, the sequencer 14 selects the string unit SU0, selects the word line WL1, the second write operation selects the word line WL0, A first write operation in which the line WL2 is selected, a second write operation in which the word line WL1 is selected, and a third write operation in which the word line WL0 is selected are executed.

  Next, the sequencer 14 selects the string units SU1 to SU3 in order as the 10th to 24th operations, and selects the word line WL1 in the same procedure as the 5th to 9th operations. Write operation, second write operation selecting word line WL0, first write operation selecting word line WL2, second write operation selecting word line WL1, and third write operation selecting word line WL0 And repeatedly. That is, when focusing on the word line WL0, the string unit SU0 is selected as the string unit SU on which the third write is executed first.

  Next, the sequencer 14 selects the string unit SU1, selects the word line WL3, the second write operation selects the word line WL2, and the word operations as the 25th to 27th operations, The third write operation with the line WL1 selected is executed.

  Next, the sequencer 14 sequentially selects the string units SU2, SU3, and SU0 as the 28th to 36th operations, and selects the word line WL3 in the same procedure as the 25th to 27th operations. One write operation, a second write operation in which the word line WL2 is selected, and a third write operation in which the word line WL1 is selected are repeatedly executed. That is, in the word line WL1, the string unit SU that is initially selected for the third write operation is shifted from SU0 to SU1.

  Next, the sequencer 14 selects the word lines WL4, WL3, and WL2 and executes the 37th to 48th operations as in the 25th to 36th operations. In the 37th to 48th operations, the string units SU2, SU3, SU0, and SU1 are selected in order. That is, in the word line WL2, the string unit SU that is initially selected for the third write operation is shifted from SU1 to SU2.

  Next, the sequencer 14 selects the word lines WL5, WL4, and WL3 and executes the 49th to 60th operations as in the 25th to 36th operations. In the 49th to 60th operations, the string units SU3, SU0, SU1, and SU2 are selected in order. That is, in the word line WL3, the string unit SU that is initially selected for the third write operation is shifted from SU2 to SU3.

  Next, the sequencer 14 selects the word lines WL6, WL5, and WL4 and executes the 61st to 72nd operations as in the 25th to 36th operations. In the 61st to 71st operations, the string units SU0, SU1, SU2, and SU3 are selected in order. That is, in the word line WL4, the string unit SU that is initially selected for the third write operation is shifted from SU3 to SU0. The same applies to the subsequent processing.

  That is, the sequencer 14 repeatedly shifts the string unit SU that first executes the third write operation from the word line WL0 toward the word line WL95 in the order of the string units SU0, SU1, SU2, and SU3. In other words, the sequencer 14 repeatedly shifts the string unit SU that first executes the second write operation from the word line WL2 toward the word line WL95 in the order of the string units SU0, SU1, SU2, and SU3. Alternatively, the string unit SU that first executes the first write operation from the word line WL3 toward the word line WL95 is repeatedly shifted in the order of the string units SU0, SU1, SU2, and SU3.

  Therefore, similarly to FIG. 11 of the first embodiment, the cycle of the selected string unit SU is repeated for every four word lines WL corresponding to the four string units SU. In the example of FIG. 28, focusing on the order of the string units SU on which the third write operation is first executed, the four word lines WL0 to WL3 are set as the word line group WG0. The same applies to the subsequent word lines WL.

5.3 Effects according to the present embodiment The configuration according to the present embodiment provides the same effects as those of the first embodiment.

  In the present embodiment, the second and third embodiments may be applied as the selection order of the string units SU.

  Further, when the memory cell transistor MT is compatible with TLC that holds 3-bit data, the first write operation, the second write operation, and the third write operation in the present embodiment are performed on the lower page write, respectively. The so-called “page-by-page” writing may be performed in correspondence with the operation, the Middle page writing operation, and the Upper page writing operation. Even in this case, the first write operation, the second write operation, and the third write operation are executed in the order shown in FIG. That is, the string unit SU that first executes the Upper page write operation (third write operation) from the word line WL0 toward the word line WL95 is repeatedly shifted in the order of the string units SU0, SU1, SU2, and SU3. . In other words, the string unit SU that first performs the Middle page write operation (second write operation) from the word line WL2 toward the word line WL95 is repeatedly shifted in the order of the string units SU0, SU1, SU2, and SU3. Is done. Alternatively, the string unit SU that first executes the lower page write operation (first write operation) from the word line WL3 toward the word line WL95 is repeatedly shifted in the order of the string units SU0, SU1, SU2, and SU3.

6). Sixth Embodiment Next, a sixth embodiment will be described. The difference from the first embodiment is that in the sixth embodiment, among the memory cell transistors MT0 to MT95 included in the NAND string NS, the memory cell transistors MT0 and MT95 arranged at both ends hold 1-bit data. (Single level cell), and the other memory cell transistors MT1 to MT94 correspond to QLC. Only differences from the first to fifth embodiments will be described below.

6.1 Data Write Order The data write order will be described with reference to FIG. FIG. 29 shows the selection order of string units SU in one block BLK. A solid square frame corresponding to the word line WL and the string unit SU indicates one memory cell group MCG. Since the memory cell group MCG connected to the word lines WL0 and WL95 can hold one page data, data is written by one write operation. Data is written in the memory cell group MCG connected to the word lines WL1 to WL94 by two write operations. For this reason, the square frames representing the memory cell groups MCG are divided vertically by a broken line, the upper stage shows the second write operation, and the lower stage shows the first write operation. In the example of FIG. 29, the write number of the data written last in the block BLK is represented by k (k = 760) for simplification of description.

  As shown in FIG. 29, the sequencer 14 performs a one-page data write operation in which the word line WL0 is selected and the string units SU0 to SU3 are sequentially selected as the first to fourth operations.

  Next, the sequencer 14 executes a first write operation that selects the word line WL0 and sequentially selects the string units SU0 to SU3 as the fifth to eighth operations.

  Next, the sequencer 14 selects the string unit SU0 as the ninth and tenth operations, and executes the first write operation that selects the word line WL2 and the second write operation that selects the word line WL1. To do. Further, the sequencer 14 sequentially selects the string units SU1 to SU3 as the 11th to 16th operations, and selects the word line WL2 in the same procedure as the 9th and 10th operations. And the second write operation in which the word line WL1 is selected are alternately executed.

  Next, the sequencer 14 selects, as the 17th to 24th operations, the first write operation that selects the word line WL3 for each string unit SU and the word line WL2, as in the 9th to 16th operations. The second write operation is executed alternately. In the 17th to 24th operations, the string units SU1, SU2, SU3, and SU0 are selected in order. That is, the string unit SU selected first is shifted from SU0 to SU1.

  Thereafter, the sequencer 14 performs the write operation while shifting the first selected string unit SU.

  Then, the sequencer 14 selects the word line WL93 for each string unit SU as the (k-23) to (k-16) th operations, as in the ninth to 16th operations. The operation and the second write operation in which the word line WL92 is selected are alternately executed. In the (k-23) to (k-16) th operations, the string units SU3, SU0, SU1, and SU2 are selected in order.

  Next, the sequencer 14 selects the word line WL94 for each string unit SU as the (k-15) th to (k-8) th operations, as in the ninth to sixteenth operations. The write operation and the second write operation with the word line WL93 selected are executed alternately. In the (k-15) to (k-8) th operations, the string units SU0, SU1, SU2, and SU3 are selected in order.

  Next, the sequencer 14 performs, as (k-7) to k-th operations, a one-page data write operation in which the word line WL95 is selected for each string unit SU and a second write operation in which the word line WL94 is selected. Execute alternately. In the (k-7) to k-th operations, the string units SU1, SU2, SU3, and SU0 are selected in order. That is, the string unit SU selected first is shifted from SU0 to SU1.

6.2 Effects according to the present embodiment The configuration according to the present embodiment provides the same effects as those of the first embodiment.

  Furthermore, with the configuration according to the present embodiment, the memory cell transistors MT0 and MT95 located at both ends of the NAND string NS support 1-bit data writing, thereby suppressing erroneous reading in these memory cell transistors MT. The reliability of the read operation can be improved.

  In the sixth embodiment, the memory cell transistors MT0 and MT95 arranged at both ends of the NAND string NS are SLC, and the other memory cell transistors MT1 to MT94 are QLC. However, the present invention is not limited to this. Not. The number of data bits that can be held by the memory cell transistors MT0 and MT95 arranged at both ends of the NAND string NS is larger than the number of data bits that can be held by the other memory cell transistors MT1 to MT94. As long as it is kept small. For example, if the memory cell transistors MT1 to MT94 are QLC, the memory cell transistors MT0 and MT95 may be MLC or TLC, not SLC.

  Furthermore, in the present embodiment, the second to fifth embodiments may be applied.

7). Seventh Embodiment Next, a seventh embodiment will be described. In the seventh embodiment, the case where the memory cell transistors MT0, MT47, MT48, and MT95 arranged at both ends in each of the upper block BLK and the lower block BLK in the third embodiment are SLC will be described. Only differences from the first to sixth embodiments will be described below.

7.1 Data Write Order The data write order will be described with reference to FIG. In the example of FIG. 30, the write number of the data written last in the upper block BLK and the block BLK is represented by k (k = 376) to simplify the description.

  As shown in FIG. 30, when writing data to the lower block BLK, the sequencer 14 writes data from the word line WL47 toward the word line WL0.

  More specifically, the sequencer 14 executes a one-page data write operation in which the word line WL47 is selected and the string units SU0 to SU3 are sequentially selected as the first to fourth operations.

  Next, the sequencer 14 executes the first write operation in which the word line WL46 is selected and the string units SU0 to SU3 are sequentially selected as the fifth to eighth operations.

  Next, the sequencer 14 selects the string unit SU0 as the ninth and tenth operations, and executes the first write operation that selects the word line WL45 and the second write operation that selects the word line WL46. To do. In addition, the sequencer 14 selects the string units SU1 to SU3 in order as the 11th to 16th operations, and selects the word line WL45 in the same procedure as the 9th and 10th operations. And the second write operation with the word line WL46 selected are executed alternately.

  Next, the sequencer 14 selects, as the 17th to 24th operations, the first write operation in which the word line WL44 is selected for each string unit SU and the word line WL45, as in the 9th to 16th operations. The second write operation is executed alternately. In the 17th to 24th operations, the string units SU1, SU2, SU3, and SU0 are selected in order. That is, the string unit SU selected first is shifted from SU0 to SU1.

  Thereafter, the sequencer 14 performs the write operation while shifting the first selected string unit SU.

  Then, the sequencer 14 performs the first write operation by selecting the word line WL2 for each string unit SU as the (k-23) th to (k-16) th operations, as in the ninth to sixteenth operations. The operation and the second write operation in which the word line WL3 is selected are alternately executed. In the (k-23) to (k-16) th operations, the string units SU3, SU0, SU1, and SU2 are selected in order.

  Next, the sequencer 14 selects the word line WL1 for each string unit SU as the (k-15) th to (k-8) th operations, as in the ninth to sixteenth operations. The write operation and the second write operation in which the word line WL2 is selected are alternately executed. In the (k-15) to (k-8) th operations, the string units SU0, SU1, SU2, and SU3 are selected in order.

  Next, the sequencer 14 performs, as (k-7) to k-th operations, a one-page data write operation in which the word line WL0 is selected for each string unit SU and a second write operation in which the word line WL1 is selected. Execute alternately. In the (k-7) to k-th operations, the string units SU1, SU2, SU3, and SU0 are selected in order. That is, the string unit SU selected first is shifted from SU0 to SU1.

  Further, when writing data to the upper block BLK, the sequencer 14 writes data from the word line WL48 toward the word line WL95. The data write order is the same as that in FIG. 29 of the sixth embodiment, and the word line WL48 in FIG. 30 corresponds to the word line WL0 in FIG.

7.2 Effects according to the present embodiment The configuration according to the present embodiment provides the same effects as those of the first and sixth embodiments.

  In the seventh embodiment, the memory cell transistors MT0, MT47, MT48, and MT95 arranged at both ends of the upper block BLK and the lower block BLK are SLC, and the other memory cell transistors MT1 to MT46 and MT49 are arranged. However, the present invention is not limited to this. The number of bits of data that can be held by the memory cell transistors MT0, MT47, MT48, and MT95 arranged at both ends of each of the upper block BLK and the lower block BLK are the other memory cell transistors MT1 to MT46 and MT49. To MT94 need only be kept smaller than the number of bits of data that can be held respectively. For example, if the memory cell transistors MT1 to MT46 and MT49 to MT94 are QLC, the memory cell transistors MT0, MT47, MT48, and MT95 may be MLC or TLC, not SLC.

8). Modification The semiconductor memory device according to the above embodiment includes a first memory unit (SU0) including a first memory string (NS) having first to third memory cells (MT0 to MT2) and a first selection transistor (ST1). A second memory unit (SU1) including a second memory string (NS) having fourth to sixth memory cells (MT0 to MT2) and a second selection transistor (ST1), and seventh to ninth memory cells ( MT0 to MT2) and a third memory unit (SU2) including a third memory string (NS) having a third select transistor (ST1) and connected to the gates of the first, fourth and seventh memory cells (MT0). First word line WL0, the second word line WL1 connected to the gates of the second, fifth, and eighth memory cells MT1, and the third, sixth, and ninth memories. A third word line (WL2) connected to the gate of the cell (MT2) and a first node connected to the first to third selection transistors, respectively. To the third selection gate lines (SGD0 to SGD2) and the first to third word lines and the row decoder (16) connected to the first to third selection gate lines. The first to ninth memory cells can each hold a plurality of bits of data, and the writing operation of the plurality of bits of data includes a first writing operation and a second writing operation. In the write operation, when the second write operation is performed on any of the first, fourth, and seventh memory cells connected to the first word line, the first memory cell is selected first, and the second word line When the second write operation is performed on any one of the second, fifth, and eighth memory cells connected to the fifth memory cell, the fifth memory cell is selected first, and the third, second, and third memory cells connected to the third word line are selected. When performing the second write operation on any of the sixth and ninth memory cells, the ninth memory cell is selected first.

  By applying the embodiment, a semiconductor memory device that can improve reliability can be provided.

  In addition, embodiment is not limited to the form demonstrated above, A various deformation | transformation is possible.

  For example, in the above embodiment, the NAND flash memory may be a planar NAND flash memory in which the memory cell transistors MT are two-dimensionally arranged on the semiconductor substrate, and the three-dimensional that the memory cell transistors MT are stacked on the semiconductor substrate. A stacked NAND flash memory may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Memory system, 10 ... Semiconductor memory device, 11 ... Memory cell array, 12 ... Command register, 13 ... Address register, 14 ... Sequencer, 15 ... Driver circuit, 16 ... Row decoder, 17 ... Data register, 18 ... Sense amplifier, DESCRIPTION OF SYMBOLS 20 ... Controller, 21 ... Host interface circuit, 22 ... Built-in memory, 23 ... Processor, 24 ... Buffer memory, 25 ... ECC circuit, 26 ... NAND interface circuit, 30 ... Host apparatus.

Claims (5)

A first memory unit including a first memory string having first to third memory cells and a first select transistor;
A second memory unit including a second memory string having fourth to sixth memory cells and a second select transistor;
A third memory unit including a third memory string having seventh to ninth memory cells and a third select transistor;
A first word line connected to the gates of the first, fourth and seventh memory cells;
A second word line connected to the gates of the second, fifth and eighth memory cells;
A third word line connected to the gates of the third, sixth and ninth memory cells;
First to third selection gate lines respectively connected to the first to third selection transistors;
A row decoder connected to the first to third word lines and the first to third selection gate lines;
Each of the first to ninth memory cells can hold a plurality of bits of data,
The multi-bit data write operation includes a first write operation and a second write operation,
In the write operation, when the second write operation is performed on any of the first, fourth, and seventh memory cells connected to the first word line, the first memory cell is selected first. When performing the second write operation on any one of the second, fifth, and eighth memory cells connected to the second word line, the fifth memory cell is selected first, and the third memory cell is selected. When performing the second write operation on any of the third, sixth, and ninth memory cells connected to a word line, the ninth memory cell is selected first. Semiconductor memory device. In the write operation, the first, fourth, and seventh memory cells connected to the first word line are arranged in the order of the first memory cell, the fourth memory cell, and the seventh memory cell. The second, fifth, and eighth memory cells connected to the second word line after two write operations are performed in the order of the fifth memory cell, the eighth memory cell, and the second memory cell. The third, sixth, and ninth memory cells that have performed the second write operation and are connected to the third word line are the ninth memory cell, the third memory cell, and the sixth memory cell. The semiconductor memory device according to claim 1, wherein the second write operation is executed in the order of. The first write operation to the second memory cell and the second write operation to the first memory cell are sequentially performed;
The semiconductor memory device according to claim 1, wherein the first write operation to the sixth memory cell and the second write operation to the fifth memory cell are sequentially performed.   In the write operation, when the first write operation is performed on any of the second, fifth, and eighth memory cells connected to the second word line, the second memory cell is selected first. The sixth memory cell is selected first when performing the first write operation on any of the third, sixth, and ninth memory cells connected to the third word line. 4. The semiconductor memory device according to any one of claims 1 to 3. A memory system comprising a semiconductor memory device and a controller,
The semiconductor memory device
A first memory unit including a first memory string having first to third memory cells and a first select transistor;
A second memory unit including a second memory string having fourth to sixth memory cells and a second select transistor;
A third memory unit including a third memory string having seventh to ninth memory cells and a third select transistor;
A first word line connected to the gates of the first, fourth and seventh memory cells;
A second word line connected to the gates of the second, fifth and eighth memory cells;
A third word line connected to the gates of the third, sixth and ninth memory cells;
First to third selection gate lines respectively connected to the first to third selection transistors;
A row decoder connected to the first to third word lines and the first to third selection gate lines;
Each of the first to ninth memory cells can hold a plurality of bits of data,
The multi-bit data write operation includes a first write operation and a second write operation,
When the controller performs the second write operation on any one of the first, fourth, and seventh memory cells connected to the first word line in the write operation in the semiconductor memory device, When selecting one memory cell first and performing the second write operation on any of the second, fifth, and eighth memory cells connected to the second word line, the fifth memory cell When first selecting and performing the second write operation on any of the third, sixth, and ninth memory cells connected to the third word line, the ninth memory cell is selected first. Instructing the semiconductor storage device to write a memory system.