JP2019149197A - Method for controlling a memory system - Google Patents

Abstract

To provide a highly convenient memory system.SOLUTION: A memory system is connectable to a host. A memory system has a nonvolatile first memory and a calculation unit. The calculation unit is notified of an access pattern and a through-put by a host. The calculation unit calculates a predicted power consumption based on at least the delivered access pattern and the through-put and the capacitance information. The predicted power consumption is used for processing the access by the delivered access pattern with the delivered through-put. The capacitance information serves as an index which shows the relation between the total storage capacity and the described capacity of the first memory which are to be used to store user data.SELECTED DRAWING: Figure 9

Description

  The present embodiment relates to a method for controlling a memory system.

  For example, a plurality of memory systems are mounted on the disk array. Each disk array is required to operate with limited power.

JP 2013-200726 A

  An object of one embodiment is to provide a highly convenient memory system.

  According to one embodiment, a method for controlling a memory system includes a first step and a second step. The first step is a step of receiving an access pattern and throughput notification from the host. In the second step, a predicted power consumption that is a power consumption for processing an access according to the access pattern at the throughput is determined by using at least the access pattern and the throughput, and a user of the nonvolatile first memory included in the memory system. This is a step of calculating based on capacity information that is an index indicating the relationship between the total storage capacity available for data storage and the notation capacity.

FIG. 1 is a diagram illustrating a configuration example of a memory system according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of a NAND memory for explaining an example of parallel operation resources. FIG. 3 is a graph illustrating an example of the relationship among the access type ratio, power consumption, and performance. FIG. 4 is a graph showing an example of the relationship between continuity of access, power consumption, and performance. FIG. 5 is a graph illustrating an example of the relationship among t_prog, power consumption, and performance. FIG. 6 is a graph showing an example of the relationship between the code rate and the power consumption. FIG. 7 is a graph illustrating an example of the relationship between the code rate, power consumption, and performance. FIG. 8 is a graph showing an example of the relationship between the gear ratio and the margin ratio. FIG. 9 is a graph showing an example of the relationship between the margin rate, power consumption, and performance. FIG. 10 is a graph illustrating an example of the relationship between the junction temperature, power consumption, and performance. FIG. 11 is a graph illustrating an example of the relationship between the junction temperature, power consumption, and performance. FIG. 12 is a graph showing another example of the relationship between power consumption and performance. FIG. 13 is a sequence diagram for explaining the operation of the memory system according to the first embodiment. FIG. 14 is a diagram illustrating a mounting example of the memory system.

  Hereinafter, a memory system according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a memory system according to the first embodiment. The memory system 1 is connected to the host 2 and the power supply device 3. The power supply device 3 supplies power to the memory system 1. The memory system 1 is driven by electric power supplied from the power supply device 3. The host 2 is a computer. The computer includes, for example, a personal computer, a portable computer, a portable communication device, or a server. The memory system 1 is connected to the host 2. Any standard can be adopted as the interface standard of the communication path connecting the memory system 1 and the host 2. The host 2 can transmit an access command to the memory system 1. In addition, the host 2 can transmit a notice of access advance notice (hereinafter referred to as advance notice) to the memory system 1. The host 2 can set the maximum allowable power consumption for the memory system 1. The maximum allowable power consumption is expressed as allowable power consumption.

  The access command includes a read command or a write command. The access command includes at least an access type and an access position. The access type is read or write. The access position is specified by logical address information. The logical address information is information indicating a position in the address space mapped by the host 2 to the memory system 1. As an example, the access position is specified in the format of LBA (Logical Block Addressing). Hereinafter, the address space mapped by the host 2 to the memory system 1 is referred to as a logical address space. Information indicating a position in the logical address space is expressed as a logical address.

  The advance notice includes a throughput and an access pattern. Throughput includes bandwidth, IOPS (Input Output Per Second), or MB / s (Mega byte per second). That is, the throughput means the performance of the memory system 1. IOPS is the number of times that data can be written per second to the NAND memory 11 (described later). If the number of times of writing is possible per unit time, the unit time can be adopted as the throughput even if it is not 1 second. MB / s is a communication speed between the host 2 and the NAND memory 11. The access pattern includes the type of access, continuity of access positions in the logical address space, or various ratios of access. A pattern in the case where a plurality of access commands are issued so that access positions in the logical address space are continuous is expressed as, for example, sequential access. When reading is performed using a sequential access pattern, the pattern is represented as sequential read. When writing is performed using a sequential access pattern, the pattern is expressed as sequential write. A pattern in the case where a plurality of access commands are issued so that access positions in the logical address space are not continuous is expressed as, for example, random access. When reading is performed with a random access pattern, the pattern is expressed as random reading. When writing is performed in a random access pattern, the pattern is expressed as random writing. The continuity of access positions in the logical address space is hereinafter referred to as access continuity.

  The memory system 1 calculates power consumption for realizing the performance notified by the notice of notice. That is, the memory system 1 predicts power consumption. The calculated power consumption is expressed as predicted power consumption. In addition, the memory system 1 negotiates power consumption with the host 2 using the predicted power consumption. Here, as an example, the host 2 compares the predicted power consumption with the power consumption allocated to the memory system 1, and sets the smaller of the predicted power consumption and the power consumption allocated to the memory system 1 as the allowable power consumption. Send to. The memory system 1 operates at as high a performance as possible among the performances that can be realized by the allowable power consumption.

  The memory system 1 includes a controller 10, a NAND memory 11, and a power supply circuit 12.

  The power supply circuit 12 converts the power supplied from the power supply device 3 or supplies the power to the controller 10 and the NAND memory 11 as they are. Here, as an example, DC power is supplied from the power supply device 3. The power supply circuit 12 includes a DC-DC converter 121. The power supply circuit 12 converts the voltage of the DC power from the power supply device 3 into a voltage that can drive the controller 10 and the NAND memory 11 by the DC-DC converter 121.

  The NAND memory 11 is a memory that functions as a storage. The NAND memory 11 operates by using power supplied from the power supply circuit 12. As the storage, any type of memory other than the NAND memory can be adopted as long as it is a nonvolatile memory. For example, a NOR type flash memory can be used as the storage.

  The NAND memory 11 includes one or more memory chips each including a NAND type memory cell array. The memory cell array includes a plurality of blocks. A block is a minimum unit of erase processing for a memory cell array. Each block includes a plurality of pages. A page is a minimum unit of read processing and write processing for the memory cell array.

  The controller 10 writes data to the NAND memory 11 or reads data from the NAND memory 11 in accordance with a command from the host 2. The controller 10 includes a performance control IF 101, a resource control unit 102, an information storage unit 103, a calculation unit 104, and a temperature sensor 105. The controller 10 includes a CPU 51, a memory 52, an encoding unit 53, and a decoding unit 54.

  Although not shown in FIG. 1, the CPU 51 is connected to the calculation unit 104, performance control IF 101, resource control unit 102, information storage unit 103, and memory 52. Therefore, the performance control IF 101 is connected to the information storage unit 103 via the CPU 51. The performance control IF 101 is connected to the host 2 and the calculation unit 104. The resource control unit 102 is connected to the parallel operation resource 50 and the information storage unit 103.

  The memory 52 is, for example, a volatile memory. The memory 52 can function as a write buffer in which data is temporarily stored when data from the host 2 is written to the NAND memory 11. The memory 52 functions as a storage area for storing management information related to the memory system 1. The management information is updated on the memory 52. Further, the memory 52 can function as a storage area in which data read from the NAND memory 11 is temporarily stored. Further, the memory 52 can function as a storage area in which a program executed by the CPU 51 is loaded from a nonvolatile memory (for example, the NAND memory 11). For example, the CPU 51 executes control based on a program loaded in the memory 52.

  The CPU 51 controls the controller 10 in an integrated manner. The CPU 51 executes, for example, processing for converting a logical address into a physical address (translation processing), garbage collection control, bad block management, or margin capacity management. The garbage collection, bad block, and surplus capacity will be described later.

  As the injection of electrons into the memory cell and the extraction of electrons are repeated, the injection of electrons into the memory cell and the outflow of electrons become easier. A change in the memory cell that occurs as the injection and extraction of electrons into the memory cell are repeated is expressed as exhaustion (in the memory cell, memory cell array, block, memory chip, or NAND memory 11). As the memory cell becomes exhausted, different events occur in the data stored in the memory cell depending on whether the data is written or read. This phenomenon is expressed as an error. The encoding unit 53 encodes user data written to the NAND memory 11 for error correction. That is, the user data sent from the host 2 is written into the NAND memory 11 after encoding. As an encoding algorithm, variable length encoding is adopted. According to variable length coding, the code rate is variable. According to variable length coding, it is possible to increase the correction capability by changing the code rate to be small. The code rate is the ratio of the size of user data in a frame to the size of the frame. A frame refers to data in a unit in which error correction is performed. The correction capability is, for example, the number of bits that can be corrected. When the correction capability is fixed, the error bit rate increases as the memory cell array becomes exhausted. When the error bit rate exceeds the correction capability, the user data becomes unreadable. The CPU 51 controls the error bit rate so as not to exceed the correction capability by reducing the code rate as the memory cell array becomes exhausted.

  The decryption unit 54 decrypts the user data read from the NAND memory 11. The decryption unit 54 detects and corrects an error included in the user data read from the NAND memory 11 by decryption. The decoding unit 54 reports the error bit rate to the CPU 51. The CPU 51 changes the code rate based on the error bit rate report.

  Note that the function of the encoding unit 53 or the decoding unit 54 may be realized by the CPU 51 executing firmware. The encoding unit 53 may be configured to be able to encode a plurality of types of algorithms, and the decoding unit 54 may be configured to be able to decode a plurality of types of algorithms.

  The controller 10 adjusts the performance of the memory system 1. In the first embodiment, the controller 10 includes a plurality of resources (parallel operation resources 50) that can be operated in parallel. The performance is adjusted by the resource control unit 102 changing the number of parallel operation resources 50 (the number of parallel operations) to be operated in parallel among the plurality of parallel operation resources 50.

The parallel operation resource 50 is a component constituting the memory system 1 or a program constituting software. The parallel operation resource 50 is, for example, the following (1) to (4).
(1) A component or program that performs information processing between the memory system 1 and the host 2 (2) A component or program that performs information processing between the controller 10 and the NAND memory 11 (3) Information processing within the controller 10 Parts or programs to be performed (4) Parts or programs to perform information processing in the NAND memory 11

  In the present embodiment, the parallel operation resource 50 will be described as the CPU 51, the memory 52, the encoding unit 53, the decoding unit 54, the NAND memory 11, or the like. Each example of the parallel operation resource 50 will be specifically described.

  FIG. 2 is a diagram illustrating a configuration example of the NAND memory 11 according to the first embodiment for describing an example of the parallel operation resource 50. The NAND memory 11 is connected in parallel to the controller 10 via eight channels (8ch: ch0 to ch7). The memory system 1 can operate the eight channel elements 11a to 11h in parallel by controlling each channel in parallel. Note that the number of channels in the NAND memory 11 is not limited to eight. Each channel corresponds to a parallel operation resource 50. The controller 10 can control the number of channel elements operated in parallel as the number of parallel operations. For example, the encoding unit 53 may be configured to execute encoding of user data independently for each channel element. In other words, the encoding unit 53 simultaneously performs encoding of a plurality of user data having different write destination channel elements. Further, the decoding unit 54 may be configured to execute decoding of user data independently for each channel element. That is, the decryption unit 54 simultaneously decrypts a plurality of user data having different read source channel elements.

  Each channel element 11a to 11h includes a plurality of banks (in this case, four banks, Bank0 to Bank3). Each bank includes a plurality of memory chips (in this case, two memory chips, Chip0, Chip1). The controller 10 can operate up to four banks in a bank interleave manner. Bank interleaving is a method in which the controller 10 issues an access command to another bank while one or more memory chips belonging to one bank are accessing the memory cell array. By bank interleaving, the total processing time between the NAND memory 11 and the controller 10 can be shortened. Each bank corresponds to a parallel operation resource 50. The controller 10 can control the number of banks operated in the bank interleave method as the number of parallel operations.

  The memory cell array of each memory chip is divided into two regions (District) in total, for example, plane 0 and plane 1. Each of plane 0 and plane 1 includes a plurality of blocks. The plane 0 and the plane 1 include peripheral circuits independent of each other (for example, a row decoder, a column decoder, a page buffer, a data cache, etc.). The controller 10 can execute erase processing / write processing / read processing on each plane simultaneously. That is, the controller 10 can operate the plane 0 and the plane 1 in parallel. The memory cell array of each memory chip may be divided into three or more districts or may not be divided at all. Each plane corresponds to the parallel operation resource 50. The controller 10 can control the number of planes operated simultaneously as the number of parallel operations.

  The CPU 51 may be configured by a plurality of processors, for example. In that case, each processor corresponds to the parallel operation resource 50. The controller 10 can control the number of processors operated simultaneously as the number of parallel operations.

  Further, the CPU 51 can execute the translation process independently in each of the plurality of processes. A process is a unit of processing realized based on a program. A process is sometimes expressed as a task. For example, the CPU 51 can divide the logical address space into a plurality of parts, and can cause different processes to execute the translation processing for the divided parts of the logical address space. Each process that executes the translation processing corresponds to the parallel operation resource 50. The controller 10 can control the number of processes operated simultaneously as the number of parallel operations. Note that processing other than translation processing may be executed in each of the plurality of processes.

  In addition, the memory 52 may include a plurality of unit areas configured such that power can be individually supplied / stopped. Each unit area corresponds to the parallel operation resource 50. The controller 10 can control the number of unit areas to which power is supplied as the number of parallel operations.

  The number of parallel operations may be a combination of some or all of the examples described above. For example, a combination of the number of channels operated in parallel, the number of banks operated in a bank interleaving manner, and the number of planes operated simultaneously may be controlled as the number of parallel operations. The combination is, for example, a solution by an arbitrary calculation. For example, the operation is multiplication. In addition, the number of parallel operations may be expressed as a numerical sequence that includes each of some or all of the examples described above as elements. In the case where the number of parallel operations is expressed in a numerical sequence, changing the number of parallel operations means changing part or all of the values of one or more elements constituting the sequence of the number of parallel operations. Specifically, in the case where the number of parallel operations is expressed by a sequence, increasing the number of parallel operations means that the performance is obtained by using a part or all of values of one or more elements constituting the sequence of the number of parallel operations. It is to change in the direction to improve. When the number of parallel operations is expressed as a sequence, reducing the number of parallel operations means changing some or all of the values of one or more elements that make up the sequence of the number of parallel operations to reduce performance. It is to be.

  The performance control IF 101 accepts a notice of notice sent from the host 2. The performance control IF 101 sends the notice of notification received from the host 2 to the calculation unit 104. That is, the calculation unit 104 is notified of an access advance notice from the host 2 via the performance control IF 101. In addition, the performance control IF 101 receives the allowable power consumption sent from the host 2. The performance control IF 101 stores the allowable power consumption received from the host 2 as the allowable power consumption 201 in the information storage unit 103. The allowable power consumption 201 is read by the calculation unit 104. That is, the calculation unit 104 is notified of the allowable power consumption from the host 2 via the performance control IF 101 and the information storage unit 103.

  The calculation unit 104 calculates the number of parallel operation settings based on the allowable power consumption 201, the notice of notice, and the correspondence information 202. The parallel operation setting number is a setting value of the parallel operation number. The calculation unit 104 stores the calculated parallel operation setting number in the information storage unit 103 as the parallel operation setting number 203. The resource control unit 102 controls the parallel operation resource 50 so that the parallel operation number becomes equal to the parallel operation setting number 203.

  The correspondence information 202 is information that defines a correspondence relationship between at least performance and power consumption. The correspondence information 202 includes one or more variables in addition to performance and power consumption. Any data structure can be adopted as the data structure of the correspondence information 202. The data structure of the correspondence information 202 is, for example, a table, a function, or a combination thereof. Hereinafter, examples of variables of the correspondence information 202 and examples of characteristics will be described.

  For example, the access type ratio is prepared as a variable of the correspondence information 202. FIG. 3 is a graph showing an example of the relationship among the access type ratio, power consumption, and performance defined by the correspondence information 202. In this figure, it is assumed that predetermined values are set for variables other than the ratio of access type, power consumption, and performance. According to this example, power consumption increases as performance increases. When the write ratio is 100%, the amount of increase in power consumption with respect to the increase in performance is larger than when the read ratio is 100%. The access type ratio is transmitted from the host 2 as a notice of advance notice, for example. Further, the controller 10 may measure the ratio of the access type from the past access, and the calculation unit 104 may use the ratio obtained by the measurement. The influence of the type of access on the relationship between performance and power consumption is not limited to the example of FIG.

  For example, continuity of access is prepared as a variable of the correspondence information 202. FIG. 4 is a graph showing an example of the relationship between access continuity, power consumption, and performance, which is defined by the correspondence information 202. In this figure, it is assumed that predetermined values are set for variables other than continuity of access, power consumption, and performance. Of random write (RW), random read (RR), sequential write (SW), and sequential read (SR), the ratio of the increase in power consumption to the increase in performance is the largest in the case of random write. Smallest for leads. In the case of sequential write, the ratio of the increase in power consumption to the increase in performance is larger than in the case of random read. The continuity of access is transmitted from the host 2 as a notice of advance notice, for example. The controller 10 may measure the continuity of access from past accesses, and the calculation unit 104 may use the continuity of access obtained by the measurement. Note that the influence of continuity of access on the relationship between performance and power consumption is not limited to the example of FIG.

  For example, the time (t_prog) required for the write process for the memory cell array is prepared as a variable of the correspondence information 202. When writing user data to the NAND memory 11, the controller 10 transmits a write command for writing unit size data to the memory cell array to the memory chip. When the memory chip receives a write command from the controller 10, the state of the memory chip changes from the ready state to the busy state. While the memory chip writes (also referred to as programming) data to the memory cell array, the state of the memory chip remains busy. When the data programming to the memory cell array is completed, the state of the memory chip changes from the busy state to the ready state. Whether the memory chip is busy or ready is notified to the controller 10 via a ready / busy signal line included in the channel. t_prog means the time during which one memory chip is kept busy in response to a write command. In other words, t_prog is the time that one memory chip spends executing the write command. FIG. 5 is a graph illustrating an example of a relationship between t_prog, power consumption, and performance, which is defined by the correspondence information 202. In this figure, it is assumed that predetermined values are set for variables other than t_prog, power consumption, and performance. For example, as t_prog decreases, the time required to program one page of data into the memory cell array decreases. The power consumption required for programming one page of data is constant regardless of the value of t_prog when the conditions other than t_prog are the same. Therefore, when t_prog is the first value, the amount of increase in power consumption relative to the amount of increase in performance is larger than when t_prog is a second value smaller than the first value. The influence of t_prog on the relationship between performance and power consumption is obtained in advance by measurement or calculation, for example, and correspondence information 202 is generated based on the obtained influence. The controller 10 can measure t_prog by monitoring the ready busy signal. For example, the controller 10 may measure t_prog, and the calculation unit 104 may use t_prog obtained by the measurement.

  As the memory cell becomes exhausted, t_prog tends to decrease. This is because it becomes easier to inject electrons into the memory cell. By utilizing this tendency, an index indicating the progress of exhaustion of the memory cell may be used as a variable instead of t_prog. As an index indicating the progress of exhaustion of the memory cell, for example, the number of times erase is executed, the accumulated energization time (power on hours count), the total amount of data written to the memory system 1, or the data stored in the NAND memory 11 Total write amount, etc. can be used. The number of erase executions, the cumulative energization time, the total amount of data written to the memory system 1, or the total amount of data written to the NAND memory 11 is recorded as statistical information by the controller 10, for example. The calculation unit 104 can acquire and use the recorded number of erase executions, the cumulative energization time, the total amount of data written to the memory system 1, or the total amount of data written to the NAND memory 11. An index indicating the degree of exhaustion of the memory cell is used for each arbitrary unit. For example, the index indicating the degree of exhaustion of the memory cell is used in units of pages, blocks, memory chips, or NAND memory 11. Note that the influence of t_prog on the relationship between performance and power consumption is not limited to the example of FIG.

  For example, the code rate is prepared as a variable of the correspondence information 202. FIG. 6 is a graph showing an example of the relationship between the code rate and the power consumption defined by the correspondence information 202. In FIG. 6, it is assumed that predetermined values are set for variables other than the code rate and the power consumption. The code rate R can be greater than 0 and less than or equal to 1. When the code rate R is 1, the power consumption is minimum. As the code rate R is closer to 0, the power consumption increases. FIG. 7 is a graph showing an example of the relationship between the code rate, power consumption, and performance defined by the correspondence information 202. In FIG. 7, it is assumed that predetermined values are set for variables other than the code rate, power consumption, and performance. When the code rate is the third value, the amount of increase in power consumption with respect to the amount of increase in performance is larger than when the code rate is a fourth value greater than the third value. The influence of the code rate on the relationship between performance and power consumption is obtained in advance by measurement or calculation, for example, and the correspondence information 202 is generated based on the obtained influence. The controller 10 controls the code rate, and the calculation unit 104 acquires and uses the code rate. Note that the influence of the code rate on the relationship between performance and power consumption is not limited to the examples of FIGS.

  For example, the margin rate is prepared as a variable of the correspondence information 202. The margin ratio is one of indexes indicating the relationship between the total storage capacity available for storing user data in the NAND memory 11 and the notation capacity. Specifically, the margin rate is obtained by dividing the margin capacity by the notation capacity. The margin capacity is a value obtained by subtracting the notation capacity from the total capacity of the areas available for storing user data. An area that can be used for storing user data is referred to as an available area here. User data is data sent from the host 2. Note that the state of the user data stored in the available area is either a valid state or an invalid state. When the second user data is sent from the host 2 with the same logical address as the first user data in a state where the first user data is stored in the NAND memory 11, the controller 10 The second user data is written in the block having the page, and the first user data is managed as invalid user data. Here, the “empty” state refers to a state in which neither invalid data nor valid data is stored. An empty page is an empty area in which data can be written. Since writing to the NAND memory 11 is performed by such a method, invalid user data and valid user data are stored in each block. Valid data means that the data is up-to-date. When a plurality of user data designated with the same logical address is stored in the NAND memory 11, the latest state is a state of user data written last by the host 2 among the plurality of user data. . Invalid data refers to user data other than user data written last by the host 2 among the plurality of user data.

  The margin ratio can change dynamically. For example, the margin rate decreases due to an increase in bad blocks. The bad block refers to a block determined to be unusable among the blocks included in the NAND memory 11. The criteria for determining the unusability are arbitrary. For example, when the error bit rate of user data stored in a certain block exceeds a predetermined value, the controller 10 manages that block as an unusable block (that is, a bad block). Further, for example, the margin rate decreases due to a decrease in the code rate. This is because the net size of the area in which user data can be written (in other words, the size of the available area) decreases as the code rate decreases.

  The margin rate affects the execution of garbage collection. Garbage collection refers to a process in which valid data from one block is moved (copied) to an empty area of another block, and then all data stored in the source block is managed as invalid data. . The source block is managed as a free block after garbage collection. A set of free blocks is referred to as a free block pool. Each free block is in a state in which no data is stored by executing the erase.

  As the user data sent from the host 2 continues to be written to the NAND memory 11, the amount of invalid user data increases and the free blocks are depleted. The CPU 51 executes garbage collection to generate a free block. That is, there are roughly two types of writing of user data to the NAND memory 11. One of the two types of lights is a write of user data sent from the host 2 (hereinafter referred to as a host light). The other of the two types of lights is a light based on garbage collection (hereinafter referred to as garbage collection light). The ratio between the amount of data written to the NAND memory 11 by host write and the amount of data written by the NAND memory 11 by garbage collection write is controlled by the CPU 51 according to the margin ratio. As an example, a value obtained by dividing the amount of data written by the NAND memory 11 by garbage collection write by the amount of data written by the host write to the NAND memory 11 is expressed as a gear ratio. The CPU 51 controls the gear ratio according to the margin rate. The CPU 51 controls the execution of garbage collection according to the gear ratio and the amount of data written to the NAND memory 11 by the host write. Specifically, for example, the CPU 51 calculates a gear ratio according to the margin rate. Then, the CPU 51 calculates a target data amount to be written to the NAND memory 11 by garbage collection from the data amount written to the NAND memory 11 by the host write and the gear ratio. Then, the CPU 51 executes garbage collection until the target data amount obtained by the calculation is reached.

  FIG. 8 is a graph showing an example of the relationship between the gear ratio and the margin ratio. As illustrated, the CPU 51 increases the gear ratio as the margin ratio decreases. That is, as the margin ratio decreases, the CPU 51 increases the ratio of the total data amount actually written to the NAND memory 11 to the data amount sent to the memory system 1 by the host write. Therefore, when the conditions other than the power consumption and the margin rate are the same, the power consumption increases as the margin rate decreases.

  FIG. 9 is a graph showing an example of the relationship between the margin rate, the power consumption, and the performance defined by the correspondence information 202. In FIG. 9, it is assumed that predetermined values are set for variables other than the margin ratio, power consumption, and performance. When the margin rate is the fifth value, the amount of increase in power consumption relative to the amount of increase in performance is larger than when the margin rate is a sixth value that is larger than the fifth value. The influence of the margin ratio on the relationship between performance and power consumption is obtained in advance by measurement or calculation, for example, and the correspondence information 202 is generated based on the obtained influence. The CPU 51 controls the margin rate, and the calculation unit 104 acquires and uses the margin rate. Note that the influence of the margin rate on the relationship between performance and power consumption is not limited to the example of FIG.

  Note that the magnitude of the influence of the margin ratio on the relationship between power consumption and performance depends on the continuity of access. For example, in the case of random writing, the margin rate has a greater influence on the relationship between power consumption and performance than in the case of sequential writing. This is because, in the case of sequential write, free blocks can be generated more efficiently than in the case of random write. A margin rate and continuity of access may be prepared as variables of the correspondence information 202.

  Note that the ratio of the total amount of data actually written to the NAND memory 11 with respect to the amount of data sent to the memory system 1 by host write is expressed as a write magnification factor (WAF). The correspondence information 202 may include a WAF as a variable instead of the margin rate. WAF is affected not only by the margin rate but also by the code rate. WAF increases as the code rate decreases. The calculation unit 104 may acquire a WAF by calculation or measurement, and use the acquired WAF.

  For example, temperature information is prepared as a variable of the correspondence information 202. The power consumption is obtained by adding the leak power and the dynamic power. The leak power is power lost due to a leak current generated in the memory 52. Leakage current occurs during power supply and does not occur when power supply is stopped. The leak power changes according to the junction temperature of the circuit that constitutes the memory 52. The dynamic power is power consumed by data transfer in the memory system 1. The dynamic power includes power consumed by erasing, reading, and writing in each memory chip. That is, dynamic power tends to increase as performance increases.

  10 and 11 are graphs showing an example of the relationship between the junction temperature, the power consumption, and the performance defined by the correspondence information 202. FIG. As shown in FIGS. 10 and 11, when the junction temperature is the same, the power consumption when the performance is high is larger than the power consumption when the performance is low. When the performance is the same, the power consumption when the junction temperature is high is larger than the power consumption when the junction temperature is low.

  For example, the temperature sensor 105 is disposed in the vicinity of the memory 52. The calculation unit 104 may calculate the junction temperature by correcting the detection value of the temperature sensor 105 by a predetermined calculation. When the temperature sensor 105 is arranged at a position away from the memory 52 (for example, a position away from the controller 10 in the memory system 1), the calculation unit 104 detects the relationship between the temperature sensor 105 and the preset relational expression. The junction temperature may be estimated based on the value. The memory system 1 may be input with temperature from the outside (for example, a housing of a computer in which the memory system 1 is mounted). For example, the calculation unit 104 may estimate the junction temperature based on the temperature input from the outside. Further, for example, the detection value of the temperature sensor 105 may be prepared as a variable of the correspondence information 202 instead of the junction temperature. This is because the junction temperature can be easily derived from the detection value of the temperature sensor 105 as described above. In addition, the influence which junction temperature has on the relationship between performance and power consumption is not limited to the example of FIG. 10 and FIG.

  In the above example, the relationship between power consumption and performance has been described as being linear if other conditions of power consumption and performance are the same. For example, the DC-DC converter 121 has a property that the efficiency improves as the load increases. Considering this property of the DC-DC converter 121, the relationship between the power consumption and the performance is, for example, as shown in the graph of FIG. 12, as the performance increases, the power consumption increases with respect to the increase in performance. A large percentage is reduced. Thus, the relationship between power consumption and performance may not be linear.

  The influence of various variables on the relationship between performance and power consumption is obtained, for example, by measurement or calculation at the time of manufacture, and correspondence information 202 is generated based on the obtained influence. The influence of various variables on the relationship between performance and power consumption may be measured individually for each memory system 1. As a result, it is possible to control power consumption independent of manufacturing variations of the memory system 1. The influence of various variables on the relationship between performance and power consumption may be measured for each of a plurality of memory systems 1 (for example, for each lot of memory systems 1).

  FIG. 13 is a sequence diagram for explaining the operation of the memory system 1 according to the first embodiment. First, the host 2 transmits a notice of advance notice to the memory system 1 (S101). In the memory system 1, the calculation unit 104 acquires values set in various variables of the correspondence information 202 in response to the reception of the notice of advance notice (S102). Based on the acquired values and the correspondence information 202, the calculation unit 104 calculates power consumption (that is, predicted power consumption) when the performance notified by the notice of notice is realized (S103).

  The acquisition includes calculation, reference, and estimation. Reference includes reference to a preset value and reference to a state value. When there is a variable for which a fixed value for calculating the prediction performance is preset among one or more variables of the correspondence information 202, the calculation unit 104 refers to the fixed value. The calculation unit 104 reads the access pattern with reference to the notice of advance notice. Further, for example, the margin ratio is recorded as a state value in a predetermined storage area (for example, the memory 52), and is updated according to the operation status. The calculation unit 104 refers to the margin rate recorded in a predetermined storage area. For example, the calculation unit 104 calculates or estimates the junction temperature based on the detection value of the temperature sensor 105. As described above, the calculation unit 104 calculates, refers to, or estimates the value to be set for the variable of the correspondence information 202 according to the type of the variable.

  In the process of S103, for example, the calculation unit 104 sets values for all the variables of the correspondence information 202 except for the power consumption. And the calculation part 104 handles the power consumption determined from the correspondence information 202 and the value set to each variable as a predicted power consumption.

  The CPU 51 transmits the predicted power consumption calculated by the calculation unit 104 to the host 2 (S104). The host 2 determines the allowable power consumption based on the predicted power consumption (S105).

  The processing method of S105 can be designed arbitrarily. For example, the host 2 calculates the power consumption allocated to the memory system 1 based on the overall power consumption balance. Alternatively, the host 2 determines the power consumption to be allocated to the memory system 1 in consideration of the amount of heat released from the memory system 1. If the predicted power consumption does not exceed the power consumption allocated to the memory system 1, the host 2 sets the predicted power consumption to an allowable power consumption. When the predicted power consumption exceeds the power consumption allocated to the memory system 1, the host 2 sets the power consumption allocated to the memory system 1 to an allowable power consumption.

  The host 2 transmits allowable power consumption to the memory system 1 (S106). When the memory system 1 receives the allowable power consumption, the performance control IF 101 stores the received allowable power consumption in the information storage unit 103 as the allowable power consumption 201. The calculation unit 104 calculates the maximum performance that can be achieved with the allowable power consumption 201 (S107). In the process of S107, for example, the calculation unit 104 sets values for all the variables except the performance among the plurality of variables of the correspondence information 202.

  The calculation unit 104 calculates the number of parallel operation settings based on the performance obtained by the process of S107 (S108). The relationship between the performance and the number of parallel operations is set in the memory system 1 in advance. For example, information (for example, a table or function) that defines the relationship between the performance and the number of parallel operations is stored in advance in a predetermined storage area (for example, the NAND memory 11). For example, the calculation unit 104 calculates the parallel operation setting number 203 by using the information and the calculated performance. The calculation unit 104 stores the calculated parallel operation setting number 203 in the information storage unit 103.

  The resource control unit 102 updates the number of parallel operations (S109). Specifically, the resource control unit 102 controls the parallel operation resource 50 so that the number of parallel operations is equal to the parallel operation setting number 203.

  In the description of FIG. 13, it has been described that the host 2 determines the allowable power consumption and notifies the memory system 1. When the power consumption allocated to the memory system 1 is larger than the predicted power consumption, the host 2 may transmit a permission notice in the process of S106. When receiving the permission notification, the performance control IF 101 stores the transmitted predicted power consumption as the allowable power consumption 201 in the information storage unit 103.

  Further, the calculation unit 104 has been described as calculating the maximum performance that can be realized with the allowable power consumption 201 in the process of S107. The calculation unit 104 may not necessarily calculate the maximum performance as long as the performance can be realized with the allowable power consumption 201.

  In the above description, the resource control unit 102 adjusts the performance by changing the number of parallel operations. The method of adjusting the performance is not limited to the method by controlling the number of parallel operations. For example, the resource control unit 102 can adjust the performance by inserting a waiting time into the response to the host 2. The response includes data read from the NAND memory 11 in response to the read command. The response may be an execution completion notification corresponding to the command from the host 2. When the response is divided into a plurality of packets and transmitted, the resource control unit 102 may insert a waiting time between the packets. The resource control unit 102 calculates the size of the waiting time according to the performance obtained by the calculation of S108.

  Further, the negotiation method between the memory system 1 and the host 2 is arbitrary. For example, the host 2 transmits a notice of notice and allowable power consumption to the memory system 1, and the memory system 1 calculates the predicted power consumption based on the notice of notice, and the larger of the predicted power consumption and the allowable power consumption. It is possible to operate with the maximum performance that can be achieved using the power consumption of For example, the host 2 may transmit the allowable power consumption to the memory system 1, and the memory system 1 may operate with the maximum performance that can be realized using the received allowable power consumption.

  As described above, in the first embodiment, the memory system 1 receives the access pattern and performance from the host 2 and calculates the predicted power consumption based on the access pattern, performance, and margin rate. Is provided. Access patterns, performance, and margin are factors that can change dynamically. Since the calculation unit 104 predicts power consumption based on these dynamically changing elements, it is possible to predict power consumption with high accuracy. The memory system 1 is highly convenient because it can predict power consumption with high accuracy.

  Further, the influence of the access pattern on the relationship between the performance and the power consumption is larger than the influence of the other variables described above. Since the calculation unit 104 predicts the power consumption using the access pattern, the prediction accuracy is improved. In addition, the influence of the margin ratio changes according to the continuity of access. For example, in the case of random writing, the influence of the margin ratio is greater than that of sequential writing. Since the calculation unit 104 predicts the power consumption using the access pattern and the margin rate, the accuracy of the prediction is improved. Note that any index other than the margin ratio can be used as a variable as long as the index indicates the relationship between the total storage capacity available for storing user data in the NAND memory 11 and the notation capacity.

  Note that the calculation unit 104 may calculate the predicted power consumption based only on the margin rate and the performance. When the calculation unit 104 is configured to calculate the predicted power consumption based only on the margin rate and the performance, even if the relationship between the performance and the power consumption is defined in the correspondence information 202 assuming a random write case. Good.

  The memory system 1 further includes a temperature sensor 105. The calculation unit 104 predicts power consumption by further using the detection value of the temperature sensor 105. As described above, the leak power of the memory 52 changes according to the junction temperature. The junction temperature is also a factor that can change dynamically. Since the power consumption can be predicted in consideration of the influence of the junction temperature, the accuracy of the prediction is improved. Note that the calculation unit 104 may calculate the junction temperature from the detection value of the temperature sensor 105. A detection value of the temperature sensor 105 may be prepared as a variable of the correspondence information 202.

  In addition, the calculation unit 104 predicts power consumption by further using the code rate. The code rate is also a factor that can change dynamically. Since the calculation unit 104 predicts the power consumption using the code rate, the prediction accuracy is improved. The code rate is one of indices indicating the relationship between the size of user data before encoding and the size of user data after encoding. If the index indicates the relationship between the size of user data before encoding and the size of user data after encoding, an index other than the code rate can be used as a variable.

  In addition, the calculation unit 104 predicts power consumption by further using t_prog. t_prog decreases with the exhaustion of the memory cell. That is, t_prog is an element that can change dynamically. Since the calculation unit 104 predicts power consumption using t_prog, the accuracy of prediction is improved. An index indicating the progress of exhaustion of the memory cell can be used instead of t_prog.

  Further, the calculation unit 104 calculates a throughput that can be executed with allowable power consumption. As a result, the memory system 1 can operate with power consumption that does not exceed the allowable power consumption. The allowable power consumption is notified from the host 2. The allowable power consumption may be determined in advance.

(Second Embodiment)
FIG. 14 is a diagram illustrating an implementation example of the memory system 1. The memory system 1 is mounted on the server system 1000, for example. The server system 1000 is configured by connecting a disk array 2000 and a rack mount server 3000 via a communication interface 4000. Any standard can be adopted as the standard of the communication interface 4000. The rack mount server 3000 includes a server rack, and one or more hosts 2 are mounted on the server rack. The disk array 2000 includes a server rack, and one or more memory systems 1 are mounted on the server rack. Other units such as HDDs may be mounted on the server rack of the disk array 2000. The disk array 2000 includes a power supply device 3. Power from the power supply device 3 is supplied to each unit mounted on the disk array 2000 via a backplane (not shown). When the disk array 2000 includes a plurality of memory systems 1, the plurality of memory systems 1 may constitute a RAID.

  The host 2 may calculate the allowable power consumption for each memory system 1 so that the temperature in the disk array 2000 does not exceed a predetermined value. Further, the host 2 may calculate the allowable power consumption for each memory system 1 based on the power supply capability of the power supply device 3 and the number of memory systems 1 provided in the disk array 2000. Since each memory system 1 has the configuration described in the first embodiment, it can exhibit the maximum performance that can be realized with allowable power consumption.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 memory system, 2 host, 3 power supply device, 10 controller, 11 NAND memory, 12 power supply circuit, 31 calculation unit, 50 parallel operation resource, 52 memory, 53 encoding unit, 54 decoding unit, 101 performance control IF, 102 Resource control unit, 103 information storage unit, 104 calculation unit, 105 temperature sensor, 121 DC-DC converter, 201 allowable power consumption, 202 correspondence information, 203 number of parallel operation settings, 1000 server system, 2000 disk array, 3000 rack mount server 4000 Communication interface.

Claims (16)

A first step of receiving an access pattern and throughput notification from the host;
Use predicted power consumption, which is power consumption for processing access by the access pattern at the throughput, for storing user data in at least the access pattern, the throughput, and the nonvolatile first memory included in the memory system. A second step of calculating based on capacity information, which is an index indicating the relationship between the total possible storage capacity and the notation capacity;
A method for controlling a memory system including: The second step is a step of calculating the predicted power consumption based further on a detection value of a temperature sensor provided in the memory system.
The method of controlling a memory system according to claim 1. The second step calculates a junction temperature of a volatile second memory that temporarily stores data included in the memory system from a detection value of the temperature sensor, and calculates the prediction based on the junction temperature of the second memory. A step of calculating power consumption,
The method of controlling a memory system according to claim 2. Encoding user data to be written to the first memory;
The second step is a step of calculating the predicted power consumption based on encoding information that is an index indicating a relationship between the size of user data before encoding and the size of user data after encoding.
The method of controlling a memory system according to claim 1. Further comprising the step of transmitting to the first memory a write command for writing unit size data to the first memory,
The second step is a step of calculating the predicted power consumption based further on a write command execution time that is a time that the first memory spends executing the write command.
The method of controlling a memory system according to claim 1. The second step is a step of calculating the predicted power consumption based further on fatigue information that is an index indicating the progress of exhaustion of the first memory.
The method of controlling a memory system according to claim 1. In the second step, the predicted power consumption is calculated by using correspondence information that is information that records at least a relationship between an access pattern, a throughput, and power consumption stored in a third memory included in the memory system. Is a step,
The method of controlling a memory system according to claim 1. The correspondence information is generated based on a measurement for the memory system when the memory system is manufactured.
The method of controlling a memory system according to claim 7. The access pattern is a ratio between read and write, or continuity of access positions in an address space that the host maps to the memory system.
The method of controlling a memory system according to claim 1. The method further includes a step of calculating an executable throughput with allowable power consumption.
The method of controlling a memory system according to claim 1. Receiving a notification of the allowable power consumption from the host;
The method of controlling a memory system according to claim 10. The second step is a step of calculating the predicted power consumption based on the notified access pattern and throughput,
A third step of notifying the host of the calculated predicted power consumption;
The method of controlling a memory system according to claim 1. A fourth step of receiving a notice of allowable power consumption from the host after the third step;
A fifth step of calculating an executable throughput with the allowable power consumption;
The memory system control method according to claim 12, further comprising: Further comprising operating the memory system at the calculated throughput,
The method of controlling a memory system according to claim 13. Receiving a throughput notification from the host;
Calculating power consumption for realizing the throughput based on capacity information which is an index indicating a relationship between a margin capacity and a notation capacity of the first memory included in the memory system;
A method for controlling a memory system comprising: Receiving an access pattern notification from the host;
A total storage capacity and a notation capacity that can be used for storing user data in at least the access pattern and a nonvolatile first memory included in the memory system that has a predicted power consumption that is a power consumption for processing an access according to the access pattern. Calculating based on capacity information, which is an index indicating the relationship between
A method for controlling a memory system comprising:

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