JP2019134350A - Management system - Google Patents

Abstract

To make node redundant with small quantity of hardware.SOLUTION: An active system node NA transmits a first operational state related to first provision processing to a dedicated line LA by a transmission circuit 12, an active system node NB transmits a second operational state related to second provision processing to a dedicated line LB by a transmission circuit 22, a standby system node NX receives the first and second operational states transmitted from the NA, the NB by a receiving circuit 33 via the dedicated lines LA, LB, respectively, and when any one of the first and second operational states received by the receiving circuit 33 indicates abnormality, an arithmetic processing circuit 31 executes alternative processing related to the first or second provision processing, in place of the NA, the NB which are transmission sources of the operational states.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a redundancy control technique for making a plurality of nodes constituting a management system redundant.

  In large-scale facilities such as plants and buildings, as a management system for operating and managing multiple facilities installed in the facility, processing for operation and management is distributed among multiple nodes connected via communication lines A distributed control system (DCS) is used.

  For example, in the case of a management system used in a plant, a node (HMI: Human Machine Interface) that an operator operates and monitors, a node (history device) that manages various data such as a plant operation history, and a network between different protocols A node (gateway device) for connection and a node (control device) that performs advanced control / calculation are used. These nodes as a whole are composed of information processing devices such as server devices, PCs, industrial controllers, and network devices.

In such a management system, even if a failure occurs in any of the nodes, it is necessary to perform so-called redundancy so that the operation and monitoring of the equipment can be maintained and the operation of the entire system can be continued.
Conventionally, as a technique for ensuring the reliability of such a management system, for each process executed on each node, two identical nodes are prepared and duplicated as hardware for executing the process. When a failure occurs in one of the nodes, a technique for switching to the other node and continuing the processing has been proposed (see, for example, Patent Document 1).

JP 2016-111454 A

  However, in such a conventional technique, each node needs to be duplicated, so that the management system as a whole requires twice the amount of hardware, increasing the cost required for system construction and complicating the system configuration. There was a problem of inviting.

  The present invention is intended to solve such a problem, and an object of the present invention is to provide a redundancy control technique capable of making a node redundant with a small amount of hardware.

  In order to achieve such an object, a management system according to the present invention is set in advance with a first active system node including a first arithmetic processing circuit that executes a first predetermined processing set in advance. When an abnormality occurs in the second operating system node having the second arithmetic processing circuit that executes the second specified processing and the first or second operating system node, instead of these operating system nodes A standby node that executes the first or second prescribed process, and a first dedicated line for notifying the second active node and the standby node of the operating state of the first active node And a second dedicated line for notifying the first active node and the standby node of the operating state of the second active node, wherein the first active node The first action regarding the regulation process of 1 A first transmission circuit configured to transmit a state to the first dedicated line, and the second active node transmits a second operation state related to the second specified process to the second dedicated line. A second transmission circuit, wherein the standby node transmits the first and second operation states transmitted from the first and second active nodes via the first and second dedicated lines. When either one of the standby system receiving circuit and the first and second operating states received by the standby system receiving circuit indicate an abnormality, the first or second transmission source of the operating state Instead of the active system node, a standby system arithmetic processing circuit that executes an alternative process related to the first or second specified process is provided.

  The configuration example of the management system according to the present invention further includes a standby dedicated line for notifying the operating state of the standby node to the first and second active nodes, and the standby node Further includes a standby transmission circuit that transmits a standby operation state related to the alternative processing to the standby dedicated line, and the first active node transmits from the second active node and the standby node. A first receiving circuit that receives the second operating state and the standby system operating state, which are received via the second dedicated line and the standby dedicated line, respectively; Indicates the first operating state and the standby system operating state transmitted from the first active node and the standby node via the first dedicated line and the standby dedicated line. A second receiving circuit for receiving each of the first arithmetic processing circuits, and the first arithmetic processing circuit, when the second operating state received by the first receiving circuit indicates an abnormality, After temporarily suspending the processing, the first prescribed processing is resumed in response to confirmation of the start of the alternative processing according to the standby operation state received by the first receiving circuit, and the second arithmetic processing circuit is If the first operating state received by the second receiving circuit indicates an abnormality, the second specifying process is temporarily stopped and then the standby operating state received by the second receiving circuit The second prescribed process is resumed in response to the confirmation of the start of the alternative process.

  Also, in one configuration example of the management system according to the present invention, the first transmission circuit includes a first detection unit that detects whether the first operation state is transmitted to the first dedicated line, The second transmission circuit includes a second detection unit that detects whether or not the second operation state is transmitted to the second dedicated line, and the first arithmetic processing circuit includes the first operation state. When the transmission of the first operation state is not detected by the first detection unit despite the fact that the normal operation is normal, the first regulation processing is stopped, and the second arithmetic processing circuit In the case where transmission of the second operation state is not detected by the second detection unit even though the second operation state indicates normality, the second defining process is stopped. .

  According to the present invention, at least two active nodes can be made redundant with one standby node, and the amount of hardware is small compared to the case where each active node is made redundant with a dedicated standby node. Thus, the node can be made redundant.

It is a block diagram which shows the structure of the management system concerning 1st Embodiment. It is a flowchart which shows the redundant control process of the active node concerning 1st Embodiment. It is a flowchart which shows the redundant control process of the standby node concerning 1st Embodiment. It is a timing chart which shows the example of operation of the management system concerning a 1st embodiment. It is explanatory drawing which shows the state (at the time of normal) of each node concerning 1st Embodiment. It is explanatory drawing which shows the state (at the time of abnormality occurrence) of each node concerning 1st Embodiment. It is explanatory drawing which shows the state (at the time of an alternative process start) of each node concerning 1st Embodiment. It is a block diagram which shows the structure of the management system concerning 2nd Embodiment. It is a flowchart which shows the redundancy control process of the active node concerning 2nd Embodiment. It is a timing chart which shows the example of operation of the management system concerning a 2nd embodiment. It is explanatory drawing which shows the state (at the time of normal) of each node concerning 2nd Embodiment. It is explanatory drawing which shows the state (at the time of disconnection generation | occurrence | production) of each node concerning 2nd Embodiment. It is explanatory drawing which shows the state (at the time of an alternative process start) of each node concerning 2nd Embodiment.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a management system 1 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of a management system according to the first embodiment.

  The management system 1 according to the present invention is a system that executes information processing related to each other in a distributed manner at a plurality of nodes. A specific example of the management system 1 is a distributed control system that is used in a large-scale facility such as a plant or a building and operates and manages a plurality of facilities provided in the facility. The application of the present invention is not limited to a management system such as the above distributed control system, but an information processing system in which a plurality of server devices cooperate to perform information processing, or a plurality of network devices cooperate. The present invention can also be applied to other management systems such as a communication processing system that performs communication processing.

  As shown in FIG. 1, the management system 1 includes an active node (first active node) NA, an active node (second active node) NB, and a standby system connected to a communication line E. The node NA, the dedicated line (first dedicated line) LA for notifying the operating state of the active node NA to the active node NB and the standby node NX, and the operating state of the active node NB And a dedicated line (second dedicated line) LB for notifying the standby node NX.

When the processes executed by the active nodes NA and NB are linked to each other, in addition to the configuration of the management system 1, the operating state of the standby node NX is notified to the active nodes NA and NB. Dedicated line (standby line) LX may be provided.
Hereinafter, a configuration in which the management system 1 includes the dedicated line LX will be described as an example. However, if the processes executed by the active nodes NA and NB are not linked to each other, the dedicated line LX may be omitted.

  The active nodes NA and NB and the standby node NX as a whole are composed of information processing devices (computers) such as server devices, PCs, industrial controllers, and network devices.

  The active node NA has an arithmetic processing circuit (first arithmetic processing circuit) 11 that executes a preset first specified process and a process related to redundancy control, and a first operation state related to the first specified process. The transmission circuit (first transmission circuit) 12 that transmits to the active node NB and the standby node NX via the dedicated line LA, and the operating states of the active node NB and the standby node NX via the dedicated lines LB and LX Receiving circuit (first receiving circuit) 13. The first operation state only needs to include at least an operation state related to the first specified process. As the first operation state, the operation state of the arithmetic processing circuit 11 and further the operation state of the active node NA are included. It may be used.

  The arithmetic processing circuit 11 includes a CPU and its peripheral circuits. By executing a pre-registered program on the CPU, the arithmetic processing circuit 11 cooperates with hardware and software to perform processing relating to the first prescribed processing and redundancy control. Has the function to execute.

  The transmission circuit 12 includes a power supply potential V connected to one end of the dedicated line LA, a ground potential GND connected to the other end of the dedicated line LA, and a switch element SWA that controls application of the power supply potential V to the dedicated line LA. The transmission I / F circuit SIFA that controls transmission of the first operation state to the dedicated line LA by controlling the SWA on / off based on the transmission signal AS from the arithmetic processing circuit 11 indicating the first operation state. And. SWA may be realized by a secondary side transistor of a photocoupler. Thereby, SIFA is realizable with the primary side light emitting diode of the said photocoupler.

  The receiving circuit 13 is a light-emitting diode LDAB connected in series to the dedicated line LB, a light-emitting diode LDAX connected in series to the dedicated line LX, and an active system node detected based on the presence or absence of light emission of these LDAB and LDAX The reception signals AB and AX indicating the second operation state relating to the second prescribed process executed in the NB and the standby operation state relating to the alternative process executed in the standby node NX are output to the arithmetic processing circuit 11. And a reception I / F circuit RIFA. LDAB and LDAX may be realized by a primary light emitting diode of a photocoupler. Thereby, RIFA is realizable with the secondary side transistor of the said photocoupler.

  The active node NB includes an arithmetic processing circuit (second arithmetic processing circuit) 21 that executes preset second prescribed processing and processing relating to redundancy control, and a second operation state relating to the second prescribed processing. The transmission circuit (second transmission circuit) 22 that transmits to the active node NA and the standby node NX via the dedicated line LB, and the operating states of the active node NA and the standby node NX via the dedicated lines LA and LX And a receiving circuit (second receiving circuit) 23 for receiving. The second operation state only needs to include at least an operation state related to the second specified process. As the second operation state, the operation state of the arithmetic processing circuit 21 and the operation state of the active node NB are included. It may be used.

  The arithmetic processing circuit 21 includes a CPU and its peripheral circuits. By executing a pre-registered program on the CPU, the arithmetic processing circuit 21 cooperates with hardware and software, and performs processing related to second regulation processing and redundancy control. Has the function to execute.

  The transmission circuit 22 includes a power supply potential V connected to one end of the dedicated line LB, a ground potential GND connected to the other end of the dedicated line LB, and a switch element SWB that controls application of the power supply potential V to the dedicated line LB. The transmission I / F circuit SIFB controls transmission of the second operation state to the dedicated line LB by controlling the SWB on / off based on the transmission signal BS from the arithmetic processing circuit 21 indicating the second operation state. And. SWB may be realized by a secondary side transistor of a photocoupler. Thereby, SIFB is realizable with the primary side light emitting diode of the said photocoupler.

  The reception circuit 23 detects the light-emitting diode LDBA connected in series to the dedicated line LA, the light-emitting diode LDBX connected in series to the dedicated line LX, and the active node detected based on the presence or absence of light emission of these LDBA and LDBX. The reception signals BA and BX indicating the first operation state relating to the first prescribed process executed by the NA and the standby operation state relating to the alternative process executed by the standby node NX are output to the arithmetic processing circuit 21. A reception I / F circuit RIFB. About LDBA and LDBX, you may implement | achieve with the primary side light emitting diode of a photocoupler. Thereby, RIFB can be realized by the secondary transistor of the photocoupler.

  The standby node NX includes an arithmetic processing circuit (standby arithmetic processing circuit) 31 that executes an alternative process relating to the first or second prescribed process and a process relating to redundancy control in place of the active nodes NA and NB, and an alternative process. A transmission circuit (standby transmission circuit) 32 for transmitting the standby system operating state to the active nodes NA and NB via the dedicated line LX and the operating status of the active nodes NA and NB are received via the dedicated lines LA and LB. Receiving circuit (standby system receiving circuit) 33. Note that the standby system operation state only needs to include at least an operation state related to alternative processing, and the operation state of the arithmetic processing circuit 31 and the operation state of the standby node NX may be used as the standby system operation state.

  The arithmetic processing circuit 31 includes a CPU and its peripheral circuits, and has a function of executing an alternative process relating to the first or second prescribed process and a process relating to redundancy control by executing a pre-registered program on the CPU. doing.

  The transmission circuit 32 includes a power supply potential V connected to one end of the dedicated line LX, a ground potential GND connected to the other end of the dedicated line LX, and a switch element SWX that controls application of the power supply potential V to the dedicated line LX. A transmission I / F circuit SIFX that controls transmission of the standby system operation state to the dedicated line LX by performing on / off control of the SWX based on the transmission signal XS from the arithmetic processing circuit 31 indicating the standby system operation state. I have. SWX may be realized by a secondary side transistor of a photocoupler. Thereby, SIFX is realizable with the primary side light emitting diode of the said photocoupler.

  The reception circuit 33 detects the light-emitting diode LDXA connected in series to the dedicated line LA, the light-emitting diode LDXB connected in series to the dedicated line LB, and the active node detected based on the presence or absence of light emission of these LDXA and LDXB. The reception processing signals XA and XB indicating the first operation state relating to the first prescribed process executed in the NA and the second operation state relating to the second prescribed process executed in the active node NB are obtained as an arithmetic processing circuit. And a reception I / F circuit RIFX that outputs the data to 31. About LDXA and LDXB, you may implement | achieve with the primary side light emitting diode of a photocoupler. Thereby, RIFX can be realized by the secondary transistor of the photocoupler.

[Operation of First Embodiment]
Next, operations of the active nodes NA and NB and the standby node NX according to the present embodiment will be described with reference to FIGS. FIG. 2 is a flowchart illustrating redundancy control processing of the active node according to the first embodiment. FIG. 3 is a flowchart illustrating redundancy control processing of the standby node according to the first embodiment.

  First, the redundancy control operation in the active nodes NA and NB will be described with reference to FIG. The operation processing circuits 11 and 21 of the active nodes NA and NB always execute the redundancy control process of FIG. In the following description, NA will be described, but the same applies to NB. Note that the redundancy control processing in FIG. 2 may be realized by executing a program by the CPUs of the arithmetic processing circuits 11 and 21, but a part thereof may be realized by a logic circuit.

  First, the arithmetic processing circuit 11 checks the operation state relating to the first specified process being executed, that is, the presence or absence of an abnormality (step S100). The presence / absence of an abnormality here may be confirmed based on, for example, a monitoring result related to the first specified process or an alert signal output from various circuits in the own node NA.

  When it is confirmed in step S100 that there is an abnormality (step S100: YES), the arithmetic processing circuit 11 stops the first specified process being executed (step S101) and stops outputting the transmission signal AS. The switch element SWA of the transmission circuit 12 is turned off (step S102), and the process returns to step S100. As a result, the output of the first operation state indicating the normal operation (power supply potential V) output from the NA to the dedicated line LA is stopped, and the occurrence of abnormality in the NA is detected in the NB and NX.

  On the other hand, when it is confirmed in step S100 that there is no abnormality (step S100: NO), the arithmetic processing circuit 11 determines whether or not there is an abnormality in another operating system node, that is, the NB, based on the reception signal AB from the reception circuit 13. Confirmation (step S103). Here, when it is confirmed that there is no abnormality in the NB (step S103: NO), the process returns to step S100.

In step S103, when it is confirmed that there is an abnormality in the NB (step S103: YES), the arithmetic processing circuit 11 temporarily stops the first defining process in its own node (step S104) and then receives from the receiving circuit 13. Based on the signal AX, the operation start in the standby node NX is confirmed (step S105), and the operation waits until the operation start is confirmed (step S105: NO).
When the operation start of NX is confirmed (step S105: YES), the arithmetic processing circuit 11 resumes the first specified processing operation in the own node NA (step S106) and returns to step S100.

  As a result, in the active nodes NA and NB, when an abnormality occurs in the first prescribed process or the second prescribed process being executed in the own node, the operation state indicating the abnormality is waited via the dedicated lines LA and LB. This is notified to the system node NX. In addition, when an abnormality occurs in the first prescribed process or the second prescribed process being executed in another active node, the first prescribed process or the second prescribed process being executed in the own node is temporarily stopped. Then, after the alternative processing at the standby node NX is started, the temporarily stopped processing is resumed.

  Next, the redundancy control operation in the standby node NX will be described with reference to FIG. The arithmetic processing circuit 31 of the standby node NX always executes the redundancy control process of FIG. 3 may be realized by executing a program by the CPU of the arithmetic processing circuit 31, but a part thereof may be realized by a logic circuit.

  First, the arithmetic processing circuit 31 confirms whether or not there is an abnormality related to the first or second prescribed processing in the active nodes NA and NB based on the received signals XA and XB from the receiving circuit 33 (step S110). Here, when it is confirmed that there is no abnormality related to the first and second defining processes (step S110: NO), the process returns to step S110.

On the other hand, when it is confirmed in step S110 that there is an abnormality in either the first or second prescribed process (step S110: YES), the arithmetic processing circuit 31 is an operation that is a transmission source of an operation state indicating an abnormality. Instead of the system nodes NA and NB, an alternative process of the first or second defining process that has been executed by the NA and NB is started (step S111).
Thereafter, the arithmetic processing circuit 31 starts outputting the transmission signal XS, turns on the switch element SWX of the transmission circuit 32 (step S112), and returns to step S110.

  Thereby, in the standby node NX, when an abnormality occurs in the first prescribed process or the second prescribed process being executed in either the active node NA or NB, the substitute process of these processes is started, and the substitute node The start of processing is notified to the NA and NB depending on the standby system operating state.

[Operation Example of First Embodiment]
Next, an operation example according to the present embodiment will be described with reference to FIG. FIG. 4 is a timing chart illustrating an operation example of the management system according to the first embodiment.
Here, a case will be described as an example in which an abnormality occurs in the first prescribed process in the active node NA and the standby node NX starts an alternative process relating to the first prescribed process in place of the NA.

It is assumed that the first and second defining processes are normally executed in NA and NB before time T1. FIG. 5 is an explanatory diagram illustrating a state (normal state) of each node according to the first embodiment.
Thereby, both SWA and SWB are controlled to be in the ON state, and the first and second operation states (power supply potential V) indicating normality are transmitted to LA and LB. Therefore, LDBA, LDXA, LTAB, and LDXB emit light, and the reception signals BA, XA, AB, and XB all indicate the H level (normal state).

  Further, before the time T1, since the first and second prescribed processes are normally executed, the substitute process in NX is not executed. Accordingly, SWX is controlled to be in an OFF state, and transmission of a standby system operation state (power supply potential V) indicating normality with respect to LX is stopped. Therefore, LDAX and LDBX are turned off, and the reception signals AX and BX are both at the L level.

It is assumed that at time T1, an abnormality occurs in the first specified process being executed at NA, and SWA is controlled to be in an OFF state at subsequent time T2. FIG. 6 is an explanatory diagram illustrating a state (when an abnormality occurs) of each node according to the first embodiment.
As a result, transmission of the first operating state (power supply potential V) indicating normality to LA is stopped. Therefore, LDBA and LDXA are turned off, and both BA and XA change to the L level.
The NB suspends the second specified process being executed in its own node at time T3 in response to the change of BA to the L level at time T2.

Further, in response to the change of XA to the L level at time T2, the NX starts execution of the alternative process related to the first prescribed process of NA at the subsequent time T4. FIG. 7 is an explanatory diagram illustrating a state of each node according to the first embodiment (at the time of starting the substitute process).
As a result, at the subsequent time T5, SWX is controlled to be in the ON state, and a standby system operation state (power supply potential V) indicating normality with respect to LX is transmitted. Therefore, LDAX and LDBX are turned on, and both AX and BX change to the H level.
In response to the change of BX to the H level at time T5, the NB resumes the second defining process at subsequent time T6.

[Effect of the first embodiment]
As described above, in this embodiment, the active node NA transmits the first operation state related to the first specified process to the dedicated line LA by the transmission circuit 12, and the active node NB transmits the first operation state by the transmission circuit 22. 2 is transmitted to the dedicated line LB, and the standby node NX receives the first and second operating states transmitted from the NA and NB by the receiving circuit 33 as the dedicated lines LA and LB. When either of the first and second operation states received by the reception circuit 33 indicates an abnormality, the arithmetic processing circuit 31 replaces NA and NB that are the transmission sources of the operation state. The alternative process related to the first or second defining process is executed.

  As a result, the two active nodes NA and NB can be made redundant with one standby node NX, and the amount of hardware is smaller than when the NA and NB are made redundant with dedicated standby nodes, respectively. Thus, the node can be made redundant.

  Further, in the present embodiment, a standby dedicated line LX for notifying NA and NB of the operation state of NX is further provided, and the NA operation processing circuit 11 performs a second operation related to NB received via LB. If the state indicates an abnormality, the first specified process is temporarily stopped, and then the first specified process is resumed in response to the confirmation of the start of the substitute process based on the standby system operating state of the NX received via LX. When the first operational state of the NA received via LA indicates an abnormality, the NB arithmetic processing circuit 21 temporarily stops its second prescribed processing and then receives it via LX. The second specified process is resumed in response to the confirmation of the start of the alternative process based on the NX standby system operating state.

  As a result, when an abnormality occurs in one of the first and second specified processes being executed by the NA and NB, the other specified process is temporarily stopped and replaced by NX. The other process is resumed in response to the start of the process. For this reason, when the first and second prescribed processes in NA and NB are linked to each other, it is possible to avoid the occurrence of a malfunction by executing only the other prescribed process having no abnormality, and the entire system is stable. Processing operations can be maintained.

[Second Embodiment]
Next, the management system 1 according to the second exemplary embodiment of the present invention will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration of a management system according to the second embodiment.
In the present embodiment, a description will be given of breakage handling in the dedicated lines LA, LB, and LX described in the first embodiment.

  In the present embodiment, the transmission circuit 12 of the active node NA includes a detection unit (first detection unit) LDA that detects whether or not the first operation state is transmitted to the dedicated line LA. The LDA is a light emitting diode that is connected in series to the LA and emits light when the switch element SWA is turned on. The transmission I / F circuit SIFA has a function of outputting, to the arithmetic processing circuit 11, a detection signal AA, which is detected based on the presence / absence of light emission from the LDA and that indicates the presence / absence of transmission in the first operation state for LA. About LDA, you may implement | achieve with the primary side light emitting diode of a photocoupler. Thereby, SIFA is realizable with the secondary side transistor of the said photocoupler.

  If the first operating state relating to the first defining process indicates normality but the detection unit LDA does not detect the transmission of the first operating state for the dedicated line LA, the arithmetic processing circuit 11 It has a function of determining that a disconnection has occurred in LA and stopping the first defining process, similar to the occurrence of an abnormality in the first defining process. Note that the arithmetic processing circuit 11 may notify the notification destination terminal (not shown) set in advance via the communication line E of the occurrence of LA disconnection in response to detection of LA disconnection.

  Further, the transmission circuit 22 of the active node NB includes a detection unit (second detection unit) LDB that detects whether or not the second operation state is transmitted to the dedicated line LB. The LDB is a light emitting diode that is connected in series to the LB and emits light when the switch element SWB is turned on. The transmission I / F circuit SIFB has a function of outputting, to the arithmetic processing circuit 11, a detection signal BB that is detected based on the presence / absence of light emission from the LDB and that indicates the presence / absence of transmission in the first operation state for the LB. About LDB, you may implement | achieve with the primary side light emitting diode of a photocoupler. Thereby, SIFB is realizable with the secondary side transistor of the said photocoupler.

  The arithmetic processing circuit 21, when the second operation state related to the second specified process indicates normal but the detection unit LDB does not detect the transmission of the second operation state to the dedicated line LB, It is determined that a disconnection has occurred in the LB, and has the function of stopping the second defining process, similar to the occurrence of an abnormality in the second defining process. Note that the arithmetic processing circuit 21 may notify the notification destination terminal (not shown) set in advance via the communication line E of the occurrence of the disconnection of the LB in response to the detection of the disconnection of the LB.

  In addition, the transmission circuit 32 of the standby node NX includes a detection unit (standby detection unit) LDX that detects whether or not the standby system operation state is transmitted to the dedicated line LX. The LDX is a light emitting diode that is connected in series to the LX and emits light in response to the switch element SWX being turned on. The transmission I / F circuit SIFX has a function of outputting, to the arithmetic processing circuit 31, a detection signal XX, which is detected based on the presence / absence of light emission of the LDX and which indicates the presence / absence of transmission of the standby operation state for the LX. About LDX, you may implement | achieve with the primary side light emitting diode of a photocoupler. Thereby, SIFB is realizable with the secondary side transistor of the said photocoupler.

The arithmetic processing circuit 31 indicates that a disconnection has occurred in the LX when the detection unit LDX does not detect the transmission of the standby system operating state to the dedicated line LX even though the standby system operating state related to the alternative processing indicates normal. It has a function of judging and stopping the substitute process in the same manner as the occurrence of an abnormality in the substitute process. Note that the arithmetic processing circuit 31 may notify the notification destination terminal (not shown) set in advance via the communication line E of the occurrence of the LX disconnection in response to the detection of the LX disconnection.
Other configurations according to the present embodiment are the same as those in FIG. 1, and a detailed description thereof is omitted here.

[Operation of Second Embodiment]
Next, operations of the active nodes NA and NB according to the present embodiment will be described with reference to FIG. FIG. 9 is a flowchart illustrating the redundancy control processing of the active node according to the second embodiment. Note that the redundancy control processing of the standby node NX according to the present embodiment is the same as in FIG. 3 described above, and detailed description thereof is omitted here.

  The operation processing circuits 11 and 21 of the active nodes NA and NB always execute the redundancy control process of FIG. In the following description, NA will be described, but the same applies to NB. Note that the redundancy control processing in FIG. 9 may be realized by executing a program by the CPUs of the arithmetic processing circuits 11 and 21, but a part thereof may be realized by a logic circuit.

  First, the arithmetic processing circuit 11 checks the operation state relating to the first specified process being executed, that is, the presence or absence of an abnormality (step S200). The presence / absence of an abnormality here may be confirmed based on, for example, a monitoring result related to the first specified process or an alert signal output from various circuits in the own node NA.

  When it is confirmed in step S200 that there is an abnormality (step S200: YES), the arithmetic processing circuit 11 stops the first defining process being executed (step S202) and stops outputting the transmission signal AS. The switch element SWA of the transmission circuit 12 is turned off (step S203), and the process returns to step S200. As a result, the output of the first operation state indicating the normal operation (power supply potential V) output from the NA to the dedicated line LA is stopped, and the occurrence of abnormality in the NA is detected in the NB and NX.

On the other hand, when it is confirmed that there is no abnormality in step S200 (step S200: NO), the arithmetic processing circuit 11 determines whether or not the first operation state is transmitted to LA based on the detection signal AA from the transmission circuit 12, that is, LA. Whether or not there is a disconnection is determined (step S201).
Here, when the transmission of the first operation state with respect to LA is not confirmed and it is determined that the disconnection occurs in LA (step S201: YES), the arithmetic processing circuit 11 proceeds to step S202, and the first rule is set. Similar to the case where an abnormality occurs in the process, the first specified process is stopped.

  When it is determined in step S201 that LA is not disconnected (step S201: NO), the arithmetic processing circuit 11 determines whether there is an abnormality in another operating node, that is, the NB, based on the reception signal AB from the reception circuit 13. Is confirmed (step S204). Here, when it is confirmed that there is no abnormality in the NB (step S204: NO), the process returns to step S200.

If it is confirmed in step S204 that there is an abnormality in the NB (step S204: YES), the arithmetic processing circuit 11 temporarily stops the first defining process in its own node (step S205), and then receives from the receiving circuit 13. The operation start in the standby node NX is confirmed based on the received signal AX (step S206), and the operation waits until the operation start is confirmed (step S206: NO).
When the operation start of NX is confirmed (step S206: YES), the arithmetic processing circuit 11 resumes the first specified processing operation in the own node NA (step S207), and returns to step S200.

  When a disconnection occurs in the dedicated lines LA and LB, even if the first specified process or the second specified process being executed is normal, it is detected as abnormal by the NX. According to the present embodiment, the disconnection of LA and LB is detected by the active nodes NA and NB, and the first specified process or the second specified process being executed is stopped. Collisions with an alternative process of the first or second prescribed process starting at NX are avoided.

[Operation Example of Second Embodiment]
Next, an operation example according to the present embodiment will be described with reference to FIG. FIG. 10 is a timing chart illustrating an operation example of the management system according to the second embodiment.
Here, an example will be described in which a disconnection occurs in the dedicated line LA of the active node NA and the standby node NX starts an alternative process related to the first specified process in place of the NA.

It is assumed that the first and second defining processes are normally executed in NA and NB before time T1. FIG. 11 is an explanatory diagram illustrating a state (normal state) of each node according to the second embodiment.
Thereby, both SWA and SWB are controlled to be in the ON state, and the first and second operation states (power supply potential V) indicating normality are transmitted to LA and LB. Therefore, LDBA, LDXA, LDAB, LDXB, LDA, and LDB emit light, and the reception signals BA, XA, AB, and XB and the detection signals AA and BB all indicate the H level (normal state).

  Further, before the time T1, since the first and second prescribed processes are normally executed, the substitute process in NX is not executed. Accordingly, SWX is controlled to be in an OFF state, and transmission of a standby system operation state (power supply potential V) indicating normality with respect to LX is stopped. Accordingly, LDAX, LDBX, and LDX are turned off, and the reception signals AX and BX and the detection signal XX all indicate L level.

Assume that a disconnection occurs at LA at time T1. FIG. 12 is an explanatory diagram illustrating the state of each node (when a disconnection occurs) according to the second embodiment.
As a result, the first operating state (power supply potential V) indicating normality with respect to LA does not reach NB and NX. Therefore, LDBA, LDXA, and LDA are turned off, and BA, XA, and AA all change to the L level.

In accordance with the change of AA to the L level at time T1, the NA stops the first specified process being executed in the node at time T2, and controls SWA to be in the OFF state at subsequent time T3.
The NB temporarily stops the second specified process being executed in its own node around the time T2 according to the change of the BA to the L level at the time T1.

Further, in response to the change of XA to the L level at time T1, the NX starts executing an alternative process related to the first prescribed process of NA at a subsequent time T4. FIG. 13 is an explanatory diagram illustrating the state of each node according to the second embodiment (at the start of substitution processing).
As a result, at the subsequent time T5, SWX is controlled to be in the ON state, and a standby system operation state (power supply potential V) indicating normality with respect to LX is transmitted. Therefore, LDAX, LDBX, and LDX are turned on, and AX, BX, and XX all change to the H level.
In response to the change of BX to the H level at time T5, the NB resumes the second defining process at subsequent time T6.

[Effect of the second embodiment]
As described above, in the present embodiment, the active node NA detects whether or not the transmission circuit 12 transmits the first operation state to the dedicated line LA, and the arithmetic processing circuit 11 determines that the first operation state is normal. In spite of the above, when transmission of the first operation state for LA is not detected, the first specified processing is stopped, and the active node NB causes the transmission circuit 22 to perform the second operation state for the dedicated line LB. If the second processing state indicates normal but the second operation state transmission to the LB is not detected, the second processing is stopped. It is what you do.

  According to the first embodiment described above, when a disconnection occurs in the dedicated lines LA and LB, even if the first specified process or the second specified process being executed is normal, the NX is detected as abnormal. Will be. According to the present embodiment, the disconnection of LA and LB is detected by the active nodes NA and NB, and the first specified process or the second specified process being executed is stopped. For this reason, it is possible to avoid a collision with an alternative process of the first or second prescribed process started at NX in response to the LA disconnection, and the entire system is stable against the occurrence of LA and LB disconnection. Processing operations can be maintained.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

  Further, in each of the above-described embodiments, the case where the two active nodes NA and NB are made redundant by one standby node NX has been described as an example, but this is the minimum in order to facilitate understanding of the present invention. However, the number of active nodes to be made redundant by one standby node NX is not limited to two. For example, if the number of dedicated lines is increased according to the number of active nodes, and the standby node NX monitors abnormalities in these active nodes, three or more active nodes are redundant with one standby node NX. It becomes possible to make a node redundant with a small amount of hardware.

  Further, in the first embodiment described above, the case where an abnormality occurs in the substitution process in the standby node NX is not mentioned, but the first or the first source of the substitution process executed in the NX is not mentioned. If the active nodes NA and NB that execute the second regulation process can operate normally, the first or second regulation process may be resumed with the original NA and NB as the NX alternative process. In this case, the NA and NB arithmetic processing circuits 11 and 21 that are not executing their own specifying process and can normally operate their own specifying process are received by the received signals AX and BX from the receiving circuits 13 and 23, respectively. What is necessary is just to restart own prescription | regulation processing at the time of detecting the abnormality of substitution processing in NX. Whether or not the self-defined processing can be normally operated may be set for the arithmetic processing circuits 11 and 21 by maintenance work after the occurrence of an abnormality, for example.

  Further, in the second embodiment described above, the occurrence of disconnection of the dedicated line LX is not mentioned, but the operation for executing the first or second prescribed process that is the source of the alternative process executed in the NX. If the system nodes NA and NB can operate normally, the NX substitution process may be restarted with the original NA and NB. In this case, the substitution process may be stopped when the NX arithmetic processing circuit 31 confirms the occurrence of the LX disconnection based on the detection signal XX from the transmission circuit 32. In addition, the NA and NB arithmetic processing circuits 11 and 21 that are not executing their own specifying process and can normally operate their own specifying process are NX based on the received signals AX and BX from the receiving circuits 13 and 23, respectively. When the substitute processing abnormality (LA disconnection) is detected, the self-defined processing may be resumed. Whether or not the self-defined processing can be normally operated may be set for the arithmetic processing circuits 11 and 21 by maintenance work after the occurrence of an abnormality, for example.

  DESCRIPTION OF SYMBOLS 1 ... Management system, NA, NB ... Active node, NX ... Standby node, LA, LB, LX ... Dedicated line, E ... Communication line, 11, 21, 31 ... Arithmetic processing circuit, 12, 22, 32 ... Transmission Circuit, 13, 23, 33... Reception circuit, SWA, SWB, SWX... Switch element, SIFA, SIFB, SIFX... Transmission I / F circuit, LDA, LDB, LDX. , LDXB ... Light emitting diode, RIFA, RIFB, RIFX ... Reception I / F circuit, AS, BS, XS ... Transmission signal, AA, BB, XX ... Detection signal, AB, AX, BA, BX, XA, XB ... Reception signal , V: power supply potential, GND: ground potential.

Claims (3)

A first active system node comprising a first arithmetic processing circuit for executing a first predetermined process set in advance;
A second active node comprising a second arithmetic processing circuit for executing a second prescribed process set in advance;
When an abnormality occurs in the first or second active node, a standby node that executes the first or second prescribed process in place of the active node;
A first dedicated line for notifying the second active node and the standby node of the operating state of the first active node;
A second dedicated line for notifying the operating state of the second active node to the first active node and the standby node;
The first active node includes a first transmission circuit that transmits a first operation state related to the first specified process to the first dedicated line;
The second active node includes a second transmission circuit that transmits a second operation state related to the second prescribed process to the second dedicated line,
The standby node is
A standby receiving circuit for receiving the first and second operating states transmitted from the first and second active nodes via the first and second dedicated lines, respectively;
If any of the first and second operation states received by the standby reception circuit indicates an abnormality, the first or second active node that is the transmission source of the operation state replaces the first operation node. A standby system processing circuit that executes an alternative process related to the first or second prescribed process. The management system according to claim 1,
A standby dedicated line for notifying the operating state of the standby node to the first and second active nodes;
The standby node further includes a standby transmission circuit that transmits a standby operation state related to the alternative processing to the standby dedicated line;
The first active node transmits the second operating state and the standby operating state transmitted from the second active node and the standby node to the second dedicated line and the standby dedicated node. A first receiving circuit for receiving each via the line;
The second active node indicates the first operating state and the standby operating state transmitted from the first active node and the standby node as the first dedicated line and the standby dedicated node. A second receiving circuit for receiving each via the line;
When the second operation state received by the first receiving circuit indicates an abnormality, the first arithmetic processing circuit pauses the first defining process, and then the first receiving circuit In response to the confirmation of the start of the alternative process according to the standby system operating state received in step 1, the first specified process is resumed.
When the first operation state received by the second receiving circuit indicates an abnormality, the second arithmetic processing circuit pauses the second defining process, and then the second receiving circuit. 2. The management system according to claim 1, wherein the second prescribed process is resumed in response to confirmation of the start of the alternative process according to the standby system operating state received in step (1). In the management system according to claim 1 or 2,
The first transmission circuit includes a first detection unit that detects whether or not the first operating state is transmitted to the first dedicated line,
The second transmission circuit includes a second detection unit that detects whether or not the second operation state is transmitted to the second dedicated line,
The first arithmetic processing circuit, when the first detection state is not detected by the first detection unit even though the first operation state indicates normality, Stop processing,
When the second operation state is not detected by the second detection unit even though the second operation state indicates normal, the second arithmetic processing circuit performs the second prescription. A management system characterized by stopping processing.

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