JP2019126131A - Power source device and electronic control apparatus - Google Patents

Abstract

To provide a power source device in which an output voltage ripple can be reduced, and provide an electronic control apparatus provided with the power source device.SOLUTION: A dummy load circuit 9 is connected in parallel with a load device (5b), allows a dummy load current Idmy to flow therethrough in parallel with a load current Imcu of the load device (5b) in a valid state, and does not allow the dummy load current Idmy to flow therethrough in an invalid state. A dummy load control circuit 10b controls the validating timing or invalidating timing of the dummy load circuit 9 on the basis of a switching timing of a switching control signal Sctl.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a power supply device and an electronic control device, and, for example, to a power supply device mounted on a vehicle-mounted ECU (Electronic Control Unit).

  Patent Document 1 discloses a semiconductor integrated circuit device for obtaining a stable output voltage against a sudden change in load current. The semiconductor integrated circuit device includes a stabilized power supply circuit (series regulator) that generates an internal voltage, and a normal load circuit and a dummy load circuit that operate in response to the internal voltage. The dummy load circuit supplies a predetermined current for a fixed period in response to the normal load circuit being turned off.

  Patent Document 2 discloses a DC-DC converter for preventing transition to a current non-continuous mode in a period from immediately after startup until a load occurs in normal operation. The DC-DC converter includes a dummy load and a switch element connected in series to the output terminal, and the switch element is controlled to be in an on state in a period from the start-up of the DC-DC converter to the normal load generation. Do.

JP, 2006-293802, A JP, 2006-74901, A

  In recent years, in the field of car electronics and the like, many electronic control units (referred to as ECUs) have been put to practical use for power train control, body control, safe traveling control, and the like. The ECU is usually equipped with a microcontroller (abbreviated as a microcomputer) responsible for various controls and a power supply device for generating a power supply of the microcomputer. The power supply device is, for example, a switching regulator type DC / DC converter that generates a power supply of a microcomputer based on a battery power supply.

  In microcomputers for ECUs, current consumption increases as the number of control targets increases, and switching of activation / deactivation (for example, sleep mode ON / OFF) of each control target The rate of change of current consumption is also increasing. Thus, even if the change rate of the consumption current of the microcomputer increases (when the load current rapidly increases / decreases from the viewpoint of the power supply), the power supply voltage fluctuation of the microcomputer (the viewpoint of the power supply) It is necessary to keep the output voltage ripple within the required range.

  As a technique for reducing the ripple of the output voltage, for example, as shown in Patent Document 1 and Patent Document 2, a method of providing a dummy load can be considered. However, in particular, in the case of a switching regulator, simply providing a dummy load may make it difficult to keep the ripple of the output voltage within the required range.

  The present invention has been made in view of the foregoing, and it is an object of the present invention to provide a power supply capable of reducing the ripple of an output voltage, and an electronic control unit including the power supply. .

  The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

  The outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  A power supply device according to one embodiment includes an inductor for supplying power to a load device, a switching element for storing power in the inductor when controlled to be on, and a switching control signal for controlling on / off of the switching element. And a dummy load circuit and a dummy load control circuit. The dummy load circuit is coupled in parallel with the load device, conducts dummy load current in parallel with the load current of the load device in a valid state, and does not flow dummy load current in a disabled state. The dummy load control circuit controls the activation timing or the deactivation timing of the dummy load circuit based on the switching timing of the switching control signal.

  The effects obtained by the representative embodiments of the invention disclosed in the present application can be briefly described as follows. The ripple of the output voltage can be reduced.

It is the schematic which shows the structural example of the principal part of the electronic control unit by Embodiment 1 of this invention. (A) And (b) is a timing chart explaining an example of the basic operation system at the time of reducing the total load current in the power supply device by Embodiment 1 of this invention. (A) And (b) is a timing chart explaining an example of the basic operation system at the time of increasing the total load current in the power supply device by Embodiment 1 of this invention. It is the schematic which shows the structural example of the principal part of the power supply device by Embodiment 1 of this invention. It is a timing chart which shows the operation example of the principal part of the power supply device of FIG. FIG. 5 is a circuit diagram showing a configuration example of a dummy load control circuit in FIG. 4. It is the schematic which shows the structural example of the principal part of the power supply device by Embodiment 2 of this invention. It is a timing chart which shows the operation example of the principal part of the power supply device of FIG. It is the schematic which shows the example of a structure of the current change prediction circuit in FIG. It is the schematic which shows the structural example of the principal part of the power supply device by Embodiment 3 of this invention. It is a timing chart which shows the operation example of the principal part of the power supply device of FIG. It is the schematic which shows the structural example of the principal part around a power supply device examined as a comparative example of this invention. It is a circuit block diagram which shows the more detailed structural example of the power supply device in FIG. It is a circuit diagram which shows the example of a structure of the dummy load circuit in FIG. (A) is a timing chart which shows the operation example of FIG. 12, (b) is a timing chart which shows the operation example different from (a).

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but unless specifically stated otherwise, they are not mutually unrelated, one is the other Some or all of the variations, details, supplementary explanations, etc. are in a relation. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. Except for the specific number, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated or considered to be obviously essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In all the drawings for describing the embodiments, the same reference numeral is attached to the same member in principle, and the repetitive description thereof will be omitted.

Embodiment 1
<< Outline of electronic control device >>
FIG. 1 is a schematic view showing a configuration example of a main part of an electronic control unit according to a first embodiment of the present invention. The electronic control unit 1 shown in FIG. 1 is, for example, an on-vehicle ECU. The electronic control unit 1 includes a DC / DC converter 2, a power supply unit 3, an input interface 4, a digital processing unit 5 as an example of a load unit, and a driver 6, which are mounted on a wiring board It is a structure. The digital processing device 5 is, for example, a microcontroller (microcomputer) or an FPGA (field programmable gate array).

  The DC / DC converter 2 converts a battery power supply Vbat (for example, 12 V or the like) into a power supply voltage Vin (for example, 5 V or the like). The power supply device 3 receives a power supply voltage (input voltage) Vin based on the battery power supply Vbat, and generates a predetermined output voltage (power supply voltage) Vo. The output voltage Vo is, for example, 1 V or the like. The digital processing device 5 has a predetermined function corresponding to the function of the ECU, and operates using the output voltage Vo of the power supply device 3 as a power supply.

  The digital processing device 5 includes, for example, a plurality of MPU cores 53 [1] to 53 [k], a memory 50, an analog-to-digital converter (ADC) 51, various peripheral circuits 52, and the like. The digital processing device 5 receives various sensor signals Sin from the outside of the device through the input interface 4, generates various control signals Sout corresponding thereto using program processing or the like, and sends it to the outside of the device through the driver 6 Send. Outside the apparatus, various actuators and the like that operate in response to the various control signals Sout are provided. The various sensor signals Sin are, for example, detection results of operating states of various actuators.

  In recent years, while the advancement of vehicles has been advanced, reduction of the number of ECUs mounted on the vehicle, and the like are required. For this reason, the control target by one electronic control device 1 tends to increase, and the current consumption also tends to increase. In order to suppress such an increase in current consumption, the digital processing device 5 activates only the necessary circuit blocks (for example, some MPU cores) in a necessary period, and sets unnecessary circuit blocks in the sleep mode. May have such functionality. In this case, from the viewpoint of the power supply device 3, a rapid increase or a rapid decrease in load current (current consumption of the digital processing device 5) may occur. In order for the digital processing device 5 to operate normally, it is necessary to keep the fluctuation (ripple) of the output voltage Vo within the required range, even when the load current rapidly increases or decreases.

<< Summary and problems of power supply unit (comparative example) >>
FIG. 12 is a schematic view showing a configuration example of main parts around a power supply device studied as a comparative example of the present invention. In FIG. 12, the power supply device 3a includes a high side switching element SWh, a low side switching element SW1, an inductor L1, a smoothing output capacitance C1, a switch driver 8, and a switching control circuit 7. The inductor L1 is provided between the drive node Nm and the load 11a, and supplies the power (output voltage Vo and total load current ILoad) to the load 11a.

  Switching element SWh is provided between input voltage Vin and drive node Nm, and switching element SWl is provided between drive node Nm and ground power supply voltage GND. The switching elements SWh and SWl are controlled on and off in a complementary manner. Switching element SWh stores power in inductor L1 via drive node Nm when controlled to be on. On the other hand, switching element SWl returns the power stored in inductor L1 when it is controlled to be on. The smoothing output capacitor C1 suppresses the ripple of the output voltage Vo.

  The switching control circuit 7 generates a switching control signal Sctl for controlling on / off of the switching elements SWh and SWl, and via the switching control signal Sctl so that the output voltage Vo serving as a feedback voltage matches the target voltage. Perform feedback control. The switching control signal Sctl is, for example, a PWM (Pulse Width Modulation) signal or a PFM (Pulse Frequency Modulation) signal. The switch driver 8 drives the switching elements SWh and SWl on or off based on the switching control signal Sct1 from the switching control circuit 7.

  FIG. 13 is a circuit block diagram showing a more detailed configuration example of the power supply device in FIG. In FIG. 13, the switching control circuit 7 includes an error detector 15 and a controller 16. The error detector 15 detects an error between an output voltage Vo which is a feedback voltage and a predetermined target voltage Vtg. The controller 16 generates the switching control signal Sctl so that the error detected by the error detector 15 approaches zero. Specifically, the controller 16 performs control of the PWM duty in the PWM signal, control of the PFM cycle in the PFM signal, and the like.

  The switch driver 8 includes a high side driver DVh and a low side driver DVl. The high side driver DVh operates at the power supply voltage Vcc (Vm + Vcc) based on the voltage Vm at the drive node Nm, and drives the high side switch SWh on or off according to the switching control signal Sctl. The low side driver DVl operates at the power supply voltage Vcc based on the ground power supply voltage GND, and drives the low side switch SWl off or on in response to the inverted signal of the switching control signal Sct1. Each of switching elements SWh and SWl includes a transistor (for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the like) and a free wheeling diode connected in parallel thereto. In some cases, the low side switching element SWl may be only a free wheeling diode.

  In FIG. 12, the load unit 11a includes a digital processing device (load device) 5a, a dummy load circuit 9, and a dummy load control circuit 10a. The digital processing device 5a switches its own operation mode such as the start mode, the normal operation mode, and the sleep mode, for example, based on the mode switching signal MD from the outside. The dummy load circuit 9 is coupled in parallel to the digital processing device 5a, and in the active state, passes the dummy load current Idmy in parallel with the load current Imcu of the digital processing device 5a. In the invalid state, the dummy load circuit 9 does not flow the dummy load current Idmy.

  FIG. 14 is a circuit diagram showing a configuration example of the dummy load circuit in FIG. Dummy load circuit 9 of FIG. 14 includes a plurality of transistors MN [1] to MN [n] coupled in parallel between output voltage Vo and ground power supply voltage GND, and has a function of adjusting total load current ILoad. Bear. The plurality of transistors MN [1] to MN [n] respectively pass dummy load currents Idmy [1] to Idmy [n] which become constant currents when they are turned on. The plurality of transistors MN [1] to MN [n] are individually controlled on / off by the dummy load control signals Sdmy [1] to Sdmy [n]. Thereby, the dummy load circuit 9 functions as a variable current source that variably controls the dummy load current Idmy in FIG.

  The dummy load currents Idmy [1] to Idmy [n] may have the same current value or different current values. For example, the current values of the dummy load currents Idmy [1] to Idmy [n] may be different at a ratio such as a power of two. Furthermore, although a digitally controlled variable current source that discretely controls the current value is used here, it is also possible to use an analog controlled variable current source that linearly controls the current value.

  In FIG. 12, the dummy load control circuit 10a individually controls activation / inactivation of the dummy load control signals Sdmy [1] to Sdmy [n] based on dummy load control information DCI from the outside. The dummy load control information DCI includes information etc. of the change rate (the amount of change in unit time) of the dummy load current Idmy. Dummy load control circuit 10a time-activates / deactivates dummy load control signals Sdmy [1] to Sdmy [n] such that dummy load current Idmy changes at a change rate based on dummy load control information DCI. Control sequentially.

  Fig.15 (a) is a timing chart which shows the operation example of FIG. 12, FIG.15 (b) is a timing chart which shows the operation example different from Fig.15 (a). In FIG. 15 (a), at time t1, with the switching from the normal operation mode to the sleep mode (power saving mode) based on the mode switching signal MD, the load current Imcu rapidly decreases. Therefore, at time t1, for example, three constant current sources (also referred to as dummy loads) (MN [1] to MN [3]) in the dummy load circuit 9 do not change the total load current ILoad (Imcu + Idmy). Are controlled on at the same time. As a result, the ripple of the output voltage Vo is suppressed.

  Thereafter, from time t2 to time t4, the three dummy loads (MN [1] to MN [3]) are controlled to be turned off one by one in order. At each time from time t2 to time t4, a ripple of the output voltage Vo occurs with the turning off of each dummy load. Each ripple amount at this time is suppressed to some extent by controlling the dummy loads one by one, but in some cases, it may be larger than the ripple amount at time t1.

  In FIG. 15B, at time t5, the three dummy loads (MN [1] to MN [3]) in the dummy load circuit 9 are simultaneously controlled to be turned on according to the completion of the power supply start. Thereafter, at time t6, the load current Imcu rapidly increases as the start mode is switched to the normal operation mode based on the mode switching signal MD. Therefore, at time t6, the three dummy loads (MN [1] to MN [3]) are simultaneously controlled to be off so as not to change the total load current ILoad (Imcu + Idmy). As a result, the ripple of the output voltage Vo is suppressed. However, at time t5, by simultaneously turning on the three dummy loads (MN [1] to MN [3]), a large ripple may occur in the output voltage Vo.

  Thus, using the operation example as shown in FIG. 15A and FIG. 15B, the ripple of the output voltage Vo is generated at the rapid decrease timing (time t1) or the rapid increase timing (time t6) of the load current Imcu. It can be suppressed sufficiently. However, when each dummy load is turned on or off at a timing different from the rapid decrease timing or the rapid increase timing of the load current Imcu, the ripple of the output voltage Vo may not be sufficiently suppressed. In the example of FIG. 15A, the ripple at the time of turning off the dummy load (time t2 to t4) is a problem, and in the example of FIG. 15B, the ripple at the time of turning on the dummy load (time t5) is a problem It becomes. In other words, there is a possibility that the ripple caused by the increase and decrease of the dummy load current Idmy can not be sufficiently suppressed.

<< Basic Operation Method of Power Supply Device (Embodiment 1) >>
FIGS. 2A and 2B are timing charts for explaining an example of the basic operation method when reducing the total load current in the power supply device according to the first embodiment of the present invention. FIGS. 2A and 2B show the relationships among the total load current ILoad, the inductor current IL flowing through the inductor L1, the switching control signal Sctl, and the output voltage Vo. The magnitude of the ripple of the output voltage Vo1 is the difference between the input current of the smoothing output capacitance C1, ie, the difference between the inductor current IL and the total load current ILoad (the shaded area in FIGS. 2A and 2B). Determined by). As the difference is larger, the ripple of the output voltage Vo1 is larger.

  In the example of FIG. 2A, at time t10 ', the invalidation (off) timing of the dummy load circuit 9 and the switching timing of the falling edge of the switching control signal Sctl are generated. Along with this, at time t10 ′, the total load current ILoad starts to sharply decrease, and the inductor current IL switches the control period Tcyc (for example, the PWM period) by switching the high side switching element SWh from the on period Ton to the off period Toff. And PFM cycle) is the largest. As a result, the input current of the smoothing output capacitor C1 (the area of the shaded portion in FIG. 2A) increases, and the ripple of the output voltage Vo also increases.

  On the other hand, in the example of FIG. 2B, at the time t10, the invalidation (off) timing of the dummy load circuit 9 and the switching timing of the rising edge of the switching control signal Sctl occur. Along with this, at time t10, the total load current ILoad starts to sharply decrease, and the inductor current IL becomes minimum in the control period Tcyc by switching the high side switching element SWh from the off period Toff to the on period Ton. There is. As a result, compared to the case of FIG. 2A, the input current of the smoothing output capacitor C1 (the area of the hatched portion in FIG. 2B) is smaller, so the ripple of the output voltage Vo is also smaller.

  FIGS. 3 (a) and 3 (b) are timing charts for explaining an example of the basic operation method when increasing the total load current in the power supply according to Embodiment 1 of the present invention. In the example of FIG. 3A, contrary to the case of FIG. 2A, at the time t11 ′, the activation (on) timing of the dummy load circuit 9 and the switching timing of the rising edge of the switching control signal Sct1. Is occurring. Along with this, at time t11 ′, the total load current ILoad starts to increase rapidly, and the inductor current IL becomes minimum in the control period Tcyc by switching the high side switching element SWh from the off period Toff to the on period Ton. ing. As a result, the input current of the smoothing output capacitor C1 (the area of the shaded portion in FIG. 3A) increases, and the ripple of the output voltage Vo also increases.

  On the other hand, in the example of FIG. 3B, at the time t11, the activation (on) timing of the dummy load circuit 9 and the switching timing of the falling edge of the switching control signal Sctl occur. Along with this, at time t11, the total load current ILoad starts to sharply increase, and the inductor current IL becomes maximum in the control period Tcyc by switching the high side switching element SWh from the on period Ton to the off period Toff. There is. As a result, as compared with the case of FIG. 3A, the input current of the smoothing output capacitor C1 (the area of the shaded portion in FIG. 3B) is smaller, so the ripple of the output voltage Vo is also smaller.

  Based on the principle as described above, the power supply device according to the first embodiment controls the enabling timing or the disabling timing of the dummy load circuit 9 based on the switching timing of the switching control signal Sct1. That is, the power supply apparatus controls the time t2 to t4 shown in FIG. 15A and the time t5 shown in FIG. 15B based on the switching timing of the switching control signal Sctl.

  Specifically, for example, when increasing the total load current ILoad as shown at time t5 in FIG. 15 (b), the power supply apparatus changes the switching element SWh from on to off as shown in FIG. 3 (b). The dummy load circuit 9 in the invalid state is validated according to the switching timing (the falling edge of the switching control signal Sctl). On the other hand, for example, when reducing the total load current ILoad as shown in FIG. 15 (a) from time t2 to t4, the power supply device switches the switching element SWh from off to on as shown in FIG. 2 (b). The dummy load circuit 9 in the valid state is invalidated according to the timing (rising edge of the switching control signal Sct1). This makes it possible to reduce the ripple of the output voltage Vo.

<< Configuration of Power Supply Device (Embodiment 1) >>
FIG. 4 is a schematic diagram showing an example of configuration of a main part of the power supply device according to Embodiment 1 of the present invention. The power supply device shown in FIG. 4 differs from the configuration example of FIG. 12 in the configuration of the load unit 11 b. The load unit 11b includes a digital processing device 5b, a dummy load circuit 9, and a dummy load control circuit 10b. The configuration and operation of dummy load circuit 9 are the same as in the case of FIG.

  The digital processing device 5b is, for example, a microcomputer, and unlike the digital processing device 5a of FIG. 12, generates the load surge signal LUP, the load surge signal LDN, and the dummy load control information DCI. The load surge signal LUP is a signal that is activated at a timing earlier than the spike timing of the load current Imcu and is deactivated at the spike timing. The rapid decrease in load signal LDN is a signal activated at the rapid decrease timing of the load current Imcu and inactivated at a timing later than the rapid decrease timing. The digital processing device 5b can generate the load spike signal LUP and the load spike signal LDN based on the switching timing of its own operation mode (for example, sleep mode, normal operation mode, etc.).

  The dummy load control information DCI is information that indicates each change amount and each change rate (change amount in unit time) when the dummy load current Idmy is rapidly increased or decreased rapidly. For example, the amount of change and the rate of change when the dummy load current Idmy is rapidly increased are set to values that offset the amount of change and the rate of change caused by the rapid decrease of the load current Imcu. Conversely, the amount of change and the rate of change when the dummy load current Idmy is sharply reduced are set to values that offset the amount of change and the rate of change associated with the rapid increase of the load current Imcu. The digital processing device 5b can generate such dummy load control information DCI by, for example, storing in advance each change amount and each change rate associated with a rapid increase or a rapid decrease of its own load current Imcu.

  Unlike the dummy load control circuit 10a of FIG. 12, the dummy load control circuit 10b adds the switching control signal Sctl from the switching control circuit 7 in addition to the load surge signal LUP, the load rapid decrease signal LDN, and the dummy load control information DCI. In response, dummy load control signals Sdmy [1] to Sdmy [n] to dummy load circuit 9 are generated. At this time, as described with reference to FIGS. 2B and 3B, the dummy load control circuit 10b selects one of the dummy load control signals Sdmy [1] to Sdmy [] based on the switching timing of the switching control signal Sct1. n] to control the enabling timing or the disabling timing of the dummy load circuit 9. The dummy load control circuit 10b may receive the dummy load control information DCI from a place other than the digital processing device 5b as in the case of FIG.

  Here, the dummy load circuit 9 and the dummy load control circuit 10b are mounted as one package component 12 together with, for example, the switching elements SWh and SW1, the switch driver 8 and the switching control circuit 7. Thereby, the mounting area in the electronic control unit 1 of FIG. 1 can be reduced, and by combining the package parts 12 with various digital processing units, it is possible to obtain a ripple reduction effect. However, in some cases, the dummy load circuit 9 and the dummy load control circuit 10b may be mounted in the digital processing device 5b, or may be mounted as package parts independent of the digital processing device 5b, the switching control circuit 7, etc. Is also possible.

<< Operation of Power Supply Device (Embodiment 1) >>
FIG. 5 is a timing chart showing an operation example of the main part of the power supply device of FIG. In FIG. 5, time t16 is the spike timing of the load current Imcu. The digital processing device 5b shifts from, for example, the sleep mode to the normal operation mode at the rapid increase timing. Since the digital processing device 5b can grasp the spike timing (time t16) in advance, it generates a load spike signal LUP which is activated at a timing earlier by a predetermined time T1 than the spike timing and deactivated at the spike timing. It is possible.

  Dummy load control circuit 10 b responds to switching timing of switching control signal Sct1 (in this example, the first falling edge timing) after activation of load surge signal LUP at time t15 prior to time t16. , And enable the dummy load circuit 9 in the invalid state. In the specification, the falling edge timing of the switching control signal Sctl (the switching element SWh is switched from on to off) after the load surge signal LUP is activated before the load current Imcu increases rapidly as at time t15. Timing) is called pre-timing.

  In this example, the dummy load control circuit 10b first activates the dummy enabling signal ENdmy, which is an internal signal, at advance timing (time t15). Then, the dummy load control circuit 10b activates a plurality of (three in this example) dummy load control signals Sdmy [1] to Sdmy [3] in response to the activation of the dummy validation signal ENdmy, and outputs three dummy load control signals Sdmy [1] to Sdmy [3]. The dummy loads (MN [1] to MN [3] in FIG. 14) are controlled to be on. Thereby, the dummy load control circuit 10b increases the dummy load current Idmy from zero to a predetermined current setting value. The predetermined current setting value (that is, the number of dummy loads controlled to be on) is determined based on the change amount of the load current Imcu included in the above-described dummy load control information DCI when the load current Imcu increases.

  As described above, at time t15, the power supply device enables the dummy load circuit 9 at the falling edge of the switching control signal Sct1 to rapidly increase the total load current ILoad (Imcu + Idmy). Therefore, as described in FIG. 3B, it is possible to reduce the ripple of the output voltage Vo as compared to the case where the switching control signal Sct1 is not used.

  At time t16 after time t15, for example, the load current Imcu increases rapidly along with the transition from the sleep mode of the digital processing device 5b to the normal operation mode. The dummy load control circuit 10b invalidates the dummy load circuit 9 in the valid state according to the rapid increase timing (time t16) of the load current Imcu. In this example, the dummy load control circuit 10b first deactivates the dummy enabling signal ENdmy in response to the deactivation of the load surge signal LUP. Then, the dummy load control circuit 10b deactivates the plurality of (three) dummy load control signals Sdmy [1] to Sdmy [3] in order in response to the deactivation of the dummy validation signal ENdmy, and the three dummy The dummy loads (MN [1] to MN [3] in FIG. 14) are sequentially controlled to be off.

  Thereby, the dummy load control circuit 10b reduces the dummy load current Idmy from the predetermined current setting value to zero at a preset change rate. The change rate is set to a value that cancels out the change rate at the time of rapid increase of the load current Imcu included in the above-described dummy load control information DCI. The dummy load control circuit 10b controls three dummy loads to be turned off via the dummy load control signals Sdmy [1] to Sdmy [3] so that the dummy load current Idmy decreases at the set change rate. Determine the timing to do and the order.

  As described above, at time t16, the dummy load current Idmy, which has been made to flow in advance at the pre-timing (time t15), is replaced with an increase in the load current Imcu. The replacement at this time is performed such that an increase in load current Imcu is canceled by a decrease in dummy load current Idmy. As a result, the total load current ILoad does not change, and since the total load current ILoad and the inductor current IL are already in a balanced state, almost no ripple of the output voltage Vo occurs.

  In FIG. 5, time t17 is the rapid decrease timing of the load current Imcu. The digital processing device 5b shifts from the normal operation mode to the sleep mode, for example, at the rapid decrease timing. Since the digital processing device 5b can grasp the rapid decrease timing (time t17), the digital processing device 5b generates the load rapid decrease signal LDN which is activated at the rapid decrease timing and inactivated at a timing later by a predetermined time T2 than the rapid decrease timing. Is possible.

  At time t17, for example, the load current Imcu decreases rapidly with the shift from the normal operation mode of the digital processing device 5b to the sleep mode. The dummy load control circuit 10b enables the dummy load circuit 9 in the invalid state according to the rapid decrease timing (time t17) of the load current Imcu. In this example, the dummy load control circuit 10b first activates the dummy enabling signal ENdmy, which is an internal signal, in response to the activation of the rapid load reduction signal LDN. Then, the dummy load control circuit 10b sequentially activates a plurality of (three) dummy load control signals Sdmy [1] to Sdmy [3] in response to the activation of the dummy validation signal ENdmy, and the three dummy The loads (MN [1] to MN [3] in FIG. 14) are sequentially controlled to be on.

  Thereby, the dummy load control circuit 10b increases the dummy load current Idmy from zero to a predetermined current setting value at a preset change rate. The predetermined current setting value (that is, the number of dummy loads controlled to be on) is determined based on the amount of change at the time of rapid decrease of the load current Imcu included in the above-described dummy load control information DCI. Further, the rate of change is set to a value that cancels out the rate of change when the load current Imcu included in the above-described dummy load control information DCI is sharply reduced. The dummy load control circuit 10b controls three dummy loads to be turned on via the dummy load control signals Sdmy [1] to Sdmy [3] so that the dummy load current Idmy increases at the set change rate. Determine the timing to do and the order.

  Thus, at time t17, the decrease of the load current Imcu is replaced with the dummy load current Idmy. The replacement at this time is performed such that the decrease of the load current Imcu is sequentially canceled by the increase of the dummy load current Idmy. As a result, the total load current ILoad does not change, and since the total load current ILoad and the inductor current IL are in a balanced state, almost no ripple of the output voltage Vo occurs.

  At time t18 later than time t17, the dummy load control circuit 10b responds to the switching timing of the switching control signal Sctl (in this example, the first rising edge) after the load reduction signal LDN is deactivated. The dummy load circuit 9 in the valid state is invalidated. In the specification, the rising edge timing of the switching control signal Sct (the switching element SWh is switched from off to on) after the load reduction signal LDN is inactivated after the load current Imcu decreases sharply as at time t18. Timing is called post-timing.

  In this example, the dummy load control circuit 10b first deactivates the dummy enabling signal ENdmy at the post-timing (time t18). Then, the dummy load control circuit 10b deactivates the plurality (three in this example) of dummy load control signals Sdmy [1] to Sdmy [3] in response to the deactivation of the dummy validation signal ENdmy, 3 Control each dummy load (MN [1] to MN [3] in FIG. 14) to OFF. Thereby, the dummy load control circuit 10b reduces the dummy load current Idmy from the predetermined current setting value to zero.

  As described above, at time t18, the power supply apparatus invalidates the dummy load circuit 9 at the rising edge of the switching control signal Sct1 to sharply reduce the total load current ILoad (Imcu + Idmy). Therefore, as described in FIG. 2B, it is possible to reduce the ripple of the output voltage Vo as compared with the case where the switching control signal Sctl is not used.

  In the example of FIG. 5, at time t15, the dummy load control signals Sdmy [1] to Sdmy [3] are simultaneously activated according to the falling edge of the switching control signal Sctl. However, when the fixed period T1 can be extended to a certain extent, it is also possible to activate them separately not simultaneously. That is, for example, the dummy load control signal Sdmy [1] is activated in response to the falling edge of a certain control cycle, and the dummy load control signal Sdmy [2] is activated in response to the falling edge of the next control cycle. It is also possible to perform such control. The same applies to time t18 in FIG.

<< Configuration of dummy load control circuit >>
FIG. 6 is a circuit diagram showing a configuration example of the dummy load control circuit in FIG. The dummy load control circuit 10b of FIG. 6 includes flip flops FF1 and FF2, an AND gate AD1, OR gates OR1 and OR2, and a slew rate control circuit 18. The flip flop FF1 latches the load spike signal LUP from the digital processing device 5b at the falling edge of the switching control signal Sct1. The AND gate AD1 performs an AND operation on the load surge signal LUP and the output signal from the flip flop FF1.

  The flip flop FF2 latches the rapid load reduction signal LDN from the digital processing device 5b at the rising edge of the switching control signal Sct1. The OR gate OR1 performs an OR operation on the rapid drop in load signal LDN and the output signal from the flip flop FF2. The OR gate OR2 performs the OR operation on the AND operation result of the AND gate AD1 and the OR operation result of the OR gate OR1 to generate the dummy validation signal ENdmy shown in FIG.

  The slew rate control circuit 18 uses the dummy validation signal ENdmy, the result of the OR operation of the OR gate OR1, and the dummy load control information DCI from the digital processing device 5b, as shown in FIG. Sdmy [1] to Sdmy [n] are appropriately controlled. The OR operation result of the OR gate OR1 is used to distinguish whether the activation of the dummy enabling signal ENdmy is a rapid increase or a rapid decrease of the load current Imcu. However, the dummy load control information DCI associated with each activation of the load surge signal LUP is input in parallel, and the dummy load control information DCI associated with each activation of the load rapid decrease signal LDN is input in parallel. In this case, since it is possible to distinguish between the rapid increase and the rapid decrease by the dummy load control information DCI, the OR operation result of the OR gate OR1 is unnecessary.

<< Main effects of Embodiment 1 >>
As described above, in the method of the first embodiment, since the enabling / disabling timing of the dummy load circuit 9 is determined based on the switching control signal Sct1, it is possible to reduce the ripple of the output voltage Vo. As a result, for example, in an on-vehicle electronic control unit (ECU) or the like, the reliability (safety) can be improved and the large change in load current can be coped with. Expansion etc. can be planned.

Second Embodiment
<< Configuration of Power Supply Device (Second Embodiment) >>
FIG. 7 is a schematic diagram showing an example of configuration of a main part of a power supply device according to Embodiment 2 of the present invention. The power supply device shown in FIG. 7 is similar to that of FIG. 12 in that the current detection circuit 20 and the current change prediction circuit 21 are provided in the load section 11 c as compared with the configuration example of FIG. Is different from the point where it is provided. In the configuration example of FIG. 4, the digital processing device 5 b generates the load spike signal LUP, the load spike signal LDN, and the dummy load control information DCI. When using the digital processing device 5a which can not generate such a signal, it is useful to use the power supply device of FIG.

  In FIG. 7, the current detection circuit 20 includes, for example, a shunt resistor serving as a current sensor, or a current transformer, and detects the load current Imcu of the digital processing device 5a. The current change prediction circuit 21 determines whether or not the change rate of the load current Imcu detected by the current detection circuit 20 has reached a predetermined threshold value for rapid decrease determination and a threshold value for rapid increase determination. The rapid decrease timing and the rapid increase timing of the load current Imcu are respectively determined. Then, the current change prediction circuit 21 is activated after the rapid decrease timing and is deactivated at a timing later than the rapid decrease timing, and after a predetermined period determined in advance from the load rapid decrease signal LDN has elapsed. A load surge signal LUP which is activated and deactivated at the surge timing is generated.

  Similar to the case of FIG. 4, the dummy load control circuit 10b determines the post-surge timing after the rapid decrease based on the switching timing of the switching control signal Sct after the load rapid decrease signal LDN is inactivated, and the load surge signal LUP Based on the switching timing of the switching control signal Sct1 after activation, the prior timing before the surge is determined. The current detection circuit 20 and the current change prediction circuit 21 are mounted on, for example, the same package parts (symbol 12 in FIG. 4) as the switching control circuit 7 and the like, as in the case of FIG. However, it is also possible to mount these on the digital processing device 5a or as an independent part.

<< Operation of Power Supply Device (Embodiment 2) >>
FIG. 8 is a timing chart showing an operation example of the main part of the power supply device of FIG. At time t20, when the digital processing device 5a shifts from the normal operation mode to the sleep mode, for example, the rapid decrease of the load current Imcu starts. As described above, when shifting from the normal operation mode to the sleep mode, the change rate of the load current Imcu (change amount in unit time) (di / dt) becomes minimum (maximum on the negative electrode side).

  In the current change prediction circuit 21, a rapid decrease determination threshold value ΔIth1 for determining whether or not the minimum change rate occurs is set in advance. At time t21, the current change prediction circuit 21 determines that the rate of change of the load current Imcu has reached a predetermined rapid decrease determination threshold value ΔIth1, and activates the rapid decrease signal LDN with the point of time as the rapid decrease timing. . Thereafter, the current change prediction circuit 21 deactivates the rapid decrease in load signal LDN after a predetermined constant period T3 has elapsed.

  Dummy load control circuit 10b receives dummy load control signals Sdmy [1] to Sdmy [3] at time t21 (sudden decrease timing) in accordance with activation of load rapid decrease signal LDN as in the case of time t17 in FIG. Activate sequentially. As a result, at the time of rapid decrease of the load current Imcu (time t20, t21), almost no ripple of the output voltage Vo occurs as in the case of time t17 in FIG. Thereafter, at time t22 (post-timing), the dummy load control circuit 10b deactivates the rapid reduction signal LDN and switches the switching control signal Sctl (rising edge timing), as in the case of time t18 in FIG. And deactivate the dummy load control signals Sdmy [1] to Sdmy [3]. As a result, at time t22 (post-timing), the ripple of the output voltage Vo can be reduced as in the case of time t18 in FIG.

  On the other hand, the current change prediction circuit 21 activates the load surge signal LUP after the elapse of a predetermined fixed period T4 after deactivating the load rapid decrease signal LDN. After that, at time t24, the digital processing device 5a shifts from, for example, the sleep mode to the normal operation mode, so that the rapid increase of the load current Imcu starts. Thus, when transitioning from the sleep mode to the normal operation mode, the change rate of the load current Imcu (the amount of change in unit time) (di / dt) becomes maximum. In the current change prediction circuit 21, a threshold value ΔIth <b> 2 for rapid increase determination for determining whether or not the maximum rate of change occurs is set in advance. At time t25, the current change prediction circuit 21 determines that the rate of change of the load current Imcu has reached a predetermined threshold value ΔIth2 for rapid determination, and deactivates the load rapid signal LUP with the timing as the rapid timing. Do.

  Dummy load control circuit 10b activates activation of load surge signal LUP and switching timing (falling edge timing) of switching control signal Sctl at time t23 (preliminary timing) as in the case of time t15 in FIG. 5. Based on this, the dummy load control signals Sdmy [1] to Sdmy [3] are activated. As a result, at time t23 (preliminary timing), it is possible to reduce the ripple of the output voltage Vo as in the case of time t15 in FIG. Thereafter, dummy load control circuit 10b receives dummy load control signals Sdmy [1] to Sdmy [] at time t25 (surge timing) in response to inactivation of load surge signal LUP, as in the case of time t16 in FIG. 3) sequentially inactivate. As a result, at the time of rapid increase of the load current Imcu (time t24, t25), almost no ripple of the output voltage Vo occurs as in the case of time t16 in FIG.

  Here, the fixed period T4 in FIG. 8 is set to, for example, a length corresponding to the shortest period in the specification required from the transition timing to the sleep mode to the return timing to the normal operation mode. As a result, after the dummy load is always controlled to be turned on according to the end timing of the fixed period T4 (after time t23), the return timing (time t24) to the normal operation mode is generated. In addition, the length of the period from time t23 to time t24 may change suitably according to actual use. In this period, the dummy load current Idmy flows in the dummy load as a preparation state for return to the normal operation mode.

<< Configuration of current change prediction circuit >>
FIG. 9 is a schematic diagram showing a configuration example of the current change prediction circuit in FIG. The current change prediction circuit 21 includes, for example, a rapid decrease determination circuit 30, a rapid increase determination circuit 31, timer circuits 32 and 33, and set / reset latch circuits SRLT1 and SRLT2. The rapid decrease determination circuit 30 receives the detection result of the current detection circuit 20 (i.e., the load current Imcu) and determines whether or not the rate of change has reached a predetermined rapid decrease determination threshold ΔIth1. Output an 'H' pulse signal. Specifically, the rapid decrease determination circuit 30 compares, for example, the difference value between two load currents Imcu acquired at two consecutive timings with the rapid decrease determination threshold value ΔIth1.

  The timer circuit 32 starts the counting operation in response to the rising edge of the output of the rapid decrease judging circuit 30, and outputs the 'H' pulse signal when counting the constant period T3 shown in FIG. The set reset latch circuit SRLT1 receives the 'H' pulse signal from the rapid decrease determination circuit 30 to activate the load rapid decrease signal LDN, and receives the H 'pulse signal from the timer circuit 32 to deactivate the load rapid decrease signal LDN. .

  The timer circuit 33 starts the count operation in response to the falling edge of the output of the set / reset latch circuit SRLT1 and outputs the 'H' pulse signal when counting the fixed period T4 shown in FIG. Surging determination circuit 31 receives the detection result of current detection circuit 20 (i.e., load current Imcu), and determines whether or not the rate of change has reached a predetermined threshold value ΔIth2 for determining whether a surge is predetermined. Output an 'H' pulse signal. The set / reset latch circuit SRLT2 receives the 'H' pulse signal from the timer circuit 33 to activate the load spike signal LUP, and receives the 'H' pulse signal from the spike determination circuit 31 to deactivate the load spike signal LUP. Do.

<< Main effects of Embodiment 2 >>
As described above, by using the method of the second embodiment, the same effect as that of the first embodiment can be obtained. Furthermore, even when the digital processing device 5a can not generate the rapid decrease signal LDN or the rapid increase signal LUP, a desired effect can be obtained.

Third Embodiment
<< Configuration of Power Supply Device (Third Embodiment) >>
FIG. 10 is a schematic diagram showing an example of configuration of a main part of the power supply device according to Embodiment 3 of the present invention. Compared to the configuration example of FIG. 7, the power supply device shown in FIG. 10 is provided with a reset control circuit 25 instead of the current detection circuit 20 and the current change prediction circuit 21 in the load section 11d. It differs from the case where a different digital processing device 5d is provided. For example, the digital processing device 5d may operate in the sleep mode while the reset signal RST is activated, and may shift to the normal operation mode when the reset signal RST is inactivated.

  Assuming that the digital processing device 5d as described above, the reset control circuit 25 supplies a reset signal RST to the digital processing device 5d, and the rapid reduction timing of the load current Imcu based on the activation timing and the deactivation timing of the reset signal RST. And the spike timing. Then, the reset control circuit 25 is activated at the rapid decrease timing and is deactivated at a later timing than the rapid decrease timing, and the rapid decrease signal LDN activated at a later timing than the rapid increase timing. A load surge signal LUP to be activated is generated.

  As in the case of FIG. 7, the dummy load control circuit 10b determines the post-surgeing post-timing based on the switching timing of the switching control signal Sct after the load reduction signal LDN is deactivated, and the load surge signal LUP Based on the switching timing of the switching control signal Sct1 after activation, the prior timing before the surge is determined. For example, an electronic control unit (ECU) as shown in FIG. 1 may be provided with a monitoring device for monitoring the presence or absence of an abnormality or the like of the digital processing device 5d. The reset control circuit 25 can be implemented, for example, in such a monitoring device.

<< Operation of Power Supply Device (Third Embodiment) >>
FIG. 11 is a timing chart showing an operation example of the main part of the power supply device of FIG. At time t30, the reset control circuit 25 activates the reset signal RST. In response to this, the digital processing device 5d shifts, for example, from the normal operation mode to the sleep mode, and the rapid decrease of the load current Imcu starts. The reset control circuit 25 recognizes the activation timing of the reset signal RST as the rapid reduction timing of the load current Imcu to activate the rapid load reduction signal LDN, and deactivates the rapid load reduction signal LDN after a predetermined constant period T5.

  Dummy load control circuit 10b receives dummy load control signals Sdmy [1] to Sdmy [3] at time t30 (sudden decrease timing) in accordance with activation of load rapid decrease signal LDN as in the case of time t17 in FIG. Activate sequentially. As a result, when the load current Imcu rapidly decreases (time t30), almost no ripple of the output voltage Vo occurs as in the case of time t17 in FIG. After that, at time t31 (post-timing), the dummy load control circuit 10b deactivates the load reduction signal LDN and the switching timing of the switching control signal Sctl (rising edge timing) as in the case of time t18 in FIG. In response to this, the dummy load control signals Sdmy [1] to Sdmy [3] are inactivated. As a result, at time t31 (post-timing), the ripple of the output voltage Vo can be reduced as in the case of time t18 in FIG.

  Thereafter, the reset control circuit 25 deactivates the reset signal RST at time t33 (surge timing). In response to this, the digital processing device 5d shifts, for example, from the sleep mode to the normal operation mode, and the surge of the load current Imcu starts. When the load current Imcu increases rapidly, the reset control circuit 25 activates the load increase signal LUP at time t32, which is a predetermined period T6 before the time t33, and the load increase signal at time t33 thereafter. Deactivate LUP.

  Dummy load control circuit 10 b activates activation of load surge signal LUP and switching timing (falling edge timing) of switching control signal Sctl at time t 32 (preliminary timing) as in the case of time t 15 in FIG. 5. In response, dummy load control signals Sdmy [1] to Sdmy [3] are activated. As a result, at time t32 (prior timing), it is possible to reduce the ripple of the output voltage Vo as in the case of time t15 in FIG. Thereafter, dummy load control circuit 10b receives dummy load control signals Sdmy [1] to Sdmy [] at time t33 (surge timing) in response to inactivation of load surge signal LUP, as in the case of time t16 in FIG. 3) sequentially inactivate. As a result, at the time of rapid increase of the load current Imcu (time t33), almost no ripple of the output voltage Vo occurs as in the case of time t16 of FIG.

<< Main effects of Embodiment 3 >>
As described above, by using the method of the third embodiment, the same effect as that of the third embodiment can be obtained. Moreover, since the current detection circuit 20 is not required compared to the case of the second embodiment, for example, power loss associated with a current sensor (such as a shunt resistor) does not occur. Furthermore, in the case of the second embodiment, there is a possibility that the problem of current consumption may occur depending on the length of the period from time t23 to time t24 in FIG. 8, but in the method of the third embodiment, such a problem is It does not occur.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. For example, the above-described embodiments are described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the described configurations. Also, part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, with respect to a part of the configuration of each embodiment, it is possible to add, delete, and replace other configurations.

  For example, the power supply apparatus of each embodiment is widely applicable as an apparatus for supplying power to a load having a large sudden change in load as well as an on-vehicle ECU.

1 electronic control unit 3, 3a power supply unit 5, 5a, 5b, 5d digital processing unit 7 switching control circuit 8 switch driver 9 dummy load circuit 10a, 10b dummy load control circuit 11b, 11c load part 12 package parts 20 current detection circuit 21 Current change prediction circuit 25 Reset control circuit C Smoothing output capacity DCI Dummy load control information IL Inductor current ILoad Total load current Idmy Dummy load current Imcu Load current L Inductor LDN Load sharpening signal LUP Load surge signal RST Reset signal SW Switching element Sctl switching Control signal Sdmy Dummy load control signal Tcyc control cycle Toff off period Ton on period Vbat battery power supply Vo output voltage ΔIth1 threshold for rapid decrease judgment ΔIth2 rapid increase Judgment threshold

Claims (15)

An inductor for supplying power to a load device having a predetermined function;
A switching element for storing power in the inductor when controlled to be on;
A dummy load circuit coupled in parallel with the load device, supplying a dummy load current in parallel with the load current of the load device in a valid state, and not flowing the dummy load current in a disabled state;
A switching control circuit that generates a switching control signal for controlling on / off of the switching element;
A dummy load control circuit that controls an activation timing or an deactivation timing of the dummy load circuit based on a switching timing of the switching control signal;
Power supply device. In the power supply device according to claim 1,
The dummy load control circuit validates the dummy load circuit in the invalid state according to an advance timing at which the switching element switches from on to off before the load current rapidly increases. The dummy load circuit in the valid state is invalidated in accordance with the rapid increase timing at which the current rapidly increases.
Power supply. In the power supply device according to claim 2,
The dummy load circuit includes a variable current source that variably controls the dummy load current, and when activated according to the advance timing, increases the dummy load current from zero to a predetermined current setting value. The dummy load current is decreased from the predetermined current setting value to zero at a preset first rate of change when being invalidated according to the rapid increase timing.
Power supply. In the power supply device according to claim 3,
The first rate of change is set to a value that cancels out the rate of change associated with the rapid increase of the load current.
Power supply. In the power supply device according to claim 2,
The load device generates a load surge signal that is activated earlier than the spike timing and deactivated at the spike timing.
The dummy load control circuit determines the advance timing based on the switching timing of the switching control signal after the load surge signal is activated.
Power supply. In the power supply device according to claim 1,
The dummy load control circuit enables the dummy load circuit in the invalid state in response to a rapid decrease timing at which the load current sharply decreases, and the switching element is turned on after the load current rapidly decreases. Disabling the dummy load circuit in the valid state according to the post-timing that is the switching timing of
Power supply. In the power supply device according to claim 6,
The dummy load circuit includes a variable current source that variably controls the dummy load current, and the dummy load current is preset from zero to a predetermined current setting value when activated in accordance with the rapid decrease timing. The dummy load current is decreased from the predetermined current setting value to zero when increased at a second rate of change and disabled according to the post-timing,
Power supply. In the power supply device according to claim 7,
The second rate of change is set to a value that cancels out the rate of change associated with the rapid decrease of the load current.
Power supply. In the power supply device according to claim 6,
The load device generates a load reduction signal that is activated at the rapid reduction timing and deactivated at a timing later than the rapid reduction timing.
The dummy load control circuit determines the post-timing based on the switching timing of the switching control signal after the load reduction signal is deactivated.
Power supply. In the power supply device according to claim 1,
The dummy load control circuit
The dummy load circuit in the invalid state is validated according to the prior timing of the switching timing from on to off of the switching element before the load current jumps, and the jump of the load current jumps timing. Disable the dummy load circuit in the valid state according to the timing;
The dummy load circuit in the invalid state is validated according to a sudden decrease timing at which the load current suddenly decreases, and a post-timing at which the switching element switches from off to on after the load current suddenly decreases Disable the dummy load circuit in the valid state according to
Power supply. The power supply device according to claim 10, further comprising:
A current detection circuit that detects the load current;
The rapid decrease timing and the rapid increase timing are determined by determining whether the change rate of the load current detected by the current detection circuit has reached a predetermined rapid decrease determination threshold and a rapid increase determination threshold. A load rapid decrease signal activated and delayed at a timing later than the rapid decrease timing, and a predetermined signal predetermined from the load rapid decrease signal are activated and are not activated at the rapid increase timing. A current change prediction circuit that generates an activated load surge signal;
Have
The dummy load control circuit determines the post-timing based on the switching timing of the switching control signal after the load reduction signal is deactivated, and the switching control after the load surge signal is activated. Determining the pre-timing based on the switching timing of the signal,
Power supply. In the power supply device according to claim 10,
Furthermore, a reset signal is supplied to the load device, and the rapid decrease timing and the rapid increase timing are respectively determined based on the activation timing and the inactivation timing of the reset signal, and activated at the rapid decrease timing and later than the rapid decrease timing. It has a reset control circuit that generates a load sharpening signal that is deactivated at timing and a load spike signal that is activated at a timing earlier than the surge timing and deactivated at the spike timing.
The dummy load control circuit determines the post-timing based on the switching timing of the switching control signal after the load reduction signal is deactivated, and the switching control after the load surge signal is activated. Determining the pre-timing based on the switching timing of the signal,
Power supply. A power supply device that generates a predetermined power supply based on a battery power supply;
A load device which has a predetermined function and is operated by the power supply from the power supply device;
An electronic control device having
The power supply device
An inductor for supplying power to the load device;
A switching element for storing power in the inductor when controlled to be on;
A dummy load circuit coupled in parallel with the load device, supplying a dummy load current in parallel with the load current of the load device in a valid state, and not flowing the dummy load current in a disabled state;
A switching control circuit that generates a switching control signal for controlling on / off of the switching element;
A dummy load control circuit that controls an activation timing or an deactivation timing of the dummy load circuit based on a switching timing of the switching control signal;
An electronic control unit having In the electronic control unit according to claim 13,
The dummy load control circuit
The dummy load circuit in the invalid state is validated according to the prior timing of the switching timing from on to off of the switching element before the load current jumps, and the jump of the load current jumps timing. Disable the dummy load circuit in the valid state according to the timing;
The dummy load circuit in the invalid state is validated according to a sudden decrease timing at which the load current suddenly decreases, and a post timing at which the switching element switches from off to on after the load current suddenly decreases Disable the dummy load circuit in the valid state according to
Electronic control unit. In the electronic control unit according to claim 14,
The load device is activated at a timing earlier than the spike timing and is activated at the spike timing, and is activated at the spike timing and is deactivated at a timing later than the spike timing. Generate a sudden decrease signal and
The dummy load control circuit determines the prior timing based on the switching timing of the switching control signal after the load surge signal is activated, and the switching control after the load surge signal is deactivated. Determining the post-timing based on the switching timing of the signal,
Electronic control unit.

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