JP2019121404A5 - - Google Patents

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JP2019121404A5
JP2019121404A5 JP2019001636A JP2019001636A JP2019121404A5 JP 2019121404 A5 JP2019121404 A5 JP 2019121404A5 JP 2019001636 A JP2019001636 A JP 2019001636A JP 2019001636 A JP2019001636 A JP 2019001636A JP 2019121404 A5 JP2019121404 A5 JP 2019121404A5
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JP
Japan
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fpga
graph
implementation
similar
design
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JP2019001636A
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Japanese (ja)
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JP2019121404A (ja
JP7065794B2 (ja
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Priority claimed from DE102018100423.0A external-priority patent/DE102018100423A1/de
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JP2019001636A 2018-01-10 2019-01-09 グラフベースの類似度検索を用いたｆｐｇａ実装のインクリメンタル方式による生成 Active JP7065794B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102018100423.0A DE102018100423A1 (de) 2018-01-10 2018-01-10 Inkrementelles Generieren einer FPGA Implementierung mit Graphen-basierter Ähnlichkeitssuche
DE102018100423.0 2018-01-10

Publications (3)

Publication Number Publication Date
JP2019121404A JP2019121404A (ja) 2019-07-22
JP2019121404A5 true JP2019121404A5 (https=) 2021-12-23
JP7065794B2 JP7065794B2 (ja) 2022-05-12

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JP2019001636A Active JP7065794B2 (ja) 2018-01-10 2019-01-09 グラフベースの類似度検索を用いたｆｐｇａ実装のインクリメンタル方式による生成

Country Status (4)

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US (1) US10706196B2 (https=)
JP (1) JP7065794B2 (https=)
CN (1) CN110020456B (https=)
DE (1) DE102018100423A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111353182B (zh) * 2020-03-11 2023-05-05 电子科技大学 一种面向fpga芯片的网表环路识别方法
US20220321403A1 (en) * 2021-04-02 2022-10-06 Nokia Solutions And Networks Oy Programmable network segmentation for multi-tenant fpgas in cloud infrastructures
CN113836863B (zh) * 2021-09-30 2024-05-28 安徽大学 一种Logisim电路图的查重方法及系统

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JP3196950B2 (ja) * 1993-11-30 2001-08-06 日本電信電話株式会社 回路情報の検証システム
US6078736A (en) * 1997-08-28 2000-06-20 Xilinx, Inc. Method of designing FPGAs for dynamically reconfigurable computing
JPH11219379A (ja) * 1998-01-30 1999-08-10 Nec Eng Ltd Ｖｈｄｌモデルの変更方法
US6453454B1 (en) 1999-03-03 2002-09-17 Oridus Inc. Automatic engineering change order methodology
US7017043B1 (en) * 1999-03-19 2006-03-21 The Regents Of The University Of California Methods and systems for the identification of circuits and circuit designs
US7055120B2 (en) * 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7237214B1 (en) * 2003-03-04 2007-06-26 Synplicity, Inc. Method and apparatus for circuit partitioning and trace assignment in circuit design
US7673164B1 (en) * 2004-12-13 2010-03-02 Massachusetts Institute Of Technology Managing power in a parallel processing environment
US7284228B1 (en) * 2005-07-19 2007-10-16 Xilinx, Inc. Methods of using ant colony optimization to pack designs into programmable logic devices
EP2063366A4 (en) * 2006-08-31 2012-08-15 Fuji Xerox Co Ltd METHOD AND SYSTEM FOR MOUNTING A CIRCUIT MODEL ON A RECONFIGURABLE DEVICE
CN101196945B (zh) * 2006-12-04 2010-06-02 富士通株式会社 电路设计支持装置及方法、印刷电路板制造方法
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CN101620643B (zh) * 2009-07-03 2011-03-09 中国人民解放军国防科学技术大学 一种基于fpga的体系结构仿真系统设计方法
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US8533643B2 (en) * 2010-12-17 2013-09-10 Advanced Micro Devices, Inc. Method and apparatus for performing template-based classification of a circuit design
KR101551045B1 (ko) * 2011-01-25 2015-09-07 마이크론 테크놀로지, 인크. 요소 이용을 위한 상태 그룹화
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