JP2019106561A - Image sensor - Google Patents

Abstract

To provide an image sensor capable of suppressing manufacturing variation and removing a noise.SOLUTION: A pixel circuit 3 includes a photodiode 4 and a constant current transistor 11. A ground voltage GND is applied to an anode of the photodiode 4. A power supply voltage Vdd is applied to a cathode of the photodiode 4 via the constant current transistor 11. The constant current transistor 11 configures a secondary side transistor of a current mirror circuit 12. The current mirror circuit 12 is configured by the constant current transistor 11, a primary side transistor 13, and a constant current source 14. The current mirror circuit 12 applies a current I2 having a predetermined ratio to a current I1 flowing through the primary side transistor 13, to the constant current transistor 11.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an image sensor that detects an image by light charge.

  Conventionally, an image sensor is known in which a MOS transistor is connected to a photodiode, and excess photocharge is removed from the photodiode using this transistor (see, for example, Non-Patent Documents 1 and 2).

David Stoppa, International Solid State Circuit Conference (ISSCC) 2015 Tutorial 10, "CMOS Sensors for 3D Imaging" p.42 Kiyoharu Aizawa, Takayuki Hamamoto, ed., "Image Information Media Core Technology Series 9 CMOS Image Sensor", Corona, August 2012, p. 177

  By the way, the image sensor described in Non-Patent Document 1 operates the MOS transistor connected to the photodiode as a switch, removes all the photocharges accumulated in the photodiode, and resets the photodiode. is there. However, since this configuration does not remove only the photocharge of noise components such as high background light, there is a problem that the necessary photocharge can not be left.

  In the image sensor described in Non-Patent Document 2, the MOS transistor connected to the photodiode is operated in the subthreshold region to remove only the excess photocharge. However, this configuration is susceptible to the process of producing the device and tends to cause manufacturing variations. In addition to this, the image sensor described in Non-Patent Document 2 has a problem that it is susceptible to various influences such as fluctuation of power supply voltage and temperature fluctuation.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide an image sensor capable of removing noise while suppressing manufacturing variations.

  In order to solve the above problems, an image sensor according to the invention of claim 1 includes a photodiode, and a transistor connected to the photodiode for reducing the photocharge accumulated in the photodiode, and the transistor is previously formed. It is characterized in that it is a constant current transistor which flows a current of a determined predetermined value.

  In the invention of claim 2, the constant current transistor is a secondary side transistor of a current mirror circuit which passes a current having a predetermined ratio with respect to the current flowing through the primary side transistor.

  In the invention of claim 3, the current mirror circuit can increase or decrease the current flowing to the primary side transistor.

  According to the invention of claim 4, it has a plurality of other secondary side transistors connected to the primary side transistor of the current mirror circuit, and the other secondary side transistor is for the current flowing to the other primary side transistors. Further includes another current mirror circuit flowing a current of a predetermined ratio, the other current mirror circuit being a current to a primary side transistor of the current mirror circuit among a plurality of other secondary side transistors It is considered that the one that flows is selectable.

  In the invention of claim 5, the other current mirror circuit selects the other secondary side transistor which causes current to flow to the primary side transistor of the current mirror circuit in accordance with the exposure amount of the light input to the photodiode. To be configured.

  According to the invention of claim 1, since the constant current transistor is connected to the photodiode, the photocharge of the noise component such as background light can be detected by appropriately setting the magnitude of the current flowing through the constant current transistor. It can be removed from Further, since the constant current transistor operates to flow a current of a predetermined value, the current value is stabilized. Therefore, compared to, for example, a transistor operated in a subthreshold region, various influences such as variations in process, power supply voltage, temperature and the like are less likely to occur, and noise removal characteristics can be stabilized.

  According to the invention of claim 2, since the constant current transistor is the secondary side transistor of the current mirror circuit, a constant ratio of current to the current flowing through the primary side transistor of the current mirror circuit is supplied to the constant current transistor Can. Further, the magnitude of the current flowing through the constant current transistor can be set in accordance with the magnitude of the current flowing through the primary side transistor of the current mirror circuit. Therefore, for example, even after the manufacture of the element, the magnitude of the current flowing in the constant current transistor can be adjusted.

  According to the invention of claim 3, since the current mirror circuit can increase or decrease the current flowing to the primary side transistor, the current mirror circuit is a secondary side transistor depending on the magnitude of the current flowing to the primary side transistor. The magnitude of the current flowing through the current transistor can be adjusted.

  According to the invention of claim 4, a plurality of other secondary side transistors of another current mirror circuit are connected to the primary side transistor of the current mirror circuit. Therefore, the sum of the currents flowing to the plurality of other secondary side transistors can be increased or decreased by individually switching ON and OFF the plurality of other secondary side transistors. As a result, the magnitude of the current flowing to the primary side transistor of the current mirror circuit can be adjusted according to the sum of the currents flowing to the plurality of other secondary side transistors.

  According to the fifth aspect of the present invention, it is possible to select another secondary side transistor which is turned on according to the exposure amount of light input to the photodiode. Therefore, the sum of the currents flowing to the other secondary side transistors can be adjusted, and the current flowing to the primary side transistor of the current mirror circuit can be increased or decreased. Further, by switching the number of other secondary side transistors in the ON state, or a plurality of other secondary side transistors having different current magnitudes, the current flowing to the primary side transistor of the current mirror circuit The size can be adjusted as a digital quantity. Therefore, the current flowing through the primary side transistor of the current mirror circuit can be digitally controlled.

FIG. 1 is a circuit diagram showing an image sensor according to a first embodiment of the present invention. It is a timing chart which shows an example of a cathode voltage etc. of a photodiode in FIG. FIG. 6 is a circuit diagram showing an image sensor according to a second embodiment of the present invention. It is a circuit diagram showing the image sensor by a 3rd embodiment of the present invention. It is a block diagram which shows the image photography system by the 4th, 5th embodiment of this invention. It is a flowchart which shows the voltage setting process by the 4th Embodiment of this invention. It is a flowchart which shows the voltage setting process by the 5th Embodiment of this invention. It is a circuit diagram showing an image sensor by a comparative example. It is a timing chart which shows an example of the cathode voltage etc. of the photodiode in FIG.

  Hereinafter, an image sensor according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

  FIG. 1 shows an image sensor 1 according to a first embodiment of the present invention. The image sensor 1 includes a pixel unit 2 composed of a plurality of pixel circuits 3 (only one is shown) and a current source circuit 15. The image sensor 1 captures an image input to the pixel unit 2, converts the image into an electrical signal, and outputs the electrical signal.

  Pixel circuit 3 includes a photodiode 4 (PD), a transfer transistor 5, a floating diffusion capacitance 6 (FD), a reset transistor 7, an amplification transistor 8, a selection transistor 9, and a constant current transistor 11. There is. The pixel circuit 3 is formed on a semiconductor substrate.

  The transfer transistor 5, the reset transistor 7, the amplification transistor 8, and the selection transistor 9 are all configured by NMOS transistors. A transfer transistor control signal TX is applied to the gate of the transfer transistor 5. The reset transistor control signal RST is applied to the gate of the reset transistor 7. The select transistor control signal SEL is applied to the gate of the select transistor 9.

  The photodiode 4 accumulates photocharges (electrons) according to the intensity and light quantity of incident light. The ground voltage GND is applied to the anode of the photodiode 4. The cathode of the photodiode 4 is connected to the source of the transfer transistor 5. The drain of the transfer transistor 5 is connected to the source of the reset transistor 7 and to the gate of the amplification transistor 8. The power supply voltage Vdd is applied to the drain of the reset transistor 7. The power supply voltage Vdd is applied to the drain of the amplification transistor 8. The source of the selection transistor 9 is connected to the vertical signal line 10. The drain of the selection transistor 9 is connected to the source of the amplification transistor 8.

  One terminal of the floating diffusion capacitor 6 is connected to the drain of the transfer transistor 5. The floating diffusion capacitance 6 is generally configured mainly by a wiring parasitic capacitance, but can be regarded as a configuration in which the ground voltage GND is applied to the other terminal. The floating diffusion capacitance 6 is an equivalent capacitance of a floating diffusion (floating region) that stores photocharges as signal charges and converts the photocharges into a voltage.

  The constant current transistor 11 is configured of a PMOS transistor. The constant current transistor 11 constitutes a secondary side transistor to which the current mirror circuit 12 is to be turned back. The current mirror circuit 12 includes a constant current transistor 11, a primary side transistor 13, and a constant current source 14. The current mirror circuit 12 supplies, to the constant current transistor 11, a current I2 having a ratio determined in advance with respect to the current I1 flowing through the primary side transistor 13 which is to be turned back.

  The ratio between the current I1 flowing through the primary side transistor 13 and the current I2 flowing through the constant current transistor 11 is determined by the ratio between the size of the primary side transistor 13 and the size of the constant current transistor 11. That is, the ratio (I2 = I1 × W2 / W1) of the current I2 to the current I1 is determined according to the ratio (W1 / W2) of the size W1 of the primary side transistor 13 and the size W2 of the constant current transistor 11.

  In the following, in order to simplify the description, it is assumed that the size of the primary side transistor 13 and the size of the constant current transistor 11 are the same. In this case, the current mirror circuit 12 passes a current I2 of the same magnitude as the current I1 of the primary side transistor 13 to the constant current transistor 11. The present invention is not limited to this, and the primary side transistor 13 and the constant current transistor 11 may have different sizes.

  The drain of the constant current transistor 11 is connected to the cathode of the photodiode 4. The power supply voltage Vdd is applied to the source of the constant current transistor 11. For this reason, the constant current transistor 11 is connected to the side (cathode side) of the photodiode 4 on which the photocharge (electron) is stored.

  Like the constant current transistor 11, the primary side transistor 13 is constituted by a PMOS transistor. The drain of the primary side transistor 13 is connected to a constant current source 14. Therefore, the current Ibias from the constant current source 14 flows in the primary side transistor 13. The power supply voltage Vdd is applied to the source of the primary side transistor 13. The gate of the primary side transistor 13 is connected to the drain of the primary side transistor 13 and to the gate of the constant current transistor 11 which is to be the secondary side transistor. Thus, when current I1 (I1 = Ibias) flows between the drain and source of primary side transistor 13, the drain and source between constant current transistor 11 serving as the secondary side transistor also has the same magnitude as current I1. A current I2 flows. At this time, a portion of the current mirror circuit 12 from which the constant current transistor 11 is omitted constitutes a current source circuit 15 which sets the magnitude of the current I2 flowing through the constant current transistor 11.

  Note that FIG. 1 shows a configuration in which one photodiode 4 is connected to one amplification transistor 8 in order to simplify the configuration. In a general configuration, in order to increase the area efficiency of the pixel unit 2, a plurality of sets of photodiodes 4 and transfer transistors 5 are connected in parallel to one amplification transistor 8. Even in this case, by connecting one constant current transistor 11 to one photodiode 4 of each set, the same effect as the configuration shown in FIG. 1 can be obtained.

  The image sensor 1 according to the first embodiment of the present invention has the above-described configuration. Next, the operation of the pixel circuit 3 will be described with reference to FIG. 1 and FIG.

  As shown in FIG. 2, the reset transistor 7 is set to the conductive state (ON) by the reset transistor control signal RST. At this time, the transfer transistor 5 is also set to the conductive state by the transfer transistor control signal TX. As a result, both the photodiode 4 and the floating diffusion capacitance 6 are reset. When the reset operation is completed, the transfer transistor 5 and the reset transistor 7 are switched to the cutoff state (OFF).

  The photodiode 4 of the pixel circuit 3 generates a light charge according to the incident light. Therefore, the cathode voltage of the photodiode 4 decreases in accordance with the photocharge. At this time, a current I2 having the same magnitude as the current I1 of the primary side transistor 13 of the current mirror circuit 12 flows through the constant current transistor 11. Therefore, a part of the photocharge generated in the photodiode 4 is removed according to the current I2. As a result, the slope when the cathode voltage falls is gentler in accordance with the magnitude of the current I2.

  The voltage of the reference level of the floating diffusion capacitance 6 is read out before the predetermined charge accumulation period Tc elapses after the end of the reset operation. At this time, the selection transistor 9 is temporarily set to the conductive state (ON) by the selection transistor control signal SEL. Thereby, the voltage of the floating diffusion capacitance 6 is output to the vertical signal line 10 in the state before the transfer of the photocharge of the photodiode 4. When the read operation of the reference level is completed, the selection transistor 9 is switched to the cutoff state (OFF).

  Next, when the charge accumulation period Tc elapses after the reset operation is completed, the signal of the photocharge accumulated in the photodiode 4 is read out. At this time, the transfer transistor 5 is set to the conductive state (ON) by the transfer transistor control signal TX. The selection transistor 9 is also set to the conductive state (ON) by the selection transistor control signal SEL.

  The photocharges stored in the photodiode 4 are transferred to the floating diffusion via the transfer transistor 5 set to the conductive state, and the floating diffusion capacitance 6 is charged. The amplification transistor 8 amplifies the voltage of the floating diffusion capacitance 6 and outputs the amplified voltage to the vertical signal line 10 via the selection transistor 9.

  Here, in the photodiode 4, light charges according to the light amount of incident light are accumulated. Therefore, as shown by the two-dot chain line in FIG. 2, when the current I2 from the constant current transistor 11 is not supplied (I2 = 0), the photodiode 4 is saturated by the photocharge of the background light. There is.

  Therefore, the image sensor 1 according to the present embodiment removes the photocharge of the background light by flowing the current I2 to the constant current transistor 11. Such an excess photo charge removal effect will be specifically described below.

  First, with respect to the image sensor 21 according to the comparative example shown in FIG. 8, an operation of removing the photocharge of background light will be described. An image sensor 21 according to this comparative example includes a pixel circuit 22 similar to the pixel circuit 3 according to the first embodiment. Therefore, the pixel circuit 22 includes the photodiode 4, the transfer transistor 5, the floating diffusion capacitance 6, the reset transistor 7, the amplification transistor 8, and the selection transistor 9.

  However, the cathode of the photodiode 4 is connected to the source of the NMOS transistor 23. The drain of the NMOS transistor 23 is supplied with the power supply voltage Vdd. In this point, the image sensor 21 of the comparative example is different from the image sensor 1 according to the first embodiment.

  FIG. 9 shows an example of a timing chart in the case of operating the image sensor 21 according to the comparative example. This timing chart does not assume a mechanical shutter as in a digital camera, for example, but assumes that light is always incident. Therefore, photocharge always occurs in the photodiode 4. Furthermore, assuming that the incident light intensity is constant, a constant amount of photocharge is generated per unit time in the photodiode 4 during the charge accumulation period Tc, and the cathode voltage of the photodiode 4 falls at a constant slope.

  For example, when the current Ist from the NMOS transistor 23 is not supplied (Ist = 0), when the incident light intensity is too strong, the photocharge accumulated in the photodiode 4 reaches the number of saturated electrons. In this case, as shown by the two-dot chain line in FIG. 9, the lower limit voltage is reached in the middle of the charge accumulation period Tc, and a normal signal level can not be read out.

  At this time, in the image sensor 21 according to the comparative example, the NMOS transistor 23 is operated (weak inversion operation) in a subthreshold region equal to or less than the threshold. As a result, since the current Ist flows through the photodiode 4, as shown by the solid line in FIG. 9, the cathode voltage of the photodiode 4 has a gentle gradient of change. Therefore, sticking to the lower limit voltage at the read timing of the signal level can be avoided.

  However, when the NMOS transistor 23 is subjected to the weak inversion operation, the current Ist tends to be unstable because it is susceptible to process variations, power supply variations, gate voltage variations, and temperature variations. As a result, as shown by a broken line in FIG. 9, there is a problem that the inclination of the cathode voltage of the photodiode 4 varies with time for each pixel and even for the same pixel.

  Next, with respect to the image sensor 1 according to the first embodiment, the removal operation of the photocharge of background light will be described.

  FIG. 2 shows an example of a timing chart when the image sensor 1 according to the first embodiment is operated. In FIG. 2, as in FIG. 9, it is assumed that the incident light intensity is constant. At this time, a constant light charge is generated per unit time in the photodiode 4 during the charge accumulation period Tc, and the cathode voltage of the photodiode 4 falls at a constant slope.

  At this time, in the image sensor 1 of the present embodiment, the constant current transistor 11 serving as the secondary side transistor of the current mirror circuit 12 is connected to the photodiode 4. When a constant current I2 is supplied via the constant current transistor 11, the photocharge accumulated in the photodiode 4 is discharged to the power supply voltage Vdd side (power supply).

  In the first embodiment, since the constant current transistor 11 constitutes the current mirror circuit 12, the predetermined current I2 can be stably supplied to the photodiode 4. As a result, accumulation of excess photocharge in the photodiode 4 can be suppressed. As a result, even when background light with high intensity is incident, saturation of the photodiode 4 can be suppressed during the charge accumulation period Tc. Therefore, the influence of background light can be reduced to detect a desired signal level according to the light from the object to be detected.

  In the first embodiment, the constant current transistor 11 is operated in the saturation region. For this reason, it is hard to receive the influence of a process, and the characteristic dispersion | variation for every element can be suppressed. In addition to this, the signal level can be stabilized without being influenced by the fluctuation of the power supply voltage Vdd or the temperature change. As a result, in the first embodiment, it is possible to suppress the variation for each pixel and the temporal change in the same pixel.

  Thus, according to the first embodiment, since the constant current transistor 11 is connected to the photodiode 4, noise such as background light can be generated by appropriately setting the magnitude of the current I2 flowing through the constant current transistor 11. Component photocharges can be removed from the photodiode 4. Further, since the constant current transistor 11 operates to flow the current I2 of a predetermined value, the magnitude (current value) of the current I2 is stabilized. For this reason, it is hard to receive various influences, such as a process, a power supply voltage, and a fluctuation | variation in temperature, and the removal characteristic of noise can be stabilized.

  Further, since the constant current transistor 11 is a secondary side transistor of the current mirror circuit 12, a current I2 of the same magnitude as the current I1 flowing through the primary side transistor 13 of the current mirror circuit 12 can be supplied to the constant current transistor 11. . Further, the magnitude of the current I2 flowing through the constant current transistor 11 can be set in accordance with the magnitude of the current I1 flowing through the primary side transistor 13 of the current mirror circuit 12. Therefore, for example, even after the manufacture of the element, the magnitude of the current flowing through the constant current transistor 11 can be adjusted.

  As in the comparative example, in the first embodiment, a PMOS transistor to be the constant current transistor 11 is added to the pixel circuit 22 configured only with the NMOS transistor. Therefore, the image sensor 1 tends to have a large pixel size. On the other hand, the image sensor 1 for distance measurement has a low request for reduction in pixel size due to the low number of pixels compared to a high pixel number image sensor required for ordinary digital cameras and portable terminals for viewing , Need high background light measures. For this reason, when the present invention is applied to the image sensor 1 for distance measurement, the effect is large.

  Next, FIG. 3 shows a second embodiment of the present invention. The feature of the second embodiment is that a current mirror circuit is configured using an NMOS transistor. In the second embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof will be omitted.

  Similar to the image sensor 1 according to the first embodiment, the image sensor 31 according to the second embodiment includes the pixel unit 32 including a plurality of pixel circuits 33 (only one is shown) and the current source circuit 37. Have.

  The pixel circuit 33 is configured substantially the same as the pixel circuit 3 according to the first embodiment. Therefore, the pixel circuit 33 includes the photodiode 4, the transfer transistor 5, the floating diffusion capacitance 6, the reset transistor 7, the amplification transistor 8, the selection transistor 9, and the constant current transistor 34.

  In the second embodiment, the power supply voltage Vdd is applied to the cathode of the photodiode 4. The anode of the photodiode 4 is connected to the source of the transfer transistor 5. In this case, the photodiode 4 accumulates photocharges (holes) according to the intensity and light quantity of the incident light.

  Further, a reset voltage Vreset (Vreset> GND + Vth), which is larger than the sum of the ground voltage GND and the threshold voltage Vth of the NMOS transistor, is applied to the drain of the reset transistor 7.

  The constant current transistor 34 is configured by an NMOS transistor as well as the other transistors 5, 7, 8, and 9. The constant current transistor 34 constitutes a secondary side transistor to which the current mirror circuit 35 is to be turned back. The current mirror circuit 35 is composed of a constant current transistor 34, a primary side transistor 36, and a constant current source 14. The current mirror circuit 35 supplies, to the constant current transistor 34, a current I2 of a predetermined ratio with respect to the current I1 flowing to the primary side transistor 36 which is the folding source.

  The ratio between the current I1 flowing through the primary side transistor 36 and the current I2 flowing through the constant current transistor 34 is determined by the ratio between the size of the primary side transistor 36 and the size of the constant current transistor 34. In the following, in order to simplify the description, it is assumed that the size of the primary side transistor 36 and the size of the constant current transistor 34 are the same, that is, the case where the current I1 and the current I2 have the same magnitude. The present invention is not limited to this, and the primary side transistor 36 and the constant current transistor 34 may have different sizes.

  The drain of the constant current transistor 34 is connected to the anode of the photodiode 4. The ground voltage GND is applied to the source of the constant current transistor 34. Therefore, the constant current transistor 34 is connected to the side (anode side) of the photodiode 4 on which the photocharges (holes) are stored.

  The primary side transistor 36, like the constant current transistor 34, is constituted by an NMOS transistor. The power supply voltage Vdd is applied to the drain of the primary side transistor 36 via the constant current source 14. The ground voltage GND is applied to the source of the primary side transistor 36. The gate of the primary side transistor 36 is connected to the drain of the primary side transistor 36 and to the gate of the constant current transistor 34 which is to be the secondary side transistor. Thus, when current I1 (I1 = Ibias) flows between the drain and source of primary side transistor 36, the drain and source of constant current transistor 34 serving as the secondary side transistor also have the same magnitude as current I1. A current I2 flows. At this time, the portion of the current mirror circuit 35 from which the constant current transistor 34 is omitted constitutes a current source circuit 37 which sets the magnitude of the current I2 flowing through the constant current transistor 34.

  Thus, also in the second embodiment, substantially the same effects as those of the first embodiment can be obtained. As compared with the first embodiment, in the second embodiment, the pixel circuit 33 can be configured by only the NMOS transistor without adding the PMOS transistor, so that the mask addition becomes unnecessary in the manufacturing process, An increase in manufacturing cost can be suppressed.

  On the other hand, since the photocharges use holes, the charge mobility is low. In addition to this, the reset voltage Vreset needs to be stably supplied separately from the power supply voltage Vdd and the ground voltage GND. That is, when resetting the photocharges stored in the photodiode 4, in the first embodiment, the source voltage of the amplification transistor 8 is the power supply voltage by releasing the photocharges (electrons) to the power supply voltage Vdd side. It rises toward Vdd. On the other hand, in the second embodiment, since the photocharges (holes) are discharged closer to the ground, the source voltage of the amplification transistor 8 drops closer to the ground voltage GND at the time of reset. However, if the gate voltage of the amplification transistor 8 is not set higher than the source voltage by the threshold voltage Vth, the amplification transistor 8 is turned off, and a voltage corresponding to the reset voltage Vreset can not be output to the source of the amplification transistor 8. Therefore, the reset voltage Vreset supplied to the drain of the reset transistor 7 needs to be set higher than the ground voltage GND by the threshold voltage Vth or more, and a separate reset voltage line 38 is required.

  Next, FIG. 4 shows a third embodiment of the present invention. The feature of the third embodiment is that the current mirror circuit can variably set the current flowing through the primary side transistor. In the third embodiment, the same components as those in the first embodiment described above are denoted by the same reference numerals, and the description thereof will be omitted.

  Like the image sensor 1 according to the first embodiment, the image sensor 41 according to the third embodiment includes the pixel unit 2 including the plurality of pixel circuits 3 (only one is shown) and the current source circuit 49. Have.

  The constant current transistor 11 constitutes a secondary side transistor to which the current mirror circuit 42 is to be turned back. The current mirror circuit 42 is configured of a constant current transistor 11, a primary side transistor 43, and a variable current source circuit 44 including a constant current source 14. The current mirror circuit 42 supplies, to the constant current transistor 11, a current I2 having a ratio determined in advance with respect to the current I1 flowing through the primary side transistor 43 which is the turn back source.

  The ratio between the current I1 flowing through the primary side transistor 43 and the current I2 flowing through the constant current transistor 11 is determined by the ratio between the size of the primary side transistor 43 and the size of the constant current transistor 11. In the following, in order to simplify the description, it is assumed that the size of the primary side transistor 43 and the size of the constant current transistor 11 are the same, that is, the case where the current I1 and the current I2 have the same magnitude. The present invention is not limited to this, and the primary side transistor 43 and the constant current transistor 11 may have different sizes.

  Like the constant current transistor 11, the primary side transistor 43 is configured of a PMOS transistor. The drain of the primary side transistor 43 is connected to the drains of a plurality of (for example, m) current setting secondary side transistors 46 constituting the variable current source circuit 44. The power supply voltage Vdd is applied to the source of the primary side transistor 43. The gate of the primary side transistor 43 is connected to the drain of the primary side transistor 43 and to the gate of the constant current transistor 11 which is to be the secondary side transistor. As a result, when the current I1 flows between the drain and source of the primary side transistor 43, the current I2 having the same magnitude as the current I1 also flows between the drain and source of the constant current transistor 11 serving as the secondary side transistor.

  The variable current source circuit 44 constitutes another current mirror circuit. The variable current source circuit 44 includes a constant current source 14, a current setting primary side transistor 45 (other primary side transistors), and a plurality of current setting secondary side transistors 46 (other secondary side transistors). It contains. The variable current source circuit 44 passes a current Ib having a predetermined ratio with respect to the current Ia flowing through the current setting primary side transistor 45 which is a turning back source to the current setting secondary side transistor 46 which is a turning destination.

  The ratio of the current Ia flowing through the current setting primary side transistor 45 to the current Ib flowing through the current setting secondary side transistor 46 is the size of the current setting primary side transistor 45 and the current setting secondary side transistor 46. It depends on the ratio with the size of. In the following, in order to simplify the description, it is assumed that the size of the current setting primary side transistor 45 is the same as the size of the current setting secondary side transistor 46, that is, the case where the current Ia and the current Ib have the same magnitude. Explain to.

  The present invention is not limited to this, and the current setting primary side transistor 45 and the current setting secondary side transistor 46 may have different sizes. Also, the plurality of current setting secondary side transistors 46 may have different sizes. In this case, the ratio of the sizes of the plurality of current setting secondary side transistors 46 may correspond to, for example, a binary code or a thermometer code, or may correspond to other codes. When the plurality of current setting secondary side transistors 46 are formed to have different sizes from each other, the currents Ib flowing through the plurality of current setting secondary side transistors 46 can be made different from each other. Therefore, the degree of freedom in adjusting the magnitude of the current I1 flowing through the primary side transistor 43 can be increased.

  The current setting primary side transistor 45 and the current setting secondary side transistor 46 are both configured by NMOS transistors. The power supply voltage Vdd is applied to the drain of the current setting primary side transistor 45 via the constant current source 14. The ground voltage GND is applied to the source of the current setting primary side transistor 45. The gate of the current setting primary-side transistor 45 is connected to the drain of the current setting primary-side transistor 45 and to the gate of the current setting secondary-side transistor 46 via the first switch 47.

  The drain of the current setting secondary side transistor 46 is connected to the drain of the primary side transistor 43. The ground voltage GND is applied to the source of the current setting secondary side transistor 46. The gate of the current setting secondary side transistor 46 is connected to the gate of the current setting secondary side transistor 46 via the first switch 47 and is also connected to ground via the second switch 48. .

  A control signal is input to the first switch 47 as it is, for example, from a data processing unit (not shown). A control signal from the data processing unit is input to the second switch 48 via the NOT circuit 48A. Therefore, control signals are input to the first and second switches 47 and 48 from the data processing unit so as to be in reverse switching states. Thus, when one of the switches 47 and 48 is in the connection state (ON), the first and second switches 47 and 48 operate such that the other is in the disconnection state (OFF).

  At this time, among the plurality of current setting secondary side transistors 46, the one whose gate is connected to the gate of the current setting primary side transistor 45 is the current between the drain and source of the current setting primary side transistor 45. Copy Ia (Ia = Ibias). That is, also between the drain and source of the current setting secondary side transistor 46, the current Ib having the same magnitude as the current Ia flows. On the other hand, among the plurality of current setting secondary side transistors 46, the one whose gate is connected to the ground is in the OFF state, and the current Ib does not flow between the drain and the source (Ib = 0).

  As described above, the first and second switches 47 and 48 are to select one that executes copying of the current Ia from the plurality of current setting secondary side transistors 46. Therefore, when all the first switches 47 are ON, a current I1 having a magnitude m times the current Ia (Ia = Ibias) flows to the primary side transistor 43 of the current mirror circuit 42. On the other hand, when all the first switches 47 are off, the current I1 does not flow in the primary side transistor 43 of the current mirror circuit 42. Since the magnitude of the current I1 flowing through the primary side transistor 43 is determined by the sum of the currents Ib, the magnitude of the current I1 can be adjusted by the number of the first switches 47 turned on.

  At this time, a portion of the current mirror circuit 42 from which the constant current transistor 11 is omitted constitutes a current source circuit 49 which sets the magnitude of the current I2 flowing through the constant current transistor 11.

  Thus, also in the third embodiment, substantially the same effects as those in the first embodiment can be obtained. In the third embodiment, another current mirror circuit (variable current source circuit 44) including a plurality of current setting secondary side transistors 46 connected to the primary side transistor 43 of the current mirror circuit 42 is further provided. . In addition to this, the variable current source circuit 44 is configured to be able to select one that allows current to flow to the primary side transistor 43 of the current mirror circuit 42 among the plurality of current setting secondary side transistors 46. Therefore, the magnitude of the current flowing through the primary side transistor 43 of the current mirror circuit 42 can be adjusted by switching the operating states of the plurality of current setting secondary side transistors 46.

  In the third embodiment, the currents Ib flowing through the plurality of current setting secondary side transistors 46 are made equal to each other, but the currents Ib flowing through the plurality of current setting secondary side transistors 46 The sizes may be different from each other. In this case, the current flowing to the primary side transistor 43 of the current mirror circuit 42 is not limited to the number of the current setting secondary side transistors 46 to be turned on, but is switched by switching the current setting secondary side transistors 46 to be turned on. I1 can be adjusted. Therefore, for example, when the ratio of the current Ib flowing through the plurality of current setting secondary side transistors 46 is set according to the binary code or the like, the current I1 flowing through the primary side transistor 43 of the current mirror circuit 42 is digitally controlled. be able to.

  Further, although the third embodiment exemplifies the case where it is applied to the pixel unit 2 (pixel circuit 3) according to the first embodiment, the pixel unit 32 (pixel circuit 33) according to the second embodiment is described. It may apply.

  Next, FIGS. 5 and 6 show a fourth embodiment of the present invention. A feature of the fourth embodiment is that an image capturing system is configured using the image sensor according to the first embodiment. In the fourth embodiment, the same components as those in the first embodiment described above are designated by the same reference numerals, and the description thereof will be omitted.

  The image photographing system 51 includes the image sensor 1 according to the first embodiment, a reading unit 52, and a data processing unit 53. In the image sensor 1 of the image photographing system 51, the reading unit 52, and the data processing unit 53, in recent years, the semiconductor substrates tend to be identical to each other. In the present invention, the semiconductor substrates of the image sensor 1, the reading unit 52, and the data processing unit 53 may or may not be the same as one another.

  The reading unit 52 includes a programmable gain amplifier and an A / D conversion circuit. The reading unit 52 converts an analog signal output from the pixel unit 2 (pixel circuit 3) via the vertical signal line 10 into a digital signal and outputs the digital signal. Therefore, the reading unit 52 outputs the digital signal of the captured image captured by the pixel unit 2 to the data processing unit 53 as a pixel output signal.

  The data processing unit 53 is configured of a logic IC, a microprocessor or the like. The data processing unit 53 has an input side connected to the reading unit 52 and an output side connected to the current source circuit 15. The data processing unit 53 executes the current setting process shown in FIG. 6 and controls the current source circuit 15 in accordance with the pixel output signal from the reading unit 52. Thus, the current I2 flowing through the constant current transistor 11 of the pixel circuit 3 is adjusted in accordance with the pixel output signal.

  Next, current setting processing by the data processing unit 53 will be described with reference to FIG. At the start of the current setting process, the initial value of the frame counter n is set to “1”.

  When the current setting process is started, first, steps 1 to 3 are executed. In step 1, the power of the data processing unit 53 and the like is switched on to activate the data processing unit 53 and the like. In step 2, a determination value Dsat for determining whether the photodiode 4 is saturated is set in a register. In step 3, imaging is started by the image sensor 1.

  In the subsequent step 4, the average value Dave of the pixel output signal is acquired for the n-th frame in accordance with the current value of the counter n, and the process shifts to step 5. The average value Dave is not limited to the calculation result of all the pixels in the frame, but may be the calculation result of thinned pixels.

  In step 5, it is determined whether the average value Dave of the pixel output signal is smaller than the determination value Dsat. When the determination in step 5 is “NO”, the average value Dave of the pixel output signal is larger than the determination value Dsat (Dsat ≦ Dave), and the photodiode 4 is in a state of being saturated by the incident light. Therefore, in step 6, the data processing unit 53 controls the current source circuit 15 to obtain the pixel output signal of the next frame (n + 1st frame), the current I1 flowing through the primary side transistor 13 Start the supply. Thereby, since the constant current transistor 11 of the pixel circuit 3 flows the current I2 having the same magnitude as the current I1, a part of the photocharge accumulated in the photodiode 4 is removed according to the current I2. As a result, it is possible to suppress the saturation of the photodiode 4 and acquire a signal level corresponding to the photographed image.

  On the other hand, when “YES” is determined in the step 5, the average value Dave of the pixel output signal is smaller than the determination value Dsat (Dsat> Dave), and the photodiode 4 is not saturated by the incident light. Therefore, in step 7, the data processing unit 53 controls the current source circuit 15 to obtain the pixel output signal of the next frame (n + 1th frame), the current I1 flowing through the primary side transistor 13 Stop the supply. As a result, the current I2 flowing to the constant current transistor 11 of the pixel circuit 3 is also stopped, so the photodiode 4 stores all the photocharges according to the intensity of the incident light and the like. As a result, based on the photocharges accumulated in the photodiode 4, it is possible to acquire a signal level corresponding to the photographed image.

  When the processes in steps 6 and 7 are completed, the process proceeds to step 8 to increase the value of the counter n by one. In the following step 9, based on the value of the counter n, it is determined whether the imaging has been completed. Specifically, it is determined whether the value of the counter n is larger than the value N corresponding to the number of all the frames (n> N). When the determination in step 9 is “NO”, since the imaging is not completed, the processing in step 4 and subsequent steps is repeated.

  On the other hand, when “YES” is determined in the step 9, the setting of the current is completed for all the frames. Therefore, the process proceeds to step 10, the power of the data processing unit 53 and the like is switched off, and the data processing unit 53 and the like are stopped.

  Thus, also in the fourth embodiment, substantially the same effects as those of the first embodiment can be obtained. In the fourth embodiment, ON and OFF of the current I1 flowing through the current source circuit 15 (primary side transistor 13) is set when acquiring the pixel output signal of the next frame according to the exposure amount in the previous frame. Do. Therefore, it is possible to obtain the pixel output signal of the photographed image while suppressing the saturation of the photodiode 4.

  Although the case where the image sensor 1 according to the first embodiment is used is exemplified in the fourth embodiment, the image sensor 31 according to the second embodiment may be used.

  Next, FIGS. 5 and 7 show a fifth embodiment of the present invention. The feature of the fifth embodiment is that an image capturing system is configured using the image sensor according to the third embodiment. In the fifth embodiment, the same components as those in the third embodiment described above are denoted by the same reference numerals, and the description thereof will be omitted.

  The image photographing system 61 includes an image sensor 41 according to the third embodiment, a reading unit 62, and a data processing unit 63.

  The reading unit 62 is configured substantially the same as the reading unit 52 according to the fourth embodiment. The reading unit 62 converts an analog signal output from the pixel circuit 3 via the vertical signal line 10 into a digital signal and outputs the digital signal. Therefore, the reading unit 62 outputs the digital signal of the captured image captured by the pixel unit 2 to the data processing unit 63 as a pixel output signal.

  The data processing unit 63 is configured of a logic IC, a microprocessor or the like. The data processing unit 63 has an input side connected to the reading unit 62 and an output side connected to the current source circuit 49. The data processing unit 63 executes the current setting process shown in FIG. 7 and controls the current source circuit 49 in accordance with the pixel output signal from the reading unit 62. Thus, the current I2 flowing through the constant current transistor 11 of the pixel circuit 3 is adjusted in accordance with the pixel output signal.

  Next, current setting processing by the data processing unit 63 will be described with reference to FIG. At the start of the current setting process, the initial value of the frame counter n is set to “1”.

  When the current setting process is started, first, steps 11 to 13 are executed. In step 11, the power of the data processing unit 63 and the like is switched on to activate the data processing unit 63 and the like. In step 12, a determination value Dsat for determining whether the photodiode 4 is saturated and a determination value Dmin for determining whether the photocharge accumulated in the photodiode 4 is insufficient are respectively registered. Set to At this time, the determination value Dsat corresponds to the highest value of the pixel output signal necessary for performing appropriate imaging. Also, the determination value Dmin corresponds to the lowest value of the pixel output signal necessary for performing appropriate imaging. In step 13, imaging is started by the image sensor 41.

  In the following step 14, the average value Dave of the pixel output signal is acquired for the nth frame in accordance with the current value of the counter n. The average value Dave is not limited to the calculation result of all the pixels in the frame, but may be the calculation result of thinned pixels.

  In the following step 15, it is determined whether the average value Dave of the pixel output signal is smaller than the determination value Dsat. When the determination in step 15 is “NO”, the average value Dave of the pixel output signal is larger than the determination value Dsat (Dsat ≦ Dave), and the photodiode 4 is in a state of being saturated by the incident light. Therefore, the process proceeds to step 16 and the data processing unit 63 controls the current source circuit 49 to obtain the current I1 flowing through the primary side transistor 43 when acquiring the pixel output signal of the next frame (n + 1st frame). increase.

  On the other hand, when “YES” is determined in the step 15, the average value Dave of the pixel output signal is smaller than the determination value Dsat (Dsat> Dave). Therefore, the process proceeds to step 17 to determine whether the average value Dave of the pixel output signal is larger than the determination value Dmin.

  When the determination in step 17 is “NO”, the average value Dave of the pixel output signal is smaller than the determination value Dmin (Dmin ≧ Dave), and the pixel output signal is in an excessively lowered state. Therefore, in step 18, the data processing unit 63 controls the current source circuit 49 to obtain the current I1 flowing through the primary side transistor 43 when acquiring the pixel output signal of the next frame (n + 1st frame). Reduce.

  On the other hand, when “YES” is determined in the step 17, the average value Dave of the pixel output signal is larger than the determination value Dmin (Dmin <Dave). Therefore, when the data processing unit 63 acquires the pixel output signal of the next frame (n + 1st frame) in step 19, the current value of the current I1 flowing through the primary side transistor 43 is set to the current value. Fix to

  When the processes in steps 16, 18 and 19 are completed, the process proceeds to step 20, where the value of the counter n is incremented by one. In the following step 21, it is determined based on the value of the counter n whether or not imaging has ended. Specifically, it is determined whether the value of the counter n is larger than the value N corresponding to the number of all the frames (n> N). When it is determined in step 21 that the result is "NO", the processing after step 14 is repeated because the imaging is not completed.

  On the other hand, when “YES” is determined in the step 21, the setting of the current is completed for all the frames. Therefore, the process proceeds to step 22 and the power of the data processing unit 63 and the like is switched off to stop the data processing unit 63 and the like.

  Next, based on the current setting process shown in FIG. 7, a specific operation of the image capturing system 61 will be described.

  When the average value Dave of the image data in the first frame is equal to or higher than a predetermined brightness, it is determined that the background light is high. Therefore, the image capturing system 61 increases the constant current I2 in the next second frame in order to discharge the excess light charge of the storage portion of the photodiode 4 with the constant current I2. Furthermore, even in the second frame, when the average value Dave of the image data is equal to or higher than the predetermined brightness, it is determined that the background light is high again. For this reason, the image capturing system 61 further increases the constant current I2 in the next third frame.

  Thus, the image capturing system 61 increases the constant current I2 until the average value Dave of the image data falls below the predetermined brightness set by the determination value Dsat set by the register or the like. Thereby, the image capturing system 61 removes the photocharge due to the high background light.

  Also, the subject and background light constantly change. Therefore, when the background light becomes weak, the image capturing system 61 reduces the constant current I2 until the brightness falls within the predetermined brightness set by the determination value Dmin set by the register or the like, or the constant current Stop I2. As a result, the image capturing system 61 prevents the desired signal of the subject from being blacked out.

  Therefore, when the current control of the image capturing system 61 is reflected in the timing chart of FIG. 2, the inclination of the cathode voltage of the photodiode 4 is controlled. That is, the larger the current I2 of the constant current transistor 11, the more the discharge of photocharges. Therefore, in the charge accumulation period Tc or the like, the slope of the voltage of the photodiode 4 becomes small, and it becomes difficult for the photocharge to be saturated in the photodiode 4. On the other hand, when the incident light intensity is weak, if the current I2 of the constant current transistor 11 is decreased, control can be performed so that the slope of the voltage of the photodiode 4 becomes large.

  Thus, also in the fifth embodiment, substantially the same effects as those in the first, third and fourth embodiments can be obtained. In the fifth embodiment, the magnitude of the current I2 flowing through the constant current transistor 11 is digitally controlled according to the exposure amount of the previous frame. At this time, the current flowing through the primary side transistor 43 of the current mirror circuit 42 is increased or decreased according to the exposure amount of light input to the photodiode 4. For this reason, the image capturing system 61 can operate adaptively to changes in the shooting environment (the light amount of the subject).

  Further, the magnitude of the current I1 flowing through the primary side transistor 43 of the current mirror circuit 42 can be adjusted as a digital amount by the number of the current setting secondary side transistors 46 of the variable current source circuit 44 to drive. Therefore, for example, in accordance with the setting of the register of the data processing unit 63, the current I1 to be supplied to the primary side transistor 43 of the current mirror circuit 42 can be digitally controlled.

  It is needless to say that each of the above-described embodiments is an exemplification, and partial replacement or combination of the configurations shown in different embodiments can be made.

1, 31, 41 image sensor 3, 33 pixel circuit 4 photodiode 11, 34 constant current transistor (secondary side transistor)
12, 35, 42 Current mirror circuit 13, 36, 43 Primary side transistor 14 Constant current source 15, 37, 49 Current source circuit 44 Variable current source circuit (other current mirror circuit)
45 Current setting primary side transistor (other primary side transistor)
46 Current setting secondary side transistor (other secondary side transistor)
51, 61 imaging system 53, 63 data processing unit

Claims (5)

With a photodiode
And a transistor connected to the photodiode to reduce light charge accumulated in the photodiode.
The image sensor characterized in that the transistor is a constant current transistor which passes a current of a predetermined value determined in advance.   The image sensor according to claim 1, wherein the constant current transistor is a secondary side transistor of a current mirror circuit that passes a current having a predetermined ratio with respect to the current flowing to the primary side transistor.   The image sensor according to claim 2, wherein the current mirror circuit can increase or decrease a current flowing to the primary side transistor. The current mirror circuit has a plurality of other secondary side transistors connected to the primary side transistor, and the other secondary side transistors have a predetermined ratio to the current flowing through the other primary side transistors. It is further equipped with another current mirror circuit through which current flows.
4. The image sensor according to claim 3, wherein the other current mirror circuit is configured to select one of a plurality of other secondary side transistors that allows current to flow to the primary side transistor of the current mirror circuit.   The other current mirror circuit is configured by selecting the other secondary side transistor that causes a current to flow to the primary side transistor of the current mirror circuit according to the exposure amount of light input to the photodiode. Image sensor described.

Images