JP2019102870A - Bit interleaver, bit deinterleaver, transmitter, receiver, and programs therefor - Google Patents

Abstract

To provide a bit interleaver for digital terrestrial broadcasting improving the transmission performance regardless of a coding structure according to the code rate of an LDPC code for coded data by an LDPC coder that performs parallel processing of LDPC coding processing that applies an LDPC parity and parity interleaving processing, a bit deinterleaver, a transmitter, a receiver, and a program therefor.SOLUTION: A bit interleaver 115 according to the present invention can be provided in a transmitter 1 and includes a parity deinterleaver 1152 that performs reverse processing of parity interleaving processing for data of an LDPC parity output from an LDPC encoder 114 that performs parallel processing of LDPC coding processing and the parity interleaving processing. A bit deinterleaver 223 according to the present invention is a functional unit that performs reverse processing of the bit interleaver 115 and can be provided in the receiver 2.SELECTED DRAWING: Figure 3

Description

  The present invention relates to the technical field of terrestrial digital broadcasting, and more particularly to a bit interleaver for terrestrial digital broadcasting, a bit deinterleaver, a transmitting apparatus, a receiving apparatus, and programs therefor.

  In digital transmission schemes, multi-level modulation schemes are often used so that more information can be transmitted in the frequency bandwidth available for each service. In order to improve frequency utilization efficiency, it is effective to increase the number of bits (modulation order) allocated per modulation signal symbol, but the relationship between the upper limit value of the information rate that can be transmitted per 1 Hz frequency and the signal to noise ratio is The modulation signal is limited by the achievable communication capacity.

  In terrestrial digital broadcasting currently used, information correction is performed in a receiver using an error correction code. It is possible to control the redundancy (coding rate) of a signal by adding it to information to be sent, which is called a parity bit, and to increase the noise resistance. The error correction code and the modulation scheme are closely related, and the theoretical upper limit of the frequency utilization efficiency for the signal to noise ratio is called the Shannon limit. In this paper, the communication capacity that can be achieved by the modulation signal is conveniently set to the Shannon limit.

  Then, in order to obtain transmission performance approaching the Shannon limit, studies are currently underway on a new generation of next-generation digital terrestrial broadcasting methods to replace the existing digital terrestrial broadcasting methods (see, for example, Patent Document 1).

  A transmitting apparatus and a receiving apparatus according to the technique of Patent Document 1 adopt an LDPC code with a code length of 16200 bits, and an LDPC coding rate of 5/15, 6/15, 7/15, 8/15, 9/15, 10 It is comprised so that error correction may be performed using the parity check matrix calculated | required from the parity check matrix initial value table among / 15, 11/15, 12/15, 13/15. Then, in the transmitting apparatus and receiving apparatus according to the technique of Patent Document 1, the combination of each coding rate and each modulation method is defined by MODCOD, and the arrangement of signal points is uniform as a constellation in the mapper. Each coding rate and rearrangement pattern in a group-wise interleaver used as part of a bit interleaver as well as corresponding to each of UC (Uniform Constellation) and non-uniform NUC (Non Uniform Constellation) It prepares individually according to the combination of each modulation system. Examples of the NUC include 1D NUC (1-dimensional M2-QAM non-uniform constellation) and 2D NUC (2-dimensional QQAM non-uniform constellation).

  An LDPC code is a linear code defined by a very sparse parity check matrix (the elements of the parity check matrix consist of 0s and 1s, and the number of 1s is very small), and the design is more appropriate as the code length increases. Under the conditions, transmission characteristics approaching the Shannon limit tend to be obtained. As described in Non-Patent Document 1, the parity check matrix of the LDPC code has a periodic structure based on the number of parallel processing (see, for example, Non-Patent Document 1), and in particular, disclosed in Non-Patent Document 1. An LDPC code using a parity check matrix as described above is also called an LDPC-IRA (Irregular Repeat Accumulate) code.

  Recently, in addition to the current 2K service by satellite and terrestrial broadcasting and 4K and 8K super hi-vision via satellite broadcasting, provision of 4K and 8K super hi-vision via terrestrial broadcasting (hereinafter, next-generation terrestrial broadcasting) is expected. However, 4K ・ 8K Super Hi-Vision (hereinafter referred to as 4K ・ 8K) has a huge amount of information, and in order to maintain a sufficiently high service time rate to construct a next-generation terrestrial broadcasting network, A sufficiently high transmission power is required which can not be buried. Moreover, in the case of satellite broadcasting, non-linear distortion in satellite repeaters and power reduction due to rainfall attenuation are the main factor of signal degradation, but in terrestrial broadcasting, signal degradation peculiar to ground propagation such as multipath fading and urban noise Occur. Therefore, as the basic performance of the error correction code in the next-generation terrestrial broadcasting, it is required that the error correction capability very close to the Shannon limit be as high as possible by applying an LDPC code with a long code length. Furthermore, since the balance between broadcast quality and service time rate differs depending on the broadcaster, the selection of the information bit rate can be flexibly changed by timely switching the plurality of coding rates, and at least the above-mentioned advanced satellite It is desirable to prepare options equal to or better than the scheme.

  Therefore, as a next-generation terrestrial digital broadcasting system, the code length of the LDPC code is currently 276480 bits, 69120 bits, or 17280 bits, and the coding rate r of the LDPC code is r = 2/16, 3 /. 13 of the LDPC code with 16, 4/16, 5/16, 6/16, 16/16, 16/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16 Classification into types is under consideration.

  A technique is also known in which parity interleaving processing is performed on the area of the LDPC parity of the LDPC code, as in ATSC 3.0, which is the US digital terrestrial television standard (for example, see Non-Patent Document 2). In this case, when hardware is configured as an LDPC coder, an LDPC code is added that is provided with an LDPC parity because information frames satisfying the LDPC coding rate and a transmission frame configured from an LDPC parity are used in the coding process of the LDPC code. The parallelization process and the process of parity interleaving are performed in parallel (for example, see Non-Patent Document 3).

WO 2015/178215 specification

Suzuki et al., "Design of LDPC Codes for Advanced BS Digital Broadcasting", The Journal of the Institute of Image Information and Television Engineers, The Institute of Image Information and Television Engineers, Image Information Media vol. 62, No. 12, December 1, 2008, pp. 1997 -2004 “ATSC standard: Physical Layer Protocol”, 6.2.1, http://www.atsc.org/wp-content/uploads/2016/10/A322-2017-Physical-Layer-Protocol.pdf M. Gomes, et al, “High Throughput Encoder Architecture for DVB-S2 LDPC-IRA Codes,” IEEE ICM (Dec. 2007)

  As described above, as the next-generation terrestrial digital broadcasting system, the code length of the LDPC code is currently 276480, 69120, or 17280 bits, and the coding rate r of the LDPC code is r = 2/16, 3 / 16, 4/16, 5/16, 6/16, 7/16, 16/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16 LDPC codes Classification into 13 types is under consideration. This coding rate number is a sufficiently wider choice than the 11 types adopted in the advanced satellite broadcasting system, and an LDPC code check matrix having performance close to the Shannon limit is optimized and designed for each coding rate.

  Also, as described above, in the LDPC encoder configured to perform parity interleaving processing on the area of the LDPC parity of the LDPC code, the LDPC encoding processing for providing the LDPC parity and the processing of parity interleaving are performed in parallel. It is supposed to be processed.

  From the beginning, the parity interleaving process can be used as one of the bit interleavers along with the group-wise interleaver process (and further the block interleaver process), and may be caused by fading or burst interference waves. The purpose is to disperse burst errors into random errors, and to combine the output results of an LDPC encoder on a logic block circuit that performs serial processing with an LDPC encoder that performs parallel processing as described later. .

  However, under a transmission environment where burst errors may occur, coding according to the code rate of the LDPC code used when the redundancy is low (that is, the code rate is high) among the LDPC codes of 13 kinds of coding rates r. In relation to the structure, it has been found that when parity interleaving processing is performed, transmission performance related to bit error rate may deteriorate.

  As described above, it was found that the deterioration tendency of the transmission performance caused by performing the parity interleaving process relates to the coding structure according to the code rate of the LDPC code, but the LDPC coding process of providing the LDPC parity When using an LDPC coder that processes in parallel the parity interleaving process and the parity interleaving process, a technique for improving transmission performance regardless of the coding structure according to the code rate of the LDPC code is desired.

  Therefore, in view of the above problems, it is an object of the present invention to provide a code rate of an LDPC code with respect to coded data by an LDPC encoder which performs parallel processing of LDPC encoding processing for giving LDPC parity and parity interleaving processing. It is an object of the present invention to provide a bit interleaver, a bit deinterleaver, a transmitting apparatus, a receiving apparatus, and a program for these for digital terrestrial broadcasting, which improve transmission performance regardless of the coding structure according to.

  The bit interleaver according to the present invention is a bit interleaver that performs bit interleaving processing on encoded data by an LDPC encoder that performs parallel processing of LDPC encoding processing that applies LDPC parity and processing of parity interleaving. The parity interleaving process in the LDPC encoder is performed on the LDPC parity data generated and added in units of M bit groups for the target data of the LDPC encoding based on the parity check matrix by the LDPC encoding process. It is configured to reorder regularly based on the code length of the LDPC code, the LDPC coding rate, and the interleaving constant determined by the parallel processing number M corresponding to the M bits, and is output from the LDPC encoder LDPC parity data pair And the processing of the parity interleave in the LDPC encoder characterized in that it comprises a parity deinterleaver for performing inverse processing.

  In the bit interleaver of the present invention, the code length is set to 276480 bits, 69120 bits, or 17280 bits.

  In the bit interleaver of the present invention, the code structure of the LDPC encoder is an LDPC-IRA code.

  Furthermore, the bit deinterleaver of the present invention is a bit deinterleaver that performs inverse processing of the bit interleaver of the present invention, and includes the same processing as parity interleaving processing in the LDPC encoder. .

  Furthermore, a transmitter according to the present invention is characterized by comprising the bit interleaver according to the present invention and the LDPC encoder preceding the bit interleaver.

  Furthermore, a receiver according to the present invention comprises: a bit deinterleaver according to the present invention; parity deinterleaving processing for performing reverse processing of parity interleaving processing in the bit deinterleaver; LDPC decoding processing using the parity check matrix; And an LDPC decoder for parallel processing.

  Furthermore, the program of the present invention is configured as a program for causing a computer to realize one or more functions of the bit interleaver in the transmission device of the present invention and the LDPC encoder.

  Furthermore, the program of the present invention is configured as a program for causing a computer to realize one or more functions of the bit deinterleaver in the receiving device of the present invention and the LDPC decoder.

  According to the present invention, even in a very poor noise environment in terrestrial broadcasting, the LDPC encoding process for parallel processing of LDPC encoding processing for giving LDPC parity and parity interleaving processing is performed for LDPC encoded data, It is possible to improve transmission performance regardless of the coding structure according to the code rate of the code.

FIG. 2 is a block diagram schematically showing only main components of a transmission apparatus in a transmission system of an embodiment according to the present invention. FIG. 5 is a block diagram schematically showing only the main components of a receiver in a transmission system of an embodiment according to the present invention. (A) is a block diagram showing a schematic configuration of a bit interleaver according to an embodiment of the present invention, and a schematic configuration of an LDPC encoder preceded by the bit interleaver; (b) is based on a conventional technique It is a block diagram which shows schematic structure of the bit interleaver of a comparative example, and schematic structure of the LDPC encoder which precedes this bit interleaver. (A) is a block diagram showing a schematic configuration of a bit deinterleaver according to an embodiment of the present invention and a schematic configuration of an LDPC decoder to be added to the bit deinterleaver, and (b) a conventional technique It is a block diagram which shows schematic structure of the bit de-interleaver of a comparative example based on, and schematic structure of the LDPC decoder followed by this bit de-interleaver. FIG. 10 is a diagram showing an interleaving constant determined for each LDPC coding rate used in a parity deinterleaver in a bit interleaver according to an embodiment of the present invention and a parity interleaver in a bit deinterleaver according to an embodiment according to the present invention. . It is a figure for demonstrating the process of the group-wise interleaver of one Example by this invention. FIG. 7 illustrates the processing of the group-wise interleaver of an embodiment according to the present invention. It is a figure for demonstrating the process of the block interleaver of one Example by this invention. It is a figure for demonstrating the process of the block interleaver of one Example by this invention. FIG. 7 is a diagram illustrating an example of block interleaver processing according to an embodiment of the present invention; FIG. 7 is a diagram showing the process (example 2) of the block interleaver according to an embodiment of the present invention; It is a figure which shows the C / N versus BER characteristic at the time of the QPSK modulation | alteration of the LDPC coding rate 7/16 which contrasts the transmission system of one Example based on this invention, and the transmission system of the comparative example based on a conventional technique.

  Hereinafter, with reference to the drawings, a transmitter 1 and a receiver 2 in a transmission system according to an embodiment of the present invention will be described. The transmission system of one embodiment according to the present invention is composed of the transmission device 1 shown in FIG. 1 assuming the next-generation terrestrial broadcast transmission method, and the reception device 2 shown in FIG.

  In the transmission system of one embodiment according to the present invention, the code length of the LDPC code is 276480, or 69120, or 17280 bits, and the coding rate r of the LDPC code is r = 2/16, 3/16, 4/16. 13 types of LDPC codes, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16.

  First, with reference to FIG. 1, a transmitter 1 of an embodiment according to the present invention will be described.

[Transmitting device]
FIG. 1 is a block diagram schematically showing only the main components of a transmitter 1 of an embodiment according to the present invention. The transmission device 1 includes a control unit 11 and a modulation signal transmission unit 12 that transmits a modulation signal generated to transmit an input bit string of a main signal through the processing of the control unit 11. The control unit 11 performs transmission signal processing of the main signal, a transmission frame generation unit 111, an energy spreading unit 112, a BCH encoding unit 113, an LDPC encoder 114, a bit interleaver 115, a mapper / modulation unit 116, and a TMCC generation. And a unit 117.

  The control unit 11 can be configured as a computer including a central processing unit (CPU), and in the storage unit (not shown) included in the computer, the CPU realizes the respective functions in the read control unit 11 by the CPU. Programs are stored.

  The TMCC generation unit 117 is configured as means for generating a TMCC signal including transmission-related parameters such as a modulation scheme and a coding rate and transmitting the TMCC signal before the main signal. That is, the TMCC generation unit 117 transmits the TMCC signal by time division multiplexing with respect to the main signal generated from the transmission frame generation unit 111, so that reception shown in FIG. It is possible to transmit to the device 2 parameters relating to the transmission. Further, the TMCC generation unit 117 instructs the LDPC encoder 114, the bit interleaver 115, and the mapper / modulation unit 116 to use the LDPC coding rate designated by the TMCC signal (hereinafter, also simply referred to as a “coding rate”). And a function of specifying a modulation scheme.

  The transmission frame generation unit 111 divides the input bit string of the main signal into a predetermined length based on the transmission frame configuration according to the LDPC coding rate, and generates a transmission frame that enables LDPC encoding. That is, in the transmission frame generation unit 111, the input bit string of the main signal is divided into (code length) × (coding rate) bits as the information bit length, and is output to the subsequent functional block each time.

  The transmission frame generated by the transmission frame generation unit 111 is composed of information bits satisfying the LDPC coding rate and LDPC parity, and the transmission device 1 performs encoding, interleaving and modulation by using this transmission frame configuration. Then, the receiving device 2 shown in FIG. 2 described later performs demodulation, deinterleaving, and decoding of an error correction code based on the transmission frame configuration.

  The energy spreading unit 112 performs energy spreading (bit randomization) on the output bit sequence of the transmission frame generation unit 111. This is realized by generating pseudo-random “1” and “0” patterns using an M sequence and adding this and data in the slot by MOD 2. As a result, since “1” or “0” will not be continuous, the synchronous reproduction can be stabilized in the receiving device 2 described later.

  The BCH coding unit 113 is an error correction coding process provided as needed as an outer code, and performs BCH coding on predetermined data. As an example of the outer code, it is possible to apply a 192-bit BCH code available for advanced satellite broadcasting, but in addition, a 168-bit BCH code can be applied.

  The BCH parity is basically treated as part of an information bit and has a role of protecting minor bit errors that can not be corrected by the LDPC code. However, most of the ability of error correction depends on the LDPC code. That is, the BCH encoding unit 113 may not be necessary. For example, when the LDPC parity length is equal to the code length of 276480 bits, 69120 bits, or 17280 bits of the LDPC code, the correction capability of the LDPC code is equivalent. Therefore, hereinafter, when using the BCH encoding unit 113, it will be described that the information bits include the parity of the BCH code.

  In any of the LDPC coding rates, the transmission frame length assuming the next-generation terrestrial broadcast transmission scheme corresponds to the LDPC code length of 276,480 bits, or 69,120 bits, or 17280 bits. The 276,480 bits consist of integer multiples of 360 and can be divided by 360 × 768. The 69120 bits are configured by integer multiples of 360 and can be divided by 360 × 192. The 17280 bits are composed of integer multiples of 360 and can be divided by 360 × 48.

  As shown in FIG. 3A, the LDPC encoder 114 performs parallel processing in parallel processing of LDPC encoding processing of giving an LDPC parity by the LDPC coding portion 1141a and processing of parity interleaving by the parity interleaving portion 1141b. A section 1141 is included.

  The LDPC encoding unit 1141a is a processing unit that performs an LDPC encoding process using a parity check matrix of an LDPC code. More specifically, the LDPC encoding unit 1141a generates a parity check matrix H, and uses this parity check matrix H to generate an LDPC code parity. The length in the row direction of the parity check matrix H corresponds to the LDPC code length N. Also, the length in the column direction of the parity check matrix H is the parity length P according to the LDPC coding rate. Also, as described in Non-Patent Document 1, the parity check matrix H has a periodic structure based on the number M of parallel processings.

  The parity interleaving unit 1141 b is a processing unit that performs parity interleaving in which parity bits of the encoded data from the LDPC encoding unit 1141 a are interleaved (bit rearrangement) at the positions of other parity bits. The parity interleaving process performed by the parity interleaving unit 1141 b may be the same as that of ATSC 3.0, which is the US digital terrestrial television standard (see, for example, Non-Patent Document 2).

  As described above, the LDPC encoder 114 is configured to perform parallel processing of LDPC encoding processing for giving LDPC parity by the LDPC encoding unit 1141 a and parity interleaving processing by the parity interleaving unit 1141 b, and the TMCC generation unit 117 LDPC encoding is performed on target data input via the energy spreading unit 112 (or via the BCH coding unit 113) based on a predetermined coding rate specified by the TMCC signal generated in Parallel processing is performed, and the processed data is output to the bit interleaver 115.

  The bit interleaver 115 performs interleaving (bit rearrangement) on data input from the LDPC encoder 114 based on the LDPC coding rate designated by the TMCC signal generated by the TMCC generation unit 117 and a predetermined modulation scheme. , And to the mapper / modulator 116. Details of the bit interleaver 115 will be described later.

The mapper / modulator 116 maps an m-bit symbol to one of 2 ^m signal points based on a predetermined modulation scheme specified by the TMCC signal generated by the TMCC generator 117, and generates an IQ signal (in-phase The modulation signal is generated by performing quadrature modulation as a quadrature signal of component I and quadrature phase component Q). The modulation scheme includes, for example, BPSK (π / 2 shift BPSK (Binary Phase Shift Keying)), QPSK, 8PSK, 16APSK or 16QAM, 32APSK or 32QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, etc., but is typically QPSK, 16 QAM, 64 QAM, 256 QAM, 1024 QAM, or 4096 QAM is used.

  Next, with reference to FIG. 2, the receiver 2 of one embodiment according to the present invention will be described.

[Receiver]
FIG. 2 is a block diagram schematically showing only the main components of the receiver 2 of one embodiment according to the present invention. The receiving device 2 includes a modulated signal receiving unit 21 that receives the modulated signal transmitted from the transmitting device 1, and a control unit 22 that performs signal processing on the modulated signal received by the modulated signal receiving unit 21. The control unit 22 includes a demodulator / demapper 221 that performs signal processing of the main signal, a bit deinterleaver 223, an LDPC decoder 224, a BCH decoder 225, an energy despreader 226, and a TMCC demodulator / decoder 222. Have.

  The demodulator / demapper 221 orthogonally demodulates the modulated signal input from the modulated signal receiver 21, demodulates and demaps the bit deinterleaver 223 (a quadrature signal of the in-phase component I and the quadrature-phase component Q) ) Is output to the bit deinterleaver 223. The TMCC demodulation / decoding unit 222 demodulates / decodes the TMCC signal prior to the demodulation / demapper 221, and designates the modulation scheme applied to the modulation of the main signal to the demodulation / demapper 221. Also, the TMCC demodulation / decoding unit 222 designates, for the bit deinterleaver 223, the coding rate and modulation method applied to the LDPC coding of the main signal, and for the LDPC decoder 224, the LDPC of the main signal Specifies the coding rate and modulation scheme applied to coding.

  The bit deinterleaver 223 corresponds to the inverse processing of the bit interleaver 115 on the transmission apparatus 1 side shown in FIG. 1, and the LDPC coding rate designated by the TMCC signal demodulated and decoded by the TMCC demodulation and decoding unit 222 and Deinterleaving (bit rearrangement) corresponding to the bit interleaver 115 on the transmitting device 1 side is performed on the symbols input from the demodulator / demapper 221 based on a predetermined modulation scheme, and the resultant is output to the LDPC decoder 224. Details of the bit deinterleaver 223 will be described later.

  As shown in FIG. 4A, the LDPC decoder 224 is a parallel processing unit that parallel processes parity deinterleaving processing by the parity deinterleaving unit 2241 a and LDPC decoding processing using an parity check matrix by the LDPC decoding unit 2241 b. It is comprised by 2241.

  Parity de-interleaving section 2241 a reverses the processing of parity interleaving by parity interleaving section 1141 b shown in FIG. 3A in LDPC encoder 114 on the transmitting device 1 side with respect to data of symbols obtained from bit de-interleaver 223. It is a processing unit that performs processing. Therefore, the parity deinterleaving process performed by the parity deinterleaving unit 2241a can be the same as that of ATSC 3.0, which is the U.S. terrestrial digital television standard (see, for example, Non-Patent Document 2).

  The LDPC decoding unit 2241b calculates a log likelihood ratio for data of symbols processed by the parity deinterleave unit 2241a, and the TMCC signal demodulated and decoded by the TMCC demodulation and decoding unit 222 corresponds to the LDPC coding rate specified It is a processing unit that performs an error correction decoding process using an LDPC decoding method such as a sum-product decoding method using the parity check matrix H.

  As described above, the LDPC decoder 224 is configured to perform parallel processing of parity deinterleaving processing by the parity deinterleaving unit 2241 a and LDPC decoding processing using the parity check matrix by the LDPC decoding unit 2241 b. The symbol data obtained from the above is deinterleaved by the parity deinterleave unit 2241a, and then using the parity check matrix H according to the LDPC coding rate, using the LDPC decoding method by the sum-product decoding method etc. Parallel processing is performed to perform error correction decoding processing, and the data after the processing is output to the BCH decoding unit 22.

  The BCH decoding unit 225 performs a decoding process corresponding to the BCH coding unit 113 of the transmission device 1 on the data decoded by the LDPC decoder 224 and outputs the data to the energy despreading unit 226. When the processing of the BCH decoding unit 113 is not required on the transmission device 1 side, the processing of the BCH decoding unit 225 is also unnecessary. Whether or not to use the BCH code may be determined in advance between transmission and reception, or may be included in the TMCC signal.

  Since the energy despreading unit 226 restores the process in which the pseudorandom code is added by MOD2 in the energy spreading unit 112 on the transmitting device 1 side to the data obtained from the BCH decoding unit 225, the same pseudorandom code is added again. It adds by MOD2 and performs energy despreading processing. Thus, the receiving device 2 restores the output bit string corresponding to the input bit string of the main signal transmitted from the transmitting device 1 and outputs the output bit string to the outside.

  As described above, the transmitting device 1 and the receiving device 2 according to the embodiment of the present invention use transmission frames corresponding to error correction codes based on LDPC codes having a long code length, and use each coding rate and each modulation scheme. Combinations can be defined and transmitted in MODCOD. Therefore, it is possible to efficiently transmit the MPEG-2 TS or other digital data stream to be transmitted as the main signal.

  The transmitter 1 and the receiver 2 according to an embodiment of the present invention adopt an LDPC code of code length 276480 bits, 69120 bits or 17280 bits and can be obtained from the parity check matrix initial value table with respect to the LDPC coding rate. It is configured to perform error correction using a parity check matrix. Then, the transmitter 1 and the receiver 2 according to the embodiment of the present invention are groupwise in the bit interleaver 115 (and the bit deinterleaver 223) by combining each coding rate defined by MODCOD and each modulation scheme. The arrangement pattern of signal points is uniform as constellations in the interleaver (and the corresponding group-wise deinterleaver) and as constellations in the mapper / modulator 116 (and demodulator / demapper 221). Optimized combinations and design values are provided for each of Uniform Constellation) and NUC (Non Uniform Constellation).

  Hereinafter, the bit interleaver 115 according to the embodiment of the present invention shown in FIG. 3A and the bit deinterleaver 223 according to the embodiment according to the present invention shown in FIG. 4A will be described in order.

(Bit interleaver)
FIG. 3A is a block diagram showing a schematic configuration of a bit interleaver 115 according to an embodiment of the present invention and a schematic configuration of an LDPC encoder 114 preceded by the bit interleaver. Further, FIG. 3B is a block diagram showing a schematic configuration of a bit interleaver 115 of a comparative example based on the conventional technique, and a schematic configuration of an LDPC encoder 114 preceding the bit interleaver 115. For convenience of explanation, similar components are given the same reference numerals.

  The configuration of the bit interleaver 115 and the LDPC encoder 114 of one embodiment according to the present invention shown in FIG. 3A, and the bit interleaver 115 of a comparative example based on the conventional technique shown in FIG. As can be understood in contrast to the configuration of the encoder 114, the bit interleaver 115 according to an embodiment of the present invention is a parity deinterleaver in front of the group-wise interleaver 1152 and the block interleaver 1153. The difference is in that a point 1151 is provided, and the other components are the same.

  As described above, in the LDPC encoder 114 shown in FIGS. 3A and 3B, the LDPC encoding process of giving the LDPC parity by the LDPC encoder 1141a and the parity interleaving by the parity interleaver 1141b are performed. It is comprised by the parallel processing part 1141 which parallelly processes with a process.

The parity interleaving unit 1141 b in the LDPC encoder 114 generates and adds LDPC in the unit of M bit groups to target data of LDPC encoding based on a parity check matrix by the LDPC encoding process of the LDPC encoding unit 1141 a. A processing unit that regularly _reorders parity data (parity bits) based on the code length of the LDPC code, the LDPC coding rate, and the interleaving constant Q _ldpc determined by the parallel processing number M corresponding to the M bits Bit interleaving is not performed). That is, the parity interleaving unit 1141 b performs the bit order of each block divided by the parallel processing number M for the bit string of the parity bit length P of the LDPC code, similarly to ATSC 3.0 which is the US digital terrestrial television standard. It is a type of block interleaving that performs read / write rearrangement.

Q _ldpc , which is a constant necessary for performing parity interleaver (herein referred to as “interleaving constant” in this specification), is the parity bit length P of the LDPC code and the number M of parallel processings of the parity check matrix of the LDPC code Is given by Q = P / M. More specifically, as shown in FIG. 5, the interleaving constant Q _{ldpc in} which the parallel processing number M = 360 is different between the code length of 276480 bits, the code length of 69120 bits, and the code length of 17280 bits. Furthermore, the coding rate r of each LDPC code r = 2/16, 3/16, 4/16, 5/16, 16/16, 17/16, 16/16, 9/16, 10/16, It has different values according to 11/16, 12/16, 13/16, 14/16.

  Here, in the bit interleaver 115 of the comparative example based on the conventional technique shown in FIG. 3 (b), under the transmission environment where burst errors may occur, in the LDPC-IRA code, LDPC codes of 13 types of coding rate r are used. It has been found that when the redundancy is low (that is, the coding rate is high), the parity interleaving process may deteriorate the transmission performance regarding the bit error rate.

  More specifically, under a transmission environment where burst errors may occur, in the case of a code length of 276,480 bits or a code length of 69,120 bits, the coding rate r = 8/16, 9/16, 10/16, 11/16, In the case of 12/16, 13/16, 14/16, in the case of a code length of 17280 bits, the coding rate r = 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, It was found that when parity interleaving processing is performed at 13/16 and 14/16, the transmission performance related to the bit error rate tends to deteriorate.

  On the other hand, under a transmission environment where burst errors may occur, in the case of a code length of 276,480 bits or a code length of 69,120 bits, the coding rate r = 2/16, 3/16, 4/16, 5/16, 6/16 , 7/16, in the case of a code length of 17280 bits, in the case of a coding rate r = 2/16, 3/16, 4/16, 5/16, 6/16, transmission with or without parity interleaving processing It was also found that there was almost no difference in performance.

  Therefore, as shown in FIG. 3A, the bit interleaver 115 of one embodiment according to the present invention has a function of interleaving (bit rearrangement) on data input from the LDPC encoder 114, and parity A deinterleaver 1151, a group-wise interleaver 1152, and a block interleaver 1153.

  The parity deinterleaver 1151 performs parity deinterleaving (reverse process of parity interleaving) corresponding to the parity interleaving unit 1141 b for parity bits of encoded data obtained from the LDPC encoder 114 (parity interleaving unit 1141 b), that is, parity Parity deinterleaving is performed to restore the positions of the parity bits rearranged by the interleaving unit 1141 b to the original positions, and the encoded data after the parity deinterleaving is output to the group-wise interleaver 1152.

  Since each process of the parity interleaving unit 1141 b and the parity deinterleaver 1151 is the opposite process, the output of the LDPC encoding unit 1141 a and the output of the parity deinterleaver 1151 are the same. Therefore, although the parity interleaving unit 1141 b and the parity interleaver 1151 can originally be omitted on the signal processing block, the process of the LDPC encoding unit 1141 a in which the LDPC encoder 114 assigns the LDPC parity, and the parity interleaving unit In the case of hardware configured to perform parallel processing with the processing of 1411, the processing of the parity deinterleaver 1151 is required to produce the operation and effect according to the present invention.

  Group-wise interleaver 1152 performs group-wise interleaving on the coded data processed by parity de-interleaver 1151, and outputs the coded data after group-wise interleaving to block interleaver 1153.

  Here, the group-wise interleaver 1152 divides the encoded data of one code into 360 bit units from the head thereof, and uses 360 bits of the one section as a bit group to encode the encoded data from the parity interleaver 1151. Interleave in bit group units.

  By performing group-wise interleaving, the error rate can be improved as compared to the case where group-wise interleaving is not performed, and as a result, good communication quality can be secured in data transmission.

  The block interleaver 1153 performs block interleaving to rearrange the encoded data from the group-wise interleaver 1152 in block units, thereby, for example, encoding data of one code into symbols of m bits as a unit of mapping. It is symbolized and output to the mapper / modulator 116.

  Here, the block interleaver 1153 is, for example, a memory in which a column as a storage area for storing a predetermined number of bits in the column direction is arranged in the row direction by the number equal to the bit number m of symbols. By writing the encoded data from the group-wise interleaver 1152 in the column direction and reading it in the row direction with respect to the area, for example, code bits of one code are output as symbols of m bits.

  When the modulation scheme in the mapper / modulation unit 116 is BPSK or QPSK, the improvement effect of the groupwise interleaver 1152 and the block interleaver 1153 is low. Each process by the selector 1152 and the block interleaver 1153 may be omitted.

(Bit de-interleaver)
FIG. 4A is a block diagram showing a schematic configuration of a bit deinterleaver 223 according to an embodiment of the present invention, and a schematic configuration of an LDPC decoder 224 provided behind the bit deinterleaver 223. FIG. 4B is a block diagram showing a schematic configuration of a bit deinterleaver 223 of a comparative example based on the conventional technique and a schematic configuration of an LDPC decoder 224 following the bit deinterleaver 223. The same reference numerals are given to the same components for convenience of explanation.

  The configuration of the bit deinterleaver 223 and the LDPC decoder 224 of one embodiment according to the present invention shown in FIG. 4A and the bit deinterleaver 223 of a comparative example based on the conventional technique shown in FIG. As understood in comparison with the configuration of the LDPC decoder 224, in the bit deinterleaver 223 according to an embodiment of the present invention, parity is added to the block deinterleaver 2231 and the group-wise deinterleaver 2232. The difference is that an interleaver 2233 is provided, and the other components are the same.

  As described above, the LDPC decoder 224 shown in FIGS. 4A and 4B performs parity deinterleaving processing by the parity deinterleaving unit 2241 a and LDPC decoding processing using the parity check matrix by the LDPC decoding unit 2241 b. And a parallel processing unit 2241 that performs parallel processing.

  The parity deinterleaving unit 2241a in the LDPC decoder 224 performs parity interleaving by the parity interleaving unit 1141b in the LDPC encoder 114 on the transmission side shown in FIG. 3A with respect to data of symbols obtained from the bit deinterleaver 223. It is a processing unit that performs reverse processing to processing. That is, the parity deinterleave unit 2241a, like ATSC 3.0, which is the U.S. terrestrial digital television standard, determines the bit order of each block divided by the parallel processing number M for the bit string of the parity bit length P of the LDPC code. Is a type of block deinterleaving that performs read / write rearrangement in accordance with.

  The bit deinterleaver 223 according to the embodiment of the present invention shown in FIG. 4A corresponds to the reverse process of the bit interleaver 115 shown in FIG. The block deinterleaver 2231, the group-wise deinterleaver 2232, and the block-wise deinterleaver 2232 have the function of performing bit deinterleaving of the likelihood of each bit that is data from the demodulator / demapper 221 in order to restore the processing of the selector 115. A parity interleaver 2233 is provided.

  The block deinterleaver 2231 is a block deinterleaver (reverse process of block interleaving) corresponding to the block interleaver 1153 on the transmitting device 1 side, with the likelihood corresponding to each bit of the symbol from the demodulator / demapper 221 as a target. That is, block deinterleaving is performed to return the position of the code bit of the encoded data rearranged by block interleaver 1153 to the original position, and the resultant encoded data is output to group-wise deinterleaver 2232.

  The group-wise deinterleaver 2232 performs group-wise de-interleaving corresponding to the group-wise interleaver 1152 on the transmission apparatus 1 side with respect to each bit likelihood output from the block de-interleaver 2231 (reverse process of group-wise interleaving) That is, by rearranging, in bit group units, the code bits of the encoded data whose arrangement has been changed in bit group units by the group-wise interleaver 1152, the original code is subjected to group-wise deinterleaving, and the resultant code is obtained. The encoded data is output to the parity interleaver 2233.

  The parity interleaver 2233 performs parity interleaving (same process as the parity interleave unit 1141 b on the transmitting device 1 side) on each bit likelihood output from the group-wise deinterleaver 2232, and obtains each bit obtained as a result. The likelihood is output to the parity deinterleave unit 2241 a in the LDPC decoder 224.

  Since each process of the parity deinterleave unit 2241a and the parity interleaver 2233 is the opposite process, the output of the group-wise deinterleaver 2232 and the output of the parity deinterleaver 2241a are the same. Therefore, although the parity deinterleave unit 2241a and the parity interleaver 2233 can originally be omitted on the signal processing block, the LDPC decoder 224 performs parity deinterleaving processing and LDPC decoding processing using a parity check matrix. When configured with hardware that performs parallel processing, the processing of the parity interleaver 2233 is required to produce the operation and effect according to the present invention.

  When the modulation scheme in the mapper / modulation unit 116 is BPSK or QPSK, the improvement effect by the groupwise interleaver 1152 and the block interleaver 1153 is considered to be low because the improvement effect by the group interleaver 115 is low. When each process by the wise interleaver 1152 and the block interleaver 1153 is omitted, each process of the group-wise deinterleaver 2232 and the block deinterleaver 2231 in the bit deinterleaver 223 is omitted.

  Hereinafter, in order to enhance the understanding of the bit interleaver 115 according to the present invention, each process by the group-wise interleaver 1152 and the block interleaver 1153 will also be described. The bit deinterleaver 223 corresponds to the reverse process of the bit interleaver 115, and the group-wise interleaver 1152 and the block interleaver 1153 will be mainly described.

(Group-wise interleaving)
The details of the process of group-wise interleaving performed by group-wise interleaver 1152 will be described with reference to FIGS. 6 and 7. FIG. 6 is a diagram for explaining the process of the group-wise interleaver 1152 according to the embodiment of the present invention, and FIG. 7 shows the process of the group-wise interleaver 1152.

  As shown in FIG. 6, the group-wise interleaver 1152 divides encoded data of one code into 360 bit units from the top, and sets 360 bits of the one section as a bit group to a predetermined pattern (hereinafter referred to as The encoded data from the parity interleaver 1151 is interleaved in units of bit groups in accordance with the “GW pattern”). The GW pattern is determined according to the combination of the modulation scheme and the LDPC coding rate, and is stored and held as a GW table in a predetermined storage unit (not shown). Therefore, as shown in FIG. 7, when the group-wise interleaver 1152 performs the process of group-wise interleaving, the GW pattern is generated from the GW table corresponding to the combination of the modulation scheme and the LDPC coding rate from the predetermined storage unit. Read and process.

  6 and 7 show an example where the code length N is 69120 bits, and when using a BCH code, LDPC according to the LDPC coding rate for information bits (K bits) including BCH parity Parity bits (M bits) are provided.

  Then, when divided by the group-wise interleaver 1152 into 360 bits as its unit size, the encoded data of code length N = 69120 bits consists of bit groups 0, 1, ..., 191, 192 (= 69120/360) bits It is divided into groups.

  Also, in the following, the GW pattern is represented by a sequence of numbers representing a bit group. For example, for coded data with a code length N of 69,120 bits, GW patterns 4, 2, 0, 3, 1 indicate the arrangement of bit groups 0, 1, 2, 3, 4 and bit groups 4, 2, 0, 3 , 1 and interleaving (sorting).

  As shown in FIG. 7, group-wise interleaver 1152 interleaves the sequence of bit groups 0 to 191 of coded data of code length N = 69,120 bits in the order of predetermined GW patterns shown in the GW table.

(Block interleaving)
Next, the details of the block interleaving process performed by the block interleaver 1153 will be described with reference to FIGS. 8 to 11. FIGS. 8 and 9 are diagrams for explaining the processing of the block interleaver 1153 according to one embodiment of the present invention, and FIG. 10 shows the processing (example 1) of the block interleaver 1153 and FIG. The process (example 2) of the block interleaver 1153 is shown. 8 to 11 show an example in which the code length N is 69120 bits.

  First, the block interleaver 1153 illustrated in FIG. 8 has a storage area called Part 1 (Part 1) and a storage area called Part 2 (Part 2). Then, the block interleaver 1153 performs block interleaving by writing and reading encoded data with respect to the part 1.

  The parts 1 and 2 both store 1 bit in the row direction and store a predetermined number of bits in the column direction, so that a column as a storage area is a symbol in the row direction. Are arranged side by side by the number C equal to the number of bits m constituting

  Assuming that the number of rows (number of bits) that each column of Part 1 stores in the column direction is the part column length R1, and the number of rows (number of bits) that each column of Part 2 stores in the column direction is the part column length R2. R1 + R2) × C is equal to the code length N (69,120 bits in this embodiment) of the encoded data to be subjected to block interleaving.

  The part column length R1 is equal to a multiple of 360 bits as a unit size, and the part column length R2 is the sum of the part column length R1 of part 1 and the part column length R2 of part 2 (hereinafter also referred to as column length ) R1 + R2 is equal to the remainder when dividing the unit size by 360 bits.

  Here, the column length R1 + R2 is equal to the value obtained by dividing the code length N of the encoded data to be subjected to block interleaving by the number of bits m constituting the symbol.

  For example, in the case of adopting 16 QAM as a modulation scheme for coded data with a code length N of 69,120 bits, the number of bits m of symbols is 4 bits, so the column length R1 + R2 is 17280 (= 69120/4) Become a bit.

  Further, since the remainder is 0 when the column length R1 + R2 = 17280 is divided by 360 bits as the unit size, the part column length R2 of part 2 is 0 bit.

  The part column length R1 of part 1 is R1 + R2-R2 = 17280 bits.

  By the way, the part column length R2 of the part 2 may be always 0 bit or may be configured to perform block interleaving only in one of the part 1 and the part 2. For example, even if the modulation scheme is any of QPSK, 16 QAM, 64 QAM, 256 QAM, 1024 QAM, and 4096 QAM, only part 1 may be subjected to block interleaving.

  However, in this example, as a combination of the code length N and the modulation method, the number of columns m of the parts 1 and 2 and the part column lengths (number of lines) R1 and R2 are configured as shown in FIG. . Referring to FIG. 9, only 1024 QAM is set as R2> 0, and the region of part 2 where block interleaving is not performed is set only when the modulation scheme is 1024 QAM. Then, the block interleaver 1153 performs block interleaving by writing and reading encoded data with respect to the part 1.

  For example, as shown in FIG. 10, when the modulation scheme is any one of QPSK, 16 QAM, 64 QAM, 256 QAM, and 4096 QAM, the block interleaver 1153 determines the code length N and the multi-level number m (the symbol bit number m By writing the encoded data from the group-wise interleaver 1152 in the row direction in the row direction and reading out in the row direction for the entire block of encoded data represented by The sign bit of is output as an m-bit symbol. If the modulation scheme is any of QPSK, 16 QAM, 64 QAM, 256 QAM, and 4096 QAM, then R2 = 0 and block interleaving is performed for the entire block of coded data.

  Further, as shown in FIG. 11, when the modulation scheme is 1024 QAM, the block interleaver 1153 starts from the block of coded data represented by the code length N and the multi-level number m (equal to the number of bits of symbol m). By writing the encoded data from the groupwise interleaver 1152 in the row direction in the row direction and reading out in the row direction for the portion of the part 1 which has been cut out, for example, the code bits for one code are m bits Output as a symbol of. R2 = 720, and part 2 does not perform block interleaving.

  Thus, in the block interleaver 1153, writing the code bits of the encoded data of one code word from the top to the bottom of the column of Part 1 (column direction) is a row from the left to the right column. It will be. Then, when the writing of the code bit is completed to the bottom of the rightmost column (m-th column) of the column of Part 1, the remaining code bits are directed downward from above the column of Part 2 (column direction) Writing is done towards the left to right column. After that, when the writing of the code bit is finished to the bottom of the rightmost column (the m-th column) of the column of Part 2, from the first row of all the m columns of Part 1 to the row direction, m The sign bit is read out in bit units. When reading of code bits from all m columns in part 1 is finished up to the last line R1, starting from the first line of all m columns in part 2, in the row direction, in m bits, The code bit is read out and is performed to the last line, the R2 line.

  As described above, the block interleaver 1153 outputs the code bits read out in the m-bit unit from the parts 1 and 2 to the mapper / modulation unit 116 as m-bit symbols.

(Error rate performance of transmission system according to one embodiment of the present invention)
As described above, when the modulation scheme is BPSK or QPSK, each processing of the group-wise interleaver 1152 and the block interleaver 1153 can be omitted in the bit interleaver 115. Therefore, in order to confirm the operation and effect according to the present invention described above, the transmitter 1 provided with the bit interleaver 115 consisting only of the parity deinterleaver 1151 and the bit deinterleaver 223 consisting only of the parity interleaver 2233 The error rate performance of the transmission system consisting of the receiver 2 was evaluated in comparison with the conventional technique assuming a form without the bit interleaver 115 and the bit deinterleaver 223. FIG. 12 shows C / N vs. BER characteristics when applying QPSK modulation with LDPC coding rate 7/16 comparing the transmission system of one embodiment according to the present invention with the transmission system of a comparative example based on the conventional technique. FIG.

Here, as the LDPC code, a parity check matrix of an LDPC-IRA code with a code length of 17280 bits is used. The coding rate is 7/16, the interleaving constant Q _ldpc = 27 (= 17280 * (1-7 / 16) / 360), and the modulation scheme is QPSK. In addition, under a Rayleigh fading channel environment where burst errors may occur, the decoding algorithm is a sum-product decoding method, the number of iterations of decoding is 50 times, and the evaluation of error rate performance is data before BCH decoding (ie, , Equivalent to no BCH code).

As understood from FIG. 12, according to the transmission system of the present invention, C / N improves by about 0.15 "dB" at bit error rate (BER) = 10 ^-7 , for example. I understand.

  In the bit interleaver 115 and the parity interleaver 2233 according to the present invention, as shown in FIGS. 3A and 4A, respectively, the group-wise interleaver 1152, the block interleaver 1153, and the block deinterleaver 2231. When the group-wise deinterleaver 2232 is provided, it is assumed that the error rate performance changes, but even in that case, the effectiveness of the present invention as illustrated in FIG. 12 is confirmed.

  Also, although only one example is shown in FIG. 12, when using a parity check matrix of an LDPC-IRA code under an environment of a Rayleigh fading transmission path where burst errors may occur, the code length is 276,480 bits or 69120 bits. In the case of a coding rate r = 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16, in the case of a code length of 17280 bits, the coding rate r = 7 When parity interleave processing is performed when / 16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16, the transmission performance regarding the bit error rate is rather It is also known that it tends to deteriorate, and the effect can be confirmed by configuring a transmission system based on the above-described technique.

  On the other hand, in the case of a Rayleigh fading channel in which burst errors may occur, in the case of a code length of 276,480 bits or a code length of 69,120 bits, the coding rate r = 2/16, 3/16, 4/16, 5 / When the coding rate is r = 2/16, 3/16, 4/16, 5/16, 16/16 in the case of the code length 17280 bits at 16, 16/16, 7/16, parity interleaving is performed. It is also possible to confirm that the operation can be confirmed by configuring a transmission system based on the above-described technique that there is almost no difference in transmission performance due to the presence or absence of processing.

  With regard to the embodiment described above, a computer functioning as the control units 11 and 22 of the transmission device 1 and the reception device 2 is configured, and the means of the bit interleaver and bit deinterleaver, and the transmission device 1 and the reception device 2 are functioned. It is possible to preferably use a program for Specifically, the control units 11 and 22 for controlling each means can be configured by a central processing unit (CPU) in a computer, and a memory that appropriately stores programs required to operate each means The unit can consist of at least one memory. That is, by causing the CPU to execute the program in such a computer, it is possible to realize the functions of the respective units described above. Furthermore, a program for realizing the function of each unit can be stored in a predetermined area of the storage unit (memory) described above. Such a storage unit can be configured by a RAM or ROM inside the device, or can also be configured by an external storage device (for example, a hard disk). Also, such a program can be configured as part of software (stored in a ROM or an external storage device) on an OS used by a computer. Furthermore, a program for causing such a computer to function as each means can be recorded on a computer readable recording medium. Further, each means described above can be configured as a part of hardware or software, and can be realized by combining each.

  Although the foregoing embodiments have been described as representative examples, it will be apparent to those skilled in the art that many modifications and substitutions can be made within the spirit and scope of the present invention. For example, as other error correction coding when combined with LDPC coding, besides BCH coding, not only block coding such as Reed-Solomon coding, but also convolutional coding may be used, or LDPC encoding may be combined. Accordingly, the present invention should not be construed as limited by the embodiments described above, but only by the scope of the claims.

  The bit interleaver and the bit deinterleaver according to the present invention, and the transmitting apparatus and the receiving apparatus are useful in a transmission system that time-division multiplexes plural kinds of digital modulation schemes when the code length of the LDPC code is different in various transmission schemes. is there.

DESCRIPTION OF SYMBOLS 1 transmitting device 11 control unit 12 modulated signal transmitting unit 111 transmission frame generating unit 112 energy spreading unit 113 BCH encoding unit 114 LDPC encoder 115 bit interleaver 116 mapper / modulation unit 117 TMCC generating unit 2 receiver 21 received modulated signal Unit 22 Control unit 221 Demodulation unit / demapper 222 TMCC demodulation / decoding unit 223 Bit deinterleaver 224 LDPC decoder 225 BCH decoding unit 226 Energy despreading unit 1141 Parallel processing unit of LDPC encoder 1141a LDPC encoding unit 1141b LDPC code Interleaver 1151 Parity deinterleaver 1152 Groupwise interleaver
1153 block interleaver 2231 block deinterleaver 2232 groupwise deinterleaver 2233 parity interleaver 2241 parallel processing unit of LDPC decoder 2241a parity deinterleaving unit of LDPC decoder 2241b LDPC decoding unit

Claims (8)

A bit interleaver that performs bit interleaving processing on coded data by an LDPC encoder that performs parallel processing of LDPC encoding processing that applies LDPC parity and parity interleaving processing,
The parity interleaving process in the LDPC encoder is performed on the LDPC parity data generated and added in units of M bit groups for the target data of the LDPC encoding based on the parity check matrix by the LDPC encoding process. It is configured to reorder regularly based on a code length of the LDPC code, an LDPC coding rate, and an interleaving constant determined by the parallel processing number M corresponding to the M bits,
A bit interleaver characterized by comprising a parity deinterleaver for performing reverse processing to the data of LDPC parity output from the LDPC encoder with parity interleave processing in the LDPC encoder.   The bit interleaver according to claim 1, wherein the code length is 276480 bits, or 69120 bits, or 17280 bits.   The bit interleaver according to claim 1 or 2, wherein a code structure of the LDPC encoder is an LDPC-IRA code.   A bit deinterleaver for performing inverse processing of the bit interleaver according to any one of claims 1 to 3, characterized in that it includes the same processing as the processing of parity interleaving in the LDPC encoder. De interleaver. A bit interleaver according to any one of claims 1 to 3;
The LDPC encoder preceded by the bit interleaver,
A transmitter comprising: A bit deinterleaver according to claim 4;
A parity de-interleaving process that reverses the parity interleaving process in the bit de-interleaver; and an LDPC decoder that parallel processes the LDPC decoding process using the parity check matrix;
A receiver comprising:   A program for causing a computer to realize one or more functions of the bit interleaver in the transmission apparatus according to claim 5 and the LDPC encoder.   A program for causing a computer to realize one or more functions of the bit deinterleaver and the LDPC decoder in the receiving device according to claim 6.