JP2019102599A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
JP2019102599A
JP2019102599A JP2017230638A JP2017230638A JP2019102599A JP 2019102599 A JP2019102599 A JP 2019102599A JP 2017230638 A JP2017230638 A JP 2017230638A JP 2017230638 A JP2017230638 A JP 2017230638A JP 2019102599 A JP2019102599 A JP 2019102599A
Authority
JP
Japan
Prior art keywords
semiconductor
insulating resin
semiconductor substrate
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017230638A
Other languages
Japanese (ja)
Inventor
博之 倉田
Hiroyuki Kurata
博之 倉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2017230638A priority Critical patent/JP2019102599A/en
Publication of JP2019102599A publication Critical patent/JP2019102599A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

To provide a semiconductor device manufacturing method which simply achieves downsizing and low profile.SOLUTION: A manufacturing method of a semiconductor device 1A which comprises an electrode 22 on a surface of a conductive semiconductor chip 21a and in which lateral faces of the semiconductor chips are coated with an insulating resin 50, includes the steps of: forming electrodes on a surface of a conductive semiconductor substrate 20; attaching a surface of the semiconductor substrate opposite to the surface where the electrodes are formed to a support member 60; dicing the semiconductor substrate by removing part of the semiconductor substrate from the surface side and forming clearances among neighboring semiconductor chips to arrange the semiconductor chips in an array on the support member in a state of keeping clearances; selectively filing up the clearances with the insulating resin so as to cover lateral faces of the semiconductor chips; and removing part of the filled up insulating resin by grinding to dice the semiconductor substrate into individual semiconductor devices. The step of dicing into semiconductor devices is a step of removing part of the insulating resin by leaving the insulating resin on the lateral faces of the semiconductor chips.SELECTED DRAWING: Figure 1

Description

本発明は、小型化、低背化の要求に応える半導体装置の製造方法に関し、特に半導体チップの側面が絶縁性樹脂で被覆された半導体装置の製造方法に関する。   The present invention relates to a method of manufacturing a semiconductor device that meets the demand for downsizing and low profile, and more particularly to a method of manufacturing a semiconductor device in which the side surface of a semiconductor chip is covered with an insulating resin.

電子機器の小型化に伴い、実装する半導体装置の小型化、低背化が求められている。そのため、半導体装置を実装基板上にベアチップ状態で直接接続する方法が採られている。図6は、ベアチップ状態の半導体装置2Aを実装基板10上に実装した状態を示す図である。実装基板10表面には、配線金属11が形成されている。一方半導体装置2Aは、導電性の半導体チップ21の表面側(図面では下側)に図示しない半導体素子が形成されており、この半導体素子に接続する電極22が半導体チップ21の表面に形成されている。
また、半導体チップ21の表面は、電極22の表面の一部を除き、絶縁膜23で覆われている。一般的に実装基板10に実装する際、配線金属11と電極22とが接合部材の半田30により接続されている。
With the miniaturization of electronic devices, miniaturization and reduction in height of semiconductor devices to be mounted are required. Therefore, a method of directly connecting a semiconductor device on a mounting substrate in a bare chip state is adopted. FIG. 6 is a view showing the bare chip semiconductor device 2A mounted on the mounting substrate 10. As shown in FIG. A wiring metal 11 is formed on the surface of the mounting substrate 10. On the other hand, in the semiconductor device 2A, a semiconductor element (not shown) is formed on the surface side (lower side in the drawing) of the conductive semiconductor chip 21 and an electrode 22 connected to the semiconductor element is formed on the surface of the semiconductor chip 21. There is.
The surface of the semiconductor chip 21 is covered with the insulating film 23 except for a part of the surface of the electrode 22. Generally, when mounting on the mounting substrate 10, the wiring metal 11 and the electrode 22 are connected by the solder 30 of the bonding member.

このように半導体装置2Aは、その表面は絶縁膜23で覆われているものの、側面は半導体チップ21の切断面を露出する構造となっていた。そのため、実装基板10に半田30を用いて実装する際、位置ずれやチップの傾き等の不具合が発生した場合、図7に示すように半田30が半導体チップ21の側面を這い上がり、導電性の半導体チップ21と短絡してしまうという問題があった。   As described above, although the surface of the semiconductor device 2A is covered with the insulating film 23, the side surface has a structure in which the cut surface of the semiconductor chip 21 is exposed. Therefore, when mounting defects on the mounting substrate 10 using the solder 30 occurs, such as misalignment or inclination of the chip, the solder 30 creeps up the side of the semiconductor chip 21 as shown in FIG. There is a problem of shorting with the semiconductor chip 21.

そこで、このような問題を解決するために、半導体チップ21の側面を絶縁化する方法が検討されている。その一つの方法として、半導体装置の側面を絶縁性樹脂で被覆することが考えられ、例えば特許文献1には、個片化した半導体チップを封止樹脂で被覆し、切断することで半導体装置の側面あるいは裏面を樹脂で覆い、その後個片化して半導体装置を形成する方法が開示されている。具体的にはまず、バンプ電極22Bを備えた半導体チップ80をインターポーザ40上に実装する(図8a)。バンプ電極22Bは高さが高い接合を形成するため、半田等の這い上がりによる不具合を防止することができる。その後全面に絶縁性樹脂50を塗布し、平坦化する(図8b)。ダイシングテープ60に絶縁性樹脂50の平坦な表面を貼り付けて、インターポーザ40側からダイシングソー70を用いて個片化する(図8c)。ここで個片化する際、絶縁性樹脂50側からは切断位置を確認することができないため、配線等が形成されたインターポーザ40側から切断することになる。また、絶縁性樹脂50をダイシングテープ60に貼り付けるため、絶縁性樹脂50は平坦にする必要があった。その結果、個片化された半導体装置2Bは、インターポーザ40上に矩形の絶縁性樹脂が形成された構造となり、インターポーザ40に形成された電極を実装基板等に実装する場合に半田の這い上がりが起こったとしても、ショート等の不具合が発生することがなくなる。   Then, in order to solve such a problem, the method of insulating the side surface of the semiconductor chip 21 is examined. As one of the methods, it is conceivable to coat the side surface of the semiconductor device with an insulating resin. For example, Patent Document 1 discloses that a semiconductor chip which has been singulated is covered with a sealing resin and cut. A method is disclosed in which the side or back surface is covered with a resin and then singulated to form a semiconductor device. Specifically, first, the semiconductor chip 80 provided with the bump electrode 22B is mounted on the interposer 40 (FIG. 8a). Since the bump electrode 22B forms a junction having a high height, it is possible to prevent a defect due to a creeping up of solder or the like. Thereafter, an insulating resin 50 is applied to the entire surface and planarized (FIG. 8b). The flat surface of the insulating resin 50 is attached to the dicing tape 60, and singulated from the interposer 40 side using the dicing saw 70 (FIG. 8c). Here, when singulating, since the cutting position can not be confirmed from the insulating resin 50 side, the cutting is performed from the interposer 40 side on which the wiring and the like are formed. Moreover, in order to affix the insulating resin 50 to the dicing tape 60, the insulating resin 50 needs to be flat. As a result, the singulated semiconductor device 2B has a structure in which a rectangular insulating resin is formed on the interposer 40, and when the electrodes formed on the interposer 40 are mounted on a mounting substrate or the like, the solder creeps up Even if it happens, problems such as short circuit will not occur.

また、半導体チップ80を被覆する絶縁性樹脂50は、半導体チップ80の信頼性を確保するように形成されるので、厚く形成されるのが一般的であった。   In addition, since the insulating resin 50 for covering the semiconductor chip 80 is formed to secure the reliability of the semiconductor chip 80, it is generally formed to be thick.

さらにまた特許文献2には、半導体ウエハをダイシングテープに貼り付け、個片化し、ダイシングテープをエキスパンドして、個片化した半導体チップ同士の間隔を広げ図8(a)に相当する状態とし、その間隙に封止樹脂を充填する(図8bに相当)技術が開示されている。その後、個片化する方法も図8(c)に示す方法と同様で、封止樹脂をダイシングテープ60に貼り付け、封止樹脂とは反対側を表面にしてダイシングソー70により個片化する方法が採られている。   Furthermore, in Patent Document 2, a semiconductor wafer is attached to a dicing tape, divided into pieces, and the dicing tape is expanded to widen the spaces between the separated semiconductor chips, to be in a state corresponding to FIG. A technique for filling the gap with a sealing resin (corresponding to FIG. 8b) is disclosed. Thereafter, the method of singulating is the same as the method shown in FIG. 8C, and the sealing resin is attached to the dicing tape 60, and singulated with the dicing saw 70 with the opposite side to the sealing resin as the surface. The method is taken.

特許第3741670号公報Patent No. 3741670 gazette 特開2003−273279号公報JP 2003-273279 A

従来、ベアチップ状態の半導体装置を半田等の接合部材で実装する際、接合部材が導電性の半導体チップの側面を這い上がり、半導体チップと短絡してしまうという問題があった。この問題を解決する方法として、半導体装置の側面を絶縁性樹脂で覆う方法も提案されている。   Conventionally, when mounting a semiconductor device in a bare chip state with a bonding member such as solder, there has been a problem that the bonding member crawls up the side surface of the conductive semiconductor chip and shorts with the semiconductor chip. As a method of solving this problem, a method of covering the side surface of the semiconductor device with an insulating resin is also proposed.

しかし、従来提案されている方法は、インターポーザ40を使用したり、絶縁性樹脂50の表面をダイシングテープに密着させるため、半導体チップ上に厚い絶縁性樹脂を塗布する必要があり、半導体装置の低背化の妨げとなっていた。   However, in the method proposed conventionally, it is necessary to apply a thick insulating resin on the semiconductor chip in order to use the interposer 40 or to bring the surface of the insulating resin 50 into close contact with the dicing tape. It had been an obstacle to turning her back on.

本発明は、半導体装置への接合部材の這い上がりによる不具合を防止するとともに、低背化を実現する半導体装置の製造方法を提供することを目的とする。   An object of the present invention is to provide a method of manufacturing a semiconductor device which prevents a defect due to creeping of a bonding member to a semiconductor device and realizes a reduction in height.

上記目的を達成するため、本願請求項1に係る半導体装置の製造方法は、導電性の半導体チップの表面に電極を備え、前記半導体チップの側面が絶縁性樹脂で被覆された半導体装置の製造方法において、導電性の半導体基板表面に前記電極を形成する工程と、前記半導体基板の電極を備えた面と反対側の面を支持用部材に貼り付けて、前記半導体基板の表面側から一部を除去して個片化し、隣接する前記半導体チップ間に間隙を形成することにより、前記支持用部材上に前記間隙を保った状態で前記半導体チップを整列配置する工程と、整列配置した前記半導体チップの側面を覆うように、前記間隙に選択的に前記絶縁性樹脂を充填する工程と、前記充填した絶縁性樹脂の一部を切削除去することにより、個々の前記半導体装置に個片化する工程を含み、前記半導体装置に個片化する工程は、前記半導体チップの側面に前記絶縁性樹脂を残し、前記絶縁性樹脂の一部を除去する工程であることを特徴とする。   In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present application is a method of manufacturing a semiconductor device in which an electrode is provided on the surface of a conductive semiconductor chip and the side surface of the semiconductor chip is covered with an insulating resin. And a step of forming the electrode on the surface of the conductive semiconductor substrate, and affixing a surface of the semiconductor substrate opposite to the surface provided with the electrode on a supporting member, and a part of the semiconductor substrate from the surface side Aligning the semiconductor chips while maintaining the gap on the supporting member by removing and singulating and forming a gap between the adjacent semiconductor chips; Selectively filling the gap with the insulating resin so as to cover the side surface of the semiconductor device, and cutting and removing a part of the filled insulating resin to singulate the individual semiconductor devices Includes a degree, the step of dicing said semiconductor device, said leaving the insulating resin on a side surface of the semiconductor chip, characterized in that it is a process of removing part of the insulating resin.

本願請求項2に係る半導体装置の製造方法は、導電性の半導体チップの表面に電極を備え、前記半導体チップの側面が絶縁性樹脂で被覆された半導体装置の製造方法において、導電性の半導体基板表面に前記電極を形成する工程と、前記半導体基板の電極を備えた面と反対側の面を支持用部材に貼り付けて、前記半導体基板の表面側から個片化の際除去される領域の一部を残して前記半導体基板に溝を形成する工程と、前記溝に選択的に前記絶縁性樹脂を充填する工程と、前記充填した絶縁性樹脂と前記半導体基板の一部を除去することにより、個々の前記半導体装置に個片化する工程を含み、前記半導体装置に個片化する工程は、前記半導体チップの側面に前記絶縁性樹脂を残し、前記絶縁性樹脂と前記半導体基板の一部を除去する工程であることを特徴とする。   A method of manufacturing a semiconductor device according to a second aspect of the present invention is a method of manufacturing a semiconductor device in which an electrode is provided on the surface of a conductive semiconductor chip, and the side surface of the semiconductor chip is covered with an insulating resin. The step of forming the electrode on the surface, and the surface of the semiconductor substrate opposite to the surface provided with the electrode are attached to a supporting member, and the region removed from the surface side of the semiconductor substrate during singulation By leaving a part and forming a groove in the semiconductor substrate, filling the groove with the insulating resin selectively, and removing the filled insulating resin and part of the semiconductor substrate And a step of singulating the individual semiconductor devices, wherein the step of singulating the semiconductor devices leaves the insulating resin on the side surface of the semiconductor chip, and forms part of the insulating resin and the semiconductor substrate. In the process of removing And wherein the Rukoto.

本願請求項3に係る半導体装置の製造方法は、請求項2記載の半導体装置の製造方法において、前記半導体装置に個片化する工程は、前記半導体チップの側面に前記絶縁性樹脂を残して、前記絶縁性樹脂を除去した後、前記半導体基板の一部を除去する際、前記半導体基板の裏面を研削する工程を含むことを特徴とする。   A method of manufacturing a semiconductor device according to a third aspect of the present invention is the method of manufacturing a semiconductor device according to the second aspect, wherein the step of singulating the semiconductor device leaves the insulating resin on the side surface of the semiconductor chip. The method may further include the step of grinding the back surface of the semiconductor substrate when removing part of the semiconductor substrate after removing the insulating resin.

本発明によれば、絶縁性を保ちつつ半導体基板の裏面を覆う絶縁性樹脂を無くすことができるので、半導体装置の小型化、低背化を実現することが可能となる。   According to the present invention, since the insulating resin covering the back surface of the semiconductor substrate can be eliminated while maintaining the insulating property, the semiconductor device can be miniaturized and the height thereof can be reduced.

また本発明の半導体装置の製造方法は、半導体基板を支持用部材上に貼り付けた後、半導体チップに個片化し、半導体チップ間の間隙を絶縁性樹脂で被覆する工程や半導体装置に個片化する工程を連続して行うことができるので、非常に簡便な方法である。   In the method of manufacturing a semiconductor device according to the present invention, after bonding the semiconductor substrate onto the supporting member, the semiconductor chip is singulated, and the space between the semiconductor chips is covered with the insulating resin. It is a very simple method because the step of forming can be carried out continuously.

特に、支持用部材上に貼り付けた状態のままで連続して半導体装置を製造するので、100μm程度の薄い半導体チップであっても問題なく製造することが可能となり、より低背化を実現できるという利点がある。   In particular, since the semiconductor device is continuously manufactured in the state of being stuck on the supporting member, even a thin semiconductor chip of about 100 μm can be manufactured without any problem, and a lower height can be realized. It has the advantage of

さらにまた、比較的厚い状態で支持用部材から取り外し、半導体基板の裏面を研削することでも、低背化を実現できるという利点がある。   Furthermore, there is an advantage that the height can be reduced by removing the support member from the supporting member in a relatively thick state and grinding the back surface of the semiconductor substrate.

本発明の第1の実施例の半導体装置の製造工程を説明する図である。FIG. 7 is a drawing for explaining the manufacturing process of the semiconductor device of the first embodiment of the present invention. 本発明の第1の実施例の製造方法による半導体装置の説明図である。It is explanatory drawing of the semiconductor device by the manufacturing method of the 1st Example of this invention. 本発明の第2の実施例の半導体装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device of the 2nd example of the present invention. 本発明の第2の実施例の製造方法による半導体装置の説明図である。It is explanatory drawing of the semiconductor device by the manufacturing method of the 2nd Example of this invention. 本発明の第3の実施例の半導体装置の製造工程を説明する図である。It is a figure explaining the manufacturing process of the semiconductor device of the 3rd example of the present invention. 半導体チップを実装基板上に実装した状態を示す図である。It is a figure which shows the state which mounted the semiconductor chip on the mounting substrate. 実装時に半導体チップ側面へ半田の這い上がりが発生した場合の説明図である。FIG. 13 is an explanatory view of a case where solder creeping up on the side surface of the semiconductor chip occurs at the time of mounting. 半導体装置を絶縁性樹脂で被覆する従来の製造方法の説明図である。It is explanatory drawing of the conventional manufacturing method which coat | covers a semiconductor device with insulating resin.

本発明は、半導体チップの側面を絶縁性樹脂で覆った半導体装置の製造方法を提案するものである。特に本発明の製造方法による半導体装置は実装する際、半田等の接合部材が半導体チップの側面を這い上がったとしても、その側面を絶縁性樹脂で被覆しており、短絡等の不具合の発生を未然に防止している。以下、本発明の実施例について、詳細に説明する。   The present invention proposes a method of manufacturing a semiconductor device in which the side surface of a semiconductor chip is covered with an insulating resin. In particular, when mounting a semiconductor device according to the manufacturing method of the present invention, even if a bonding member such as solder crawls up the side surface of the semiconductor chip, the side surface is covered with an insulating resin, and problems such as short circuit occur. It is preventing in advance. Hereinafter, examples of the present invention will be described in detail.

まず、本発明の第1の実施例について、半導体チップの側面全体を絶縁性樹脂で被覆する構造の半導体装置の製造方法を例にとり、詳細に説明する。   First, a method of manufacturing a semiconductor device having a structure in which the entire side surface of a semiconductor chip is covered with an insulating resin will be described in detail with reference to the first embodiment of the present invention.

図1に本実施例の半導体装置の製造方法を示す。通常の半導体装置の製造方法に従い、厚さ630μm程度の導電性の半導体基板20の表面側(図1の上側)に図示していない所望の半導体素子を形成し、この半導体素子に接続する電極22を半導体基板20の表面に形成する。半導体基板20の表面は、電極22表面の一部を露出するように絶縁膜23で被覆されている。次に必要に応じて通常の半導体装置の製造工程に従って、半導体基板20の裏面側を所定の厚さ(例えば260μm程度)となるまで研削する(図示省略)。   FIG. 1 shows a method of manufacturing the semiconductor device of this embodiment. A desired semiconductor element (not shown) is formed on the surface side (upper side in FIG. 1) of a conductive semiconductor substrate 20 having a thickness of about 630 μm in accordance with a general semiconductor device manufacturing method, and an electrode 22 connected to this semiconductor element Are formed on the surface of the semiconductor substrate 20. The surface of the semiconductor substrate 20 is covered with an insulating film 23 so as to expose a part of the surface of the electrode 22. Next, the back surface side of the semiconductor substrate 20 is ground (not shown) to a predetermined thickness (for example, about 260 μm) in accordance with the usual semiconductor device manufacturing process as needed.

続いて、半導体基板20の表面と反対側の裏面をダイシングテープ60(支持用部材に相当)に貼り付ける。ダイシングソー70Aを用いて、半導体基板20の表面側から半導体基板20の一部を格子状に、ダイシングテープ60へ到達する領域まで除去し、第1の貫通溝90aを設ける。図1(a)は、ダイシング工程の途中工程を示しており、図中点線で示す領域が第1の貫通溝90aの形成予定領域であり、隣接する半導体チップ間の間隙に相当する。   Subsequently, the back surface opposite to the front surface of the semiconductor substrate 20 is attached to a dicing tape 60 (corresponding to a supporting member). A part of the semiconductor substrate 20 is removed in a lattice shape from the surface side of the semiconductor substrate 20 to the area reaching the dicing tape 60 using the dicing saw 70A, and a first through groove 90a is provided. FIG. 1A shows an intermediate step of the dicing step, and a region shown by a dotted line in the drawing is a formation planned region of the first through groove 90a, which corresponds to a gap between adjacent semiconductor chips.

第1の貫通溝90aにより分離状態とした半導体チップ21aは、ダイシングテープ60上に所定の間隔(ダイシングソー70Aにより切削除去された幅)を保ち配置した状態となる。一例としては、厚さ50μmのダイシングソー70Aを使用して半導体基板20を個片化すると、第1の貫通溝90aは幅50μm程度となる。一般的な半導体装置の製造工程では、このように個片化した後にダイシングテープ60をエキスパンドし、半導体チップ21a間の間隔を広げる。しかしながら本実施例では、整列配置の状態を保つために、ダイシングテープ60をエキスパンドしない。   The semiconductor chips 21a separated by the first through grooves 90a are arranged on the dicing tape 60 with a predetermined interval (width cut and removed by the dicing saw 70A). As an example, when the semiconductor substrate 20 is singulated using a dicing saw 70A having a thickness of 50 μm, the first through groove 90a has a width of about 50 μm. In a general semiconductor device manufacturing process, the dicing tape 60 is expanded after being singulated in this manner to widen the space between the semiconductor chips 21a. However, in the present embodiment, the dicing tape 60 is not expanded in order to maintain the state of alignment.

続いて、この整列配置の状態を保ったまま半導体基板の外周端から1cm程度離れたダイシングテープ60上にディスペンス法により、高さ1mm程度のダムで囲む(図示省略)。ダム材料としては、シリコーン樹脂やエポキシ樹脂等から選ぶことができる。   Subsequently, with the alignment state maintained, a dam of about 1 mm in height is surrounded by a dispensing method on a dicing tape 60 separated by about 1 cm from the outer peripheral end of the semiconductor substrate (not shown). The dam material can be selected from silicone resin and epoxy resin.

次に、この整列配置の状態を保ったまま半導体チップ21aとダムとの間のダイシングテープ60上に絶縁性樹脂50を塗布する(図示省略)。   Next, the insulating resin 50 is applied on the dicing tape 60 between the semiconductor chip 21a and the dam while maintaining the state of the alignment (not shown).

絶縁性樹脂50として、例えば常温で粘度が200mPa・s程度の液状エポキシ樹脂を温度50℃に加熱して流動性を増した状態として第1の貫通溝90aに充填する。絶縁性樹脂50はエポキシ樹脂以外でもよい。   As the insulating resin 50, for example, a liquid epoxy resin having a viscosity of about 200 mPa · s at normal temperature is heated to a temperature of 50 ° C. to fill the first through groove 90a in a state where the fluidity is increased. The insulating resin 50 may be other than epoxy resin.

流動性の増した状態となった絶縁性樹脂50は、毛細管現象により第1の貫通溝90a内に均一に充填される。第1の貫通溝90aに流入した絶縁性樹脂50は表面張力により、半導体チップ21aの表面に這い上がることはない。   The insulating resin 50 in the flowable state is uniformly filled in the first through groove 90a by capillary action. The insulating resin 50 that has flowed into the first through groove 90a does not creep up on the surface of the semiconductor chip 21a due to surface tension.

次に、温度60℃で4時間加熱し、絶縁性樹脂50を硬化する。硬化した絶縁性樹脂50は、連続する絶縁膜23の側面と半導体チップ21aの側面とを被覆する(図1b)。   Next, the insulating resin 50 is cured by heating at a temperature of 60 ° C. for 4 hours. The cured insulating resin 50 covers the side surface of the continuous insulating film 23 and the side surface of the semiconductor chip 21a (FIG. 1b).

続いて、厚さ30μmのダイシングソー70Bを使用して、第1の貫通溝90aの中央部分の絶縁性樹脂50の一部をダイシングテープ60に達する深さまで切削除去すると、半導体チップ21aの側面に絶縁性樹脂50が残る状態となる(図1c)。なお図1(c)は、個片化工程の様子を示しており、図中点線の間の領域が切削除去される領域を示している。   Subsequently, when a portion of the insulating resin 50 in the central portion of the first through groove 90 a is cut and removed to a depth reaching the dicing tape 60 using a dicing saw 70 B with a thickness of 30 μm, the side surface of the semiconductor chip 21 a is The insulating resin 50 is left (FIG. 1c). FIG. 1C shows the state of the singulation step, and the region between dotted lines in the drawing shows the region to be removed by cutting.

ここで厚さ30μmのダイシングソー70Bを使用して幅50μm程度の絶縁性樹脂50を切削除去するので、残る絶縁性樹脂50の幅それぞれの厚さは10μm程度となる。この残った絶縁性樹脂50が、半導体チップ21aの表面を被覆する絶縁膜23の側面と半導体チップ21aの側面とを被覆する絶縁性樹脂となる。この個片化工程が終わるとダイシングテープ60上に半導体装置1Aが整列配置した状態となる(図1d)。   Here, since the insulating resin 50 having a width of about 50 μm is cut and removed using a dicing saw 70B having a thickness of 30 μm, the thickness of each width of the remaining insulating resin 50 is about 10 μm. The remaining insulating resin 50 is an insulating resin which covers the side surface of the insulating film 23 covering the surface of the semiconductor chip 21a and the side surface of the semiconductor chip 21a. After the dicing step, the semiconductor devices 1A are aligned on the dicing tape 60 (FIG. 1d).

本実施例の製造方法によると半導体装置1Aは、側面のみが絶縁性樹脂50により被覆され、裏面は絶縁性樹脂50により被覆されていない構造であるので、従来の裏面まで絶縁性樹脂で被覆された半導体装置よりも低背化することができる。   According to the manufacturing method of this embodiment, only the side surface is covered with the insulating resin 50, and the back surface is not covered with the insulating resin 50. Therefore, the conventional back surface is covered with the insulating resin. The height can be reduced compared to the semiconductor device.

さらに本実施例の製造方法によれば、半導体基板20を一旦ダイシングテープ60に貼り付ければ、第1の貫通溝90aの形成による半導体チップ21aへの個片化、第1の貫通溝90aへ絶縁性樹脂50の充填、半導体装置1Aへの個片化までの製造工程を連続して進めることが可能である。また半導体基板20表面を露出するようにダイシングテープ60に貼り付けるため、半導体基板20表面に形成している位置合わせ用のアライメントマークを利用して、位置精度の高い個片化を行うことができる。特に半導体装置1Aへの個片化工程では、半導体基板20をダイシングテープ60に貼り付けたときと同じ状態を保っているので半導体チップ21aの側面に均一な厚みの絶縁性樹脂50を残しながら、半導体装置1Aに個片化することが可能となる。   Furthermore, according to the manufacturing method of the present embodiment, once the semiconductor substrate 20 is attached to the dicing tape 60, singulation to the semiconductor chip 21a by formation of the first through groove 90a, insulation to the first through groove 90a It is possible to continuously advance the manufacturing process up to the filling of the insulating resin 50 and the singulation to the semiconductor device 1A. In addition, since the semiconductor chip 20 is attached to the dicing tape 60 so as to expose the surface of the semiconductor substrate 20, singulation with high positional accuracy can be performed by using alignment marks for alignment formed on the surface of the semiconductor substrate 20. . Particularly in the step of singulating the semiconductor device 1A, since the same state as when the semiconductor substrate 20 is attached to the dicing tape 60 is maintained, the insulating resin 50 having a uniform thickness is left on the side surface of the semiconductor chip 21a. It becomes possible to separate the semiconductor device 1A.

図2(a)は第1の実施例の製造方法により製造した半導体装置1Aの断面図を、図2(b)は図2(a)に示す半導体装置1Aをフェイスダウン状態で実装した際、半田が這い上がった状態の断面図を示す。半導体装置1Aを実装基板10に実装する際、図2(b)に示すように半田30の這い上がりが発生したとしても、半導体チップ21aの表面を覆う絶縁膜23と半導体チップ21aの側面を覆う絶縁性樹脂50とが存在するため、電極22と半導体チップ21aとの間で短絡等の不具合が発生することがなくなる。   FIG. 2 (a) is a cross-sectional view of a semiconductor device 1A manufactured according to the manufacturing method of the first embodiment, and FIG. 2 (b) is a mounted face-down of the semiconductor device 1A shown in FIG. 2 (a). The sectional view in the state where the solder crawled up is shown. When mounting the semiconductor device 1A on the mounting substrate 10, even if the solder 30 creeps up as shown in FIG. 2B, the insulating film 23 covering the surface of the semiconductor chip 21a and the side surface of the semiconductor chip 21a are covered. Since the insulating resin 50 is present, a problem such as a short circuit does not occur between the electrode 22 and the semiconductor chip 21a.

次に、本発明の第2の実施例について、半導体チップの側面を選択的に絶縁性樹脂で被覆する構造の半導体装置の製造方法を例にとり、詳細に説明する。   Next, a method of manufacturing a semiconductor device having a structure in which the side surface of a semiconductor chip is selectively covered with an insulating resin will be described in detail as to a second embodiment of the present invention.

図3に本実施例の半導体装置の製造方法を示す。まず、上記第1の実施例と同様の厚さ630μm程度の導電性の半導体基板20の表面側(図3の上側)に図示しない所望の半導体素子と、この半導体素子に接続する電極22と、電極22の表面の一部を露出するように半導体基板20の表面を被覆する絶縁膜23とを形成する。   FIG. 3 shows a method of manufacturing the semiconductor device of this embodiment. First, a desired semiconductor element (not shown) on the surface side (upper side in FIG. 3) of the conductive semiconductor substrate 20 having a thickness of about 630 μm similar to that of the first embodiment, and an electrode 22 connected to the semiconductor element. An insulating film 23 covering the surface of the semiconductor substrate 20 is formed to expose a part of the surface of the electrode 22.

続いて、半導体基板20の表面と反対側の裏面をダイシングテープ60(支持用部材に相当)に貼り付ける。ここまでは、上記第1の実施例と同じ工程となる。続いて幅50μmのダイシングソー70Aを用いて、半導体基板20の表面側から半導体基板20の一部を格子状に、深さ300μmまで切削除去し、第1の溝91bを形成する(図3a)。   Subsequently, the back surface opposite to the front surface of the semiconductor substrate 20 is attached to a dicing tape 60 (corresponding to a supporting member). Up to this point, the process is the same as that of the first embodiment. Subsequently, a part of the semiconductor substrate 20 is cut and removed in a grid shape from the surface side of the semiconductor substrate 20 to a depth of 300 μm using a dicing saw 70A with a width of 50 μm to form a first groove 91b (FIG. 3a) .

続いて実施例1と同様に、第1の溝91bを形成した半導体基板の外側に約1cm離れたダイシングテープ60上に、高さ1mm程度のダムを形成する(図示省略)。さらに、半導体基板とダムとの間のダイシングテープ60上に、第1の溝91bに流入可能な高さまで絶縁性樹脂50を塗布する。   Subsequently, as in the first embodiment, a dam having a height of about 1 mm is formed on the dicing tape 60 separated by about 1 cm outside the semiconductor substrate in which the first groove 91 b is formed (not shown). Furthermore, the insulating resin 50 is applied on the dicing tape 60 between the semiconductor substrate and the dam to such a height that the first groove 91 b can flow.

例えば、上記実施例1と同様のエポキシ樹脂を用いた場合、加熱により流動性が増した状態として第1の溝91bに充填する。第1の溝91bに流入した絶縁性樹脂50は表面張力により、半導体基板20aの表面に這い上がることはない。   For example, in the case of using the same epoxy resin as that of the first embodiment, the first groove 91b is filled in a state in which the flowability is increased by heating. The insulating resin 50 that has flowed into the first groove 91 b does not creep up on the surface of the semiconductor substrate 20 a due to surface tension.

次に、温度60℃で4時間加熱し、絶縁性樹脂50を硬化する。硬化した絶縁性樹脂50は、実施例1と同様に絶縁膜23の側面と半導体チップ21aの側面とを被覆する(図3b)。   Next, the insulating resin 50 is cured by heating at a temperature of 60 ° C. for 4 hours. The cured insulating resin 50 covers the side surface of the insulating film 23 and the side surface of the semiconductor chip 21a as in the first embodiment (FIG. 3b).

続いて、厚さ30μmのダイシングソー70Bを使用して、第1の溝91bの中央部分の絶縁性樹脂50の一部をダイシングテープ60に達する深さまで切削除去すると、第2の貫通孔90bが形成される。この第2の貫通孔90bの側面は、絶縁性樹脂50からなる面と半導体基板20aが露出する面とが連続する切削面である。ここで厚さ30μmのダイシングソー70Bを使用して幅50μm程度の絶縁性樹脂50を切削除去するので、残る絶縁性樹脂50のそれぞれの厚さは10μm程度となる。(図3c)。   Subsequently, when a portion of the insulating resin 50 in the central portion of the first groove 91 b is cut and removed to a depth reaching the dicing tape 60 using a dicing saw 70 B with a thickness of 30 μm, the second through hole 90 b It is formed. The side surface of the second through hole 90 b is a cutting surface in which the surface made of the insulating resin 50 and the surface on which the semiconductor substrate 20 a is exposed are continuous. Here, since the insulating resin 50 having a width of about 50 μm is cut and removed using a dicing saw 70B having a thickness of 30 μm, the thickness of each of the remaining insulating resin 50 is about 10 μm. (Figure 3c).

この残った絶縁性樹脂50が半導体チップ21bの表面の絶縁膜23の側面と半導体基板20aの側面の一部とを被覆する絶縁性樹脂となる。個片化工程が終わると、ダイシングテープ60上に半導体装置1Bが整列配置した状態となる(図3d)。   The remaining insulating resin 50 is an insulating resin which covers the side surface of the insulating film 23 on the surface of the semiconductor chip 21b and a part of the side surface of the semiconductor substrate 20a. After the dicing step, the semiconductor devices 1B are aligned on the dicing tape 60 (FIG. 3d).

本実施例の製造方法においても、実施例1の場合と同様に不要な短絡が生じる可能性のある側面のみが絶縁性樹脂50により被覆され、裏面は絶縁性樹脂50により被覆されていない構造であるので、従来の裏面まで絶縁性樹脂で被覆された半導体装置よりも低背化することができる。   Also in the manufacturing method of the present embodiment, as in the case of the first embodiment, only the side surface that may cause an unnecessary short circuit is covered with the insulating resin 50, and the back surface is not covered with the insulating resin 50. As a result, the height can be reduced compared to the conventional semiconductor device covered with the insulating resin up to the back surface.

図4(a)は、第2の実施例の製造方法により製造した半導体装置1Bの断面図を、図4(b)は図4(a)に示す半導体装置1Bをフェイスダウン状態で実装した際、半田が這い上がった状態の断面図を示す。本実施例の半導体装置1Bでも半田30の這い上がりが発生したとしても、半導体チップ21bの表面を覆う絶縁膜23と半導体チップ21bの側面を覆う絶縁性樹脂50とが存在するため電極22と半導体チップ21bとの間で短絡等の不具合が発生することはない。   FIG. 4 (a) is a cross-sectional view of a semiconductor device 1B manufactured by the manufacturing method of the second embodiment, and FIG. 4 (b) is a face-down mounting of the semiconductor device 1B shown in FIG. 4 (a). The figure shows a cross-sectional view of a state in which the solder creeps up. Even in the semiconductor device 1B of this embodiment, even if creeping up of the solder 30 occurs, the insulating film 23 covering the surface of the semiconductor chip 21b and the insulating resin 50 covering the side surface of the semiconductor chip 21b are present. There is no problem such as a short circuit with the chip 21b.

次に、本発明の第3の実施例について、本発明の第1の実施例で製造した半導体装置1Aより更に低背化した半導体装置の製造方法を例にとり、詳細に説明する。   Next, a third embodiment of the present invention will be described in detail with reference to a method of manufacturing a semiconductor device whose height is further reduced than that of the semiconductor device 1A manufactured in the first embodiment of the present invention.

図5に本実施例の半導体装置の製造方法を示す。まず、上記第1、第2の実施例と同様の厚さ630μm程度の導電性の半導体基板20の表面側(図5の上側)に図示しない所望の半導体素子と、この半導体素子に接続する電極22と、電極22の表面の一部を露出するように半導体基板20の表面を被覆する絶縁膜23とを形成する。   FIG. 5 shows a method of manufacturing the semiconductor device of this embodiment. First, a desired semiconductor element (not shown) on the surface side (upper side in FIG. 5) of the conductive semiconductor substrate 20 having a thickness of about 630 μm similar to the first and second embodiments and electrodes connected to this semiconductor element 22 and an insulating film 23 covering the surface of the semiconductor substrate 20 so as to expose a part of the surface of the electrode 22.

続いて、第2の実施例と同様に、半導体基板20の表面と反対側の裏面をダイシングテープ60に貼り付け、表面側に形成した第1の溝91bの中に絶縁性樹脂50を充填した半導体基板20aを準備する(図3bに相当)。   Subsequently, as in the second embodiment, the back surface opposite to the front surface of the semiconductor substrate 20 is attached to the dicing tape 60, and the insulating resin 50 is filled in the first groove 91b formed on the front surface side. The semiconductor substrate 20a is prepared (corresponding to FIG. 3b).

続いて、本実施例では絶縁性樹脂50を充填した第1の溝91bの底部を構成する半導体基板20aの一部が露出するまで、厚さ30μmのダイシングソー70Bを使用して絶縁性樹脂50の一部を切削除去し、第2の溝91cを形成する(図5a)。   Subsequently, in the present embodiment, the insulating resin 50 is used using the dicing saw 70B with a thickness of 30 μm until a part of the semiconductor substrate 20a constituting the bottom of the first groove 91b filled with the insulating resin 50 is exposed. The second groove 91c is formed (FIG. 5a).

半導体基板20aの表面と反対側の裏面側に貼り合わせたダイシングテープ60を剥離し、半導体基板20aの表面側に保護用部材であるバックグラインドテープ61を貼り付ける。そして、図中点線で示した絶縁性樹脂50と第2の溝91cが露出する厚さまで半導体基板20aの裏面側から研削する(図5b)。なお上記第2の溝91cを形成する代わりに、図5(a)に示す深さより浅い別の第2の溝を形成しておき、この第2の溝が露出したところで、半導体基板20aの研削を停止してもよい。または、上記第2の溝91cを形成する代わりに、図5(a)に示す深さより深い別の第2の溝を形成しておき、この第2の溝が露出したところで、半導体基板20aの研削を停止してもよい。   The dicing tape 60 bonded to the back surface side opposite to the front surface of the semiconductor substrate 20a is peeled off, and a back grind tape 61 as a protective member is bonded to the front surface side of the semiconductor substrate 20a. Then, grinding is performed from the back surface side of the semiconductor substrate 20a to a thickness at which the insulating resin 50 and the second groove 91c shown by dotted lines in the drawing are exposed (FIG. 5b). Instead of forming the second groove 91c, another second groove shallower than the depth shown in FIG. 5A is formed, and when the second groove is exposed, the semiconductor substrate 20a is ground. You may stop it. Alternatively, instead of forming the second groove 91c, another second groove deeper than the depth shown in FIG. 5A is formed, and when the second groove is exposed, the semiconductor substrate 20a is formed. Grinding may be stopped.

この裏面研削により半導体基板20aは第3の貫通孔90cにより半導体チップ21cへ分離される。この分離により半導体チップ21cの側面には均一な厚みの絶縁性樹脂50を残しながら半導体装置1Cに個片化され、バックグラインドテープ61上に整列配置した状態となる(図5c)。また、半導体装置1Cは半導体基板20aの裏面研削により所望の厚さに低背化することができ、例えば100μm程度の厚みにすることが可能である。   The semiconductor substrate 20a is separated into the semiconductor chips 21c by the third through holes 90c by this back surface grinding. As a result of this separation, the semiconductor device 1C is singulated while leaving the insulating resin 50 of uniform thickness on the side surface of the semiconductor chip 21c, and is in a state of being aligned on the back grind tape 61 (FIG. 5c). The semiconductor device 1C can be reduced in height to a desired thickness by grinding the back surface of the semiconductor substrate 20a. For example, the thickness can be about 100 μm.

第3の実施例の製造方法により製造した半導体装置1Cは、第1の実施例あるいは第2の実施例で製造した半導体装置1A,1Bよりも低背化した半導体装置となる。   The semiconductor device 1C manufactured by the manufacturing method of the third embodiment becomes a semiconductor device having a smaller height than the semiconductor devices 1A and 1B manufactured in the first embodiment or the second embodiment.

以上本発明の実施例について説明したが、本発明は上記実施例に限定されるものではないことは言うまでもない。   Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments.

例えば、半導体基板表面への貫通溝及び溝の形成または半導体チップへの個片化または半導体装置への個片化において、上記実施例ではダイシングソーを用いたがレーザー等による個片化方法を用いても良い。   For example, in the formation of the through groove and the groove on the surface of the semiconductor substrate or the singulation into semiconductor chips or singulation into semiconductor devices, a dicing saw is used in the above embodiment, but a singulation method using a laser or the like is used It is good.

1A,1B,1C,2A,2B:半導体装置、10:実装基板、11:配線金属、20,20a:半導体基板、21a,21b:半導体チップ、22:電極、23:絶縁膜、30:半田、50:絶縁性樹脂、60:ダイシングテープ、61:バックグラインドテープ、70,70A,70B:ダイシングソー、90a:第1の貫通溝、90b:第2の貫通溝、90c:第3の貫通溝、91b:第1の溝、91c:第2の溝 1A, 1B, 1C, 2A, 2B: semiconductor device, 10: mounting substrate, 11: wiring metal, 20, 20a: semiconductor substrate, 21a, 21b: semiconductor chip, 22: electrode, 23: insulating film, 30: solder, 50: Insulating resin, 60: dicing tape, 61: back grind tape, 70, 70A, 70B: dicing saw, 90a: first through groove, 90b: second through groove, 90c: third through groove, 91b: first groove, 91c: second groove

Claims (3)

導電性の半導体チップの表面に電極を備え、前記半導体チップの側面が絶縁性樹脂で被覆された半導体装置の製造方法において、
導電性の半導体基板表面に前記電極を形成する工程と、
前記半導体基板の電極を備えた面と反対側の面を支持用部材に貼り付けて、前記半導体基板の表面側から一部を除去して個片化し、隣接する前記半導体チップ間に間隙を形成することにより、前記支持用部材上に前記間隙を保った状態で前記半導体チップを整列配置する工程と、
整列配置した前記半導体チップの側面を覆うように、前記間隙に選択的に前記絶縁性樹脂を充填する工程と、
前記充填した絶縁性樹脂の一部を切削除去することにより、個々の前記半導体装置に個片化する工程を含み、
前記半導体装置に個片化する工程は、前記半導体チップの側面に前記絶縁性樹脂を残し、前記絶縁性樹脂の一部を除去する工程であることを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device, an electrode is provided on a surface of a conductive semiconductor chip, and a side surface of the semiconductor chip is covered with an insulating resin,
Forming the electrode on the surface of a conductive semiconductor substrate;
The surface opposite to the surface provided with the electrodes of the semiconductor substrate is attached to a supporting member, and a part is removed from the surface side of the semiconductor substrate for singulation, and a gap is formed between the adjacent semiconductor chips. Aligning the semiconductor chips in a state in which the gap is maintained on the supporting member;
Selectively filling the gap with the insulating resin so as to cover the side surfaces of the aligned semiconductor chips;
Including the step of singulating the individual semiconductor devices by cutting and removing a part of the filled insulating resin,
A method of manufacturing a semiconductor device, wherein the step of singulating the semiconductor device is a step of leaving the insulating resin on the side surface of the semiconductor chip and removing a part of the insulating resin.
導電性の半導体チップの表面に電極を備え、前記半導体チップの側面が絶縁性樹脂で被覆された半導体装置の製造方法において、
導電性の半導体基板表面に前記電極を形成する工程と、
前記半導体基板の電極を備えた面と反対側の面を支持用部材に貼り付けて、前記半導体基板の表面側から個片化の際除去される領域の一部を残して前記半導体基板に溝を形成する工程と、
前記溝に選択的に前記絶縁性樹脂を充填する工程と、
前記充填した絶縁性樹脂と前記半導体基板の一部を除去することにより、個々の前記半導体装置に個片化する工程を含み、
前記半導体装置に個片化する工程は、前記半導体チップの側面に前記絶縁性樹脂を残し、前記絶縁性樹脂と前記半導体基板の一部を除去する工程であることを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device, an electrode is provided on a surface of a conductive semiconductor chip, and a side surface of the semiconductor chip is covered with an insulating resin,
Forming the electrode on the surface of a conductive semiconductor substrate;
The surface opposite to the surface provided with the electrode of the semiconductor substrate is attached to a supporting member, and a groove is formed in the semiconductor substrate leaving a part of the region to be removed in the singulation from the surface side of the semiconductor substrate. Forming the
Selectively filling the groove with the insulating resin;
Including the step of singulating the individual semiconductor devices by removing the filled insulating resin and a part of the semiconductor substrate,
The step of singulating the semiconductor device is a step of leaving the insulating resin on the side surface of the semiconductor chip and removing the insulating resin and a part of the semiconductor substrate. Method.
請求項2記載の半導体装置の製造方法において、
前記半導体装置に個片化する工程は、前記半導体チップの側面に前記絶縁性樹脂を残して、前記絶縁性樹脂を除去した後、前記半導体基板の一部を除去する際、前記半導体基板の裏面を研削する工程を含むことを特徴とする半導体装置の製造方法。
In the method of manufacturing a semiconductor device according to claim 2,
In the step of singulating the semiconductor device, after removing the insulating resin after leaving the insulating resin on the side surface of the semiconductor chip, when removing a part of the semiconductor substrate, the back surface of the semiconductor substrate A method of manufacturing a semiconductor device, comprising the step of:
JP2017230638A 2017-11-30 2017-11-30 Semiconductor device manufacturing method Pending JP2019102599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017230638A JP2019102599A (en) 2017-11-30 2017-11-30 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017230638A JP2019102599A (en) 2017-11-30 2017-11-30 Semiconductor device manufacturing method

Publications (1)

Publication Number Publication Date
JP2019102599A true JP2019102599A (en) 2019-06-24

Family

ID=66977127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017230638A Pending JP2019102599A (en) 2017-11-30 2017-11-30 Semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JP2019102599A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021068832A (en) * 2019-10-25 2021-04-30 三菱電機株式会社 Manufacturing method of semiconductor device
JP2022038870A (en) * 2020-08-27 2022-03-10 株式会社東芝 Semiconductor package and marking method

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02237051A (en) * 1989-03-09 1990-09-19 Fuji Electric Co Ltd Manufacture of semiconductor element
JPH10163370A (en) * 1996-12-03 1998-06-19 Nec Corp Bare chip mounting board
JP2001053033A (en) * 1999-08-12 2001-02-23 Texas Instr Japan Ltd Dicing method of semiconductor device
JP2001230222A (en) * 2000-02-15 2001-08-24 Rohm Co Ltd Method of manufacturing semiconductor chip
JP2003197655A (en) * 1996-07-12 2003-07-11 Fujitsu Ltd Method of manufacturing semiconductor device, mold for manufacturing semiconductor device, semiconductor device, and mounting method thereof
US20030143819A1 (en) * 2002-01-25 2003-07-31 Infineon Technologies Ag Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips
JP2005216941A (en) * 2004-01-27 2005-08-11 New Japan Radio Co Ltd Chip-sized semiconductor device and its manufacturing method
JP2007266191A (en) * 2006-03-28 2007-10-11 Nec Electronics Corp Wafer processing method
JP2011210925A (en) * 2010-03-30 2011-10-20 Toppan Forms Co Ltd Electronic component and method of manufacturing the same, component mounting substrate
JP2014072415A (en) * 2012-09-28 2014-04-21 Nichia Chem Ind Ltd Light-emitting device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02237051A (en) * 1989-03-09 1990-09-19 Fuji Electric Co Ltd Manufacture of semiconductor element
JP2003197655A (en) * 1996-07-12 2003-07-11 Fujitsu Ltd Method of manufacturing semiconductor device, mold for manufacturing semiconductor device, semiconductor device, and mounting method thereof
JPH10163370A (en) * 1996-12-03 1998-06-19 Nec Corp Bare chip mounting board
JP2001053033A (en) * 1999-08-12 2001-02-23 Texas Instr Japan Ltd Dicing method of semiconductor device
JP2001230222A (en) * 2000-02-15 2001-08-24 Rohm Co Ltd Method of manufacturing semiconductor chip
US20030143819A1 (en) * 2002-01-25 2003-07-31 Infineon Technologies Ag Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips
JP2005216941A (en) * 2004-01-27 2005-08-11 New Japan Radio Co Ltd Chip-sized semiconductor device and its manufacturing method
JP2007266191A (en) * 2006-03-28 2007-10-11 Nec Electronics Corp Wafer processing method
JP2011210925A (en) * 2010-03-30 2011-10-20 Toppan Forms Co Ltd Electronic component and method of manufacturing the same, component mounting substrate
JP2014072415A (en) * 2012-09-28 2014-04-21 Nichia Chem Ind Ltd Light-emitting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021068832A (en) * 2019-10-25 2021-04-30 三菱電機株式会社 Manufacturing method of semiconductor device
JP2022038870A (en) * 2020-08-27 2022-03-10 株式会社東芝 Semiconductor package and marking method

Similar Documents

Publication Publication Date Title
KR101500038B1 (en) Sawing underfill in packaging processes
US7915080B2 (en) Bonding IC die to TSV wafers
US6867489B1 (en) Semiconductor die package processable at the wafer level
CN102969305B (en) For the tube core of semiconductor structure to tube core clearance control and method thereof
US9153566B1 (en) Semiconductor device manufacturing method and semiconductor device
US10128153B2 (en) Method of fabricating a semiconductor device and the semiconductor device
KR20180027679A (en) Semiconductor package and method of fabricating the same
US20150262975A1 (en) Manufacturing method of semiconductor device and semiconductor device
US9337172B2 (en) Semiconductor device
JP2006100535A (en) Semiconductor device and manufacturing method therefor
JP2019102599A (en) Semiconductor device manufacturing method
US11721654B2 (en) Ultra-thin multichip power devices
US11367714B2 (en) Semiconductor package device
JP2014203868A (en) Semiconductor device and semiconductor device manufacturing method
TWI719006B (en) Semiconductor device
US20170287863A1 (en) Semiconductor die, semiconductor wafer and method for manufacturing the same
US20140091472A1 (en) Semiconductor device and manufacturing method of the same
JP2020061511A (en) Lamination body of electrical component and manufacturing method of the same
JP2018182095A (en) Semiconductor device and manufacturing method for the same
JP2010073803A (en) Manufacturing method for semiconductor device
TWI726279B (en) Semiconductor package device
JP4639155B2 (en) Semiconductor device and manufacturing method thereof
JP2008283216A (en) Semiconductor device, and manufacturing method thereof
JP2005142593A (en) Semiconductor device
JP2007042807A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200929

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210914

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210921

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211110

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20220412

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20220520

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20221004