JP2019097254A - Motor control device, sheet transfer device, and image forming device - Google Patents

Abstract

To provide a motor control device capable of making a motor control correspond to a vector control system.SOLUTION: A motor control device measures a period of one pulse of a full-step pulse input into a driving circuit of a motor having two phase windings, and stores a measurement result. The measurement result stored is read out at the timing of the 2nd pulse of the full-step pulse or a prescribed timing for the rest of them, a micro-step pulse is generated seven times by measuring the timing in an eight-division micro-step period, and the 8th micro-step pulse is generated so as to be matched with the period of the corresponding full-step pulse. A current value on a ground side of the driving circuit is detected, an electric angle is detected by estimating an induction voltage occurred in the phase winding of the motor on the basis of the current value detected, a vector control is performed on the basis of the electric angle detected and the micro-step pulse, a PWM signal is generated in accordance with the result obtained by detecting the current value for each micro-step pulse and the vector control, and a motor control is performed by being synchronized with the full-step pulse input.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a motor control device, a sheet conveying device, and drive control of a plurality of motors in an image forming apparatus.

In an electrophotographic image forming apparatus such as a copying machine or a printer, a stepping motor is used as a driving source for transporting a recording material (for example, a sheet) for recording a copy image.
In the stepping motor, speed control is performed by controlling a pulse cycle applied to the motor. In the stepping motor, position control is also performed by controlling the number of pulses given to the motor.

On the other hand, when the load torque applied to the motor exceeds the torque range that the motor can output, the stepping motor may fall into an uncontrollable step out without being synchronized with the input pulse.
For example, in order to avoid a step-out, the current supplied to the motor has a predetermined margin so that the torque corresponding to the torque change on the load side due to various variations can be output with respect to the load torque required in the device. It will need to be provided. As a result, power may be consumed more than necessary, or vibration and noise may be caused due to excess torque.

  As one method for solving this problem, a method called vector control (or FOC: Field Oriented Control) has been proposed (for example, Patent Document 1).

Unexamined-Japanese-Patent No. 2003-284389

  The above-mentioned vector control is a method of controlling the phase and amplitude of the current so as to generate the maximum torque in a rotational coordinate system in which the magnetic flux direction component of the rotor is defined as d axis and the direction orthogonal to d axis as q axis. It is. In the rotational coordinate system, the current component contributing to the torque given to the rotor of the motor is the q-axis current, and the current component affecting the strength of the magnetic flux penetrating the motor winding is the d-axis current.

  Further, in a stepping motor or the like using a permanent magnet for the rotor, the d-axis current is not necessary because the field is made of a permanent magnet, and torque control of the motor can be performed only by controlling the q-axis current. As a result, the waveform of the drive current of the motor in the stationary coordinate system becomes an ideal sinusoidal waveform, which enables not only control with the highest power efficiency but also vibration and noise due to excess torque.

Further, as a method of detecting the rotational speed and position of the rotor, which is required for vector control, a method using a rotary encoder is generally used. However, it is necessary to increase the cost and the arrangement space by newly adding a rotary encoder which is unnecessary in the conventional stepping motor control.
As a solution to these problems, for example, there is a method of detecting a drive current of a motor and estimating a rotor position by taking an inverse tangent of an induced voltage ratio in A phase and B phase estimated based on a voltage equation. The rotor rotational speed can be obtained by time-differentiating the estimated position result.

  Here, a full bridge circuit of FET (Field Effect Transistor) is used as a driving driver of the stepping motor, and the FET is excited and controlled by a PWM (Pulse Width Modulation) signal to supply a driving current to the motor. In such a case, as a method of detecting the drive current, a general configuration is such that a shunt resistor is disposed on the ground side of the bridge circuit, a voltage applied to the resistor is amplified by an operational amplifier and detected using an A / D converter. It is.

Further, in order to effectively perform torque control to be a sine wave at an electrical angle, it is desirable to perform feedback control of the electrical angle of each motor in a plurality of microsteps of at least about eight divisions.
Further, the full-step pulse generation means for giving a position command to the motor is configured as a system that operates the main host CPU, the timer circuit and the CPU interrupt in real time. Further, the full-step pulse generating means is configured to perform an image forming operation in consideration of a plurality of sensor information for detecting the state of the paper conveyance mechanism in the machine, the sheet, and the device.

However, it is not easy to change the existing image forming apparatus completed before introducing the vector control method to correspond to the vector control method.
For example, in the case of using the electrical angle detection based on the induced voltage, it is necessary to perform AD input reception on a plurality of channels, PWM value feedback control, and calculation of vector quantity each time with the microstep equivalent frequency or more. In addition, component variation correction of a plurality of motors, change of control mode and reverse rotation, and communication for timing control and control are also required, and the control timing burden on the sequence control unit increases rapidly.

  For this reason, the host CPU needs eight times the CPU processing capacity equivalent to the number of microsteps compared to that before the change, and the host CPU needs a significant performance increase, which results in cost increase. In addition, there is a case where redesign of sequence software is required, and there is a problem that it is not easy to cope with vector control.

  The main object of the present invention is to provide a motor control device capable of making a motor control method compatible with a vector control method. Further, the present invention provides an image forming apparatus having the motor control device.

  A motor control apparatus according to the present invention comprises: measuring means for measuring a cycle of a full step pulse input to a drive circuit for driving a motor having two phase windings; storage means for storing the measurement result; The measurement result stored in the storage means is read out from the second pulse of the pulse or a predetermined timing thereafter, the timing is measured at a microstep period divided by an integer N of 8 or more, and the microstep pulse is N Pulse generation means for generating the microstep pulse which is generated -1 time and the Nth microstep pulse coincides with the period of the corresponding full step pulse, and the current value on the ground side of the drive circuit is detected And the induced voltage generated in the phase winding of the motor based on the detected A / D converter and the detected current value. Estimation means, control means for detecting an electrical angle based on the estimated induced voltage and performing vector control based on the detected electrical angle and the micro step pulse, and controlling a switching element of the drive circuit And generating means for generating a PWM signal according to the vector control according to the result of detection of the current value for each microstep pulse and the vector control. The motor control is performed in synchronization with the full step pulse.

  According to the present invention, it is possible to provide a motor control device capable of making the control method of the motor correspond to the vector control method.

FIG. 1 is a diagram showing an example of the configuration of an image forming system according to the present embodiment. FIG. 2 is a block diagram for explaining an example of the functional configuration of a system controller of the image forming apparatus. (A), (b) is a figure for demonstrating the function structure of the interruption controller which a system controller has. FIG. 2 is a schematic view showing an example of the configuration of a stepping motor. (A), (b) is a figure which shows an example of the timing chart which concerns on timer interruption. The timing chart which shows an example of the periodic relationship of the various signals containing a general eight division micro step period. FIG. 6 is an enlarged view of a start portion and an end portion of the timing chart shown in FIG. The timing chart which shows an example of the PWM signal of A phase. The timing chart which shows an example of the detection timing of the A / D converter by interruption of a timer. The flowchart which shows an example of the timer interruption control of interruption controller IRQC180. 11 is a flowchart showing an example of AD conversion value acquisition and PWM data arithmetic processing shown in FIG. The figure for demonstrating an example of the full bridge circuit of a PWM function part. (A), (b) is a figure for demonstrating the direction of the drive current which flows into a motor winding according to a PWM signal. The conceptual diagram of a triangular wave comparison system. The timing chart which shows an example of a plurality of PWM pulses when a phase makes one rotation, and a PWM generation section. The flowchart which shows an example of the interruption flow of timer 181. The flowchart which shows an example of the interruption flow of timer 191a. The flowchart which shows an example of the interruption flow of timer 191b.

Hereinafter, an image forming apparatus having a motor control device to which the present invention is applied will be described as an example.
In the present embodiment, a case where the present invention is applied to an electrophotographic laser beam printer which is an example of an image forming apparatus will be described as an example. The present invention can also be applied to other image forming apparatuses such as an inkjet printer and a sublimation printer. Further, the present invention can be applied to a sheet conveying apparatus for conveying a sheet.

[Example of embodiment]
FIG. 1 is a diagram showing an example of the configuration of an image forming system according to the present embodiment.
An image forming system 10 shown in FIG. 1 includes a document feeder (ADF: Auto Document Feeder) 201, a reader 202, and an image forming apparatus 301.

The original placed on the original placement unit 203 of the original feeding device 201 is fed sheet by sheet by the feed roller 204 and conveyed to the original glass table 214 of the reading device 202 via the conveyance guide 206. Further, the document is conveyed by the conveyance belt 208 at a constant speed, and discharged by the discharge roller 205 outside the apparatus.
Reflected light from the original image irradiated by the illumination system 209 at the reading position of the reading device 202 is converted into an image signal by the image reading unit 101 by the optical system including the reflection mirrors 210, 211 and 212. The image reading unit 101 includes a lens, a CCD (Charge Coupled Device) which is a photoelectric conversion element, a drive circuit of the CCD, and the like.

The image forming apparatus 301 has, for example, a first reading mode and a second reading mode as document reading modes. In the first reading mode, the document image is read while conveying the document at a constant speed with the illumination system 209 and the optical system stopped.
In the second reading mode, the document placed on the document glass table 214 is read while moving the illumination system 209 and the optical system at a constant speed. Usually, the sheet-like document is read in the first reading mode, and the bound document is read in the second reading mode.

The image signal (read data) converted by the image reading unit 101 is formed on a recording material (for example, a sheet) by the image forming apparatus 301 in page units.
The image signal is modulated to a signal of laser light by a semiconductor laser (not shown) or the like. The modulated laser beam is exposed on the photosensitive drum 309 whose surface is uniformly charged by the charger 310 via the light scanning device 311 including the polygon mirror and the mirrors 312 and 313, and the outer periphery of the photosensitive drum 309 An electrostatic latent image is formed on the surface.
The electrostatic latent image is developed by the toner of the developing device 314, and the toner image is transferred to the recording material by the transfer charger 315.

The recording material is stored in the paper cassettes 302 and 304. In the present embodiment, for example, plain paper A4 is stored in the paper cassette 302, and thick paper A4 is stored in the paper cassette 304.
The recording material of the paper cassette 302 is conveyed by the paper feed roller 303 and the conveyance roller 306 to the registration roller 308.

On the other hand, the recording material of the paper cassette 304 is conveyed to the registration roller 308 by the paper feed roller 305 and the conveyance rollers 306 and 307.
The registration roller 308 conveys the recording material to a position (transfer position) where the toner image is transferred to the recording material, in accordance with the transfer timing at which the toner image is transferred to the recording material.
The recording material to which the toner image has been transferred is conveyed by the conveyance belt 317 to the fixing device 318, and the toner image is fixed on the recording material by heat and pressure by the fixing device 318.

For example, when the mode of the image forming apparatus 301 is the single-sided printing mode, the recording material from the fixing unit 318 is discharged to the outside of the apparatus by the fixing discharge roller 319 and the discharge roller 324. When the mode of the image forming apparatus 301 is the double-sided printing mode, the recording material is conveyed from the fixing discharge roller 319 via the conveyance roller 320 to the reverse path 325 by the reverse roller 321.
Further, the rotation of the reversing roller 321 is reversed immediately after the trailing edge of the recording material passes the merging point with the double-sided path 326, whereby the recording material is reversed and conveyed to the double-sided path 326.

The recording material conveyed to the duplex path is conveyed by the conveyance rollers 322 and 323, and is conveyed again to the registration roller 308 via the conveyance roller 306.
Thereafter, an image is formed on the second surface (rear surface) of the recording material by the method described above, and then the sheet is discharged out of the machine.
When the recording material from the fixing unit 318 is turned upside down and discharged to the outside of the apparatus, the recording material is conveyed to the conveyance roller 320. Thereafter, the rotation of the conveyance roller 320 is reversed immediately before the trailing end of the recording material passes the conveyance roller 320, and the recording material is discharged outside the machine in a state of being turned upside down.

  The conveyance rollers 306 and 307, the fixing discharge roller 319, the reverse roller 321, the conveyance rollers 322 and 323, the discharge roller 324, and the like provided in the image forming apparatus 301 are driven and controlled by a system controller 751 shown in FIG. Be done.

FIG. 2 is a block diagram for explaining an example of the functional configuration of the system controller 751 that the image forming apparatus 301 has.
FIG. 3 is a diagram for explaining functional configurations of an interrupt controller IRQC 780 and an interrupt controller IRQC 180 which the system controller 751 has.
FIG. 4 is a schematic view showing an example of the configuration of the stepping motor 167a. For example, as shown in FIG. 4, the stepping motor 167a is a two-phase stepping motor having two phase windings of A phase (windings 401a and 401c) and B phase (windings 401b and 401d).

The system controller 751 illustrated in FIG. 2 includes a central processing unit (CPU) 751a, a read only memory (ROM) 751b, a random access memory (RAM) 751c, an interrupt controller IRQC 780, a communication unit 752, and pulse generation units 770a to 770e. .
The CPU 751a executes various sequences related to a predetermined image forming sequence by reading out and executing the program stored in the ROM 751b. The CPU 751a is configured to be able to communicate with each module in the system controller 751 via the bus 751d. The RAM 751 c stores, for example, a high voltage setting value for the high voltage control unit 155, various data, image formation command information from the operation unit 152, and the like.

  The system controller 751 changes the setting of the image processing unit 102 by transmitting specification setting value data of each unit to the image processing unit 102. The system controller 751 receives a signal from each unit, for example, an original image density signal or the like (a signal from the sensors 159), and changes a setting value of the high voltage control unit 155 in order to form an optimum image. Thus, the output voltage of the high voltage unit 156 (the unit for controlling the charger 310, the developing device 314, and the transfer charger 315) is controlled.

  The detection signal of the thermistor 154 converted into a digital signal by the A / D converter 753, which is a current detector of analog to digital conversion type, is input to the system controller 751. The system controller 751 controls the fixing heater 161 to have a desired temperature by controlling the AC driver 160 based on this signal.

  The system controller 751 acquires information such as a copying magnification and a density setting value set by the user via the operation unit 152. In addition, the system controller 751 shows the status of the image forming apparatus, for example, the number of sheets for image formation, whether the image is being formed or not, occurrence of jamming, the location, double feeding, etc. to the operation unit 152. Send the data of

  The system controller 751 is configured to be connectable to the motor driver unit 150 as an electrical unit capable of replacement maintenance. The system controller 751 is connected to the vector control IC 151 (described later) in the motor driver unit 150 via the communication unit 752 so as to be capable of serial communication.

As described above, the operation sequence in the image forming apparatus is executed by the system controller 751.
At this time, the five motors 167a to 167e which are drive sources for the respective drive rollers of the sheet conveyance system are also driven. The motors are both A-phase and B-phase two-phase stepping motors such as the motor 167a shown in FIG.
The system controller 751 controls the respective motors by outputting position command pulses 171a to 175b to the motor drivers 157a to 157e at predetermined time intervals via pulse generation units 171a to 171e of the vector control IC 151.

Host CPU timer
Next, a sequence in which the CPU 751a performs drive control of five motors will be described.
The system controller 751 performs arithmetic and timing control of five motors by a combination of a plurality of counter timer functions in the interrupt controller IRQC 780 and each timer interrupt instruction 780a.

The interrupt controller IRQC 780 shown in FIG. 3A has a total of five timers 781 to 785. These timers count on a crystal oscillation clock basis.
The timers 781 to 785 are timers for generating a position command full step pulse (hereinafter referred to as a full step pulse) for controlling acceleration / deceleration and stop of the full stepping unit of each of the five motors.

FIG. 5 is a diagram showing an example of a timing chart related to timer interruption.
FIG. 5A is an example of a timing chart of the interruption of the timer 781 and shows from start to stop of the motor along a time axis.

The pulse generation unit 770a for the first stepping motor (motor 167a) outputs a full-step pulse in accordance with an instruction from the CPU 751a. The CPU 751a controls the pulse generation unit 770a according to the signal output from the timer 781. The timer 781 is stopped while the motor 167a is stopped.
When the motor is started, the pulse generation unit 770a starts outputting a full step pulse with the self-starting pulse width. When the motor is started, the timer 781 starts counting.
The timer 781 shortens the cycle of the signal output to the CPU 751a stepwise. As a result, the cycle of the full-step pulse output from the pulse generation unit 770a is shortened stepwise, and the motor is accelerated.
When the cycle of the full-step pulse to be output becomes a cycle corresponding to the target velocity f1, the timer 781 outputs a signal to be output to the CPU 751a at a constant cycle. As a result, the cycle of the full-step pulse output from the pulse generation unit 770a becomes a constant cycle, and the motor rotates at a constant speed.
In addition, when stopping the motor, the timer 781 increases the cycle of the signal output to the CPU 751a stepwise. As a result, the cycle of the full-step pulse output from the pulse generation unit 770a is shortened stepwise, and the motor is decelerated.
The timer 781 outputs a signal up to a self-starting pulse width at which the motor stops, and stops the timer 781.

  Similarly, also for the four stepping motors 167b to 167e, the timers 782 to 785 function at the timing when the driving of the respective motors is started, and output a signal to the CPU 751a.

  The CPU 751a controls the pulse generation units 770a to 770e to output the rotation direction command signals (771d to 775d). When the rotation direction command signal is L level, the motor rotates in the forward direction, and when the rotation direction command signal is H level, the motor reversely rotates.

[Sub CPU]
Subsequently, a sequence in which the CPU 151a (hereinafter referred to as the CPU 151a) included in the vector modulation IC 151 performs vector control of five motors (167a to 167e) via the A / D converters 153a and 153b will be described. The vector modulation IC 151 functions as a motor control device that controls the motor using vector control. Further, the A / D converter 153a is a first A / D converter, and the A / D converter 153b is a second A / D converter. The interrupt controller IRQC 180 shown in FIG. 3B has a total of 17 timers 181 to 185, 191a to 195a, 191b to 195b, 196, and 197.

The CPU 151a interrupts and receives full step pulses (771a to 775a) output from the pulse generation units 770a to 770e based on the timers 181 to 185 of the interrupt controller IRQC 180.
The CPU 151a controls the timing of the operation regarding the five motors by the interrupt instruction 180a which instructs each timer in the interrupt controller IRQC 180 to interrupt. The CPU 151a measures the interruption intervals of each of the five motors.

  FIG. 6 is a timing chart showing an example of the cycle relationship of the full-step clock for switching the levels of 8-step micro-step cycle, A-phase and B-phase full-step pulses, and A-phase and B-phase full-step pulses. is there. In the timing chart of FIG. 6, the vertical axis represents the type of signal and the horizontal axis represents time.

The position command pulse width information θ_ref is command information of a current electrical angle (a relative angle between the rotor 402 and the phase winding) estimated (estimated) from the number of full step pulses and the number of micro step pulses. The position command pulse width information θ_ref is defined in units of electrical angles of 24 bits, where the initial phase is 0 and one cycle is FFFFFFh, and is held in the RAM 751 c.
In this embodiment, it is assumed that the number of interruptions of 8-division microsteps is counted (measured) in the microstep period divided into N (N is an integer of 8 or more, and the integer N division is 8 or more). . As a result, the count number (measurement result) is converted into position command pulse width information θ_ref, and the position command pulse width information θ_ref is used for vector calculation in the subsequent stage. The details of the micro step timing interrupt generation will be described later.

  The CPU 151a performs vector control based on the position command pulse width information θ_ref and the read information from the A / D converters 153a and 153b included in the motor driver unit 150 (see FIG. 2).

  The A / D converters 153a and 153b are 8-ch AD converter modules each incorporating an 8-channel analog selector and one A / D converter, and AD convert the terminals 0 to 7 sequentially in time division Function to crawl.

When two modules of the A / D converters 153a and 153b are combined, 16 channels are obtained. The current detection signal 168a of the connected motor corresponds to the current flowing through the A-phase winding of each motor, and is input to the 0th to the 4th of the A / D converter 153a. The motor current detection signal 168b corresponds to the current flowing through the B-phase winding of each motor, and is input to the 0th to the 4th of the A / D converter 153b.
The current detection signals 168a and 168b, which are abbreviated as buses in the drawing, are ten individual signals of two phases of each motor. Since the fifth, sixth, and seventh numbers of the A / D converters 153a, 153b are not used, their inputs are grounded.

[Sub CPU's PWM pulse]
FIG. 8 is a timing chart showing an example of the A-phase PWM signal 171a and the B-phase PWM signal 171b of the stepping motor 167a. In the timing chart of FIG. 8, the vertical axis represents voltage and the horizontal axis represents time.
Further, a timer 196 shown in FIG. 3B is a timer for generating a common PWM cycle gcnt for excitation PWM adjustment common to all the motors.

The timer 196 generates a common PWM cycle timing (S520) with a cycle of 256 [μsec] for five stepping motors.
The PWM pulses are controlled to generate edges symmetrically in time before and after the common timing (S520).

  Note that the Hi width of PWM is a value calculated based on the position command pulse width information θ_ref and the calculation result of the drive algorithm described later.

The PWM terminal function is a clock counter logic for generating a PWM pulse width for exciting PWM adjustment of each motor, and generates an A-phase PWM signal 171 a and a B-phase PWM signal 171 b.
Similarly, with respect to four stepping motors, PWM pulses of A phase timing and B phase timing of each motor are generated at 172a to 175a and 172b to 175b by four PWM terminal functions.

[AD conversion period]
FIG. 9 is a timing chart showing an example of detection timing of the A / D converters 153a and 153b by interruption of the timer 196 and the timer 197 of the CPU 151a. In the timing chart of FIG. 9, the vertical axis represents the type of timer and the horizontal axis represents time. The numerical value of the step number scnt 197 corresponds to the input terminal number at which the two data of the A / D converters 153a and 153b are read immediately before.

FIG. 10 is a flowchart showing an example of timer interrupt control of the interrupt controller IRQC 180.
FIG. 10 shows an example of a processing procedure in an interrupt task of the timer 196 and the timer 197 in the interrupt controller IRQC 180. Control of each timer in the interrupt controller IRQC 180 is performed based on an instruction of the CPU 151a.
The case where the motor to be controlled is the stepping motor 167a will be described as an example.

When the interrupt task of the timer 196 is started, the CPU 151a starts moving the timer 196 (S810). The timing at which the timer 196 starts moving corresponds to the timing S520 of the PWM cycle of FIG. Further, the CPU 151a starts moving the timer 197 (S820). In the present embodiment, the CPU 151a operates the timer 197 continuously eight times during one operation of the timer 196 (corresponding to 0 to 7 shown in FIG. 9).
Next, the CPU 151a performs AD conversion of the current value corresponding to the motor corresponding to the number of repetitions of AD conversion, and acquires an AD conversion value. Further, PWM data of the motor corresponding to the number of repetitions of the timer is calculated (S 830).

The CPU 151a repeats the start of the timer 197 (S820) and the calculation of PWM data (S830) continuously eight times (S840).
When the timer 196 counts up to a predetermined value, the CPU 151a starts the process of the interrupt task of the timer 196 shown in FIG. 8 again. That is, as shown in FIGS. 8 and 9, the process starting from the timing S520 is repeated.

In the present embodiment, the timer 196 generates PWM cycle timing at a cycle of 256 [μsec], and the timer 197 generates AD conversion timing (Fig. 9: timings S523 to S527) at a cycle of 16 [μsec].
Then, as shown in FIG. 8, the PWM function unit generates the PWM signal of the PWM cycle (256 [μsec]) in synchronization with the PWM cycle timing S520.

  As described above, the CPU 151a performs drive control of five motors while sharing the A / D converter. The combination of the functions of the counter timers 181 to 185, 191a to 195a, 191b to 195b, 196, and 197 in the interrupt controller IRQC 180 and the timer interrupt instruction 180a performs arithmetic operation and timing control of the five motors.

FIG. 11 is a flowchart showing an example of acquisition of AD conversion values and calculation processing of PWM data shown in FIG. The case where the motor to be controlled is the stepping motor 167a will be described as an example. Further, each process shown in FIG. 11 is controlled by the CPU 151a.
A sequential operation (FIG. 10: processing of step S550) for determining the width of the PWM signal from the AD conversion value will be described with reference to FIG.

The CPU 151a reads the state of the PWM signal 171c of the PWM terminal function via the CPU bus, and recognizes which phase the current selection is (S551). In the case of Hi, the A phase is selected.
The CPU 151a performs AD conversion of the current value corresponding to the motor corresponding to the number of repetitions of AD conversion, and acquires an AD conversion value (S510). The acquired AD conversion value is stored, for example, in the RAM 751c.

  The CPU 151a acquires the position command pulse (θ_ref) count value which is the time value from the position command pulse width information to the current current detection interruption (S553). The acquired position command pulse (θ_ref) count value is stored, for example, in the RAM 751 c.

The CPU 151a determines the period of the current position command pulse based on the difference between the obtained position command pulse (θ_ref) count value and the position command pulse (θ_ref) count value at the time of the previous interruption (time change of electrical angle θ). A commanded velocity value ω, which is information, is derived (S514).
The CPU 151a determines whether the derived command speed ω is larger than a second threshold value threshold speed ωth (S515). Thus, it is determined whether or not the stable speed is exceeded in the process of step S515.

When the command speed ω is larger than the constant speed value (ωth) (S515: Yes), the CPU 151a regards the state of the motor as the state of high speed rotation and shifts to the vector operation mode (S560). If not (S515: No), the state of the motor is regarded as a state of low speed rotation, and the mode is shifted to the open calculation mode (S570).
In this manner, a motor control system for controlling the stepping motor 167a is specified according to whether or not the stable speed is exceeded.

[Vector operation mode]
Here, the vector operation mode will be described. The basic configuration of this method is inverter control using coordinate conversion used in a brushless DC motor, an AC servomotor or the like.
Specifically, a stationary coordinate system representing a normal current vector flowing in the A phase and the B phase of the stepping motor 167a follows a direction in which the magnetic pole direction of the rotor is advanced by 90 degrees as shown in FIG. It is converted to a rotational coordinate system defined as the q axis. The inverter control is roughly divided into two control operation loops, position PID control and current PID control.

  In the position PID control configured of the proportional and integral compensation steps, the current is reduced based on the detected electrical angle θ of the output shaft of the stepping motor 167a and the position command pulse (θ_ref) count value. The command values iq_ref and id_ref are derived.

In addition, in vector control, in order to perform position PID control, it is necessary to feed back position information of the stepping motor 167a to position control.
Usually, in order to detect such information, a rotary encoder is attached to the stepping motor, and position information is acquired based on the number of output pulses of the rotary encoder. And speed information is acquired based on the output pulse cycle in the acquired position information.

  However, the addition of a rotary encoder, which is essentially unnecessary to drive the stepping motor, causes problems such as an increase in the manufacturing cost of the device and a need for an arrangement space. Therefore, sensorless control has been proposed which estimates the position and speed information of the stepping motor 167a without using an encoder.

However, in vector control based on detection of an induced voltage (detection of an induced voltage component) in the sensorless control described above, rotation at a constant speed (ωth) or more is required.
Therefore, in a limited control state (such as low speed rotation) where the speed at the start or stop of the stepping motor is extremely slow (such as low speed rotation), the open operation mode (open control: excitation PWM of each phase based on current detection of each phase Determine the cycle). Thus, the stepping motor may be drive-controlled.

[Induced voltage calculation]
Here, the details of the PWM data calculation process in the process (vector calculation mode) of step S560 will be described.
The CPU 151a performs an induced voltage calculation.
Specifically, the CPU 151a derives alternating currents iα and iβ and drive voltages vα and vβ of the stepping motor 167a. The alternating current iα corresponds to the AD converted value acquired from the A / D converter 153a, and the alternating current iβ corresponds to the AD converted value acquired from the A / D converter 153b.
Then, the CPU 151a estimates the induced voltages Eα and Eβ of the stepping motor 167a based on the following voltage equation in the motor equivalent circuit based on the input current value and the output voltage value. The induced voltages Eα and Eβ can be derived using the following formulas (1) and (2).

Eα = Vα-R * iα-L * diα / dt (1)
Eβ = Vβ-R * iβ-L * diβ / dt (2)

  Here, R: winding resistance, L: winding reactance, and the values of R and L are stored in advance in the ROM 751 b.

  The CPU 151a performs position calculation to derive the electrical angle θ of the stepping motor 167a. The electrical angle θ can be derived using the following equation (3).

θ = ATAN (−Eβ / Eα) (3)

  The derived electrical angle θ is fed back to the position PID control described above. The derived electrical angle θ is also used in coordinate conversion processing.

[Current control]
The current values flowing through the respective phases of the motor are detected by the A / D converters 153a and 153b as current detection signals 168a and 168b, and the CPU 151a obtains the current detection process (FIG. 9: step S510).
The CPU 151a performs position PID control. Specifically, the CPU 151a derives the current command values iq_ref and id_ref based on the position command pulse (θ_ref). The current command values iq_ref and id_ref are current command values after being converted from the αβ axis to the dq axis.

  The CPU 151a performs coordinate conversion processing. Specifically, the CPU 151a sets the current flowing through the stepping motor 167a in the stationary coordinate system as i.alpha. = I * cos.theta., I.beta. = I * sin.theta., Where .theta. Is the relative angle between the .alpha. Corner). In this case, the current value in the rotational coordinate system can be expressed as id = cos θ * iα + sin θ * iβ, iq = −sin θ * iα + cos θ * iβ.

  By this conversion, the alternating currents iα and iβ flowing in the A phase and the B phase and the current command values iq_ref and id_ref can be expressed by direct current. Here, the d-axis current is a component capable of controlling the amount of magnetic flux and does not contribute to torque. On the other hand, the q-axis current is a component that governs the generated torque of the stepping motor 167a.

  As described above, dq conversion is performed by coordinate conversion processing to obtain the q-axis current iq and the d-axis current id. The deviation between the obtained q-axis current and d-axis current and the current command values iq_ref and id_ref output from the above-described position PID control is used for the current PID control. In normal vector control, the d-axis current is controlled such that an id component that does not contribute to torque is zero.

  The CPU 151a performs current PID control. Specifically, the CPU 151a performs coordinate conversion processing after amplifying the amount of current deviation via an integral compensator, as in the case of position PID control. Thus, the CPU 151a inversely converts the current values iq, id into the current amounts iα, iβ of the stationary coordinate system. Moreover, reverse conversion can be performed using following formula (3), (4).

iα = cos θ * iq−sin θ * id equation (3)
iβ = sin θ * iq + cos θ * id equation (4)

The CPU 151a derives drive voltages vα and vβ based on the converted current values iα and iβ.
The CPU 151a performs reservation setting of the inversion timing of the PWM signal. Specifically, the CPU 151a makes a reservation setting in the register so that the PWM signals 171a and 171b function based on the drive voltages vα and vβ. Thus, the interrupt task by the timer 197 per motor is ended. The generation pattern of the PWM signal is as shown in the timing chart shown in FIG.
By constructing such a feedback system, in vector control, a necessary minimum drive current according to the load is constantly applied to the motor, and power saving and low noise motor drive can be realized.

Next, the details of the PWM data calculation process in the process of step S570 (open calculation mode) will be described.
The CPU 151a performs an induced voltage calculation. Specifically, the CPU 151a derives alternating currents iα and iβ converted into digital values by the A / D converters 153a and 153b, and driving voltages vα and vβ of the stepping motor 167a.
Then, the CPU 151a estimates the induced voltages Eα and Eβ of the stepping motor 167a based on the voltage equation in the motor equivalent circuit described above based on the input current value and the output voltage value.

The CPU 151a sets a target current (ia_ref, ib_ref).
The CPU 151a performs current PID control. Specifically, the CPU 151a performs coordinate conversion processing after amplifying the amount of current deviation via an integral compensator, as in the case of position PID control.
The CPU 151a performs reservation setting of the inversion timing of the PWM signal.

FIG. 15 is a timing chart showing an example of a plurality of PWM pulses and a PWM generation section in the case where the phase makes one rotation by the control described above. In the timing chart of FIG. 15, the vertical axis represents voltage and the horizontal axis represents time.
By constructing such a feedback system, in vector control, a necessary minimum drive current according to the load is constantly applied to the motor, and it becomes possible to realize a power saving and low noise motor drive. At this time, it becomes a periodic characteristic like a sine wave.

[Motor driver]
FIG. 12 is a diagram for explaining an example of a full bridge circuit of the PWM function unit.
FIG. 13 is a diagram for explaining the direction of the drive current flowing through the motor winding according to the PWM signal. Specifically, FIG. 13 (a) shows the direction of drive current flowing in the motor winding when the PWM signal is Hi, and FIG. 13 (b) shows flow in the motor winding when the PWM signal is Low. It represents the direction of the drive current.
FIG. 14 is a conceptual view of a triangular wave comparison method.
The driving method of the PWM inverter and the current detection method will be described by taking the motor driver 157a as an example using FIG. The PWM terminal function is configured of a full bridge circuit using an FET, and in the case of a two-phase stepping motor, it has two full bridge circuits for A phase and B phase.

The full bridge circuit has four FETs of left and right FETs on the high side (high region) side close to the power supply voltage and left and right FETs on the low side. The PWM signal indicating the drive voltage is connected to the gate signal of the high side left side and low side (low region) right FET, and the inverted signal of the PWM signal is connected to the other high side right side and low side left side.
As a result, the ratio of the Hi width of the PWM signal in the PWM control cycle (hereinafter referred to as the PWM signal positive duty) can be adjusted, a desired drive voltage can be applied to both ends of the motor winding, and the drive current can flow through the motor winding.

  The drive current flowing in each phase of the motor is amplified by an operational amplifier (not shown) applied to the current detection resistors 507 and 508 disposed on the ground side of the full bridge circuit by an operational amplifier (not shown), converted to a digital signal by an A / D converter, and the CPU 151a get.

At this time, since the PWM signal turns on / off the FET switch (switching element, see FIG. 13) to apply a desired drive voltage to the motor winding, Hi / Low is repeated. Since switching noise of the FET is generated at the time of Hi / Low switching, the current detection time (predetermined time) is preferably the central portion of each of the Hi width and the Low width of the PWM signal.
As described above, when performing a digital operation of the triangular wave comparison method in which the triangular wave is the carrier and the motor drive voltage is the modulated wave, the change time of the modulated wave is synchronized with either the peak or the valley of the triangular wave See Figure 14).

As a method of detecting the drive current, a shunt resistor is disposed on the ground side of the bridge circuit, and a voltage applied to the resistor is amplified by an operational amplifier and detected using an A / D converter. In this case, even if the direction of the drive current flowing through the motor is constant, the direction of the detection current flowing through the shunt resistor differs depending on whether the PWM signal is Hi or Low.
In order to align the direction of the detected current, the CPU 151a inverts the sign of the detected current value according to which time the PWM signal is detected at Hi or Low. Note that it is determined which of the high width and the low width of the PWM signal is relatively long according to the positive / negative of the drive voltage data.

  As shown in FIG. 13, in order to make the positive and negative detection currents have the same voltage value, (Vcc / 2) is made a current zero point by the operational amplifier circuit component, and voltage conversion is performed to a voltage value corresponding to the positive and negative current amounts. Convert. It can be seen that in the CPU 151a, the interpretation of the sign of the detected current value changes depending on whether it is higher or lower than (Vcc / 2).

Next, the generation of the micro-step timing interrupt process step of the CPU 151a will be described with reference to FIG. 5 (b).
Three timers 181, 191a and 191b are used exclusively for control of the first stepping motor 167a.
The timer 181 is a counter timer that monitors and measures the interrupt 771a.
The timers 191a and 191b are timers for reproducing the microstep timing delayed by one full step pulse from the interrupt 771a.

  FIG. 5 (b) is a timing chart graphed with reference to FIG. 5 (a), with the interrupt period of the timer 181 from start to stop of the motor and the interrupt period of the timers 191a and 191b as the speed. is there.

When the interrupt cycle of the timer 181 reaches the frequency f1 corresponding to the full step clock, the interrupt cycle generated by the timer 191 becomes the frequency f2 corresponding to the microstep cycle divided into eight. f2 is eight times faster than f1.
The timer 181 has a cycle of 10 pps for self-starting and 500 pps for the constant speed f1. At this time, the periods of the timers 191a and 191b are 80 pps for self-starting and 4000 pps for the constant speed f2.

[Description of FIFO Function]
FIG. 7 is an enlarged view of the start and end portions of the timing chart shown in FIG. The timing chart of FIG. 7 shows an example of the timing relationship between the start part and end part of the timing chart shown in FIG. 5B and the interrupt signal 771a.
Further, the three timers cooperate to share a total of eight address memories in the RAM 751c, and function to reproduce sequentially while sequentially recording the period of the signal. The eight addresses are configured as follows.

Address 0 Start count value memory FIFO [0]
Address 1 5-stage FIFO buffer first-stage value memory FIFO [1]
Address 2 5th stage FIFO buffer second stage value memory FIFO [2]
Address 3 5-stage FIFO buffer 3rd-stage value memory FIFO [3]
4th stage value memory FIFO of address 4 5 stage FIFO buffer [4]
Address 5 5-stage FIFO buffer 5th stage value memory FIFO [5]
Address 6 write pointer memory w
Address 7 Read pointer memory r

  At the beginning of power-on, the motor and three timers are stationary, and the interrupt counter value is fixed at the maximum value. In the following description, it is assumed that the register x and the register y in the CPU 151a and the stationary speed threshold ωp (program ROM fixed value) which is the first threshold are used.

[Timer 181]
FIG. 16 is a flowchart showing an example of the interruption flow of the timer 181.
The timer 181 is a counter timer that monitors and measures the interrupt 771a, and functions in the interrupt flow shown in FIG. Also, the CPU 151a starts control from the waiting state of the interrupt 771a.

The CPU 151a starts the timer 181 at the first interrupt 771a at the start of startup, and acquires the interrupt counter value into the register x (S1101).
The CPU 151a clears (initializes) the value of the interrupt interval counter (S1102).
The CPU 151a compares the value of the register x with the value of the stationary speed threshold ωp (S1103). Here, assuming that the stationary speed threshold value ωp = 130 [msec], the comparison result branches to YES because the maximum value of the register x is sufficiently long, and the motor start sequence is obtained.

In the start sequence, the CPU 151a clears the values of the write pointer memory w and the read pointer memory r (w = r = 0) (S1114).
The CPU 151a sets the interruption permission by the next interruption 771a of the timer 191a (S1115). Thus, the first interrupt processing ends.

In the second interrupt 771a, the CPU 151a has x of 100 [msec] and is shorter than the value of ωp, so that the comparison result (S1103) branches to NO.
The CPU 151a writes the value of x into the FIFO [0] (S1104).
The CPU 151a increments the write pointer memory w and writes w = 1 (S1105). Thus, the second interrupt processing ends.

  In the third and subsequent interrupts 771a, the CPU 151a writes the value of x to the FIFO [1] and thereafter, increments w, and writes w = 2 and later. Increment is cyclically repeated as 1, 2, 3, 4, 5, 1, 2, 3,.

[Timer 191a]
FIG. 17 is a flowchart showing an example of the interrupt flow of the timer 191a.
The function is started in the interrupt flow of FIG. 17 in parallel from the second interrupt 771a continued by the timer 191a permitted to interrupt by the first interrupt.

The CPU 151a masks the interrupt 771a (S1121).
The CPU 151a clears (initializes) the interrupt interval counter (S1122).
The CPU 151a compares the values of the write pointer memory w and the read pointer memory r (S1123). In addition, since it is "w = 1 or more and r = 0" for the first time, determination branches to NO.

The CPU 151a reads the value of FIFO [0] into the register y (S1124).
The CPU 151a sets the register y to the counter of the timer 191a and sets the next interrupt as a reservation (S1125).
The CPU 151a increments the read pointer memory r and writes r = 1 (S1126). Subsequently, the setting related to the interruption of the timer 191b described later is performed.

The CPU 151a clears the value of the micro step counter u (u = 0) (S1127).
The CPU 151a calculates y / 8, sets the calculation result in the timer 191b counter, and sets the next interrupt as a reservation (S1128).
The CPU 151a generates position command pulse width information θ_ref (S1129). Thus, the second (second pulse) interrupt processing ends.

If the interruption reserved in the process of step S1125 occurs next time, “w = 2 or more and r = 1” in the process of step S1123, and the process branches to NO again.
In this case, the CPU 151a reads the value of FIFO [1] into the register y (S1124). Then, the value of the register y is set in the timer 191a counter to reserve the next interrupt (S1125), and the read pointer memory r is incremented to write r = 2 (S1126).

In the third and subsequent interrupt reservations, the CPU 151a reads out the FIFO [2] and thereafter, increments the read pointer memory r, and writes r = 3 and later. Increment is cyclically repeated as 1, 2, 3, 4, 5, 1, 2, 3.
It should be noted that when the generation of the motor pulse continues, the written FIFO will be read behind, and the comparison result (S1123) will not match.

[Timer 191b]
FIG. 18 is a flow chart showing an example of the interruption flow of the timer 191b.
The timer 191b permitted to be interrupted in the first interruption processing of the timer 191a starts the function with the interruption flow of FIG. 18 in parallel after y / 8 hours have elapsed from the first interruption of the concerned 191a.

The CPU 151a clears (initializes) the interrupt interval counter (S1142).
The CPU 151a reads the value of FIFO [0] into the counter y (S1124).
The CPU 151a increments the microstep counter u and writes u = 1 (S1147).

The CPU 151a sets the value of the register y in the timer 191a counter, and sets the next interrupt as a reservation (S1125).
The CPU 151a increments the read pointer memory r and writes r = 1 (S1126).

The CPU 151a calculates y / 8, sets the calculation result in the timer 191b counter, and sets the next interrupt as a reservation (S1148).
The CPU 151a generates position command pulse width information θ_ref (S1149).
The CPU 151a determines whether the value of the microstep counter u is less than 7 (less than N-1) (S1143). Since “u = 0” is set for the first time, the process branches to NO, and the first interrupt processing is completed.

If the interruption reserved in the process of step S1148 occurs next time, “u = 1” is obtained in the process of step S1143, and the process branches to NO again.
In this case, the CPU 151a reads the value of FIFO [1] into the register y (S1144), increments the microstep counter u, writes u = 2 (S1147), and sets the next interrupt as a reservation (S1148). become.

  In the third and subsequent interrupt reservations, the CPU 151a holds the measured value in the FIFO [2] or later, increments the microstep counter u, and writes u = 3 or later. Increment is cyclically repeated as 1, 2, 3, 4, 5, 6, 7.

  Further, after the seventh time reaching “u = 7”, the process branches to YES in the process of step S1143 to mask the timer 191b interruption (S1151), and the process is ended without making the next interruption reservation. Therefore, seven times u = 0 to 6 correspond to one interruption of the timer 191a and end repeatedly.

From the above description to the start portion of the timing chart shown in FIG. 7, FIFO writing is repeated from the input of the self-starting full step 1 pulse (timing S411) (timing S411, S413). Then, eight micro step timings corresponding to the full step 1 pulse FIFO readout value are repeatedly generated (timings S421 and S422), and the value of the position command pulse width information θ_ref is updated.
The micro step timing is generated delayed by the self-starting full step one pulse Δt. The microstep timing cycle is longest at self-startup 12.5 [msec] and shortest at the maximum speed of 50 [μsec].

Due to the presence of the above-described multi-stage FIFO buffer, even if the motor rotation command accelerates rapidly, following the initial position shift of one pulse, the continuous form of the position command pulse information is completely completed without any loss. It becomes possible to continue recording and reproduction.
In addition, since there are five stages of FIFOs, it is possible to cope with a sudden acceleration in a range in which the indicated position does not deviate by more than four full step pulses in a cumulative manner.

[Last 1 pulse]
Next, the motor stop time will be described. When the interrupt 771a is stopped as a motor stop instruction as in the central portion (timing S431, S432) of the timing chart shown in FIG. 7, the timer 181 is stopped waiting for the next interrupt. That is, the write pointer memory w is not incremented.
In this case, as the read pointer memory r is incremented, the values of the write pointer memory w and the read pointer memory r match in the comparison (S1123) in the timer 191a, and the comparison result branches to YES and the stop sequence (timing S441) It becomes.

  In the stop sequence, the read pointer memory r is forcibly set to 0 (r = 0) (S1134), and an interrupt mask (interrupt disablement) at the next activation of the timer 191a is set (S1135). The timer 191a ends the interrupt processing so that the FIFO [0] reading of the self-starting pulse value finally comes out of circulation. The timer 191b also generates and stops 7 pulses from the FIFO [0] read (timing S442).

As described above, in the image forming apparatus having the motor control device according to the present embodiment, when starting and stopping the motor, starting from the pulse rising reference with the low level setting the common self-starting frequency as the initial state, It is considered as an I / F without a final rise.
Therefore, the corresponding "accumulated pulse number" from start to stop is output even to the host CPU for which measurement of the final pulse width is not performed by processing that does not forcibly set the reading part of the self-starting pulse value as normal FIFO forcibly. It becomes possible to function with the number of microsteps.
Also, in stop detection based on the threshold value ωp near such a self start, care is taken to reverse the processing order etc. by the write interrupt and write pointer in the CPU bus operation and the simultaneous access of read interrupt and read pointer. There is no need to do this, and more stable stop detection is possible.

For example, the apparatus can be improved so that motor control can be performed by a vector control method by a plurality of motor common ICs including a commercially available motor driver, shunt resistor, AD detection circuit, sub CPU and AD conversion circuit. it can.
At this time, the host CPU has the same performance as that before the change, and redesign of the sequence software and the communication system is almost unnecessary. In addition, it is possible to easily and inexpensively change the existing image forming apparatus completed prior to the introduction of the vector control method to correspond to the vector control method.

  In the present embodiment, the control of the first stepping motor 167a has been described as an example. Similarly, for the five stepping motors 167a-167e, timers 182-185 are made to function with the timing of each motor and the separate FIFO memory area allocated to each motor. In this manner, position command pulse width information θ_ref of each motor can be periodically generated.

  Further, in the present embodiment, an example in which the FIFO has five stages is shown, but the present invention is not limited to this. Depending on the acceleration range of each motor, it is also possible to individually increase or decrease the number of stages of the FIFO, and it is sufficient to set an appropriate memory capacity and adaptability to the acceleration range.

  Further, in the present embodiment, the steps up to motor stop have been described with reference to the timing chart shown in FIG. For example, in the case of a motor that resumes rotation continuously after stopping, it is also possible to interlock the operation of reversing the rotation direction instruction signal and changing the vector control setting accordingly in conjunction with such a stop detection state. It becomes possible. Therefore, smart reverse rotation control can be performed while reducing the real-time communication load between the host CPU and the sub CPU.

  The embodiments described above are for more specifically describing the present invention, and the scope of the present invention is not limited to these examples.

  171 to 175: PWM terminal function, 167: stepping motor, 153: A / D converter, 751: system controller, 151: vector modulation IC (motor control device).

Claims (9)

Measuring means for measuring the period of a full step pulse input to a drive circuit for driving a motor having two phase windings;
Storage means for storing the result of the measurement;
The measurement result stored in the storage means is read out from the second pulse of the full step pulse or at a predetermined timing thereafter, and the timing is measured by a micro step period divided by an integer N of 8 or more to perform a micro step Pulse generation means for generating a pulse N-1 times and generating the microstep pulse so that the Nth microstep pulse coincides with the period of the corresponding full step pulse;
An A / D converter for detecting a current value on the ground side of the drive circuit;
Estimation means for respectively estimating an induced voltage generated in a phase winding of the motor based on the detected current value;
Control means for detecting an electrical angle based on the estimated induced voltage and performing vector control based on the detected electrical angle and the micro-step pulse;
Generation means for generating a PWM signal for controlling the switching element of the drive circuit;
The control means causes the generation means to generate a PWM signal according to the result of detection of the current value for each microstep pulse and the vector control, and performs motor control in synchronization with the input full step pulse. And
Motor controller. The A / D converter comprises a first A / D converter and a second A / D converter,
The first A / D converter detects a drive current of a first phase of the plurality of motors,
The second A / D converter detects a drive current of a second phase of the plurality of motors.
The motor control device according to claim 1. The drive circuit is configured as a full bridge circuit for driving the motor.
The motor control device according to claim 1. The motor is a stepping motor.
A motor control device according to claim 1, 2 or 3. The A / D converter is an analog-to-digital conversion type current detector that performs current detection of a plurality of phases of the motor in a time sharing manner.
The motor control device according to any one of claims 1 to 4. Each of the plurality of motors functions as a sheet feeding unit included in the image forming apparatus.
The control means is configured to perform the vector control according to a measurement result obtained by measuring an interval of a motor pulse input to the motor, or constant an output of a PWM signal without estimating the induced voltage. Performing the motor control in any one of the open operation modes.
The motor control device according to any one of claims 1 to 5. When the measurement result exceeds the first threshold, the control means considers that the state of the motor is a stop state, permits switching to reverse rotation in the rotational direction, initializes the pulse generation means, and performs an open operation. Switch to the mode
If the measurement result is smaller than the first threshold value and larger than the second threshold value, the state of the motor is regarded as a low speed rotation state, and the mode is shifted to the open calculation mode;
When the number of the micro step pulses is N or more and the measurement result is smaller than a second threshold, the state of the motor is regarded as a state of high speed rotation, and transition to a vector operation mode is performed.
The motor control device according to claim 6. It has a motor control device according to any one of claims 1 to 7.
Sheet conveying device. It has a motor control device according to any one of claims 1 to 7.
Image forming apparatus.

Images