JP2019096745A - Semiconductor integrated circuit, method of manufacturing the same, and semiconductor design support device - Google Patents

Abstract

To improve utilization efficiency of a multi-bit FF and reduce a circuit area, in a semiconductor integrated circuit.SOLUTION: A semiconductor integrated circuit includes a combination of a single FF (flip-flop) cell, a multi-bit FF cell, and a dummy cell, and has the multi-bit FF cell having bits of the number greater than a predetermined bit number. Unused bits of the multi-bit FF cell are used as a dummy FF cell.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a semiconductor integrated circuit, a method of manufacturing a semiconductor integrated circuit, and a semiconductor design support apparatus.

  In semiconductor design, when designing a semiconductor integrated circuit in a standard cell system, it is called a dummy cell or spare cell which is not necessary for the original circuit function in order to minimize mask pattern correction when circuit correction is required. Techniques for incorporating cells in advance are already known. The dummy cell or the spare cell is a generic term including logic cells such as AND, OR, and NAND in addition to FF (flip flop). In addition, there is already known a technique of replacing a multi-bit or multi-bit FF cell when a common clock or reset system is used in a set of FF cells which are single cells.

  For example, as a technology for efficiently increasing the number of cells in a cell, circuit design is performed based on the circuit specification, circuit information (HDL) is generated, and the circuit using the cell library including cell information of the semiconductor integrated circuit Perform logic synthesis on information. Furthermore, logic circuit information (NETLIST) including cell arrangement and wiring arrangement and wiring information for the cell is generated, and cell arrangement and wiring for the cell are performed based on the NETLIST arrangement and wiring information. There is known a technique of referring to a cell library based on the implementation results of placement and wiring, and multibiting a small bit cell of NETLIST (for example, Patent Document 1).

  However, when multiple single FFs are collected and multi-bited conventionally, if there is no multi-bit FF cell of the same bit width prepared as a standard cell, a cell whose bit width is larger than the number of single FFs If you use a bit, you can create unused bits, apply some of the cells smaller in bit width than the number of single FF, and keep the rest as single FF to maximize the efficiency of multibiting. There was a problem that it was impossible.

  In addition, the circuit scale has increased due to the recent increase in integration and scale of semiconductor integrated circuits, and the amount of insertion of dummy cells also tends to increase along with it, and the circuit scale of dummy cells not normally used is also increasing. There is also a problem.

  The present invention has been made in view of the above-described points, and it is an object of the present invention to improve the utilization efficiency of multi-bit FFs and reduce the circuit area in a semiconductor integrated circuit.

  Therefore, in order to solve the above problems, a semiconductor integrated circuit includes a combination of a single flip-flop (FF) cell, a multi-bit FF cell and a dummy cell, and has a multi-bit FF cell larger than a predetermined number of bits. An unused bit of the bit FF cell is used as a dummy FF cell.

  In a semiconductor integrated circuit, it is possible to improve the utilization efficiency of multi-bit FFs and reduce the circuit area.

It is a figure showing the flow from combination to layout in semiconductor integrated circuit design. It is a figure for demonstrating the multi-bit-ization of FF cell. It is a figure which shows the example which arrange | positions a dummy FF cell to the multi-bit FF cell in embodiment of this invention. It is a figure which shows the structural example of the dummy FF cell which implement | achieves clock gating in the multi-bit FF cell in embodiment of this invention. FIG. 7 is a diagram showing an example in which dummy logic cells are arranged in the vicinity of a multi-bit FF cell including a dummy FF cell according to an embodiment of the present invention. It is a figure which shows the example of rearrangement of the dummy FF cell after multi-bit-ization in embodiment of this invention. It is a figure which shows the example of the processing flow of the semiconductor design in embodiment of this invention. It is a figure showing the example of hardware constitutions of the semiconductor design support device in an embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described based on the drawings.

  FIG. 1 is a diagram showing a flow from synthesis to layout in semiconductor integrated circuit design. In step S1, the dummy cell placement module list is input to the logic synthesis / DFT stage (S5) or the layout stage (S9). In step S2, the library is input to the logic synthesis / DFT stage (S5). In step S3, data described in RTL (register transfer level) which may include dummy cells is input to the logic synthesis / DFT stage (S5). In step S4, the constraints are input to the logic synthesis / DFT stage (S5).

  The logic synthesis / DFT stage (S5) includes the steps of synthesis / optimization (S51), multi-bit conversion (S52), and dummy cell incorporation (S53). The logic synthesis / DFT stage (S5) outputs a netlist (S7), which is input to the layout stage (S9). In step S6, the library is input to the layout stage (S9). In step S8, the constraints are input to the layout stage (S9).

  The layout stage (S9) includes the steps of CTS (Clock Tree Synthesis: forming and inserting a clock tree) (S91), placement and routing (S92), multi-bit conversion (S93), and dummy cell incorporation (S94). The layout stage (S9) outputs a netlist (S10) and a mask pattern (S11). Unlike dummy cell incorporation (S53), in dummy cell incorporation (S94), the layout tool performs dummy cell incorporation in consideration of placement, such as performing random or distributed placement called shotgun placement as placement of the entire chip. Be done.

  As shown in FIG. 1, in multibiting (S52) performed in the logic synthesis / DFT step (S5), there is no information on placement and routing in the layout step (S9), so single FF groups are multibited. In this case, depending on the combination, the wiring may be distant as the timing error occurs, and multi-bitization may be canceled at the layout stage even in multi-bit organization. Therefore, in multi-bit conversion (S52), FFs of bus signals that are likely to be arranged in the vicinity of both the input and output sides are often converted to multi-bit conversion.

  In multi-bit conversion at the layout stage (S93), there is known a method of multi-bit converting adjacent single FF groups using information on placement and routing.

  FIG. 2 is a diagram for explaining multi-bitization of FF cells. In FIG. 2, as an example of multi-bit conversion of adjacent FF cells not producing unused bits, for example, multi-bit conversion when seven single FF groups having a common clock and reset system in the periphery are present at the layout stage. An example of Although the reset line is not shown in FIG. 2, it may be wired in common with the clock line.

  As shown in FIG. 3A, since there are seven single FF groups, unused bits are generated when mapped to an 8-bit multibit FF cell. Therefore, seven single FF groups are configured by 4-bit multi-bit FF cells and three single FF cells, as shown in FIG. 3B. Furthermore, two of the three single FF cells may be mapped to a 2-bit multi-bit FF cell.

  FIG. 3 is a diagram showing an example in which dummy FF cells are arranged in multi-bit FF cells according to the embodiment of the present invention. In the arrangement of dummy cells, FFs and logic cells for implementing correction logic are often arranged in sets. Example 1 will be described below.

  In the first embodiment, the dummy FF cells are arranged to be included in the multi-bit FF cells. With this arrangement, it is possible to take advantage of the reduction in arrangement area by multi-bit FF cells.

For example, although there is a tendency that the area of about 10 to 15% becomes smaller with one 8-bit multi-bit FF cell compared with the addition of the area of 8 single FF cells, an example of a certain semiconductor manufacturing process As a value representing the size of the area occupied by the FF is described as follows,
The size of one bit FF is 3.5 * 0.7 = 2.45
The multibit 2FF (2BitFF) is 3.22 * 1.4 = 4.508,
Multi-bit 4FF (4BitFF) is 6.02 * 1.4 = 8.428
Multi-bit 8FF (8BitFF) is 5.88 * 2.8 = 16.464
Here, the area occupied by eight FFs is 2.45 * 8 = 19.6.
1) The area occupied by 4 FF1 + 4 FFs shown in FIG. 3A is 8.428 + 2.45 * 4 = 18.228, so the ratio of the area to be reduced compared to 8 FFs is 1-18.228 / 1. 19.6 = 1-0.93 = 0.07
2) The area occupied by 4 FF1 pieces + 2 FF 1 pieces + 2 pieces is 8.428 + 4.508 + 2.45 * 2 = 17.836, so the ratio of the area reduced compared to 8 pieces of FF is 1-17.836 / 19. .6 = 1-0.91 = 0.09
3) Since the area occupied by one 8FF shown in FIG. 3B is 16.464, the ratio of the area to be reduced in comparison with eight FFs is 1−16.464 / 19.6 = 1−0.84 = 0.16
As described above, there is an advantage to reduce the area by 7%, 9% and 16% with respect to eight FFs, for example, the area reduced by one 8-bit multi-bit FF is 19.6-16.464 = 3. It becomes 136 and becomes smaller by 2.45 or more for one FF.

  In addition, when collecting a plurality of single FF cells and converting them into multi bits, if there is no multi-bit FF cell of the same bit width prepared as a standard cell, a multi with a larger bit width than the number of single FF cells Use of bit FF cells will result in unused bits. The unused bit can be included as a dummy FF cell in the multi-bit FF cell.

  By arranging the dummy FF cells in the multi-bit FF cells as in the first embodiment described above, the area can be reduced by effectively using the multi-bit FF cells.

  In addition, by using unused bits of multi-bit FF cells as dummy FF cells, the area can be reduced as compared with the case where the conventional dummy FF cells are separately provided.

  FIG. 4 is a diagram showing a configuration example of a dummy FF cell that performs clock gating in a multi-bit FF cell according to the embodiment of the present invention. Since the dummy FF cell is not normally used, useless power consumption occurs when the clock is continuously supplied. Therefore, clock gating is performed to stop the supply of the clock before the FF. FIG. 4 shows an example of clock gating using a simple AND cell. FIG. 4A shows an example in which clock gating is performed on a single FF dummy FF cell, and an EN signal for enabling the clock and a clock clk are input to the AND cell. Example 2 will be described below.

  In the second embodiment, in order to apply clock gating to a multi-bit FF cell, a multi-bit FF cell having a bit capable of clock gating is used. As a method, there is a method in which a gating cell is included inside, or a method in which a clock to be gated is drawn out and supported.

  FIG. 4B shows a method of including a gating cell inside. As shown in FIG. 4B, in the multi-bit FF cell, the clock and reset system is one system.

  FIG. 4C shows a scheme of attaching a gating cell to the outside. As shown in FIG. 4C, in the multi-bit FF cell, a plurality of clock and reset systems can correspond.

  In addition, the configurations shown in FIGS. 4B and 4C may be implemented in combination. That is, in the multi-bit FF cell, a gating cell may be included in one FF cell, and a gating cell may be included in the other FF cells.

  The multi-bit FF cell that performs clock gating has a larger area than a normal multi-bit FF cell. However, the size of the AND cell is 0.56 * 0.7 = 0.392 in an example of a semiconductor manufacturing process, and one FF is 3.5 * 0.7 = 2.45. The size of is smaller than that of one FF by about 6.25. Therefore, it can be said that the increase in the size of the area of the multi-bit FF cell is relatively small.

  As in the second embodiment described above, when the gating cell is included inside the multi-bit FF cell, the wiring efficiency is improved, so it is more efficient than a single FF group. When the gating cell is attached to the outside of the multi-bit FF cell, the area for wiring extraction increases. However, the wiring efficiency is improved as in the case where the gating cell is included inside the multi-bit FF cell.

  However, both the method of including the gating cell in the multi-bit FF cell and the method of arranging it outside will increase the number of wires if they are made compatible with multiple clock and reset systems, so the advantage of improving the wiring efficiency will be reduced. Therefore, which method to use may be determined depending on whether there are a plurality of clock and reset systems in the dummy cell installation module.

  FIG. 5 is a diagram showing an example in which dummy logic cells are arranged in the vicinity of multi-bit FF cells including dummy FF cells according to the embodiment of the present invention. Since the layout tool can find unused terminals of cells, we propose a method to automatically arrange dummy logic cells other than FF cells in the vicinity if there are unused terminals in multi-bit FF cells. FIG. 5A shows a multi-bit FF cell including dummy FF cells. Example 3 will be described below.

  If it is not an unused terminal after scanning by DFT (Design For Testability), a dummy FF cell is estimated from the cell name when replacing a single FF cell with a multi-bit FF cell. Since it is necessary to maintain a single-time name in multi-bitization so that the designer can recognize after substitution into multi-bit FF cells, dummy FF cells can be found from the names.

  As a reason to move the dummy logic cell to the vicinity of the dummy FF cell so as to change from the arrangement of FIG. 5B to the arrangement of FIG. 5C, correction is made when a circuit failure is actually detected and the dummy FF cell is used. The timing may not be satisfied unless there is a logic cell for realizing the later logic, and if the type of logic cell that can be used for correction is small, the waveform may become dull and the design rule may not be observed. It is because sex becomes high.

  Therefore, as shown in FIG. 5C, in the third embodiment, when dummy FF cells are included in a multi-bit FF cell, dummy logic cells are arranged in the vicinity to facilitate correction when a circuit failure occurs. .

  FIG. 6 is a diagram showing an example of rearranging dummy FF cells after multi-bit conversion in the embodiment of the present invention. FIG. 6 simply illustrates only the multi-bit FF cells including the dummy FF cells and the dummy FF cells. In FIG. 6, the multibit FF is described as MBFF. Example 4 will be described below.

  When multi-bit conversion including dummy FF cells is performed, as shown in FIG. 6A, the arrangement of dummy FF cells may be biased in the module. The dummy FF cells are cells for correction at the time of failure occurrence, and if the dummy FF cells are concentratedly arranged, the wiring distance from the dummy FF cells to the failure occurrence point becomes long as described in FIG. Problems such as failure to meet timing may occur, which may cause problems.

  For example, as shown in FIG. 6A, if circuit correction occurs at the position of the upper right (“X” in the figure) of the module in a biased lower left state, there is no dummy FF cell in the periphery. It may be possible.

  Therefore, the layout tool verifies the arrangement of the dummy FF cells, and when the arrangement of the dummy FF cells is biased, as shown in FIG. 6B, the dummy FF cells are moved and rearranged and distributed and arranged. Arrange the cells within the module to a certain degree. As shown in FIG. 6B, the distribution may be performed for both a single dummy FF cell and a multibit FF cell including the dummy FF cell.

  As in the fourth embodiment described above, by arranging the dummy FF cells in a distributed manner in the module, it is possible to easily correct when a circuit failure occurs.

  FIG. 7 is a diagram showing an example of a processing flow of semiconductor design in the embodiment of the present invention. The design support device S200 and each means shown in FIG. 7 indicate functions and procedures.

  In the position recognition means S201a, the design support device S200 receives the net list S101, the dummy cell installation module list S102, the library S103, and the layout information S104 and recognizes the positions of the single FF cell and the multi-bit FF cell. When the dummy cell installation module list is defined in the net list S101 with a name that can be recognized as a dummy cell, it is unnecessary because it can be searched and recognized.

  Subsequently, in the replacing means S202, the process of replacing the FF cells excluding the FFs in the list of non-multibit locations from the position information of all the FF cells obtained from the position recognizing means S201a is replaced with multibit FF cells. Do. The replacement is performed when the clock and reset systems are identical and are concentratedly arranged FF cells. At the time of replacement, a normal FF cell and a dummy FF cell are taken together as a multibit conversion target candidate, and the dummy FF cell is also assigned to the multibit FF cell. If there is an output floating terminal in the cell by searching with the multi-bit FF cell name, it can be judged as a multi-bit FF cell including the dummy FF cell, so other dummy logic cell groups are arranged in the vicinity.

  Even in the case of a module in which a plurality of clock and reset systems exist, replacement is possible by using a multi-bit FF cell having a configuration as shown in FIG. 4C. However, since there is a possibility that the merit as a circuit may be small, the process of multi-bitizing the FF group and the dummy FF having the same clock reset system is given priority.

  Subsequently, in comparison means S203, whether there is a merit as a circuit before and after replacement is compared. In order to compare the area merit of the area from the cell size information and the wiring merit and timing merit from the wiring condition, the comparison target comparison result is output (S300).

  Subsequently, if there is no restriction S100 for multi-bit conversion in the determination means S204, a replacement judgment is automatically made as it is based on the result of the comparison means, but a signal which one does not want multi-bit conversion other than the non-target list (S105) If there is a problem, the added comparison target comparison result (S300) is output to be excluded from the multi-bit conversion target, re-setting is performed, and re-processing of replacement is performed (return to S202) or direct replacement specification is performed (S301) .

  In the position recognition means S201b, the position of the entire FF is recognized again by multi-bit FF conversion determined by the judgment means (S204).

  Subsequently, in the rearrangement means S205, when there is a bias in the arrangement of the dummy FF cells from the positional relation of all the FFs rerecognized by the position recognition means S201b and the positional relation of the dummy FF cells therein, Relocate to distribute the position. As described in FIG. 6, due to its function, dummy FF cells are not distributed in the module in which the dummy FF cells are inserted, and the case where correction is required at a location far from the arrangement position is supported. Since it can not be done, distributed arrangement is required.

  The present invention can be applied to a method of manufacturing a semiconductor integrated circuit by laying out a semiconductor integrated circuit using the process flow of semiconductor design shown in FIG.

  FIG. 8 is a diagram showing an example of a hardware configuration of the semiconductor design support device in the embodiment of the present invention. The hardware configuration of the semiconductor design support device according to the embodiment of the present invention has a CPU (Central Processing Unit) 10, a memory 11, a hard disk 12, a keyboard 13, a mouse 14, a display 15 and the like as shown in FIG. . The hard disk 12 stores necessary circuit information, library information and the like. Further, various information and programs stored in the hard disk 12 are read into the memory 11 and are operated and processed by the CPU 10 to realize each means shown in FIG. The result of the process is output to the display 15 and the hard disk 12.

  As described above, according to the embodiment of the present invention, the multi-bit FF cells can be effectively used to reduce the area by arranging the dummy FF cells in the multi-bit FF cells. In addition, wiring efficiency can be improved by including a gating cell for the clock to the dummy FF cell inside the multi-bit FF cell. When the dummy FF cells are included in the multi-bit FF cells, arranging the dummy logic cells in the vicinity facilitates correction when a circuit failure occurs. Also, by arranging the dummy FF cells in a distributed manner in the module, it is possible to easily correct the circuit failure.

  As described above, in the semiconductor integrated circuit, the utilization efficiency of multi-bit FFs can be improved, and the circuit area can be reduced.

  In the embodiment of the present invention, the comparing means S203 and the judging means S204 are an example of the comparing and judging means.

  Although the embodiments or examples of the present invention have been described above in detail, the present invention is not limited to such specific embodiments, and is within the scope of the present invention as set forth in the claims. Various modifications and changes are possible.

10 CPU
11 Memory 12 Hard Disk 13 Keyboard 14 Mouse 15 Display

JP, 2016-218670, A

Claims (10)

A semiconductor integrated circuit including a combination of a single flip-flop (FF) cell, a multi-bit FF cell and a dummy cell,
Have multi-bit FF cells larger than a predetermined number of bits,
The semiconductor integrated circuit in which the unused bit of the multi-bit FF cell is used as a dummy FF cell.   2. The semiconductor integrated circuit according to claim 1, wherein clock gating is performed on dummy FF cells included in the multi-bit FF cells, and the clock gating is performed commonly in the multi-bit FF cells.   3. The semiconductor integrated circuit according to claim 1, wherein a dummy logic cell is arranged in the vicinity of a dummy FF cell included in the multi-bit FF cell.   The semiconductor according to any one of claims 1 to 3, wherein the dummy FF cells included in the multi-bit FF cells are distributed and disposed on the semiconductor integrated circuit together with the dummy FF cells composed of a single FF cell. Integrated circuit. A method of manufacturing a semiconductor integrated circuit including a combination of a single flip-flop (FF) cell, a multi-bit FF cell, and a dummy cell, comprising:
A position recognition step that recognizes the arrangement of all FFs including single FF cells and multi-bit FF cells;
And a replacing step of replacing a plurality of single FF cells including dummy FF cells with multi-bit FF cells based on the recognized arrangement of FFs,
A method of manufacturing a semiconductor integrated circuit, wherein unused bits of the multi-bit FF cells are arranged as dummy FF cells in the semiconductor integrated circuit.   6. The semiconductor integrated circuit manufacturing method according to claim 5, further comprising a comparison / determination step of comparing the arrangement of the FF before substitution and the arrangement of the FF after substitution to decide whether or not to carry out the substitution. Method. The position recognition step is
Further including the step of recognizing the arrangement of the replaced multi-bit FF cell,
The replacing step is
7. The method of manufacturing a semiconductor integrated circuit according to claim 5, further comprising the step of distributing and relocating the recognized replaced multi-bit FF cell on the semiconductor integrated circuit. A semiconductor design support device for a semiconductor integrated circuit including a combination of a single flip-flop (FF) cell, a multi-bit FF cell, and a dummy cell,
Position recognition means for recognizing the arrangement of all FFs including single FF cells and multi-bit FF cells;
And replacement means for replacing a plurality of single FF cells including dummy FF cells with multi-bit FF cells based on the recognized arrangement of FFs,
The semiconductor design support device arranges the unused bits of the multi-bit FF cells as dummy FF cells in the semiconductor integrated circuit.   9. The semiconductor design support device according to claim 8, further comprising comparison determination means for determining whether or not replacement is to be performed by comparing the placement of the FF before replacement and the placement of the FF after replacement when performing the replacement. . The position recognition means
Recognize the arrangement of the replaced multi-bit FF cell,
The replacement means is
10. The semiconductor design support device according to claim 8, wherein the arrangement of the recognized replaced multi-bit FF cells is distributed and rearranged on the semiconductor integrated circuit.

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