JP2019091492A - Memory device and method of controlling nonvolatile memory - Google Patents

Abstract

To provide a highly convenient memory device.SOLUTION: A memory device 3 includes a nonvolatile memory 5, and a controller 4 for controlling the nonvolatile memory. The controller includes first to third processors. The first processor determines a processor to execute a new queued process which can be executed in any of the first to third processors. The controller determines at least one of new processes having the execution processor determined by the first processor, so as to be executed next by one of the second and third processors, on the basis of priority information including priority on the new processes.SELECTED DRAWING: Figure 1

Description

  The present embodiment relates to a control method of a memory device and a non-volatile memory.

  A solid state drive (SSD) includes non-volatile memory such as, for example, NAND flash memory. The NAND flash memory includes a plurality of blocks (physical blocks). The plurality of blocks include a plurality of memory cells arranged at intersections of word lines and bit lines.

JP, 2012-141944, A

  The present embodiment provides a highly convenient memory device and a non-volatile memory control method.

  According to the present embodiment, the memory device includes a non-volatile memory and a controller for controlling the non-volatile memory. The controller includes first to third processors. The first processor is waiting for execution and determines a new process execution destination that can be executed by any of the first to third processors. The controller determines an execution destination determined by the first processor to be executed next by one of the second and third processors based on the priority information including the priority for new processing. Determine at least one of the new processing to have.

FIG. 1 is a block diagram showing an example of a configuration of an information processing system according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a control program according to the first embodiment. FIG. 2 is a block diagram showing an example of a built-in state of the memory device according to the first embodiment. The block diagram which shows an example of the relationship between the components of the information processing system which concerns on 1st Embodiment. 5 is a flowchart showing an example of processing executed by a control program and a hardware unit according to the first embodiment. The block diagram which shows an example of the relationship between the components of the information processing system which concerns on 2nd Embodiment. FIG. 10 is a block diagram showing an example of the relationship between components of a memory device according to a third embodiment. FIG. 13 is a block diagram showing an example of the relationship between a processor and a memory according to a third embodiment. The flowchart which shows an example of the 1st process of the scheduler which concerns on 3rd Embodiment. The flowchart which shows an example of 2nd process of the scheduler which concerns on 3rd Embodiment. A block diagram showing an example of a notice state of field information between tasks concerning a 3rd embodiment. FIG. 13 is a block diagram showing an example of the relationship between tasks and memory areas according to the third embodiment. FIG. 13 is a block diagram showing an example of a detailed configuration of an information processing system according to a fourth embodiment. FIG. 14 is a perspective view showing an example of a storage system according to a fourth embodiment. FIG. 16 is a block diagram showing an example of the configuration of a software defined platform according to the fifth embodiment. The figure which illustrates two types of scheduling implement | achieved by the software defined SSD platform which concerns on 5th Embodiment. FIG. 16 is a view showing an example of parameters held in each layer of the memory device according to the fifth embodiment; The flowchart which shows an example of the scheduling which concerns on 5th Embodiment. The figure which shows the 1st example of the scheduling which concerns on 5th Embodiment. The figure which shows the 2nd example of the scheduling which concerns on 5th Embodiment. A figure showing the 3rd example of scheduling concerning a 5th embodiment. The figure which shows the example of the task chain which concerns on 5th Embodiment. The figure which shows the example of delivery of the information between the tasks which concern on 5th Embodiment. The figure which shows the example of the work area corresponding to the task which concerns on 5th Embodiment. The flowchart which shows the example of the communication by HAL which concerns on 5th Embodiment. The block diagram which shows the example of the communication by HAL which concerns on 5th Embodiment. 16 is a flowchart showing an example of processing compliant with the HAL API for the NAND flash driver according to the fifth embodiment. FIG. 13 is a block diagram showing an example of a HAL API for a NAND flash driver according to a fifth embodiment. FIG. 16 is a block diagram showing an example of task assignment using an NCQ according to a fifth embodiment. The block diagram which shows an example of the function of the software defined type SSD platform concerning a 5th embodiment.

  Hereinafter, each embodiment will be described with reference to the drawings. In the following description, substantially the same functions and components will be denoted by the same reference numerals, and redundant description will be made only when necessary.

First Embodiment
The present embodiment describes a memory device comprising a Software Defined Platform.

  The software-defined platform, for example, decouples the functionality of the memory device from the control of the hardware and performs the control by software.

  In the present embodiment, the memory device is, for example, an SSD, but various types of memory such as a memory card, a hard disk drive (HDD), a hybrid memory device including an HDD and an SSD, an optical disk, a storage device, and a memory server It may be a device. When the memory device is an SSD, the memory device has the same communication interface as the HDD.

  The memory device, which is an SSD, includes non-volatile memory. In the present embodiment, the case where the non-volatile memory includes a NAND flash memory will be described. However, the nonvolatile memory may be, for example, a NAND flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a resistive random access memory (ReRAM), or an electric random access memory (FeRAM). Other types of memory other than the flash memory may be included. The non-volatile memory may also include a three-dimensional flash memory.

  In the non-volatile memory, data is collectively erased for each erase unit area. The erase unit area includes a plurality of write unit areas and a plurality of read unit areas. When the non-volatile memory is a NAND flash memory, the erase unit area corresponds to a block. The write unit area and the read unit area correspond to pages.

  In the present embodiment, access means both writing data to the memory and reading data from the memory.

  In the present embodiment, the processing unit is a task. However, for example, other processing units such as jobs, processes, transactions, threads may be used. For example, a thread is a minimum processing unit corresponding to parallel processing, and in other words, it may be a minimum unit which can not be processed simultaneously if it is disassembled. For example, a task may include one or more threads. For example, a process may include one or more tasks. For example, a transaction is a processing unit managed to prevent conflicts, and may include one or more processes. For example, the job may be a unit of processing executed for an instruction requested by the information processing apparatus or program.

  In the present embodiment, the program is a computer program. In a computer program, processes to be performed by a computer are described in order. The program can be implemented by a computer to implement various functions such as issuing and accepting commands, data, and information, data processing, operations, and the like.

  In the present embodiment, a computer is, for example, a machine that executes an operation or a process according to an instruction. For example, a computer includes a memory and a processor. The memory stores the program. The processor is hardware for executing an instruction set (for example, data transfer, calculation, processing, control, management) described in a program stored in the memory. In the present embodiment, the computer should be interpreted in a broad sense, and includes, for example, an information processing device, a controller of a memory device, a personal computer, a large computer, a microcomputer, a server device, and the like. In the present embodiment, instead of the computer, a computer system in which a plurality of computers operate in cooperation may be used.

  FIG. 1 is a block diagram showing an example of an information processing system according to the present embodiment.

  The information processing system 1 includes an information processing device 2 and a memory device 3. The information processing device 2 can operate as a host device corresponding to the memory device 3.

  The memory device 3 may be built in the information processing device 2, and the information processing device 2 and the memory device 3 may be connected to be able to transmit and receive data via a network or the like. The memory device 3 may be communicably connected to the plurality of information processing devices 2. Also, a plurality of memory devices 3 may be communicably connected to one or more information processing devices 2.

  The memory device 3 includes a controller 4 as an example of a control circuit and a non-volatile memory 5. The controller 4 and the non-volatile memory 5 may be detachable, and the memory capacity of the memory device 3 may be freely expanded. Here, the memory capacity is the maximum amount of data that can be written to the memory.

  The hardware unit of the controller 4 includes an interface unit 6, memories 7A and 7B, processors P0 to PN, and a memory controller 9. The controller 4 is electrically connected to, for example, the non-volatile memory 5. In the present embodiment, a case where the controller 4 includes a plurality of processors P0 to PN will be described as an example, but the number of processors provided in the controller 4 can be freely changed to one or more.

  The interface unit 6 controls reception of data, information, signals, commands, messages, requests, commands and the like from an external device such as the information processing device 2 and controls transmission to the external device.

  The memory 7A is used as a working memory. The memory 7A stores, for example, a program to be processed by the processors P0 to PN, data, information, and the like. The memory 7A may be a volatile memory such as, for example, a dynamic random access memory (DRAM) or a static random access memory (SRAM), or may be a non-volatile memory.

  The memory 7B is, for example, a non-volatile memory. However, part of the memory 7B may be volatile memory. The memory 7B stores the address conversion data 10, the control program 11, and the programs F0 to FM. Even if part or all of the address conversion data 10, the control program 11, and the programs F0 to FM are stored in other memories such as the memories in the processors P0 to PN, the memory 7A, and the non-volatile memory 5 Good.

  In the example of FIG. 1, although the case where the controller 4 is equipped with several program F0-FM is demonstrated as an example, the number of the programs with which the controller 4 is equipped can be freely changed by 1 or more.

  The address conversion data 10 is data in which a logical address (for example, Logical Block Addressing (LBA)) of write data or read data and a physical address (for example, Physical Block Addressing (PBA)) are associated, for example, LUT (Look Up Table) ). The address conversion data 10 may have a data structure in a table format, or may have another data structure such as a list format.

  The software-defined platform according to the present embodiment includes a control program 11, a hardware unit of the controller 4, and a non-volatile memory 5. For example, when the memory device 3 is an SSD, the control program 11, the hardware unit of the controller 4, and the non-volatile memory 5 are software-defined SSD platforms (memory device platforms). By using a software-defined SSD platform, the functions of the SSD can be separated from hardware control and software controlled.

  In the present embodiment, the term “platform” refers to an aggregate of hardware, operating system (OS), middleware, combinations thereof, settings, environment, etc. as a basis required to operate hardware or software.

  The processors P0 to PN execute the control program 11 and the programs F0 to FM. The processors P0 to PN include management units C0 to CN, respectively. However, the processors P0 to PN and the management units C0 to CN may be separately configured. In the present embodiment, the processor P0 is a master's processor, and the processors P1 to PN are slave processors that operate dependent on the master. The processor P0 may include a function as a subordinate processor in the same manner as the processors P1 to PN in addition to the function as a master processor. For example, queues may be used as the management units C0 to CN, and the execution waiting tasks may be managed in a first-in first-out manner. However, the execution waiting tasks in the management units C0 to CN may be managed according to other criteria, such as high priority tasks being executed among the plurality of execution waiting tasks, for example.

  The control program 11 abstracts the hardware part. For example, abstraction of the hardware part is realized by conforming data, information, signals, commands, messages, requests, instructions, etc. exchanged between the programs F0 to FM and the control program 11. Ru. For example, the programs F0 to FM can use functions implemented by the control program 11 by issuing a command conforming to a specific interface to the control program 11. The control program 11 executes processing on the hardware unit in accordance with a command conforming to the specific interface issued by the program F0 to FM, or information conforming to the specific interface received from the program F0 to FM Convert to information in the format corresponding to the hardware part.

  In the present embodiment, the specific interface is, for example, a rule and procedure defined for one program to use the other program. More specifically, the specific interface calls, for example, a function of a certain program and data to be managed from another program, and a procedure and data format for using the called function and data to be managed, etc. It is a defined rule.

  The control program 11 implements basic operations between the programs F0 to FM and the hardware unit so that the programs F0 to FM become independent of the hardware unit such as the controller 4 of the memory device 3, It is a common module that absorbs differences in hardware. In the present embodiment, independence is at least a property that can continue to be used even if the other cooperating software or hardware is replaced. Therefore, the control program 11 conforms to an API (Application Programming Interface), a logical interface such as an LBA interface, and a physical interface such as an PBA interface. For example, the control program 11 can exchange data, information, signals, commands, messages, requests, instructions, and the like with a replaceable SSD module independent of the hardware unit using an API and a logical interface. For example, the modules 131 to 136 of FIG. 4 described later may be SSD modules.

  In the present embodiment, for example, the physical interface may be a hardware interface.

  In the present embodiment, for example, the logical interface may be a software interface, for example, logically configured on the physical interface, and used, for example, to add an address on the physical interface.

  For example, the control program 11 is issued by one of the programs F0 to FM according to a specific interface defined to receive commands, information, data, etc. when executed by the hardware part of the controller 4 In response to the command, the controller 4 includes a driver that executes control on the hardware unit of the controller 4 and the non-volatile memory 5 according to the command, and causes the hardware unit of the controller 4 to access the non-volatile memory 5.

  In addition, the control program 11 manages management information for the non-volatile memory 5, and when receiving an output command of management information issued by any of the programs F0 to FM according to a specific interface, Send to the output command issuer.

  Further, when control program 11 receives setting information for processing for nonvolatile memory 5 issued by any of programs F0 to FM according to a specific interface, processing for nonvolatile memory 5 according to the setting information Run.

  In the present embodiment, the programs F0 to FM may be freely combined.

  The control program 11 performs, for example, task scheduling. Thus, the processor P0 monitors the states of the management units C1 to CN provided in the processors P1 to PN, and the management unit C1 to CN having a small number of tasks waiting for tasks managed by the management unit C0. Allocate to one. The respective processors P1 to PN execute tasks managed by the management units C1 to CN.

  In the present embodiment, the storage position of the control program 11 in the memories 7A and 7B, the storage position of the programs F0 to FM, the position of the work area of the control program 11, and the position of the work area of each program F0 to FM It is determined at boot time and is not relocated during boot up. This eliminates the need for time for relocation, and can speed up the process.

  The programs F0 to FM can use the function of the control program 11 by using the API, and operate in cooperation with the control program 11. The programs F0 to FM are, for example, various software such as firmware, application programs, modules, or handlers. For example, a handler is a program that is activated when a processing request occurs. In the present embodiment, the programs F0 to FM will be described by taking the case of firmware as an example, but the types of the programs F0 to FM are not limited to this. In the present embodiment, the programs F0 to FM may be, for example, a program created by the user of the memory device 3 or a program created by the maker of the memory device 3.

  For example, the processors P0 to PN function as a reception unit 81, an address conversion unit 82, a writing unit 83, and a reading unit 84 by cooperation of the control program 11 and the programs F0 to FM.

  Since the programs F0 to FM and the control program 11 operate in cooperation with each other in the memory device 3, the software developer of the programs F0 to FM does not consider the programs F0 to FM without considering the hardware part of the memory device 3. Can be generated.

  The memory controller 9 controls access to the non-volatile memory 5.

  At the time of data writing, the information processing device 2 transmits a write command, write data, and a logical address indicating the write data to the memory device 3.

  The receiving unit 81 realized by the processors P0 to PN receives a write command, write data, and a logical address from the information processing device 2 via the interface unit 6.

  The address conversion unit 82 converts the logical address attached to the write command into the physical address of the non-volatile memory 5 with respect to the address conversion data 10 when the reception unit 81 receives the write command. Relate.

  The writing unit 83 writes the write data to the position indicated by the physical address of the non-volatile memory 5 obtained by the address conversion unit 82 via the memory controller 9.

  At the time of data read, the information processing device 2 transmits a read command and a logical address indicating read data to the memory device 3.

  The receiving unit 81 receives a read command and a logical address from the information processing device 2 via the interface unit 6.

  When the receiving unit 81 receives a read command, the address conversion unit 82 converts the logical address attached to the read command into a physical address using the address conversion data 10.

  The reading unit 84 reads the read data from the position indicated by the physical address of the non-volatile memory 5 via the memory controller 9. Then, the reading unit 84 sends the read data to the information processing device 2 via the interface unit 6.

  FIG. 2 is a block diagram showing an example of the configuration of the control program 11 according to the present embodiment.

  The control program 11 conforms to the API. Therefore, the programs F0 to FM can use various functions of the control program 11. Here, the API is, for example, a specification used by a plurality of programs to exchange data, information, signals, commands, messages, requests, instructions, etc. with each other. The API includes, for example, specifications such as subroutines, data structures, object classes, and variables.

Also, the control program 11 conforms to the logical interface and the physical interface. Therefore, the memory device 3 can realize the same operation as a typical SSD. Here, the logical interface is, for example, a specification for handling a logical address with software. The physical interface is, for example, a specification for handling a physical address with hardware.
For example, the control program 11 includes an inter-module communication unit 111, a priority control unit 112, an interrupt handler 113, an access unit 114, an information management unit 115, a hardware driver 116, and a processing execution unit 117.

  The inter-module communication unit 111 transmits and receives, for example, data, information, signals, commands, messages, requests, instructions, etc. among various programs in accordance with a specific interface.

  The priority control unit 112 switches the programs F0 to FM to be executed, for example, according to the priorities of the programs F0 to FM. More specifically, the priority control unit 112 manages, for example, the priorities of the various programs F0 to FM in units of tasks, and prioritizes and executes tasks with high priorities.

  The interrupt handler 113 detects an interrupt event from any hardware or software of the memory device 3 and executes processing in accordance with the detected interrupt.

  The access unit 114 controls basic operations such as erasing, reading, and writing to the non-volatile memory 5.

  The information management unit 115 manages various management information 115 a for the non-volatile memory 5. For example, the information management unit 115 generates and manages management information 115 a including, for example, statistical information, tally information, control information, and the like. The management information 115 a managed by the information management unit 115 is at least information necessary for generating setting information 117 a used in the process for the non-volatile memory 5. The management information 115a includes, for example, the number of erases for each block of the NAND flash memory included in the non-volatile memory 5, the number of erases for each block, the number of reads for each page, the number of reads for each page, and the number of writes for each page Write frequency for each page, size of each block, number of pages in each block, size of each page, estimated writing speed, estimated writing delay time, estimated reading speed, estimated reading delay time, etc. Including one.

  When the information management unit 115 receives an output command of the management information 115a from any of the programs F0 to FM, the information management unit 115 sends the management information 115a to the issuer of the output command.

  The hardware driver 116 controls various hardware of the memory device 3. Examples of the hardware driver 116 include a driver that controls the interface unit 6, a driver that controls power, and a driver that controls a timer.

  When the process execution unit 117 receives the setting information 117a of the process for the non-volatile memory 5 from any of the programs F0 to FM, the process execution unit 117 executes the process for the non-volatile memory 5 according to the setting information 117a.

  For example, the setting information 117 a may be at least a parameter used in the process for the non-volatile memory 5. More specifically, for example, the setting information 117a may be garbage collection execution condition information, and the process execution unit 117 may execute garbage collection according to the garbage collection execution condition information. Further, for example, the setting information 117 a is write position information indicating what kind of data is to be written in which position of the nonvolatile memory 5, and the processing execution unit 117 performs data at a position indicated by the write position information in the nonvolatile memory 5. You may write

  FIG. 3 is a block diagram showing an example of a built-in state of the memory device 3 according to the present embodiment. In FIG. 3, although the case where the program F0 is incorporated is described as an example, the same applies to the case where another program such as the programs F1 to FM is incorporated.

  The maker of the memory device 3 generates the memory device 3. The memory device 3 initially includes a software-defined SSD platform including the control program 11, the hardware unit 4H of the controller 4, and the non-volatile memory 5. In the present embodiment, the memory device 3 may not initially include the program F0 such as firmware or an application program. Here, initial is, for example, at the time of product shipment, at the time of delivery, or at the time of sale. The memory device 3 may initially include a typical program or a standard program recommended by the manufacturer in cooperation with the software-defined SSD platform.

  In addition, the manufacturer provides or sells the software development apparatus 13 supporting the development of the program F0 to a third party such as a user, a customer, a purchaser of the memory device 3, or a software developer. In this embodiment, a case where a software developer uses the software development apparatus 13 will be described as an example.

  The software development device 13 includes an emulator of the non-volatile memory 5 and a simulator of the memory device 3. Thus, for example, even in a closed development environment in which the external network is physically isolated, the software developer can proceed with the development of the program F0 using the software development apparatus 13.

  The software development device 13 supports the development of the program F0 by the software developer. The software developer may be, for example, a user of the memory device 3 or a purchaser. In the present embodiment, the program F0 is, for example, a user-defined replaceable module, and is an upper layer module of the control program 11.

  Since the control program 11 conforms to the API and the logical interface, the software developer efficiently generates the program F0 according to the request of the user of the memory device 3 or the purchaser, and controls the program F0. Can work together.

  When the program F0 is generated, the user of the memory device 3, the purchaser, or the software developer incorporates the program F0 into the memory device 3.

  In the present embodiment, since the control program 11 is provided in the memory device 3, the program F0 can operate without being aware of the hardware unit 4H.

  The user or purchaser can easily implement and use the program F0 suitable for him / her in the memory device 3.

  In the present embodiment, a first interface or protocol is applied between the non-volatile memory 5 and the hardware 4H. A second interface or protocol is applied between the hardware 4H and the control program 11. A third interface or protocol is applied between programs F0 to FM and control program 11. Thus, even if at least a part of the non-volatile memory 5, the hardware 4H, the control program 11, and the programs F0 to FM is replaced, other software or hardware can be used continuously.

  FIG. 4 is a block diagram showing an example of the relationship between the components of the information processing system 1 according to the present embodiment.

  The memory device 3 supports the development of the replaceable SSD modules 131 to 137 mainly by providing two abstraction layers. The programs F0 to FM correspond to the replaceable SSD modules 133 to 136.

  The first abstraction layer includes a software defined SSD platform. The software-defined SSD platform includes a control program 11, a hardware unit 4H, and a non-volatile memory 5. The software-defined SSD platform is generated by, for example, the maker of the memory device 3 and implemented in the memory device 3. In the first abstraction layer, the non-volatile memory 5 includes, for example, a plurality of NAND flash memories B0 to BP.

  The second abstraction layer includes replaceable SSD modules 131-137. The second abstraction layer performs memory control on top. The replaceable SSD modules 131 to 136 can exchange data, information, signals, commands, messages, requests, instructions, and the like with the control program 11 using, for example, an API and a logical interface. In the second abstraction layer, the interrupt handler 137 can exchange data, information, signals, commands, messages, requests, instructions, etc. with the hardware unit 4 H without using the control program 11.

  In the second abstraction layer, the SSD module 131 and the new module 132 are, for example, generated by the manufacturer and incorporated into the memory device 3 as a standard SSD module or function.

  The modules 133 to 135, the driver module 136, and the interrupt handler 137 are generated by a third party such as a software developer and incorporated in the memory device 3.

  The SSD module 131, the new module 132, and the modules 133 to 135 communicate data, information, signals, commands, messages, requests with the drivers 141 to 145 provided in an external device such as the information processing apparatus 2 or the like. , And can exchange commands.

  The driver module 136 and the interrupt handler 137 can exchange data, information, signals, commands, messages, requests, commands, etc. with an external hardware unit 146 such as, for example, a network device, an imaging device, or a sensor. is there. The driver module 136 can control the external hardware unit 146. The interrupt handler 137 detects an interrupt event from the external hardware unit 146 or the hardware unit 4H, and executes processing corresponding to the detected interrupt on the hardware unit 4H or the external hardware unit 146.

  Furthermore, the modules 133 to 135 and the driver module 136 can exchange data, information, signals, commands, messages, requests, instructions and the like with the control program 11 in accordance with a specific interface.

  FIG. 5 is a flowchart showing an example of processing executed by the control program 11 and the hardware unit 4H according to the present embodiment.

  In step S501, the control program 11 receives an access command from any of the programs F0 to FM in accordance with a specific interface. For example, the control program 11 receives a write command, a logical address, and write data. For example, the control program 11 receives a read command and a logical address.

  In step S502, the control program 11 and the hardware unit 4H convert a logical address into a physical address in accordance with the access command, and write data to the non-volatile memory 5 or read data to be read. When the read data is read from the nonvolatile memory 5, the control program 11 sends the read data to the issuer of the read command.

  In step S 503, the control program 11 generates management information 115 a for the non-volatile memory 5.

  In step S504, the control program 11 receives an output command of the management information 115a from any of the programs F0 to FM in accordance with a specific interface.

  In step S505, the control program 11 sends the management information 115a to the issuer of the output command in accordance with the output command.

  In step S506, the control program 11 receives a process execution command and setting information 117a from any of the programs F0 to FM according to a specific interface.

  In step S507, the control program 11 and the hardware unit 4H execute the process for the non-volatile memory 5 in accordance with the process execution command and the setting information 117a.

  In the embodiment described above, programs F0 to FM, replaceable SSD modules 131 to 136 are generated without depending on the hardware unit 4H of the memory device 3, and programs F0 to FM, replaceable SSD modules 131 to 131 are generated. The memory device 3 can be used by incorporating the memory device 136 into the memory device 3.

  Thereby, the convenience of the memory device 3 can be improved.

  In the present embodiment, even if the hardware unit 4H of the memory device 3 is changed or upgraded, the programs F0 to FM and the replaceable SSD modules 131 to 136 are continuously used in the new memory device 3. It is possible.

  The programs F0 to FM and the replaceable SSD modules 131 to 136 can be developed without being aware of the hardware unit 4H of the memory device 3.

  The user or purchaser of the memory device 3 continues the previously generated programs F0 to FM and replaceable SSD modules 131 to 136 with the new memory device 3 even if the new memory device 3 is introduced. Can be used.

  Therefore, in the present embodiment, the effort, cost, and time for development, maintenance, and maintenance of the memory device 3 can be reduced, and the development work can be streamlined.

  In this embodiment, the user or purchaser of the memory device 3 can use the programs F0 to FM and the replaceable SSD modules 131 to 137 suitable for the user. Therefore, the user can easily introduce his / her know-how into the operation of the memory device 3.

  In the present embodiment, the manufacturer of the memory device 3 can mass-produce and sell the memory device 3.

  In the present embodiment, the user independently develops programs F0 to FM such as firmware or application programs, etc., replaceable SSD modules 131 to 137 independently, and programs F0 to FM, replaceable SSD modules 131 to memory device 3. 137 can be easily implemented.

  In the present embodiment, the external hardware unit 146 such as a network device, an imaging device, or a sensor is easily connected to the memory device 3, and the data received from the external hardware unit 146 is written to the non-volatile memory 5. Can. In other words, in the present embodiment, when the memory device 3 includes the driver module 136, the memory device 3 can easily implement a communication interface with the external hardware unit 146. Therefore, the memory device 3 according to the present embodiment is suitable for, for example, the IoT (Internet of Things).

  In the present embodiment, for example, the maker of the memory device 3 can select one of the control program 11, the hardware unit 4H, and the software development device 13 cheaply or without charge for the user who purchases and uses the non-volatile memory 5 of his company. Provide at least one. Thereby, the maker of the memory device 3 can promote the sales of its own nonvolatile memory 5.

  In this embodiment, even before selling or delivering the memory device 3, the software developer can use the software development device 13 to generate the programs F0 to FM and the replaceable SSD modules 131 to 137. In this embodiment, the maker of the memory device 3 can quickly sell or deliver the memory device 3 without developing a program specific to the user or the purchaser. Therefore, the period from the manufacture of the memory device 3 to the delivery of the memory device 3 to the user or the purchaser can be shortened.

  The user of the memory device 3 or the purchaser can freely change the garbage collection execution conditions, delete the garbage collection, and decide what data should be written to which position in the non-volatile memory 5. The lifetime of the non-volatile memory 5 can be extended according to its own use mode.

  In the present embodiment, the storage position of the control program 11, the storage position of the programs F0 to FM, the position of the work area of the control program 11, and the position of the work area of each program F0 to FM are determined when the memory device 3 is started. And then not relocated during operation. Thus, the operation of the memory device 3 can be speeded up without the need for relocation of programs and data.

  In the present embodiment, even if at least a part of the non-volatile memory 5, the hardware unit 4H, the control program 11, the programs F0 to FM, and the replaceable SSD modules 131 to 137 is replaced, other software or hardware Is still available. For example, even if the generation of the non-volatile memory 5 is changed due to the development of the non-volatile memory 5, the existing programs F0 to FM, the replaceable SSD modules 131 to 137, and the hardware unit of the controller 4 4H and the control program 11 can be reused.

Second Embodiment
In the present embodiment, a modification of the information processing system 1 described in the first embodiment will be described.

  In the present embodiment, the memory device 3 assigns a virtual memory device (virtual SSD) to each virtual machine.

  FIG. 6 is a block diagram showing an example of the relationship between components of the information processing system according to the present embodiment.

  An information processing system 1A according to the present embodiment includes a memory device 3 and virtual machines VM0 to VMP.

  The memory device 3 has a large memory capacity. The memory device 3 includes virtual memory devices VS0 to VSP, a control program 11, and NAND flash memories B0 to BP. The NAND flash memories B0 to BP correspond to the non-volatile memory 5 of FIG.

  The virtual memory devices VS0 to VSP are associated with virtual machines VM0 to VMP, respectively. The respective virtual memory devices VS0 to VSP can operate independently of one another, thereby achieving stable performance.

  The control program 11 can operate according to a standard command set (Common Command Set). The control program 11 cooperates with the plurality of virtual memory devices VS0 to VSP in the memory device 3. The control program 11 individually changes and manages the parameters of each of the virtual memory devices VS0 to VSP.

  For example, the control program 11 changes the memory capacity, the setting of garbage collection, the setting of over provisioning, the setting of memory granularity, the degree of reliability (error correction capability) for each of the virtual memory devices VS0 to VSP. It is possible. Here, the garbage collection is a function of automatically releasing an unnecessary area in the memory area dynamically allocated by the program. Over-providing means securing a spare area. The granularity of memory means, for example, the size of a block and a page of NAND flash memory, the size of a sector such as hard disk sector, the size of a unit to write, the size of a unit to read, and the size of a unit to erase Do.

  The control program 11 can appropriately change the number of each of the virtual memory devices VS0 to VSP and the memory capacity of each of the virtual memory devices VS0 to VSP.

  The control program 11 comprises different software ports for each of the virtual memory devices VS0 to VSP. The control program 11 assigns NAND flash memories B0 to BP to the virtual memory devices VS0 to VSP. For example, the control program 11 manages the NAND flash memories B0 to BP allocated to the respective virtual memory devices VS0 to VSP by using the namespaces corresponding to the respective virtual memory devices VS0 to VSP. In other words, the non-volatile memory 5 is divided into a plurality of namespaces, and each of the virtual memory devices VS0 to VSP is associated with the namespace corresponding to itself.

  In the present embodiment, the namespace is a memory space obtained by dividing a plurality of blocks included in the non-volatile memory 5. By assigning a name space to each of the virtual memory devices VS0 to VSP, identification information of the name space and the logical address are used even if logical addresses overlap in at least two virtual memory devices of the virtual memory devices VS0 to VSP. And can be used to access the appropriate data.

  In the embodiment described above, one memory device 3 can be treated as a plurality of virtual memory devices VS0 to VSP, and the convenience of the memory device 3 can be further improved.

  In this embodiment, the virtual memory devices VS0 to VSP access the NAND flash memories B0 to BP to manage allocation of the NAND flash memories B0 to BP to the virtual memory devices VS0 to VSP using a name space. Accuracy can be improved.

  In the present embodiment, since the respective virtual memory devices VS0 to VSP can operate independently of each other, stable performance can be realized.

Third Embodiment
This embodiment is a modification of the first and second embodiments, and describes a memory device that controls a plurality of processors by a control program 11 including a scheduler.

  FIG. 7 is a block diagram showing an example of the relationship between the components of the memory device 3 according to the present embodiment. In FIG. 7, the control program 11, the modules 131 to 136, and the interrupt handler 137 are software. The drivers 141 to 145 and the external hardware unit 146 are hardware.

  The memory device 3 includes a control program 11, a hardware unit 4H, and a plurality of NAND flash memories B0 to BP. Hardware unit 4H includes a plurality of processors P1 to PN and a memory 7A.

  The control program 11 includes a function as the scheduler 15. The scheduler 15 may be realized by hardware.

  The memory 7A is shared by a plurality of processors P1 to PN. One of the processors P1 to PN stores data, information, signals, commands, messages, requests, instructions in the memory 7A, and another processor of the processors P1 to PN receives data, information, signals, commands, or the like from the memory 7A. Data, information, signals, commands, messages, requests, instructions can be exchanged between the processors P1 to PN by reading out messages, requests, and instructions.

  For example, data, information, signals, commands, messages, requests, commands can be exchanged between the modules 131 to 136 and the control program 11 by a standardized specific interface.

  For example, between the SSD modules 131 to 136, and the drivers 141 to 145 and the external hardware unit 146 provided in the external device, data, information, signals, commands, messages, requests, commands can be transmitted by using a unique interface. It can be exchanged. The external hardware unit 146 may be, for example, an external memory device for the memory device 3 or an external NAND flash memory.

  For example, the plurality of NAND flash memories B0 to BP are generated by the maker of the nonvolatile memory 5.

  For example, the hardware unit 4 H is generated by the manufacturer of the controller 4.

  For example, the control program 11 is generated by the maker of the non-volatile memory 5, the maker of the controller 4, or the first software developer.

  For example, the modules 131 and 132 are generated by the maker of the non-volatile memory 5, the maker of the controller 4, or the first software developer.

  For example, modules 133-135, driver module 136, and interrupt handler 137 are generated by a second software developer.

  In the present embodiment, for example, the scheduler 15 dynamically determines which processor is to execute which task. In other words, the scheduler 15 includes, for example, a dynamic task scheduler.

  Hereinafter, an example of control by the control program 11 according to the present embodiment will be described.

FIG. 8 is a block diagram showing an example of the relationship between the processors P0 to P2 and the memory 7A according to the present embodiment. Although FIG. 8 illustrates the case of three processors as an example to simplify the description, the same applies to the case of four or more processors. If the master processor P0 also includes a function as a dependent processor, the number of processors may be two or more.

  The processors P0 to P2 respectively include management units C0 to C2 and schedulers 150 to 152. The processors P0 to P2 control the other hardware of the hardware unit 4H, thereby controlling writing of write data to the non-volatile memory 5, reading of read data, and erasing of the written data.

  The management unit C0 corresponds to the processor P0, and can manage a plurality of execution waiting processes and their execution orders.

  The management unit C1 can manage the execution waiting process executed by the processor P1 and the execution order thereof.

  The management unit C2 can manage the execution waiting process executed by the processor P2 and the execution order thereof.

  In the present embodiment, the maximum number of tasks manageable by the management units C1 and C2 is two, but may be three or more.

  The scheduler 15 includes a scheduler 150 that performs scheduling in the processor P0, a scheduler 151 that performs scheduling in the processor P1, and a scheduler 152 that performs scheduling in the processor P2. However, the scheduler 15 may operate centrally on, for example, the processor P0 without being distributed.

  The scheduler 150 is a master scheduler, and schedules the execution waiting tasks of the management unit C0 so that the loads of the dependent processors P1 and P2 or the number of execution waiting tasks in the management units C1 and C2 are equalized. Allocate to 151,152.

  The schedulers 151 and 152 are subordinate schedulers and shorten the processing time and delay time of the processors P1 and P2.

  The schedulers 151 and 152 obtain the number of tasks of the management units C1 and C2, respectively.

  The scheduler 151 determines whether the number of execution waiting tasks managed by the management unit C <b> 1 is equal to or less than a first threshold, and sends the determination result to the master scheduler 150.

  The scheduler 152 determines whether the number of execution waiting tasks managed by the management unit C 2 is less than or equal to a second threshold, and sends the determination result to the master scheduler 150.

  The scheduler 150 notifies the scheduler 151 of the execution waiting tasks managed by the management unit C0 when the number of execution waiting tasks managed by the management unit C1 is equal to or less than the first threshold. The scheduler 151 manages the task waiting for execution notified from the scheduler 150 in the management unit C1.

  The scheduler 150 notifies the scheduler 152 of the execution waiting tasks managed by the management unit C0 when the number of execution waiting tasks managed by the management unit C2 is equal to or less than the second threshold. The scheduler 152 manages the task waiting for execution notified from the scheduler 150 in the management unit C2.

  In the present embodiment, the scheduler 150 stores, in the memory 7A, the task identification information for identifying the task waiting for execution and the priority information 16 in which the execution priority of the task waiting for execution is associated.

  When changing the management destination of the task waiting for execution from the managing unit C0 to the managing unit C1 or the managing unit C2, the scheduler 150 refers to the priority information 16 and executes the high priority managed by the managing unit C0. Determine the waiting task as the task whose management destination is to be changed. More specifically, for example, the scheduler 150 may determine the highest priority pending task as the task whose management destination is to be changed. For example, among the execution waiting tasks managed by the management unit C0, the scheduler 150 determines any one of the execution waiting tasks belonging to the higher priority group as the task whose management destination is to be changed. It is also good. For example, when the managing unit C0 manages an execution waiting task whose priority is a predetermined value or more, the scheduler 150 sets an execution waiting task whose priority is a predetermined value or more as a task whose management destination is changed. If it is determined and the execution waiting task whose priority is equal to or higher than a predetermined value is not managed by the management unit C0, the task whose management destination is to be changed may be determined according to the first-in first-out method.

  In the following, the same processes in the processors P1 and P2 will be described using the processor P1, and the description of the processor P2 will be omitted or briefly described.

  The scheduler 151 executes the next task managed by the management unit C1 when the processor P1 finishes executing the task.

  The scheduler 151 refers to the priority information 16 when executing the next task managed by the management unit C1, and then executes the high priority execution waiting task managed by the management unit C1 next. Decide as a task. More specifically, for example, the scheduler 151 may determine the task with the highest priority as the task to be executed next. For example, the scheduler 151 may determine, among the tasks managed by the management unit C1, any one of the tasks belonging to the higher priority group as the task to be executed next. For example, when the management unit C1 manages a task having a priority equal to or higher than a predetermined value, the scheduler 151 determines a task having a priority equal to or higher than a predetermined value as a task to be executed next. When a task having a priority equal to or higher than a predetermined value is not managed in C1, the task to be executed next may be determined according to the first-in first-out method.

  The scheduler 151 sends, to the scheduler 150, task end information indicating that the task execution has ended when the processor P1 completes the task execution. The scheduler 150 determines the task whose management destination is to be changed when the execution waiting task is managed by the management unit C0, and notifies the scheduler 151 which has issued the task end information of the task whose management destination is to be changed. The scheduler 151 manages the task notified from the scheduler 150 in the management unit C1.

  Scheduler 151 notifies a new task to the scheduler corresponding to one processor when a new task to be started next to the task executed by processor P1 is executed by one of processors P1 and P2 You may. In this case, the scheduler corresponding to one processor causes the managing unit corresponding to one processor to manage a new task.

  The scheduler 151 notifies the new task to the scheduler 150 corresponding to the processor P0 when the new task to be started next to the task executed by the processor P1 can be executed by either of the processors P1 and P2. It is also good. In this case, the scheduler 150 causes the management unit C0 to manage a new task.

  The scheduler 151 can execute a new task to be started next to the task executed by the processor P1 by either of the processors P1 and P2, and the number of tasks managed by the management unit C1 is the first. If it is below the threshold value, the new task may be notified to the scheduler 151 corresponding to the processor P1. In this case, the scheduler 151 causes the management unit C1 to manage a new task.

  The scheduler 151 can execute a new task to be started next to the task executed by the processor P1 by either of the processors P1 and P2, and the second number of tasks managed by the management unit C2 is If it is below the threshold value, the new task may be notified to the scheduler 152 corresponding to the processor P2. In this case, the scheduler 152 causes the management unit C2 to manage a new task.

  The scheduler 151 can execute a new task to be activated next to the task executed by the processor P1 by either of the processors P1 and P2, and the number of tasks managed by the management units C2 and C3 is If it is greater than the one threshold and the second threshold, the new task may be notified to the scheduler 150 corresponding to the processor P0. In this case, the scheduler 150 causes the management unit C0 to manage a new task.

  The tasks executed by the processors P1 and P2 do not include waiting tasks for accessing the hardware unit 4H. For example, the waiting task may be a task waiting for a certain event to occur. In this case, when execution of a task is started in the processors P1 and P2, interruption does not occur except in the case where exception processing occurs in response to an interrupt or the like in the processors P1 and P2.

  The control program 11 controls the memory 7A required for all tasks at the time of activation of the memory device 3 or before the tasks managed by the management units C1 and C2 are executed by the processors P1 and P2. Allocate a memory area 20.

  The control program 11 stores area information 17 in which the task to be executed is associated with the memory area 20 allocated to the task in the memory 7A. The control program 11 refers to the area information 17 and determines a memory area 20 to be used when executing a task.

  When stopping at least one of the processors P1 and P2, the control program 11 stops changing the management destination of the task from the management unit C0 corresponding to the processor P0 to the management unit corresponding to the processor to be stopped. The management destination of the task is changed from the management unit C0 corresponding to the processor P0 to the management unit corresponding to the unstopped processor. For example, the processor is shut down by shutting off the power supply.

  When the processor P1 receives an interrupt, the control program 11 manages the task following the interrupt in the management unit C1 corresponding to the processor P1.

  The control program 11 is hardware identification information for identifying a task and a part of the hardware unit 4H used in the execution of the task when the task needs to be executed by a part of the hardware unit 4H. And hardware information 19 associated with each other in the memory 7A. The control program 11 refers to the hardware information 19 and determines a hardware unit to be used for execution of the task when executing the task. Then, the control program 11 manages the task in the management unit corresponding to the determined hardware unit. Specifically, when the control program 11 receives an access request and hardware identification information from the information processing device 2, the control program 11 stores hardware information 19 in which a task corresponding to the access request is associated with hardware identification information. Store in 9 When executing a task corresponding to the access request, the control program 11 manages the task by a management unit corresponding to the processor indicated by the hardware identification information.

  FIG. 9 is a flowchart showing an example of the first process of the scheduler 15 according to the present embodiment. FIG. 9 exemplifies processing until the management destination of the task is changed from the management unit C0 to the management unit C1. However, the processing until the management destination of the task is changed from the management unit C0 to another management unit such as the management unit C2 is the same.

  In step S901, the scheduler 15 manages tasks in the management unit C0.

  In step S902, the scheduler 15 determines whether the number of tasks managed by the management unit C1 is equal to or less than a first threshold.

  If the number of tasks managed by the management unit C1 is not equal to or less than the first threshold, the process proceeds to step S905.

  When the number of tasks managed by the management unit C1 is equal to or less than the first threshold, the scheduler 15 refers to the priority information 16 in step S903 and changes the management destination from the management unit C0 to the management unit C1. Select the task to be

  In step S904, the scheduler 15 changes the management destination of the selected task to the management unit C1.

  In step S905, the scheduler 15 shifts the processing to step S901 when the processing is continued, and ends the processing when the processing is not continued.

  FIG. 10 is a flowchart showing an example of the second process of the scheduler 15. FIG. 10 exemplifies a process until a new task activated next to the executed task is assigned to any of the management units C0 to C2.

  In step S1001, the scheduler 15 determines whether a new task activated next to the executed task is executed by the processor P1, executed by the processor P2, or executable by either of the processors P1 and P2, To judge.

  When the execution destination of the new task is the processor P1, in step S1002, the scheduler 15 manages the new task by the management unit C1.

  If the execution destination of the new task is the processor P2, in step S1003, the scheduler 15 manages the new task by the management unit C2.

  When the execution destination of the new task can be either of the processors P1 and P2, in step S1004, the scheduler 15 manages the new task by the management unit C0.

  FIG. 11 is a block diagram showing an example of a notification state of area information between tasks according to the present embodiment.

  The first task T1 is executed by one of the processors P1 and P2. The memory area 181 is a memory area used in the first task T1.

  The second task T2 is executed by one of the processors P1 and P2.

  The second task T2 uses a part or all of the memory area 181 used in the first task T1. In this case, the first task T1 notifies the second task T2 of the area information of the memory area 181. The area information includes, for example, position information of the memory area 181.

  The notification of the area information from the first task T1 to the second task T2 may be executed when the memory device 3 is powered on and the memory area 181 is assigned to the task T1. The notification of the area information from the first task T1 to the second task T2 may be executed by activation of the second task T2.

  In the present embodiment, the control program 11 does not allocate the memory area corresponding to the task to another task even when the execution of the task is completed. In addition, when the same task is re-executed after completion of task execution, the same memory area is reused.

  The task may be a boot program task. In this case, one of the management units C0 to C2 of the processors P0 to P2 manages the task of executing the power on process based on the power on of the memory device 3.

  At least one of the hardware unit 4H and the control program 11 may perform error detection. If an error is detected, the task of executing the error correction process is managed by any of the management units C0 to C2 of the processors P0 to P2.

  In the present embodiment, the control program 11 of the memory device 3 performs memory information such as the number of times of erasing for each block of the NAND flash memory B0 to BP, the number of pages in the block, the block size, the page size, etc. It may be sent to 136 or the like.

  When the control program 11 receives an allocation request or release request of the NAND flash memories B0 to BP from the task, the control program 11 executes an allocation process or release process, and the NAND flash allocated or released for the task The blocks in the memories B0 to BP may be notified to the task.

  FIG. 12 is a block diagram showing an example of the relationship between tasks and memory areas according to the present embodiment.

  At least one of the tasks T1 to T3 may receive requests from other tasks.

  When the task T1 is executed, the task T1 sends a request and identification information of the task T1 that has issued the request to a task T2 executed after the task T1. Further, the task T1 stores the information obtained by the execution in the memory area 181 corresponding to the task T1 or stores the information obtained in the execution in the memory area 182 corresponding to the task T2.

  The task T2 is executed using the information stored in the memory area 181 or the information stored in the memory area 182. Then, the task T2 sends a request and identification information of the task T2 that has issued the request to a task T3 to be executed after the task T2. In addition, the task T2 stores the information obtained by the execution in the memory area 182 corresponding to the task T2 or stores the information obtained in the execution in the memory area 183 corresponding to the task T3.

  For example, when the task T2 receives requests from a plurality of other tasks, the task T1 sends, to the task T2, the identification information of the task T1 that has issued the request and the identification information of the task T3 executed after the task T2. . The task T2 is executed using the information of the memory area 181 corresponding to the task T1 or the memory area 183 corresponding to the task T3. Then, the task T2 stores the information obtained by the execution in the memory area 181 corresponding to the task T1 or the memory area 183 corresponding to the task T3.

  For example, when the task T2 receives requests from a plurality of other tasks, the task T1 sends, to the task T2, the identification information of the task T1 that has issued the request and the identification information of the task T3 executed after the task T2. . The task T2 is executed using the information of the memory area 181 corresponding to the task T1. Then, the task T2 stores the information obtained by the execution in the memory area 183 corresponding to the task T3.

  When the control program 11 receives a command and identification information of a subsequent process from the information processing device 2, the control program 11 may execute the task indicated by the identification information of the subsequent process after the command is executed. As a result, after executing processing according to the same command, it is possible to switch the subsequent processing.

  For example, the hardware unit 4H of the memory device 3 may be divided into a plurality of parts, and the identification information of the subsequent process may indicate a part of the hardware unit 4H.

  The identification information of the subsequent process may be a queue number of a command queue managed in the memory device 3.

  In the embodiment described above, a memory sharing type parallel computing method (Symmetric Multiprocessing) in which the physical memory is shared and managed in the memory device 3 is adopted.

  In the present embodiment, scheduling of the modules 131 to 136 can be performed automatically.

  In the present embodiment, the external device and the external hardware unit 136 can be easily applied to the memory device 3.

  In the present embodiment, the plurality of processors P1 to PN of the memory device 3 can be efficiently used, and the performance of the memory device 3 can be improved.

  In the present embodiment, the second software developer can develop modules 133 to 136 without being aware of task scheduling.

  In this embodiment, when a task is executed, no interruption occurs until the execution of the task is completed. In the present embodiment, exchange of data or information does not occur between the processors P1 and P2 until the processing is completed. In the present embodiment, the execution order of tasks can be switched until the start of task execution, but the task execution order is not reversed after task execution is started. In the present embodiment, for example, execution of a task is not interrupted except when receiving an interrupt from the interrupt handler 137. Therefore, in the present embodiment, execution of task switching can be reduced during task execution, and processing can be speeded up. Also, in the present embodiment, the total execution time of tasks does not change, and only the execution waiting time changes. Therefore, the delay time generated in the memory device 3 can be stabilized.

  In the present embodiment, the dynamic allocation of the memory 7A is performed when the memory device 3 is started, and the allocation is not changed when switching tasks. In this embodiment, the shared memory 7A is used to exchange information between related tasks, and memory protection is not implemented between tasks. In the present embodiment, each task refers to a corresponding memory area. In the present embodiment, it is possible to reduce the number of occurrences and the occurrence frequency of task interruptions. Therefore, in the present embodiment, the delay time due to task switching can be reduced.

  In this embodiment, common software can be used by a plurality of controllers 4, and software update and function addition are easy.

Fourth Embodiment
In this embodiment, detailed configurations of the information processing systems 1 and 1A described in the first to third embodiments will be described.

  FIG. 13 is a block diagram showing an example of a detailed configuration of the information processing system according to the present embodiment.

  The information processing system 1B includes an information processing device 2 and a memory system 3B.

  The memory system 3B according to the present embodiment can execute the programs F0 to FM and the control program 11.

  The memory device 3 according to the first to third embodiments corresponds to a memory system 3B.

  The processors P0 to PN of the memory device 3 correspond to central processing units (CPUs) 43A and 43B.

  The interface unit 6 corresponds to the host interface 41 and the host interface controller 42.

  The memories 7A and 7B correspond to the DRAM 47.

  The address conversion data 10 corresponds to the LUT 45.

  The memory controller 9 corresponds to a NAND controller (NAND controller) 50.

  The information processing device 2 functions as a host device of the memory system 3B.

  The controller 4 of the memory system 3B includes a front end 4F and a back end 4B.

  The front end (host communication unit) 4F includes a host interface 41, a host interface controller 42, an encryption / decryption unit (Advanced Encryption Standard (AES)) 44, and a CPU 43F.

  The host interface 41 communicates requests (write command, read command, erase command, etc.), LBA, data, etc. with the information processing apparatus 2.

  The host interface controller (control unit) 42 controls the communication of the host interface 41 according to the control of the CPU 43F.

  The encryption / decryption unit 44 encrypts the write data (plaintext) transmitted from the host interface controller 42 in the data write operation. The encryption / decryption unit 44 decrypts the encrypted read data transmitted from the read buffer RB of the back end 4B in the data read operation. Note that it is also possible to transmit the write data and the read data without passing through the encryption / decryption unit 44 as necessary.

  The CPU 43F controls the respective configurations 41, 42, and 44 of the front end 4F to control the overall operation of the front end 4F.

  The back end (memory communication unit) 4B includes a write buffer WB, read buffer RB, LUT 45, DDRC 46, DRAM 47, DMAC 48, ECC 49, randomizer RZ, NANDC 50, and CPU 43B.

  The write buffer (write data transfer unit) WB temporarily stores the write data transmitted from the information processing device 2. Specifically, the write buffer WB temporarily stores data until the write data has a predetermined data size suitable for the nonvolatile memory 5.

  The read buffer (read data transfer unit) RB temporarily stores read data read from the non-volatile memory 5. Specifically, in the read buffer RB, the read data is rearranged in the order suitable for the information processing device 2 (the order of the logical address LBA designated by the information processing device 2).

  The LUT 45 is a table for converting the logical address LBA into the physical address PBA.

  The DDRC 46 controls double data rate (DDR) in the DRAM 47.

  The DRAM 47 is, for example, a volatile memory that stores the LUT 45.

  A DMAC (Direct Memory Access Controller) 48 transfers write data, read data, etc. via the internal bus IB. Although one DMAC 48 is illustrated in FIG. 13, the controller 4 may include two or more DMACs 48. The DMAC 48 is set at various positions in the controller 4 as needed.

  The ECC 49 adds an ECC (Error Correcting Code) to the write data transmitted from the write buffer WB. The ECC 49 corrects the read data read from the non-volatile memory 5 as necessary, using the added ECC when transmitting to the read buffer RB.

  The randomizer RZ (or Scrambler) distributes the write data so that the write data is not biased in the direction of a specific page or word line of the nonvolatile memory 5 during the data write operation. As described above, by distributing the write data, the number of times of writing can be equalized, and the cell life of the memory cell MC of the non-volatile memory 5 can be prolonged. Therefore, the reliability of the non-volatile memory 5 can be improved. In addition, the randomizer RZ executes reverse processing of the randomizing processing at the time of writing to restore the original data at the time of the data read operation.

  The NANDC 50 accesses the non-volatile memory 5 in parallel using a plurality of channels (here, four channels CH0 to CH3) in order to satisfy the predetermined speed requirement.

  The CPU 43B controls the above-described configurations (45 to 50, RZ) of the back end 4B, and controls the overall operation of the back end 4B.

  In addition, the structure of the controller 4 shown in FIG. 13 is an illustration, It is not limited to this structure.

  FIG. 14 is a perspective view showing an example of a storage system according to the present embodiment.

  The storage system 100 includes a memory system 3B as an SSD.

  The memory system 3B is, for example, a relatively small module. The size and dimensions of the memory system 3B can be appropriately changed to various sizes.

  In addition, the memory system 3B can be used by being attached to the information processing apparatus 2 such as a server in, for example, a data center or cloud computing system operated by a company (enterprise). Therefore, the memory system 3B may be an enterprise use SSD (eSSD).

  The memory system 3B includes, for example, a plurality of connectors (for example, slots) 101 opened upward.

  The plurality of memory systems 3B are respectively attached to the connectors 101 of the information processing device 2, and are supported side by side in a substantially upright posture. According to such a configuration, the plurality of memory systems 3B can be mounted compactly and mounted, and the memory system 3B can be miniaturized. Furthermore, each shape of the memory system 3B according to the present embodiment is a 2.5-type small form factor (SFF). With such a shape, the memory system 3B can have a compatible shape (compatible shape) with the enterprise HDD (eHDD), and can realize easy system compatibility with the eHDD.

  The memory system 3B is not limited to the one for enterprise. For example, the memory system 3B is also applicable as a storage medium of a consumer electronic device such as a notebook portable computer or a tablet terminal.

  As described above, in the information processing system 1B and the storage system 100 having the configuration described in this embodiment, the same effects as those of the first to third embodiments can be obtained for large-capacity storage. .

Fifth Embodiment
In this embodiment, modified examples or specific examples of the first to fourth embodiments will be described.

  In the present embodiment, the functions of the software-defined SSD platform will be described.

  The software-defined SSD platform according to the present embodiment is, for example, an OS portable to a controller provided with a plurality of processors, and realizes parallel processing.

  The software defined SSD platform is generated, for example, in accordance with a unified Flash Translation Layer (FTL) design. More specifically, the software-defined SSD platform includes, in order from top to bottom, a common interface layer, an FTL, and a device driver. The common interface layer provides a common interface to the program. The FTL which is a lower layer of the common interface layer performs overall management such as allocation of an area such as a block to non-volatile memory, address conversion, wear leveling, garbage collection and the like. Here, the wear leveling is, for example, processing for evenly distributing data rewrite to the non-volatile semiconductor memory to extend the service life.

  In addition, the software defined SSD platform manages namespace allocation, size, number management and access control.

  Management by these software defined SSD platforms is performed according to management information.

  The software-defined SSD platform includes an automatic performance tuning function, a dynamic load balancing function, and a task scheduling function, and abstracts the hardware unit 4H.

  FIG. 15 is a block diagram showing an example of the configuration of the software defined platform according to the present embodiment.

  The program F is, for example, various software such as firmware, an application program, a module, or a handler. In the present embodiment, the program F will be described as an example of the SSD firmware, but the type of the program F is not limited to this.

  The program F is divided into a plurality of modules as tasks for each process content. For example, the program F may be divided into a host interface control unit Fa, a write control unit Fb, a read control unit Fc, or a module unit other than these. Furthermore, the program F may include, for example, an FTL unit and a wear leveling unit.

  A plurality of modules conform to an inter task communication API in order to communicate between tasks, and exchange data, information, signals, commands, messages, requests, commands.

  The software-defined platform includes a dynamic task scheduler 15D, a hardware abstraction layer (HAL) 301, a device driver 311, a hardware unit 4H, and a non-volatile memory 5.

  The dynamic task scheduler 15D controls the execution order of tasks. More specifically, the dynamic task scheduler 15D conforms to the HAL API, and exchanges data, information, signals, commands, messages, requests, commands with a plurality of modules and with the HAL 301. Do.

  The HAL 301 abstracts the hardware unit 4H. For example, the HAL 301 is implemented by software existing between the hardware unit 4H of the memory device and the device driver 311 and the program F operating on the memory device. The HAL 301 hides a difference that differs from hardware to the program F and the dynamic task scheduler 15D. More specifically, the HAL 301 includes the dynamic task scheduler 15D and the hardware unit 4H and the device driver 311 so that the program F and the dynamic task scheduler 15D become independent of the hardware unit 4H and the device driver 311. It is a common module that realizes the basic operation between them and absorbs the difference between the hardware units 4H. For example, when the specification change occurs in the hardware unit 4H or the device driver 311, only the HAL 301 may be corrected according to the specification change, and the program F and the dynamic task scheduler 15D are the specifications of the hardware unit 4H or the device driver 311 Not affected by changes.

  The device driver 311 is software for accessing the hardware unit 4H. The device driver 311 may include a plurality of device drivers, and includes, for example, a device driver 311 a for NAND flash, a device driver 311 b for peripheral devices, a device driver 311 c for host device, or other device drivers. The device driver 311 may be realized by hardware.

  The hardware unit 4H is hardware, and includes, for example, a device driver 311, a plurality of processors P1 to PN, and a memory 7A.

  As described above, in the software-defined SSD platform, access to the non-volatile memory 5 is performed hierarchically from the program F through the dynamic task scheduler 15D, the HAL 301, the device driver 311, and the hardware unit 4H.

  FIG. 16 is a diagram illustrating two types of scheduling implemented by the software defined SSD platform according to the present embodiment. In FIG. 16, the case where the number of processors accessible to the shared memory SM is four is illustrated. However, the number of processors accessible to the shared memory SM may be two or more. FIG. 16 exemplifies the case where the number of processors that can communicate in the interconnection network N is four. However, the number of processors that can communicate in the interconnection network N may be two or more.

  The software-defined SSD platform includes a dynamic task scheduler 15D and a static task scheduler 15S.

  The dynamic task scheduler 15D manages which one of a plurality of processors is assigned a task.

  The static task scheduler 15S manages the execution order of tasks assigned to each processor.

  Memories M0 to M8 correspond to processors P0 to P8, respectively, and are accessed by processors P0 to P8, respectively. The shared memory SM is accessible from a plurality of processors P0 to P3. The interconnection network N is a network for transmitting and receiving data, information, signals, commands, messages, requests, commands, and the like among the plurality of processors P5 to P8.

  In the first architecture, a shared memory platform is applied. In the first architecture, a plurality of processors P0 to P3 exchange data, information, signals, commands, messages, requests, instructions via the shared memory SM. The dynamic task scheduler 15D is responsible for assigning a task to which processor. The static task scheduler 15S determines, for each of the processors P0 to P3, a task to be executed next among assigned tasks.

  In the shared memory platform, any processor P0 to P3 can access the same shared memory SM. For this reason, the dynamic task scheduler 15D adjusts performance so that the load on each processor becomes constant by detecting low-load processors and allocating tasks.

  The second architecture includes a single processor P4 and a memory M4 corresponding to this processor P4. The static task scheduler 15S determines the next task to be executed by the processor P4.

  In the third architecture, a distributed memory platform is applied. In the third architecture, a plurality of processors P5 to P8 send and receive data, information, signals, commands, messages, requests, commands via the interconnection network N with one another. The static task scheduler 15S determines the task to be executed next for each of the processors P5 to P8.

  In the distributed memory platform, when each of the processors P5 to P8 executes a series of tasks (hereinafter referred to as a task chain), high-speed processing is possible by determining in advance the processor to be processed for each task according to the task content. Can be For example, when a large number of task chains that sequentially process a read task, a host communication task, and a write task are input, the processor P5 for read, the host communication is a processor P6 having a host communication interface, and the write is allocated for processor P7 .

  However, in the distributed memory platform, communication among the processors P5 to P8 is required. For example, the processor P5 that has executed the read task passes the processing result (including read data and the like) of the read task to the processor P6 that executes the host communication task. Here, if the communication time between the processors P5 to P8 is not sufficiently smaller than the processing time of the task, the processing may be delayed if the processor to be processed is separated for each task. In this case, processing is speeded up by allocating a certain number of tasks to a specific processor. That is, tasks belonging to the same task chain are allocated to the same processor to a certain extent (for example, a predetermined number) to prevent the execution of the task chain from being forwarded (for example, repeated) among a plurality of processors.

  In this embodiment, it is assumed that reading and writing do not occur simultaneously in execution of the task chain.

  In the present embodiment, as a rule for generating a task, for example, a global variable, a static variable, a heap memory, a function for dynamically securing a memory such as, for example, a mallock function and a free function are not used.

  As a rule for creating a task, for example, a queue for prioritizing is used without using a spin lock.

  As a rule for generating a task, for example, the hardware is not directly controlled.

  As a rule for generating a task, an automatic variable may be used, or a hardware accelerator may be used via the HAL 301. Here, the hardware accelerator is, for example, hardware added to accelerate processing of a computer.

  In the present embodiment, the dynamic task scheduler 15D performs low latency task switching together with the static task scheduler 15S.

  The tasks according to this embodiment are performed in an order prioritized cooperatively by each processor.

  The dynamic task scheduler 15D uses, for example, a lock-free algorithm. Unlike an algorithm that locks and protects shared data, the Lock-free algorithm is an algorithm that allows multiple tasks to read and write simultaneously without destroying certain target data.

  The dynamic task scheduler 15D performs, for example, run-to-completion scheduling. Run-to-completion scheduling is a scheduling model that causes a task to be executed until it completely ends or explicitly gives control to a scheduler.

  For example, message passing type inter-task communication is used for inter-task communication.

  In this embodiment, the master scheduler enables task porting, and performs dynamic load balancing and automatic performance tuning. The dependent scheduler reduces task switching latency.

  FIG. 17 is a diagram showing an example of parameters held in each layer of the memory device according to the present embodiment.

  As described above, the program F hierarchically accesses the NAND flash memories B0 to BP through the dynamic task scheduler 15D, the HAL 301, the device driver 311, and the hardware unit 4H. Here, the parameters held in each layer at the time of access may be the same parameter or may be written in a format different for each layer. Thereby, parameters can be held at an appropriate abstraction level for each hierarchy.

  For example, FIG. 17 exemplifies a description system in each hierarchy of the access delay time allowed in the access to the nonvolatile memory 5. Incidentally, by allowing a delay time in accessing the non-volatile memory 5, it is possible to take time in processing for data transmission and reception. For example, lengthening the error correction code reduces errors in reading and writing. be able to.

  The parameter P1701 indicates the access delay time held by the program F. In program F, for example, access delay time is 2 bits of information, and four types of delay times (do not tolerate delay, allow short delay, allow general delay, allow long delay) are defined. Ru. This access delay time may be defined by, for example, a standard.

  The parameter P1702 indicates the access delay time held by the HAL 301. In the HAL 301, for example, the access delay time is defined as 8-bit information. In this case, when the program F accesses the HAL 301, parameter conversion is performed. For example, if the program F is "00", it becomes 0 in the HAL 301, if it is "01" in the program F, it becomes any of 1 to 85 in the HAL 301, and if it is "10" in the program F, If the program F is "11", the HAL 301 is any of 171 to 255. The parameter P1701 in the program F is converted into an appropriate value on the HAL 301, for example, in relation to other parameters.

  The parameter P1703 indicates the access delay time held by the hardware unit 4H. In the hardware unit 4H, for example, the access delay time is defined as three types of parameters (presence or absence of the Direct Look Ahead (DLA) method, the number of times of repeated decoding, and a delay time threshold). The DLA method is a method of compensating in the read operation the influence of the shift of the threshold voltage due to the interference between memory cells. The possible values of each parameter may be, for example, 1 bit information of On or Off for the presence or absence of the DLA method, the number of times of repeated decoding is 1 to 5, the delay time threshold is 1 to 5, and so on. The hardware unit 4H may hold some combinations of these values as parameter sets. The parameter P1702 in the HAL 301 is converted into an appropriate parameter set or parameter set number on the hardware unit 4H in relation to other parameters and the like.

  In the present embodiment, the parameter P1701 is the program F, the parameter P1702 is the HAL 301, and the parameter P1703 is the hardware unit 4H, but the hierarchy in which the parameters are held may be a hierarchy different from these. For example, the parameter P1702 may be held in the NAND controller or the device driver 311a of the NAND flash, and the parameter P1703 may be held in the NAND flash memories B0 to BP.

  The operation of the task scheduler will be described using FIG. 18 to FIG. In the following FIGS. 18 to 21, an example will be described in which execution commands for instructing execution of respective tasks are managed by various queues. However, targets managed by various queues may be task bodies instead of execution commands.

  FIG. 18 is a flowchart showing an example of scheduling according to the present embodiment.

  FIG. 19 is a diagram illustrating a first example of scheduling according to the present embodiment, and illustrates an operation of S1801 in FIG.

  FIG. 20 is a diagram illustrating a second example of scheduling according to the present embodiment, and illustrates an operation of S1802 in FIG.

  FIG. 21 is a diagram illustrating a third example of scheduling according to the present embodiment, and illustrates an operation of S1803 in FIG.

  The hardware unit 4H includes a master processor Pm and subordinate processors PS1, PS2. Master processor Pm is associated with master queue MQ and dependent queue SQ0. The dependent processors PS1 and PS2 are associated with the dependent queues SQ1 and SQ2, respectively.

  The master queue MQ is managed by the dynamic task scheduler 15D.

  The dependent queues SQ0, SQ1, SQ2 are managed by the static task scheduler 15S.

  Tasks include portable tasks and dedicated tasks. The portable task can be executed by either the master processor Pm or the dependent processors PS1 and PS2. The dedicated task is a task that needs to be executed by a specific processor among the master processor Pm and the dependent processors PS1 and PS2.

  In step S1801, the dynamic task scheduler 15D stores the portable task execution command in the master queue MQ for load distribution of a plurality of processors.

  In the example of FIG. 19, the dependent processor PS1 and the dependent processor PS2 store the portable task execution commands CO1 to CO4 in the master queue MQ according to the dynamic task scheduler 15D.

  In step S1802, the dynamic task scheduler 15D corresponds to an execution command selected from among execution commands managed by the master queue MQ to a processor with a low load, so that all processing ends within a predetermined time. Pass to the static task scheduler 15S. The static task scheduler 15S stores the received execution command in the dependent queue. Specifically, the dynamic task scheduler 15D monitors the state of each processor Pm, PS1, PS2, and moves the portable task execution command to the dependent queue of the processor with the lowest processing load. For example, the dynamic task scheduler 15D may determine whether the amount (number) of task execution commands stored in each of the dependent queues SQ0, SQ1, SQ2 exceeds a predetermined amount. . If there is no processor with a low processing load, the dynamic task scheduler 15D may not move the task execution command.

  In the example of FIG. 20, the dynamic task scheduler 15D determines that the processing load of the master processor Pm, the dependent processor PS1 and the dependent processor PS2 is low, and among the execution commands CO1 to CO4 of the tasks held by the master queue MQ, The execution command CO3 is moved to the dependent queue SQ0, the execution command CO1 for the task is moved to the dependent queue SQ1, and the execution command CO2 for the task is moved to the dependent queue SQ2.

  In step S1803, the dynamic task scheduler 15D directly passes the execution command of the dedicated task to the static task scheduler 15S of the processor corresponding to the dedicated task, and the static task scheduler 15S stores the received execution command in the dependent queue. Do.

  In the example of FIG. 21, the master processor Pm and the dependent processor PS1 pass the execution commands CO5 and CO6 of the dedicated task of the dependent processor PS1 to the static task scheduler 15S according to the dynamic task scheduler 15D, and the static task scheduler 15S is dedicated The task execution commands CO5 and CO6 are stored in the dependent queue SQ1. Further, the dependent processor PS2 passes the execution command CO7 of the dedicated task of the master processor Pm to the static task scheduler 15S according to the dynamic task scheduler 15D, and the static task scheduler 15S transfers the execution command CO7 of the dedicated task to the dependency queue SQ0. Store.

  In step S1804, the static task scheduler 15S manages the execution order of the portable task execution command or dedicated task execution command stored in each dependent queue, for example, the execution command to be executed according to the first-in first-out method select. That is, the static task scheduler 15S selects an execution command at the top of the queue as a processing target, and deletes the execution command that is the processing target from the queue.

  In step S1805, the static task scheduler 15S determines whether the execution command of the next task generated as a result of execution is an execution command of the portable task.

  If the execution command for the next task is a portable task execution command, in step S1806, the static task scheduler 15S passes the execution command for the next task to the dynamic task scheduler 15D, and the dynamic task scheduler 15D receives the execution command. Store the executed command in the master queue MQ.

  If the execution command of the next task is a dedicated task execution command, in step S1807, the static task scheduler 15S passes the execution command of the next task to the static task scheduler 15S of the execution destination processor, and executes the static task The scheduler 15S stores the received execution command in the corresponding dependent queue.

  The order of S1803, and S1801 and S1802 may be reversed. Although FIGS. 19 to 21 have been described by way of example of the case where there are two dependent processors, the number of dependent processors may be n (n is any positive number). If there is no portable task, steps S1801 and S1802 may be omitted. If there is no dedicated task, step S1803 may be omitted.

  FIG. 22 is a diagram illustrating an example of a task chain.

  Each queue Q in FIG. 22 may correspond to the master queue MQ, the dependent queues SQ0 to SQn, or both the master queue MQ and the dependent queues SQ0 to SQn. In FIG. 22, task execution commands are managed in the queue Q after occurrence until the corresponding task is executed.

  The task chain is, for example, a connection of two or more tasks that are sequentially executed. The HAL 301 h receives data, information, signals, commands, messages, requests, instructions, etc. from the outside according to a specific interface. For example, the HAL 301 h issues an execution command based on an external interrupt event such as an input / output command from the host device or nonvolatile memory, a power supply event, a timer event, an event of the NAND flash memory, etc. Store in the queue Q of More specifically, the external interrupt event is, for example, a data transmission / reception command for the HAL 301 h, a read or write or erase command for the non-volatile memory 5, a power control event, or a timer interrupt event. The external interrupt event is not limited to the one described above.

  After completion of the task chain, the HAL 301h sends data, information, signals, commands, messages, requests, commands, etc. to the outside according to a specific interface.

  All task chains are callable by the interrupt handler. The task prepares all information (parameters) necessary for the next task before calling the next task.

  After execution of the task, the executed task may be able to select a task to be executed next from a plurality of tasks. For example, when the task T ends normally, the task T may select the task chain TC1 as normal processing, and store an execution command of the task Tn to be processed next in the queue Q. When the task T abnormally ends, the task T may select the task chain TC2 as exception processing, and store an execution command of the task Te to be processed next in the queue Q.

  Also, when the task chain TC1 for normal processing and the task chain TC2 for exception processing are being processed by the dependent processor PS1, for example, the dynamic task scheduler 15D once transmits an execution command of a task included in the task chain to the master queue MQ. , It takes time to send and receive, and processing is delayed. Therefore, when determining that the load of the dependent processor PS1 is low, the dynamic task scheduler 15D may pass an execution command of the task to be processed next to the static task scheduler of the dependent processor PS1.

  The hardware abstraction layer HAL 301h on the host device side does not access the device. Actual device access is performed by the device driver HAL 301 d included in the task chain TC1 or task chain TC2 started by the task T. The details of the device access by the HAL 301 d will be described later with reference to FIGS.

  The task T may be able to call a branch destination task during execution. Specifically, the task T may allocate one or more parallel processable tasks (for example, Tb1 and Tb2) in the task chain TC1 for normal processing or the task chain TC2 for exception processing to a processor with a low load. In this case, task T generates branch task chains TC3 and TC4. The branch process may be a branch process having no access to the HAL 301 d like the task chain TC3, or may be a branch process having an access to the HAL 301 d like the task chain TC4. The branching process is, for example, log recording.

  After executing the task at the end of the task chain, the HAL 301 d fetches the execution command stored in the queue Q from the queue Q and executes the fetched execution command, for example, to the outside, data, information, signal, command, message , Send requests, commands etc.

  FIG. 23 is a diagram illustrating an example of information exchange between tasks. For example, information passed between tasks is called an intertask message.

  In FIG. 23, the task Tp currently being processed or processed is selected in the work area WAp, and the next task Tn selected when the task Tp ends normally is selected in the work area WAn, the exception selected when the task Tp ends abnormally. The tasks Te are respectively associated with the work area WAe, and each task can write and read information from the corresponding work area. Work area WAp, work area WAn, and work area WAe are included in memories M0 to M8 of FIG.

  The task Tp, the next task Tn, and the exceptional task Te can store (write) and reference (read) information in the shared work area CWA, respectively. The shared work area CWA is included in the shared memory SM of FIG.

  The work area WAp, the work area WAn, the work area WAe, and the shared work area CWA may include a plurality of types of memories (for example, SRAM, DRAM).

  As described above, the execution command of the next task or the execution command of the exceptional task, which is generated after the task Tp is executed, is managed by the queue Q. The execution command generated after the next task Tn is executed and the execution command generated after the exception task Te is also managed by the queue Q, respectively. In FIG. 23, the description of the queue Q existing between the task Tp and the next task Tn and the exceptional task Te is omitted.

  The task Tp may be able to refer to information in the work area corresponding to the task executed before the task Tp is executed.

  The task Tp may be capable of storing information in the work area WAn corresponding to the next task Tn executed after the task Tp is executed or in the work area WAe corresponding to the exceptional task Te.

  The next task Tn and the exceptional task Te may be able to refer to information in the work area WAp corresponding to the next task Tn and the task Tp executed before the exceptional task Te is executed.

  The next task Tn and the exceptional task Te may be capable of storing information in the work area corresponding to the task to be executed next.

  More specifically, methods for passing messages between tasks include the following first to third methods. The arrow in FIG. 23 indicates the direction in which the inter-task message moves.

  The first method is a method of storing an inter-task message in the work area WAp of the task Tp, as indicated by an arrow S2301. In this case, the task to be processed next (next task Tn or exceptional task Te) accesses the work area WAp and refers to the inter-task message.

  The second method is a method in which the task Tp stores an intertask message in the work area of the task to be processed next, as indicated by an arrow S2302. If the task to be processed next is the next task Tn, the inter-task message is stored in the work area WAn, and the next task Tn refers to the inter-task message stored in the work area WAn. If the task to be processed next is the exceptional task Te, the inter-task message is stored in the work area WAe, and the exceptional task Te refers to the inter-task message stored in the work area WAe.

  The third method is a method in which a plurality of tasks access an inter-task message in the shared work area CWA as indicated by an arrow S2303. The task Tp stores the inter-task message in the shared work area CWA, and the task to be processed next (next task Tn or exceptional task Te) refers to the inter-task message stored in the shared work area CWA.

  Each task is called by a previous task or an external handler. The previous task prepares all necessary information (parameters) before calling the next task. Each task stores an inter-task message in at least one of a work area corresponding to a processor executing the task and a work area of the next task.

  FIG. 24 is a diagram showing an example of a work area corresponding to a task.

  The work area includes a high-speed accessible work area WAf and a work area WAl having a large storage capacity. The task control API defines the relationship between tasks and the exchange of local work area information. Task T is executed after the previous task Tpp. After the task T is executed, the next task Tn or the exceptional task Te is executed. Task T may have access to the work area of another task. The task T refers to the information in the shared work area CWA or stores the information in the shared work area CWA.

  A hierarchical structure may be provided among a plurality of tasks. Resources held by the parent task and the child task may be mutually referable. For example, when the parent task Tpa of the task T exists, the task T may be able to refer to the task control structure of the parent task Tpa and the work area position in the task control structure.

  The HAL API is used for host interface control, NAND control, power control, and timer control.

  The host interface control notifies the scheduler of host events such as command arrival and data arrival.

  NAND control queues read commands, write commands, and erase commands using priorities. The NAND control notifies the scheduler of NAND events related to the NAND flash memory.

  The power control notifies the scheduler of a power event and controls the power mode.

  The timer control sets or resets parameters to the timer. Timer control notifies the scheduler of timer events.

  Communication between tasks using the HAL will be described with reference to FIGS.

  FIG. 25 is a flowchart showing an example of communication by the HAL according to the present embodiment.

  FIG. 26 is a block diagram showing an example of communication by the HAL according to the present embodiment.

  The HAL 301 d includes a device driver task Td and an interrupt handler 303. Further, the HAL 301 d includes a device driver task queue DQ and a work area WAh for managing the processing order of the device driver tasks Td. In FIG. 26, the description of the queue Q existing between the task Tp and the device driver task Td, and the queue Q existing between the interrupt handler 303 and the next task Tn and the exceptional task Te is omitted. The device driver task queue DQ and the work area WAh may be arranged on the same memory space. The work area WAh is inaccessible from other tasks.

  In step S2501, the task Tp activates the HAL 301d. Specifically, the task Tp stores the execution command of the device driver task Td in the queue Q after the processing of the task Tp is completed, and the static task scheduler 15S or the dynamic task scheduler 15D executes the execution stored in the queue Q The device driver task Td to be processed next is started according to the command.

  In step S2502, the device driver task Td acquires information on the next task Tn to be processed next and parameters necessary for device access. The device driver task Td may read information on the next task Tn and necessary parameters from the work area WAp of the task Tp as an inter-task message.

  In step S2503, the device driver task Td issues a device access request. Device access requests are stored in the device driver task queue DQ. The device driver task Td stores the inter-task message read in step S2502 in the work area WAh.

  In step S2504, the device driver task Td fetches one device access request from the device driver task queue DQ and generates an interrupt for device access.

  In step S2505, the interrupt handler 303 is activated by the interrupt generated in step S2504.

  In step S2506, the device driver 311 accesses the device in accordance with the interrupt handler 303, that is, within the processing sequence of the interrupt handler 303, and performs the requested processing.

  In step S2507, the interrupt handler 303 may store the device access result (return value) obtained from the device driver 311 in the work area WAp of the task Tp.

  In step S2508, the interrupt handler 303 stores the execution command of the next task Tn or the execution command of the exceptional task Te in the queue Q in accordance with the processing result of the device driver task Td. The static task scheduler 15S or the dynamic task scheduler 15D starts the next task Tn or exception task Te to be processed next.

  If the task to be processed next is the next task Tn, the next task Tn refers to the work area WAp of the task Tp in step S2509, and acquires the device access result (return value) stored in step S2507. Even when the task to be processed next is the exceptional task Te, the exceptional task Te similarly acquires the device access result (return value) from the work area WAp.

  The HAL 301 d may be called from a plurality of tasks. In this case, the HAL 301 d may acquire identification information identifying which of a plurality of tasks is a device access request from an inter-task message stored in the work area WAh. Also, a plurality of tasks can identify their respective next tasks or exceptional tasks.

  In the present embodiment, the HAL 301 d stores the device access result as an inter-task message in the work area WAp of the task Tp, and the task to be processed next obtains the inter-task message by referring to the work area WAp of the task Tp. Thereby, the task Tp and the next task Tn to be processed next behave as direct inter-task communication without being aware of the presence of the HAL 301 d. That is, in inter-task communication, the HAL 301 d can be concealed.

  FIG. 27 is a flowchart showing an example of processing compliant with the HAL API for the NAND flash driver.

  FIG. 28 is a block diagram showing an example of the HAL API for the NAND flash driver.

  In step S2701, the device driver task Td reads the identification information of the next task Tn to be executed next to the task Tp and the NAND flash parameters necessary for device access from the work area WAp of the task Tp as an intertask message.

  In step S2702, a NAND flash access request managed by the queue Q is issued to the NAND flash driver 311a. Device access requests are stored in the device driver task queue DQ. The device driver task Td stores the inter-task message read in step S2701 in the work area WAh.

  In addition, the NAND flash driver 311a accesses the NAND flash memories B0 to Bp.

  In step S2703, after the access to the NAND flash memories B0 to Bp is completed, the device driver task Td stores the access result in the work area WAp of the task Tp. The access result may be, for example, memory status information indicating the states of the NAND flash memories B0 to Bp.

  In step S2704, the device driver task Td stores an execution command of the next task Tn, which is a task to be processed next, in the queue Q. The static task scheduler 15S or the dynamic task scheduler 15D starts the next task Tn in accordance with the execution command of the next task Tn.

  In this embodiment, a software-defined SSD platform performs host control. Host control, for example, supports commands, controls namespaces, and performs QoS (Quality of Service) control.

  As command support, for example, host control performs native command queuing (NCQ) in which multiple commands in read and write are rearranged and executed in the most efficient order.

  As control of namespaces, for example, host control performs QoS control for each namespace. QoS control includes, for example, differentiating transfer processing and guaranteeing bandwidth according to the attribute of traffic. For example, host control specifies a task chain corresponding to each namespace.

  As QoS control, for example, host control manages acceptable latency information for the NAND flash controller, and priority control for task control.

  FIG. 29 is a block diagram showing an example of task assignment using NCQ.

  Each task chain TC1 to TCn is distinguished by an ID. Each task chain TC1 to TCn is processed independently. Task programs P1 to Pm may be shareable among a plurality of task chains TC1 to TCn. Work areas WA1 to WAm corresponding to tasks T1 to Tm included in respective task chains TC1 to TCn are independently secured for each of task chains TC1 to TCn.

  Specifically, for example, when the host device accesses the nonvolatile memory 5, n read commands are issued from the host device, and task chains TC1 to TCn corresponding to the n read commands are executed. The task chains TC1 to TCn respectively include m tasks T1 to Tm. Task chains ID may be assigned to the task chains TC1 to TCn, for example, by the host device or the memory device.

  Here, since all of the task chains TC1 to TCn are read commands, the tasks T1 to Tm included in the task chains TC1 to TCn are common regardless of the task chain ID. Therefore, the programs P1 to Pm of the tasks T1 to Tm are shared among the task chains TC1 to TCn, so that resources managed by the entire system are compared with the case where independent programs are held for each of the task chains TC1 to TCn. Is reduced. Specifically, the task T1 of each task chain TC1 to TCn shares the program P1, and the task Tm of each task chain TC1 to TCn shares the program Pm.

  As described above, since each task chain TC1 to TCn shares a program that processes the same task, the same task included in different task chains is not processed at the same time. For example, tasks T1 of task chains TC1 to TCn processed by program P1 are not processed at the same time. In each task chain TC1 to TCn, a plurality of commands are not executed simultaneously in one task chain.

  Also, the same task included in different task chains reserves different work areas in order to hold different parameters. For example, task T1 secures work area WA1, and task Tm secures work area WAm. The parameters held by the task include, for example, progress management parameters representing a processing range (elapsed) and processing results of the task.

  Although FIG. 29 illustrates the case where all task chains TC1 to TCn are the same command, task chains TC1 to TCn may be task chains of different commands.

  FIG. 30 is a block diagram showing an example of the function of the software defined SSD platform according to the present embodiment. FIG. 30 divides the configuration of the software defined type SSD platform shown in FIG. 15 into functional block units to express the relationship between functional blocks. The following describes the case where the non-volatile memory 5 accessed by the program F is a NAND flash memory, but the non-volatile memory 5 is not limited to the NAND flash memory.

  The software-defined SSD platform includes, for example, a command control unit 3101, a transmission / reception control unit 3102, a write control unit 3103, a read control unit 3104, a write buffer 3105, a NAND write control unit 3106, a read buffer 3107, a NAND read control unit 3108, lookup The table 3109 includes a look-up table cache 3110, a NAND control unit 3111, and a garbage collection control unit 3112.

  The command control unit 3101 transmits and receives commands to and from the host device. The command control unit 3101 sends a write command to the write control unit 3103 when the command received from the host device is a write command. When the command received from the host device is a read command, the command control unit 3101 sends a read command to the read control unit 3104.

  Even when the command transmitted and received between the host device and the command control unit 3101 has the same name as the command transmitted and received inside the software defined SSD platform, the command format may be different.

  The transmission and reception control unit 3102 transmits and receives data to and from the host device. The transmission / reception control unit 3102 stores the data received from the host device in the write buffer 3105. The transmission / reception control unit 3102 receives data read from the NAND flash memory from the read buffer 3107 and transmits the data to the host device.

  The write control unit 3103 controls the write buffer 3105 and the NAND write control unit 3106 according to the write command from the command control unit 3101. Specifically, a command is sent to the NAND write control unit 3106 to write the data stored in the write buffer 3105 into the NAND flash memory.

  The read control unit 3104 controls the read buffer 3107 and the NAND read control unit 3108 according to the read command from the command control unit 3101. Specifically, after the data stored in the NAND flash memory is read, a command is sent to the NAND read control unit 3108 so as to be stored in the read buffer 3107.

  The NAND write control unit 3106 transmits a write command to the NAND control unit 3111. At this time, the reference result may be transmitted to the NAND control unit 3111 by referring to the lookup table 3109.

  The NAND read control unit 3108 stores the read data in the read buffer 3107.

  The lookup table cache 3110 is a cache memory for accelerating access to the lookup table 3109, and stores at least a part of the lookup table 3109. The lookup table cache 3110 may be rewritten by the write control unit 3103 via the write buffer 3105 or may be read from the read control unit 3104 via the read buffer 3107.

  The NAND control unit 3111 performs data writing and reading on the NAND flash memory according to the write command and the read command. The NAND control unit 3111 transmits the read data to the NAND read control unit 3108.

  The garbage collection control unit 3112 controls the write control unit 3103 and the read control unit 3104 to perform garbage collection.

  The write control unit 3103 and the NAND write control unit 3106 may not be separated. The read control unit 3104 and the NAND read control unit 3108 may not be separated.

  In the embodiment described above, the hardware unit 4H is concealed by the HAL 301. Further, the next task Tn to be processed next to the task Tp obtains the access result of the task Tp to the HAL 301 by referring to the work area WAp of the task Tp. That is, since the hardware unit 4H is concealed in inter-task communication, the security of communication is enhanced. Further, since the dynamic task scheduler 15D and the program F do not have to be aware of the specification change of the hardware unit 4H or the device driver 311, maintenance and management of the program code become easy.

  In the present embodiment, a shared memory platform is employed. For this reason, the software defined SSD platform can adjust the performance so that the load on a plurality of processors becomes constant by dynamic task scheduling.

When the software defined type SSD platform according to the present embodiment holds the same parameter in each layer, the upper layer (for example, program F) and the lower layer (for example, HAL 301, device driver 311, hardware unit 4H) , Change the content of the parameters. Thereby, parameters can be held at an appropriate abstraction level for each hierarchy.

  In the present embodiment, the task chain may be branched into a task chain for normal processing and a task chain for exception processing according to the processing result of task T. As a result, the task T can be easily replaced with hardware since complicated branch processing, whether normal processing or exception processing, is unnecessary in the task chain.

  In the present embodiment, the task T under processing allocates one or more parallel processable tasks in the task chain TC1 for normal processing or the task chain TC2 for exception processing to the processor with low load. This can reduce the processing time of the entire software defined SSD platform.

  In this embodiment, as a method of inter-task communication, a method of storing an inter-task message in the work area WAp of the task Tp, and storing an inter-task message in the work area WAn of the next task Tn to be processed next A method and a method for referencing inter-task messages among tasks using the shared work area CWA are prepared. This allows the developer to select an optimal inter-task communication method for implementation.

  In the present embodiment, tasks shared among a plurality of task chains executed according to a plurality of commands from the host device are executed based on a common program. This makes it possible to reduce the resources managed by the entire system as compared to the case where programs are held independently for each task chain.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

  DESCRIPTION OF SYMBOLS 1 ... Information processing system, 2 ... Information processing apparatus, 3 ... Memory apparatus, 4 ... Controller, 5 ... Nonvolatile memory, 6 ... Interface part, 7A, 7B ... Memory, P0-PN ... Processor, C0-CN ... Management part , 81: reception unit, 82: address conversion unit, 83: writing unit, 84: reading unit, 9: memory controller, 10: address conversion data, 11: control program, F0 to FM: program, 111: inter-module communication unit , 112: priority control unit, 113: interrupt handler, 114: access unit, 115: information management unit, 116: hardware driver, 4H: hardware unit, B0 to BP: NAND flash memory, 131 to 137: replaceable SSD module, 141 to 145: driver, 146: external hardware unit, VS0 to VSP: virtual memory Device, VM0 to VMP ... virtual machine.

Claims (28)

Non-volatile memory,
A controller for controlling the non-volatile memory;
Equipped with
The controller comprises first to third processors,
The first processor is waiting for execution and determines an execution destination of a new process that can be executed by any of the first to third processors but is not allocated.
The controller is determined by the first processor to be executed next by one of the second and third processors based on priority information including priority for the new process Determine at least one of the new processes that may be performed by the target of execution,
Memory device. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
The program refers to the priority information and determines the new process whose management destination is changed from the first management unit to one of the second and third management units.
The memory device of claim 1. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
The program refers to the priority information including a priority related to the process managed by the second management unit, and is executed next among the processes managed by the second management unit. To determine the
The program refers to the priority information including the priority regarding the process managed by the third management unit, and is executed next among the processes managed by the third management unit. To determine the
The memory device of claim 1. Non-volatile memory,
A controller for controlling the non-volatile memory;
Equipped with
The controller comprises first to third processors,
The first processor is waiting for execution and determines an execution destination of a new process that can be executed by any of the first to third processors but is not allocated.
In the second processor, a process performed by the second processor is to be performed by the second processor, and a next process is to be performed subsequent to the process performed by the second processor. If the process executed by the second processor has the dependency, the next process should be executed by the second processor. Decide,
Memory device. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
If the next process is to be executed by the second processor, the program manages the next process using the second manager.
The program manages the next process using the first managing unit, when the next process can be executed by any of the second and third processors.
The memory device of claim 4. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
When the next process is to be executed by the second process, the program manages the next process using the second manager.
In the case where the next process can be executed by any of the second and third processors, and the number of processes managed by the second manager is equal to or less than the first threshold value, The program manages the next processing using the second management unit, and the next processing can be executed by any of the second and third processors, and the third processing The program manages the next process using the third manager, when the number of processes managed by the manager of the second group is equal to or less than the second threshold value,
The number of processes managed by the second management unit is greater than the first threshold, and the number of processes managed by the third management unit is greater than the second threshold If there are many, the program manages the next process using the first managing unit.
The memory device of claim 4. Non-volatile memory,
A controller for controlling the non-volatile memory;
Equipped with
The controller comprises first to third processors,
The first processor is waiting for execution and determines an execution destination of a new process that can be executed by any of the first to third processors but is not allocated.
The controller further includes a shared memory shared by the first to third processors, and allocates a memory area of the shared memory used in the pre-execution processing to the pre-execution processing.
Memory device. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
The memory device of claim 7. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
The program manages processing associated with hardware identification information indicating a part of the controller in a management unit corresponding to the hardware identification information among the first to third management units.
The memory device of claim 7. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
The first process is executed by any of the second and third processors,
The second process is executed after the first process in any of the second and third processors.
The first process includes area information of at least a part of the memory area when at least a part of a memory area of the shared memory used in the first process is used in the second process. , Notify the second process,
The memory device of claim 7. It further comprises a memory for storing a program to be executed by the controller,
The first to third processors are controlled by the program,
The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The controller
A first management unit corresponding to the first processor and managing an execution order of the new process and the new process;
A second manager corresponding to the second processor and managing a process to be executed by the second processor and an execution order of the process to be executed by the second processor;
A third management unit corresponding to the third processor, managing a process to be executed by the third processor and an execution order of the processes to be executed by the third processor;
Equipped with
If the number of processes managed by the second management unit is less than or equal to the first threshold, the program determines the management destination of the new process managed by the first management unit. Changing from the first management unit to the second management unit,
If the number of processes managed by the third management unit is less than or equal to the second threshold, the program is determined to be the management destination of the new process managed by the first management unit. , From the first management unit to the third management unit,
The first process is executed by any of the second and third processors,
The second process is executed after the first process in any of the second and third processors.
The third process is performed after the second process in any of the second and third processors,
The second process receives identification information indicating at least one of the first to third processes from the first process, and uses information to be used in the second process as the first to third processes. The first memory area of the shared memory corresponding to at least one of the third processes is read, and the execution result of the second process is stored in at least one of the first to third processes. Store in the corresponding second memory area
The memory device of claim 7. The second process reads information used in the second process from a memory area corresponding to the first process, and the execution result of the second process is a memory area corresponding to the third process. To store,
The memory device of claim 11. Non-volatile memory,
A controller for controlling the non-volatile memory;
Equipped with
The controller comprises first to third processors,
The first processor is waiting for execution and determines an execution destination of a new process that can be executed by any of the first to third processors but is not allocated.
The controller further includes shared memory shared by the first to third processors, and allocates a memory area of the shared memory used in the pre-execution processing to the pre-execution processing,
The first process is executed by any of the second and third processors,
The second process is executed after the first process in any of the second and third processors.
The third process is performed after the second process in any of the second and third processors,
The second process receives identification information indicating at least one of the first to third processes from the first process, and uses information to be used in the second process as the first to third processes. The first memory area of the shared memory corresponding to at least one of the third processes is read, and the execution result of the second process is stored in at least one of the first to third processes. Store in the corresponding second memory area
Memory device. The first processor is the execution destination of the new process managed by the first processor when the number of pending processes to be executed by the second processor is equal to or less than a first threshold. Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The second process reads information used in the second process from a memory area corresponding to the first process, and the execution result of the second process is a memory area corresponding to the third process. To store,
The memory device of claim 13. A control method of non-volatile memory comprising a controller including first to third processors, comprising:
The first processor determines the execution destination of a new process, and the new process is awaiting execution and can be executed by any of the first to third processors but is not allocated. When,
By the controller based on priority information, including priority for the new process, by the first processor to be executed next by one of the second and third processors Determining at least one of the new processes that may be performed by the determined destination;
Control method. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Equipped with
The program refers to the priority information and determines the new process whose management destination is changed from the first management unit to one of the second and third management units.
The control method of claim 15. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the execution order of the new process and the new process by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Equipped with
The program refers to the priority information including a priority related to a new process managed by the second management unit, and executes the next one of the processes managed by the second management unit. Determine the processing to be
The program refers to the priority information including a priority related to a new process managed by the third management unit, and executes the next one of the processes managed by the third management unit. Determine the processing to be done,
The control method of claim 15. A control method of non-volatile memory comprising a controller including first to third processors, comprising:
The first processor determines the execution destination of a new process, and the new process is awaiting execution and can be executed by any of the first to third processors but is not allocated. When,
The processing executed by the second processor by the second processor should be executed by the second processor, the next processing being activated following the processing executed by the second processor Determining whether or not there is a dependency that is
Determining by the second processor that the next processing should be performed by the second processor if the processing performed by the second processor has the dependency;
Control method. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Managing the next process by the program using the second manager, if the next process is to be performed by the second processor;
Managing the next process using the first managing unit by the program when the next process can be executed by any of the second and third processors;
Equipped with
The control method of claim 18. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Managing the next process by the program using the second manager, if the next process is to be performed by the second process;
In the case where the next process can be executed by any of the second and third processors, and the number of processes managed by the second manager is equal to or less than the first threshold value, Managing the next process using the second management unit according to the program, and the next process can be performed by either the second or third processor, and Managing the next process using the third manager by the program when the number of processes managed by the third manager is less than or equal to the second threshold value; ,
The number of processes managed by the second management unit is greater than the first threshold, and the number of processes managed by the third management unit is greater than the second threshold Managing the next process by using the first managing unit according to the program if the number is large;
Equipped with
The memory device of claim 18. A control method of non-volatile memory comprising a controller including first to third processors, comprising:
The first processor determines the execution destination of a new process, and the new process is awaiting execution and can be executed by any of the first to third processors but is not allocated. When,
Assigning the memory area of the shared memory used in the pre-execution processing to the pre-execution processing by the controller, wherein the shared memory is shared by the first to third processors;
Control method. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Equipped with
22. The method of claim 21. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Equipped with
The program manages processing associated with hardware identification information indicating a part of the controller in a management unit corresponding to the hardware identification information among the first to third management units.
22. The control method of claim 21. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Executing a first process on any of the second and third processors;
Executing a second process on either of the second and third processors after the first process;
Equipped with
In the first process, when at least a part of the memory area used in the first process is used in the second process, area information of at least a part of the memory area is Notify process 2
22. The control method of claim 21. The controller includes first to third management units.
If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
The control method is
Executing a program for controlling the controller;
Managing the new processing and the execution order of the new processing by the first management unit corresponding to the first processor;
Managing the processing to be executed by the second processor and the execution order of the processing to be executed by the second processor by the second manager corresponding to the second processor;
Managing the processing to be executed by the third processor and the execution order of the processing to be executed by the third processor by the third manager corresponding to the third processor;
If the number of processes managed by the second management unit is less than or equal to the first threshold value, the management destination of the new process managed by the first management unit is selected by the program. Changing from the first management unit to the second management unit;
When the number of processes managed by the third management unit is less than or equal to the second threshold value, the management destination of the new process managed by the first management unit by the program Changing the first management unit to the third management unit;
Executing a first process on any of the second and third processors;
Executing a second process on either of the second and third processors after the first process;
Executing a third process on either of the second and third processors after the second process;
Equipped with
The second process receives identification information indicating at least one of the first to third processes from the first process, and uses information to be used in the second process as the first to third processes. The first memory area of the shared memory corresponding to at least one of the third processes is read, and the execution result of the second process is stored in at least one of the first to third processes. Store in the corresponding second memory area
22. The control method of claim 21. In the second process, information used in the second process is read out from a memory area corresponding to the first process, and a result of execution of the second process is a memory area corresponding to the third process. To store,
The control method of claim 25. A control method of non-volatile memory comprising a controller including first to third processors, comprising:
The first processor determines the execution destination of a new process, and the new process is awaiting execution and can be executed by any of the first to third processors but is not allocated. When,
Assigning the memory area of the shared memory used in the pre-execution processing to the pre-execution processing by the controller, wherein the shared memory is shared by the first to third processors;
Executing a first process on any of the second and third processors;
Executing a second process on either of the second and third processors after the first process;
Executing a third process on either of the second and third processors after the second process;
Equipped with
The control method is used in the second process, receiving, from the first process, identification information indicating at least one of the first to third processes in the second process. Reading out information from a first memory area of the shared memory corresponding to at least one of the first to third processes, and execution results of the second process, the first to third Storing in a second memory area corresponding to at least one of the processes of
Control method. If the number of pending processes to be executed by the second processor by the first processor is less than or equal to a first threshold, the execution destination of the new process managed by the first processor Is determined to be the second processor and the number of pending processes to be executed by the third processor is less than or equal to a second threshold, the new number being managed by the first processor Determine that the execution destination of the process is the third processor,
In the second process, reading information used in the second process from a memory area corresponding to the first process, and an execution result of the second process correspond to the third process. Storing in a memory area;
The control method of claim 27.

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