JP2019083338A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having a fin capable of alleviating wiring congestion and avoiding an increase in an area when semiconductor elements are connected across a tap region.SOLUTION: A semiconductor device 1A includes a p-type first well provided in a semiconductor substrate in an NMOS region 10, a p-type second well provided in the semiconductor substrate in a PWTAP region 20, an N-type fin 11 on the first well, a P-type fin 21 on the second well, and an NM second electrode 12b connected to the first and second fins.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a semiconductor device, for example, to a semiconductor device having a fin-type FET structure.

  One of the typical structures of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is a planar type FET structure. In the planar FET structure, the source region, the drain region, and the channel region are planarly disposed on the substrate. Patent Document 1 discloses a semiconductor device having a planar FET structure. In the semiconductor device of Patent Document 1, a plurality of p-channel field effect transistors (PMOS) and n-channel field effect transistors (NMOS) are formed in an n-type well region and a p-type well region on a semiconductor substrate, respectively. .

  The PMOS and the NMOS each have a gate electrode formed on a semiconductor substrate via a gate insulating film. In the planar FET structure, the channel is controlled from the upper side by the gate electrode on the semiconductor substrate. The plurality of MOSFETs are connected by a first layer wiring in the upper layer of the gate electrode to form a desired circuit.

  Further, on the semiconductor substrate, a diffusion layer for feeding called "tap" is formed to extend in one direction. The taps include an n-well tap for supplying a power supply potential VDD to an n-type well region in which a PMOS is formed, and a p-well tap for supplying a power supply potential VSS to a p-type well region in which an NMOS is formed. The n-well tap is connected to one PMOS source region via the first layer wiring, and the p-well tap is connected to one NMOS source region via the first layer wiring .

JP, 2010-141187, A

  In the planar FET structure described above, the gate electrode does not extend to the tap formation region. Therefore, in the case of connecting the semiconductor element so as to straddle the tap, it is necessary to use a wiring above the gate electrode. As described above, when the wiring in the upper layer of the gate electrode is used to connect the semiconductor elements, the number of usable wiring tracks is reduced, the wiring is congested, and the area is increased.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, the semiconductor device is provided on the first well of the semiconductor substrate, provided on the first well of the same conductivity type as the first well, and on the second well, and the second well It has the 2nd fin of different conductivity type, and the 1st electrode connected to the 1st and 2nd fin.

  According to the embodiment, it is possible to provide a semiconductor device having fins capable of alleviating wiring congestion and avoiding an increase in area.

FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment. It is a perspective view explaining the relationship between the fin of FIG. 1, an electrode, and a wiring layer. It is IV-IV sectional drawing of FIG. It is a V-V sectional view of FIG. FIG. 6 is a plan view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram of a semiconductor device according to a second embodiment. It is the VIII-VIII sectional view of FIG. FIG. 18 is a plan view showing a configuration of a semiconductor device according to Third Embodiment. FIG. 16 is a circuit diagram of a semiconductor device in accordance with a third embodiment. It is XI-XI sectional drawing of FIG. FIG. 18 is a plan view showing a configuration of a semiconductor device according to Fourth Embodiment. FIG. 18 is a circuit diagram of a semiconductor device in accordance with a fourth embodiment. It is XVI-XVI sectional drawing of FIG. It is XV-XV sectional drawing of FIG. FIG. 26 is a plan view showing a configuration of a semiconductor device according to Fifth Embodiment. FIG. 18 is a circuit diagram of a semiconductor device in accordance with a fifth embodiment. It is XVIII-XVIII sectional drawing of FIG. FIG. 26 is a plan view showing the configuration of a semiconductor device according to Sixth Embodiment. FIG. 18 is a circuit diagram of a semiconductor device in accordance with a sixth embodiment. It is XXI-XXI sectional drawing of FIG. FIG. 26 is a plan view showing the configuration of a semiconductor device according to a seventh embodiment. It is the figure seen from the XXIII-XXIII cutting plane line of FIG. 22 toward the arrow direction. It is the figure seen in the arrow direction from the XXIV-XXIV cutting plane line of FIG. FIG. 7 is a V-V cross-sectional view in a case where the NM first electrode and the NM second electrode in FIG. 1 are in contact with only the end of the side surface in the longitudinal direction of the n-type fin and the end of the upper surface. It is a top view showing composition of a semiconductor device concerning a comparative example. It is XXVI-XXVI sectional drawing of FIG.

  Hereinafter, embodiments will be described with reference to the drawings. The following description and drawings are omitted and simplified as appropriate for clarification of the explanation. Specific values and the like shown in the following embodiments are merely examples for facilitating the understanding of the invention, and are not limited thereto unless otherwise specified. In the drawings, the same elements are denoted by the same reference numerals, and the redundant description is omitted as necessary.

  In the following embodiments, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MOS, a p-channel MOSFET is abbreviated as PMOS, and an n-channel MOSFET is abbreviated as NMOS. Also, in the following description, the diffusion layer for substrate contact for supplying power is referred to as a tap (TAP).

  In the semiconductor device according to the following embodiments, the conductivity type (p-type or n-type) of the semiconductor substrate, the semiconductor layer, the diffusion layer (diffusion region) or the like may be reversed. Therefore, when one of n-type and p-type conductivity types is a first conductivity type and the other conductivity type is a second conductivity type, the first conductivity type is p-type and the second conductivity type is n-type. Alternatively, the first conductivity type may be n-type, and the second conductivity type may be p-type.

  Prior to the description of the semiconductor device according to the embodiment, a semiconductor device according to a comparative example will be described with reference to FIGS. FIG. 26 is a plan view showing the configuration of a semiconductor device according to a comparative example, and FIG. 27 is a cross-sectional view taken along the line XXVI-XXVI in FIG. The comparative example shown in FIGS. 26 and 27 is a semiconductor device having a planar FET structure. In FIG. 27, illustration of the gate insulating film and the like is omitted.

  As shown in FIG. 27, in the semiconductor device 100 according to the comparative example, the p-type well region 101 and the n-type well region 102 are formed on the semiconductor substrate. In addition, an element isolation film 103 is formed on the semiconductor substrate. The element isolation film 103 defines an active region in which a semiconductor element is formed.

  As shown in FIG. 26, in the p-type well region 101, two n-channel field effect transistor (NMOS) regions 110 are formed. In each NMOS region 110, a plurality of NMOSs are formed. The NMOS is controlled by a gate electrode 111 formed on the NMOS region 110 via a gate insulating film. A PW (p-type well) TAP region 120 for supplying the power supply potential VSS to the p-type well region 101 is formed between the two NMOS regions 110. The PWTAP region 120 is formed between the two NMOS regions 110 so as to extend in one direction.

  In the n-type well region 102, two p-channel field effect transistor (PMOS) regions 130 are formed. In each PMOS region 130, a plurality of PMOSs are formed. The PMOS is controlled by a gate electrode 131 formed on the PMOS region 130 via a gate insulating film. An NW (n-type well) TAP region 120 for supplying the power supply potential VDD to the n-type well region 102 is formed between the two PMOS regions 110. The NWTAP region 140 is formed to extend in one direction between the two PMOS regions 130.

  The source region and the drain region of the NMOS are each composed of a low concentration n-type semiconductor region (not shown) formed in the n-type well region 101 and a high concentration n-type semiconductor region N +. On the surface of PWTAP region 120, a high concentration p-type semiconductor region P + formed in p-type well region 101 is formed. The source region and the drain region of the PMOS are each composed of a low concentration n-type semiconductor region (not shown) formed in the p-type well region 102 and a high concentration n-type semiconductor region P +. At the surface of the NWTAP region 140, a high concentration n-type semiconductor region N + formed in the n-type well region 102 is formed.

  An interlayer insulating film (not shown) is provided on these regions. A contact hole is formed in the interlayer insulating film, and a plug 104 is formed in the contact hole. The drains of the two NMOSs disposed opposite to each other via the PWTAP region 120 are connected via the upper interconnection layer 105. The drains of the two PMOSs disposed opposite to each other via the NWTAP region 140 are connected via the upper wiring layer 105. The upper wiring layer 105 is formed of a first metal layer M1 formed on the upper layer of the gate electrode.

  The upper wiring layer 105 extends in a direction substantially orthogonal to the direction in which the PWTAP region 120 and the NWTAP region 140 extend. The upper wiring layer 105 is formed to straddle the PWTAP region 120 and the NWTAP region 140, respectively. As described above, in the semiconductor device according to the comparative example, since the wiring layer above the gate electrode is used to connect the PMOS and NMOS, the number of usable wiring tracks decreases, the wiring becomes crowded, and the area increases. Cause problems.

  In such a planar type FET, with the recent miniaturization of the device, problems such as a decrease in mobility due to the increase in impurity concentration and an increase in leakage current have become problems. As one of the measures against these problems, a Fin-type FET has been proposed. The fin-type FET has a structure in which a fin-shaped channel region formed on a semiconductor substrate is sandwiched between U-shaped gate electrodes, and the channels are controlled from three directions. Therefore, it is possible to effectively suppress the leak current which has been a problem in the conventional planar type FET.

  Thus, from the planar type FET to the fin type FET, the layout rules up to that point are largely changed. One of them is to form an electrode used as a gate of a transistor on a diffusion layer for substrate contact (tap). The present inventors examined using the electrode formed on the diffusion layer for the tap as a wiring to alleviate the congestion of the wiring layer, which is a problem in the planar FET.

  The semiconductor device according to the embodiment will be described below. The semiconductor device according to the embodiment has a fin-type FET structure transistor, and is applicable to microcomputers and System-on-a-chip (SoC) products.

Embodiment 1
The semiconductor device 1 according to the first embodiment will be described with reference to FIGS. FIG. 1 is a plan view showing the configuration of the semiconductor device 1, and FIG. 2 is a circuit diagram of the semiconductor device 1. FIG. 3 is a perspective view for explaining the relationship between the fins of FIG. 1 and electrodes and wiring layers. 4 is a cross-sectional view taken along line IV-IV of FIG. 1, and FIG. 5 is a cross-sectional view taken along line V-V of FIG.

  As shown in FIG. 1, the semiconductor device 1 has two NMOS regions 10 and a PWTAP region 20. The two NMOS regions 10 are formed to face each other with the PWTAP region 20 interposed therebetween. As shown in FIGS. 4 and 5, a p-type well region 15 is formed in the NMOS region 10 in the semiconductor substrate. In the semiconductor substrate, a p-type well region 15 is formed in the PWTAP region 20. Thus, in the first embodiment, the well regions respectively formed in the NMOS region 10 and the PWTAP region 20 have the same conductivity type.

  An element isolation film 16 is formed on the semiconductor substrate. The element isolation film 16 has a function of partitioning an active region in which a semiconductor element is formed and preventing interference between elements formed on a semiconductor substrate. The element isolation film 16 is formed, for example, by an STI (Shallow Trench Isolation) method in which a trench is formed in a semiconductor substrate and an insulating film such as a silicon oxide film is embedded in the trench.

  An n-type fin 11 is formed on the p-type well region 15 in the NMOS region 10. The p-type well region 15 and the n-type fin 11 have different conductivity types. The n-type fin 11 has a thin strip shape (rectangular shape). In the example shown in FIG. 1, three n-type fins 11 are arranged at predetermined intervals. The direction in which the n-type fins 11 extend is taken as the x direction.

  On the n-type fin 11, three electrodes (NM first electrode 12a, NM second electrode 12b, NM third electrode 12c) are formed. These three electrodes extend in the y direction orthogonal to the x direction, and intersect with the three n-type fins 11. Therefore, the gate insulating film 17 is formed between the n-type fin 11 and the three electrodes 12a to 12c, respectively. The gate insulating film 17 is made of, for example, a silicon oxide film. The thickness of the gate insulating film 17 is 2 nm or less, preferably about 1 nm. Further, the element isolation film 16 is thicker than the gate insulating film 17.

  Here, the relationship between the n-type fin 11 and the NM second electrode 12 b will be described with reference to FIG. 3. The NM second electrode 12 b is formed to straddle the surface of the n-type fin 11 via the gate insulating film 17. A region covered by the NM second electrode 12 b of the n-type fin 11 functions as a channel region. That is, the NMOS has a tri-gate structure in which both side surfaces and the upper surface of the n-type fin 11 are channel regions. The NM second electrode 12 b becomes a gate electrode of the NMOS. A region not covered by the NM second electrode 12 b of the n-type fin 11 is a source region or a drain region.

  The three electrodes 12a to 12c are formed of a conductive film, for example, a polycrystalline silicon film. An n-type conductive impurity such as phosphorus or arsenic may be introduced into the NM second electrode 12 b serving as the gate electrode of the NMOS on the p-type well region 15. Moreover, it is also possible to use gate metal materials, such as tungsten, as a material of electrode 12a-12c.

  As shown in FIG. 4, the NM first electrode 12 a and the NM third electrode 12 c are formed to cover the end of the n-type fin 11. That is, the end of the n-type fin 11 is disposed in the NM first electrode 12 a and the NM third electrode 12 c. That is, the NM first electrode 12 a and the NM third electrode 12 c are in contact with the end of the side surface in the longitudinal direction of the n-type fin 11, the end of the upper surface, and the side surface in the lateral direction. The arrangement of the NM first electrode 12a and the NM third electrode 12c is not limited to this. For example, the NM first electrode 12 a and the NM third electrode 12 c may be disposed so as to be in contact with only the side surface of the n-type fin 11 in the short direction. Further, the NM first electrode 12a and the NM second electrode 12b are formed so as to be in contact with only the end of the side surface in the longitudinal direction of the n-type fin 11 and the end of the upper surface and not the side surface in the lateral direction It is also good. That is, the end of the n-type fin 11 may be within the range indicated by the broken line in FIG. In FIG. 25, the NM first electrode and the NM second electrode in FIG. 1 contact only the end of the side face in the longitudinal direction of the n-type fin and the end face of the upper face but do not contact the side face in the lateral direction VV sectional drawing is shown. As shown in FIG. 25, the lateral side surface of the n-type fin 11 is exposed from the NM first electrode 12 a.

  The NM first wiring layer 13a is formed between the NM first electrode 12a and the NM second electrode 12b. The NM first wiring layer 13 a is connected to the NM first electrode 12 a by the NM connection wiring layer 14. Further, an NM second wiring layer 13 b is formed between the NM second electrode 12 b and the NM third electrode 12 c. The NM first wiring layer 13a, the NM second wiring layer 13b, and the NM connection wiring layer 14 are newly added in the fin-type FET, unlike the upper wiring layer 105 in the upper layer of the gate electrode described in the comparative example. It consists of a metal layer M0.

  The metal layer M0 is a layer located between the gate and the metal layer M1 in the comparative example. The NM first wiring layer 13a and the NM second wiring layer 13b are wiring layers extending in the vertical direction on the n-type fin 11, and are referred to as metal layers M0_V. The NM connection wiring layer 14 is a wiring extending in the horizontal direction in parallel with the n-type fin 11, and is referred to as a metal layer M0_H. Therefore, although not shown in the embodiment, the first metal film M1 connected via the plug is disposed in the upper layer of the metal layer M0.

  The metal layer M0 is formed, for example, by embedding a barrier metal film and a conductive film mainly made of copper in a groove formed in an interlayer insulating film (not shown). The barrier metal film is made of tantalum, tantalum nitride or a laminated film thereof. The same configuration can be applied to the first wiring layer (metal layer M1) and later layers above the metal layer M0. Note that it is also possible to integrally form the wiring layer and the plug that are upper than the metal layer M0.

  As shown in FIG. 3, the NM first wiring layer 13 a is formed across the surface of the n-type fin 11. Although not shown in FIG. 3, the NM second wiring layer 13 b is also formed so as to straddle the surface of the n-type fin 11.

  As shown in FIG. 5, p-type fins 21 are formed on the p-type well region 15 in the PWTAP region 20. The p-type well region 15 and the p-type fin 21 have the same conductivity type. Like the n-type fins 11, the p-type fins 21 have a narrow strip shape (rectangular shape). In the example shown in FIG. 1, two p-type fins 21 are arranged at a predetermined interval. The p-type fins 21 extend in the x direction, which is the same as the direction in which the n-type fins 11 extend.

  Three electrodes (NM first electrode 12 a, PWTAP first electrode 22 a, PWTAP second electrode 22 b) are formed on the p-type fin 21. The gate insulating film 17 is formed to cover the p-type fin 21. Therefore, the gate insulating film 17 is formed between the p-type fin 21 and these three electrodes. The PWTAP first electrode 22 a and the PWTAP second electrode 22 b extend in the y direction orthogonal to the x direction, and intersect with two p-type fins 21. The PWTAP first electrode 22a and the PWTAP second electrode 22b can also be formed of the same material as the three electrodes 12a to 12c.

  As shown in FIG. 5, the gate insulating film 17 is formed not only between each electrode and each fin but also on the element isolation film between the fins. In other words, the gate insulating film 17 is formed on the entire lower surface of each of the three electrodes (the NM first electrode 12a, the PWTAP first electrode 22a, and the PWTAP second electrode 22b). The same applies to the other embodiments.

  The PWTAP first electrode 22 a and the PWTAP second electrode 22 b are formed to cover the end of the p-type fin 21. As described for the n-type fin 11 with reference to FIGS. 4 and 25, the end of the p-type fin 21 is the end from the inner end of the PWTAP first electrode 22a and the second end of the PWTAP 22b. It can be arranged in the range up to the part.

  The NM first electrode 12 a extends from one NMOS region 10 through the PWTAP region 20 to the other NMOS region 10. The NM first electrode 12 a is also connected to the NM first wiring layer 13 a of the other NMOS region 10 via the NM connection wiring layer 14. Accordingly, the drains of the two NMOSs formed on both sides of the PWTAP region 20 are connected to each other, resulting in the circuit configuration shown in FIG.

  That is, the NMOS (NM first electrode 12 a) formed in the same step as the electrode (NM second electrode 12 b) used as the gate of the NMOS on the PWTAP region 20 is formed of NMOS on both sides of the PWTAP region 20. It is used as a wire for transmitting a signal. That is, the NM first electrode 12 a on the PWTAP region 20 is a wire connecting the upper and lower NMOSs of the PWTAP region 20 and is a signal node which is not a power supply. The NM first electrode 12 a is connected to the semiconductor substrate by the p-type fin 21 in the PWTAP region 20.

  The PWTAP first wiring layer 23a is disposed between the NM first electrode 12a and the PWTAP first electrode 22a. In addition, a PRTAP second electrode 22b is disposed between the NM first electrode 12a and the PWTAP second electrode 22b. The PWTAP first wiring layer 23a and the PWTAP second wiring layer 23b are each connected to the power supply potential VSS. The power supply potential VSS can be set to a reference potential (ground potential) GND.

  The p-type fin 21 supplies the power supply potential VSS to the p-type well region 15 to fix the p-type well region 15 at a constant potential. Unlike the upper wiring layer 105 of the comparative example, the PRTAP first wiring layer 23a and the PWTAP second wiring layer 23b are the above-described metal layers M0_V.

  As described above, in the semiconductor device according to the first embodiment, the NM first electrode 12 a on the PWTAP region 20 is made to function as a wire for transmitting signals other than the power supply without using the upper wiring layer as in the comparative example. Can. Therefore, it is possible to prevent the wiring from being crowded and to reduce the area of the semiconductor device.

Second Embodiment
The semiconductor device 1A according to the second embodiment will be described with reference to FIGS. FIG. 6 is a plan view showing the configuration of the semiconductor device 1A, and FIG. 7 is a circuit diagram of the semiconductor device 1A. 8 is a cross-sectional view taken along line VIII-VIII of FIG.

  As shown in FIG. 6, the semiconductor device 1A has one NMOS region 10 and a PWTAP region 20. As shown in FIG. 8, in the NMOS region 10, a p-type well region 15 is formed on the semiconductor substrate. In the PWTAP region 20, a p-type well region 15 is formed on the semiconductor substrate. Thus, in the second embodiment, the well regions respectively formed in the NMOS region 10 and the PWTAP region 20 have the same conductivity type. An element isolation film 16 is formed on the semiconductor substrate to partition the active region.

  In the NMOS region 10, three n-type fins 11 are formed on the p-type well region 15 so as to extend in the x direction. In the PWTAP region 20, two p-type fins 21 are formed on the p-type well region 15 so as to extend in the x direction. In the example shown in FIG. 6, the length of the p-type fin 21 is approximately half of the length of the n-type fin 11. Although not shown, a gate insulating film 17 is formed on the n-type fin 11 and the p-type fin 21 so as to cover them.

  On the n-type fin 11, three electrodes (NM first electrode 12a, NM second electrode 12b, NM third electrode 12c) are formed. These three electrodes extend in the y direction orthogonal to the x direction, and are formed to cross the three n-type fins 11. The NM second electrode 12 b becomes a gate electrode of the NMOS. The NM first electrode 12 a and the NM third electrode 12 c are formed to cover the end of the n-type fin 11.

  In the second embodiment, the NM second electrode 12 b serving as the gate electrode extends to the PWTAP region 20. The NM second electrode 12 b is disposed to cover one end of the p-type fin 21. A PWTAP electrode 22 is formed on the other end of the p-type fin 21. The PWTAP electrode 22 is formed to cover the other end of the p-type fin 21. As described in FIGS. 4 and 25, the end of the n-type fin 11 may be between the two side surfaces of the NM first electrode 12a and the NM third electrode 12c extending in the longitudinal direction. Further, the end of the p-type fin 21 may be between two side surfaces extending in the longitudinal direction of the PWTAP electrode 22 and between two side surfaces extending in the longitudinal direction of the NM second electrode 12 b.

  The NM first wiring layer 13a is formed between the NM first electrode 12a and the NM second electrode 12b. Further, an NM second wiring layer 13 b is formed between the NM second electrode 12 b and the NM third electrode 12 c. In the PWTAP region 20, a PWTAP wiring layer 23 is formed between the PWTAP electrode 22 and the NM second electrode 12b. The PWTAP wiring layer 23 is connected to the power supply potential VSS.

  A gate contact 24 is connected to the NM second electrode 12 b of the PWTAP region 20. The gate contact 24 is formed in the PWTAP region 20 at a position farther from the NMOS region 10 than the PWTAP wiring layer 23 which supplies the power supply potential VSS to the p-type well region 15. The gate contact 24 is made of the metal layer M0_V described above. The semiconductor device according to the second embodiment has a circuit configuration shown in FIG.

  As described above, in the second embodiment, a voltage can be applied to the gate of the NMOS via the NM second electrode 12 b on the PWTAP region 20. This enables the metal layer for the gate contact to be separated from the source and drain. Therefore, the density of the wiring layers can be avoided, and the area of the semiconductor device can be reduced.

Third Embodiment
A semiconductor device 1B according to the third embodiment will be described with reference to FIGS. FIG. 9 is a plan view showing the configuration of the semiconductor device 1B, and FIG. 10 is a circuit diagram of the semiconductor device 1B. 11 is a cross-sectional view taken along the line XI-XI of FIG.

  As shown in FIG. 9, the semiconductor device 1B includes an NMOS region 10, a PWTAP region 20, and a PMOS region 30. As shown in FIG. 11, in the NMOS region 10, a p-type well region 15 is formed on the semiconductor substrate. In the PWTAP region 20, a p-type well region 15 is formed on the semiconductor substrate. In the PMOS region 30, an n-type well region 35 is formed on the semiconductor substrate. As described above, in the third embodiment, the well regions respectively formed in the NMOS region 10 and the PWTAP region 20 have the same conductivity type, which is different from the conductivity type of the well region formed in the PMOS region 30. An element isolation film 16 is formed on the semiconductor substrate to partition the active region.

  In the NMOS region 10, three n-type fins 11 are formed on the p-type well region 15 so as to extend in the x direction. In the PWTAP region 20, two p-type fins 21 are formed on the p-type well region 15 so as to extend in the x direction. In the PMOS region 30, three p-type fins 31 are formed to extend in the x direction on the n-type well region 35. In the example shown in FIG. 9, the lengths of the n-type fins 11 and the p-type fins 31 are substantially equal. Further, the length of the p-type fin 21 is approximately half that of the n-type fin 11 and the p-type fin 31. Although not shown, a gate insulating film 17 is formed on the n-type fin 11, the p-type fin 21 and the p-type fin 31 so as to cover them.

  On the n-type fin 11, three electrodes (NM first electrode 12a, NM second electrode 12b, NM third electrode 12c) are formed. These three electrodes extend in the y direction orthogonal to the x direction, and are formed to cross the three n-type fins 11. The NM second electrode 12 b becomes a gate electrode of the NMOS. The NM first electrode 12 a and the NM third electrode 12 c are formed to cover the end of the n-type fin 11.

  In the third embodiment, all of the three electrodes (NM first electrode 12a, NM second electrode 12b, NM third electrode 12c) extend from NMOS region 10 to PRTAP region 20 to PMOS region 30. doing. The NM first electrode 12 a is arranged to cover the other end of the p-type fin 21 and one end of the p-type fin 31. The NM second electrode 12 b covers one end of the p-type fin 21 and is disposed to straddle the p-type fin 31. The NM second electrode 12 b is a gate electrode of the NMOS and a gate electrode of the PMOS.

  The NM third electrode 12 c is disposed to cover the other end of the p-type fin 31. The end of the n-type fin 11 and the end of the p-type fin 31 may be between two side surfaces of the NM first electrode 12a and the NM third electrode 12c extending in the longitudinal direction. Further, the end of the p-type fin 21 may be between the two side surfaces of the NM second electrode 12 b and the NM third electrode 12 c extending in the longitudinal direction.

  In the NMOS region 10, the NM first wiring layer 13a is formed between the NM first electrode 12a and the NM second electrode 12b. The NM first electrode 12 a is connected to the NM first wiring layer 13 a via the NM connection wiring layer 14. Further, in the NMOS region 10, the NM second wiring layer 13b is formed between the NM second electrode 12b and the NM third electrode 12c. In the PWTAP region 20, a PWTAP wiring layer 23 is formed between the NM first electrode 12a and the NM second electrode 12b. The PWTAP wiring layer 23 is connected to the power supply potential VSS.

  In the PMOS region 30, a PM first wiring layer 33a is formed between the NM first electrode 12a and the NM second electrode 12b. The NM first electrode 12 a is connected to the PM first wiring layer 33 a via the PM connection wiring layer 34. In the PMOS region 30, a PM second wiring layer 33b is formed between the NM second electrode 12b and the NM third electrode 12c.

  The gate contact 24 is connected to the NM second electrode 12 b. Gate contact 24 is formed on the boundary between PWTAP region 20 and PMOS region 30. Therefore, in the semiconductor device 1B, the gate electrodes of the NMOS and PMOS formed on both sides of the PWTAP region 20 and the drains thereof are connected to each other, resulting in a circuit configuration shown in FIG.

  As described above, in the third embodiment, the NM first electrode 12 a on the PWTAP region 20 can function as a wire for transmitting signals other than the power supply. Also, the metal layer for gate contact can be separated from the source and drain. This makes it possible to prevent wiring congestion and reduce the area of the semiconductor device.

  In the third embodiment, in the PWTAP region 20, the diffusion layer (p-type fin 21) is cut below the NM first electrode 12a and the NM second electrode 12b. That is, the p-type fins 21 are disposed in the range from the NM first electrode 12 a to the NM second electrode 12 b. Therefore, as compared with the fourth embodiment described below, there is no PWTAP wiring layer 23 connected to the power supply potential VSS on the left side of the NM second electrode 12b, and there is an effect that the parasitic capacitance therebetween is reduced. This effect is the same in the PWTAP region 20 of FIG.

Fourth Embodiment
A semiconductor device 1C according to the fourth embodiment will be described with reference to FIGS. FIG. 12 is a plan view showing the configuration of the semiconductor device 1C, and FIG. 13 is a circuit diagram of the semiconductor device 1C. 14 is a cross-sectional view taken along line XIV-XIV of FIG. 12, and FIG. 15 is a cross-sectional view taken along line XV-XV of FIG. The semiconductor device 1C of the fourth embodiment is a modification of the semiconductor device 1B of the third embodiment.

  As shown in FIG. 12, the semiconductor device 1C includes an NM fourth electrode 12d in addition to the three electrodes 12a to 12c of the semiconductor device 1B. The NM fourth electrode 12 d is provided on the opposite side of the NM first electrode 12 a to the NM second electrode 12 b in the x direction. The four electrodes 12a to 12d are arranged in the x direction at predetermined intervals. Each of the four electrodes 12 a to 12 d extends from the NMOS region 10 to the PMOS region 30 beyond the PWTAP region 20. The NM first electrode 12a connects the drain of the NMOS and the drain of the PMOS. The NM second electrode 12 b is a gate electrode of NMOS and PMOS. Therefore, the circuit configuration of the semiconductor device 1C is as shown in FIG.

  Unlike the semiconductor device 1B, in the semiconductor device 1C, the NM first electrode 12a connecting the drains of the NMOS and PMOS and the p-type fin 21 under the NM second electrode 12b serving as the gate electrodes of the NMOS and PMOS are disconnected. Absent. That is, the p-type fin 21 extends from the NM third electrode 12c to below the NM second electrode 12b and the NM first electrode 12a to the NM fourth electrode 12d.

  In the PWTAP region 20, a PWTAP wiring layer 23 is provided between the NM first electrode 12a and the NM fourth electrode 12d. The PWTAP wiring layer 23 is connected to the power supply potential VSS. Although omitted in FIGS. 14 and 15, a gate insulating film 17 is formed on the n-type fin 11, the p-type fin 21 and the p-type fin 31 so as to cover them.

  As described above, also in the fourth embodiment, concentration of lead-in metal for drain contact and gate contact can be avoided, and the area of the semiconductor device can be reduced.

Embodiment 5
A semiconductor device 1D according to the fifth embodiment will be described with reference to FIGS. FIG. 16 is a plan view showing the configuration of the semiconductor device 1D, and FIG. 17 is a circuit diagram of the semiconductor device 1D. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII of FIG.

  In the NMOS region 10, three n-type fins 11 are formed on the p-type well region 15 so as to extend in the x direction. In the PWTAP region 20, two p-type fins 21 are formed on the p-type well region 15 so as to extend in the x direction. In the PMOS region 30, three p-type fins 31 are formed to extend in the x direction on the n-type well region 35. In the example shown in FIG. 16, the lengths of the n-type fin 11, the p-type fin 21 and the p-type fin 31 are equal. Although not shown, a gate insulating film 17 is formed on the n-type fin 11, the p-type fin 21 and the p-type fin 31 so as to cover them.

  On the n-type fin 11, three electrodes (NM first electrode 12a, NM second electrode 12b, NM third electrode 12c) are formed. These three electrodes extend in the y direction orthogonal to the x direction, and are formed to cross the three n-type fins 11. The NM second electrode 12 b becomes a gate electrode of the NMOS. The NM first electrode 12 a and the NM third electrode 12 c are formed to cover the end of the n-type fin 11.

  In the fifth embodiment, the NM first electrode 12 a and the NM third electrode 12 c extend from the NMOS region 10 to the PMOS region 30 beyond the PWTAP region 20. The NM first electrode 12 a covers one end of the p-type fin 21 and the p-type fin 31. The NM third electrode 12 c covers the other end of the p-type fin 21 and the p-type fin 31. As described above, with regard to the positions of the end portions of the n-type fin 11, the p-type fin 21, and the p-type fin 31, as described above, the two extending in the longitudinal direction of the NM first electrode 12a or NM third electrode 12c. It should be between the sides.

  In the NMOS region 10, the NM first wiring layer 13a is formed between the NM first electrode 12a and the NM second electrode 12b. The NM first electrode 12 a is connected to the NM first wiring layer 13 a via the NM connection wiring layer 14. Further, in the NMOS region 10, the NM second wiring layer 13b is formed between the NM second electrode 12b and the NM third electrode 12c.

  In the PWTAP region 20, the PWTAP electrode 22 is formed so as to straddle a substantially central portion of the p-type fin 21. Although not shown in FIG. 18, a gate insulating film 17 is formed between the p-type fin 21 and the PWTAP electrode 22. Between the PWTAP electrode 22 and the NM first electrode 12a and the NM third electrode 12c, a PWTAP first wiring layer 23a and a PWTAP second wiring layer 23b are formed, respectively. The PWTAP first wiring layer 23 a, the PWTAP second wiring layer 23 b, and the PWTAP electrode 22 are connected by the PWTAP connection wiring layer 25. The PWTAP connection wiring layer 25 is connected to the power supply potential VSS.

  In the PMOS region 30, a PM electrode 32 is formed so as to straddle a substantially central portion of the p-type fin 31. Although not shown in FIG. 18, a gate insulating film 17 is formed between the p-type fin 31 and the PM electrode 32. A PM first wiring layer 33a and a PM second wiring layer 33b are formed between the PM electrode 32 and the NM first electrode 12a and the NM third electrode 12c, respectively. The NM first electrode 12 a is connected to the PM first wiring layer 33 a via the PM connection wiring layer 34. The NM first electrode 12a connects the drain of the NMOS and the drain of the PMOS. Accordingly, the semiconductor device 1D has a circuit configuration shown in FIG.

  Thus, in the fifth embodiment, the PWTAP electrode 22 on the PWTAP region 20 is separated from the gate electrodes of PMOS and NMOS. The PWTAP electrode 22 is disposed only in the PWTAP region 20 and connected to the power supply. Also in such a configuration, concentration of lead-in metal for drain contact can be avoided, and the area of the semiconductor device can be reduced.

Sixth Embodiment
A semiconductor device 1E according to the sixth embodiment will be described with reference to FIGS. FIG. 19 is a plan view showing the configuration of the semiconductor device 1E, and FIG. 20 is a circuit diagram of the semiconductor device 1E. 21 is a cross-sectional view taken along line XXI-XXI of FIG. The semiconductor device 1E of the sixth embodiment is a modification of the semiconductor device 1D of the fifth embodiment, and the description of the same configuration as that of the fifth embodiment will be omitted.

  As shown in FIG. 19, in the semiconductor device 1E, the NM second wiring layer 13b of the NMOS region 10 extends to the PWTAP region 20. That is, the source of the NMOS is connected to the power supply potential VSS by the metal layer M0_V. The drain of the NMOS and the drain of the PMOS are connected by the NM first electrode 12a. Accordingly, the semiconductor device 1E has a circuit configuration shown in FIG. Although the element isolation film 16 and the gate insulating film 17 are not shown in the cross-sectional view shown in FIG. 21, the gate insulating film 17 includes n-type fins 11 and p-type as in the above embodiment. The fins 21 and the p-type fins 31 are stacked.

  As described above, the metal layers M0_V in the respective regions may be connected to each other unless the metal layers M0_V are connected to different power supplies. Also in the first to fifth embodiments described above, the metal layers M0_V in each region may be connected to each other.

Embodiment 7
A semiconductor device 1F according to the seventh embodiment will be described with reference to FIGS. FIG. 22 is a plan view showing the configuration of the semiconductor device 1F. FIG. 23 is a view from the XXIII-XXIII cutting line in FIG. 22 in the arrow direction, and FIG. 24 is a view from the XXIV-XXIV cutting line in FIG. 22 in the arrow direction.

  As shown in FIG. 22, the semiconductor device 1F includes the PWTAP region 20 and the NWTAP region 40, and does not include a transistor. The PWTAP region 20 and the NWTAP region 40 are disposed opposite to each other. As shown in FIG. 23, in the PWTAP region 20, a p-type well region 15 is formed on the semiconductor substrate. As shown in FIG. 24, in the NWTAP region 40, an n-type well region 42 is formed on the semiconductor substrate. Thus, in the seventh embodiment, the well regions respectively formed in the PWTAP region 20 and the NWTAP region 40 have different conductivity types.

  In the p-type well region 15 and the n-type well region 42, an element isolation film 16 and an element isolation film 45 which respectively define active regions are formed. In the PWTAP region 20, p-type fins 21 are provided on the p-type well region 15. In the example shown in FIG. 22, three p-type fins 21 extending in the x direction are formed to be arranged at predetermined intervals in the y direction. The p-type fin 21 and the p-type well region 15 have the same conductivity type. In the NWTAP region 40, an n-type fin 41 is provided on the n-type well region 42. In the example shown in FIG. 22, three n-type fins 41 extending in the x direction are formed to be arranged at predetermined intervals in the y direction. The n-type fin 41 and the n-type well region 42 have the same conductivity type.

  Six PWTAP electrodes 22 are formed on the p-type fins 21. The PWTAP electrode 22 extends in the y direction orthogonal to the x direction and intersects three p-type fins 21. The PWTAP electrode 22 is formed to straddle the p-type fin 21 as described in FIG. Although not shown in FIG. 23, the gate insulating film 17 is formed on the entire lower surface of the PWTAP electrode 22 so as to cover the p-type fin 21.

  Six PWTAP electrodes 22 extend from PWTAP region 20 to NWTAP region 40. Each PWTAP electrode 22 is arranged to straddle the n-type fin 41. Although not shown in FIG. 24, the gate insulating film 17 is formed on the entire lower surface of the PWTAP electrode 22 so as to cover the n-type fin 41. Therefore, the gate insulating film 17 is formed between the p-type fin 21 and the n-type fin 41 and the PWTAP electrode 22.

  Among the six PWTAP electrodes 22, the PWTAP electrodes 22 disposed at both ends are formed so as to cover the end of the p-type fin 21 and the end of the n-type fin 41. As in FIGS. 4 and 25, the end portions of the p-type fin 21 and the n-type fin 41 are in the range from the inner end to the outer end of the PWTAP first electrode 22a and PWTAP second electrode 22b. Can be placed.

  In the PWTAP region 20, the PWTAP wiring layer 23 is formed between the PWTAP electrodes 22. The PWTAP wiring layer 23 is made of the above-described metal layer M0_V. A PRTAP connection wiring layer 25 is formed on the PRTAP electrodes 22 disposed first, third, and fifth from the right on the p-type fin 21 disposed in the center. The PWTAP connection wiring layer 25 is connected to the power supply potential VSS. The PWTAP connection wiring layer 25 is made of the above-described metal layer M0_H. The p-type fin 21 supplies the power supply potential VSS to the p-type well region 15 to fix the p-type well region 15 at a constant potential.

  In the NWTAP region 40, an NWTAP wiring layer 43 is formed between the PWTAP electrodes 22. The NWTAP wiring layer 43 is also made of the above-mentioned metal layer M0_V. An NWTAP connection wiring layer 44 is formed on the PRTAP electrodes 22 arranged second, fourth and sixth from the right on the n-type fin 41 arranged in the center. The NWTAP connection wiring layer 44 is connected to the power supply potential VDD. The n-type well region 42 supplies the power supply potential VDD to the n-type well region 42 and fixes the n-type well region 42 at a constant potential. The NWTAP connection wiring layer 44 is also made of the above-described metal layer M0_H.

  As described above, in the seventh embodiment, the PWTAP connection wiring layer 25 and the NWTAP connection wiring layer 44 respectively connected to the power supply potentials VSS and VDD are alternately disposed on the PWTAP electrode 22. This makes it possible to form a VDD / VSS varactor element with the same TAP area. Therefore, the decoupling capacitance can be increased, and the stability of the power supply can be increased.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the embodiment mentioned already, A various change in the range which does not deviate from the gist It goes without saying that it is possible.

(Supplementary Note 1)
A semiconductor substrate,
A first well provided in the semiconductor substrate;
A second well provided on the semiconductor substrate;
A first fin on the first well;
A second fin on the second well;
A first electrode connected to the first and second fins;
Have
The semiconductor device, wherein the first well and the first fin have the same conductivity type, and the second well and the second fin have different conductivity types.

(Supplementary Note 2)
The semiconductor device according to claim 1, wherein the first well and the second well have the same conductivity type.

(Supplementary Note 3)
The semiconductor device according to claim 1, wherein the first well and the second well are of different conductivity types.

(Supplementary Note 4)
A third fin on the second well,
A second electrode connected to the second and third fins;
The semiconductor device according to claim 1, further comprising

(Supplementary Note 5)
The semiconductor device according to claim 4, wherein the second electrode is also connected to the first fin.

(Supplementary Note 6)
The semiconductor device according to claim 4, further comprising: a third electrode connected to the second and third fins and provided between the first electrode and the second electrode in a plan view.

(Appendix 7)
The semiconductor device according to claim 6, wherein the third electrode is also connected to the first fin.

(Supplementary Note 8)
A third fin on the first well;
A second electrode connected to the first and third fins;
The semiconductor device according to claim 1, further comprising

(Appendix 9)
The semiconductor device according to appendix 8, wherein the second electrode is also connected to the second fin.

(Supplementary Note 10)
The semiconductor device according to claim 8, further comprising a third electrode connected to the first and third fins and provided between the first electrode and the second electrode in plan view.

(Supplementary Note 11)
The semiconductor device according to claim 10, wherein the third electrode is also connected to the second fin.

(Supplementary Note 12)
The semiconductor device according to claim 10, wherein the third electrode is connected to a first potential.

(Supplementary Note 13)
A semiconductor substrate,
A first well provided in the semiconductor substrate;
A second well provided on the semiconductor substrate;
A first fin type transistor provided in the first well;
A fin provided in the second well;
Have
An electrode of the first fin-type transistor is connected to the fin provided in the second well,
The first well and the first fin-type transistor are of different conductivity types,
The semiconductor device, wherein the second well and the fin have the same conductivity type.

(Supplementary Note 14)
A semiconductor substrate,
A first well provided in the semiconductor substrate;
A second well provided on the semiconductor substrate;
A first fin on the first well;
A second fin on the second well;
A first electrode connected to the first and second fins;
Have
The first well and the first fin are of the same conductivity type,
The second well and the second fin are of the same conductivity type,
The semiconductor device, wherein the first well and the second well have different conductivity types.

(Supplementary Note 15)
A semiconductor substrate,
A first conductivity type well provided in the semiconductor substrate;
A first conductive type first fin on the first conductive type well,
A first conductivity type second fin on the first conductivity type well;
A second conductive third fin on the first conductive well;
A first electrode connected to the first and second fins;
A second electrode connected to the first and third fins.

(Supplementary Note 16)
A semiconductor substrate,
A first conductivity type well provided in the semiconductor substrate;
A second conductivity type well provided in the semiconductor substrate;
A first conductive type first fin on the first conductive type well,
A first conductivity type second fin on the first conductivity type well;
A first conductive third fin on the second conductive well;
A first electrode connected to the first and second fins;
A second electrode connected to the first and third fins.

(Supplementary Note 17)
The semiconductor device according to claim 4, wherein the first electrode is also connected to the third fin.

(Appendix 18)
The semiconductor device according to appendix 8, wherein the first electrode is also connected to the third fin.

Reference Signs List 1 semiconductor device 1A to 1F semiconductor device 10 NMOS region 11 n-type fin 12a NM first electrode 12b NM second electrode 12c NM third electrode 12d NM fourth electrode 13a NM first wiring layer 13b NM second wiring layer 14 NM connection Wiring layer 15 p-type well area 16 element isolation film 17 gate insulating film 20 pwtap area 21 p-type fin 22 pwtap electrode 22 a pwtap first electrode 22 b pwtap second electrode 23 pwtap wiring layer 23 a pwtap first wiring layer 23 b pwtap second wiring Layer 24 Gate contact 25 PRTAP connection wiring layer 30 PMOS region 31 p-type fin 32 PM electrode 33a PM first wiring layer 33 b PM second wiring layer 34 PM connection wiring layer 35 n-type well region 40 NWTAP region 41 n-type fin 42 n Mold well area 43 NWTAP wiring layer 44 NWTAP connection wiring layer 45 isolation film

Claims (10)

A semiconductor substrate,
A first well region provided in the semiconductor substrate;
A first fin provided integrally with the semiconductor substrate on the first well region and extending in a first direction in a plan view;
A first electrode formed on the first fin via a first gate insulating film, and extending in a second direction intersecting the first direction in the plan view;
A tap region provided adjacent to the first well region in the second direction in the semiconductor substrate and supplying a first potential to the first well region;
A second fin formed integrally with the semiconductor substrate on the tap region and extending in the first direction in the plan view;
The second fin is formed to extend in the second direction on the second fin at a position overlapping the tap area in the plan view, and the first well area is formed via the second fin and the tap area. A first wiring layer for supplying the first potential to the
The semiconductor device, wherein the first electrode is formed on the second fin via a second gate insulating film. A second well region provided on the semiconductor substrate opposite to the first well region with respect to the tap region in the second direction;
And a third fin integrally provided with the semiconductor substrate on the second well region and extending in the first direction in the plan view;
The semiconductor device according to claim 1, wherein the first electrode is formed on the third fin via a third gate insulating film in the plan view. The first well region, the second well region, and the tap region are of a first conductivity type,
The first fin is a second conductivity type different from the first conductivity type, and the third fin is a second conductivity type.
The first fin is provided with a first source region and a first drain region of a first field effect transistor,
The third fin is provided with a second source region and a second drain region of a second field effect transistor,
The semiconductor device according to claim 2, wherein the first electrode is connected to the first source region or the first drain region, and connected to the second source region or the second drain region. . The first well region and the tap region are of a first conductivity type,
The first fin is a second conductivity type different from the first conductivity type,
The third fin is of the first conductivity type,
The semiconductor device according to claim 2, wherein the second well region is of the second conductivity type. The first fin is provided with a first source region and a first drain region of a first field effect transistor,
The third fin is provided with a second source region and a second drain region of a second field effect transistor,
The semiconductor device according to claim 4, wherein the first electrode is connected to the first source region or the first drain region, and is connected to the second source region or the second drain region. . The first fin is provided with a first source region and a first drain region of a first field effect transistor,
The third fin is provided with a second source region and a second drain region of a second field effect transistor,
The semiconductor device according to claim 2, wherein the first gate electrode of the first field effect transistor and the second gate electrode of the second field effect transistor comprise the first electrode.   The semiconductor device according to claim 1, wherein the first electrode is formed to cover an end of the second fin on the tap region. It is formed on the first fin, the second fin and the third fin via the fourth gate insulating film, the fifth gate insulating film and the sixth gate insulating film, respectively, and the second Further comprising a second electrode (12c) extending in the
The second electrode includes an end of the first fin, an end of the second fin, and the third via the seventh gate insulating film, the eighth gate insulating film, and the ninth gate insulating film, respectively. The semiconductor device according to claim 2, wherein the semiconductor device is formed to cover the ends of the fins. And a second wire extending in the second direction and disposed on the second fin and the third fin,
The first well region and the tap region are of a first conductivity type,
The first fin is a second conductivity type different from the first conductivity type,
The third fin is of the first conductivity type,
The second well region is of the second conductivity type,
The first fin is provided with a first source region and a first drain region of a first field effect transistor,
The third fin is provided with a second source region and a second drain region of a second field effect transistor,
The second wiring is formed on the second source region or the second drain region, and is electrically connected to the second source region or the second drain region. The semiconductor device of description. A semiconductor substrate,
A first tap region of a first conductivity type provided on the semiconductor substrate;
A second tap region of a second conductivity type which is disposed adjacent to the first tap region in the first direction in a plan view, and which is different from the first conductivity type;
A first fin integrally provided on the first tap region with the semiconductor substrate and extending in a second direction intersecting the first direction;
A second fin integrally provided on the second tap region with the semiconductor substrate and extending in the second direction;
A first electrode extending in the first direction and disposed on the first fin and the second fin via a first gate insulating film and a second gate insulating film, respectively;
A second different from the first electrode, which extends in the first direction and is disposed on the first fin and the second fin via a third gate insulating film and a fourth gate insulating film, respectively. An electrode,
A first connection wiring layer provided on the first electrode and supplying a first potential to the first electrode;
A second connection wiring layer provided on the second electrode and supplying a second potential different from the first potential to the second electrode;
A first wiring layer disposed between the first electrode and the second electrode in the second direction and extending in the first direction on the first tap region;
A semiconductor comprising: a second wiring layer disposed between the first electrode and the second electrode in the second direction and extending in the first direction on the second tap region apparatus.

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