JP2019069318A - Game machine - Google Patents

Abstract

To provide a game machine capable of properly updating numeric information.SOLUTION: A main control board 301 includes: a hard random number clock circuit 313 for outputting a hard random number clock signal; and an MPU 311 for controlling a progress of games. The MPU 311 includes a counter circuit 317 for updating a big win random number counter on the basis of an input of the hard random number clock signal from the hard random number clock circuit 313. Here, the main control board 301 includes a modulation circuit 314 for varying an update interval of the big win random number counter. Therefore, it is difficult to identify the update timing of the big win random number counter.SELECTED DRAWING: Figure 14

Description

  The present invention relates to a gaming machine.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Whether or not the jackpot state occurs is determined at the timing when the gaming ball enters the operation opening. For example, it has a counter that is regularly updated within a certain range (for example, 1 count is updated in the range of 0 to 300 every 2 ms), and acquires the value of the counter when the gaming ball enters the operation opening Then, when the value of the counter matches a predetermined winning value such as "7", for example, a bonus is given to the player in which the gaming state shifts to the jackpot state (see, for example, Patent Document 1).

JP 2004-756 A

  Here, it is preferable that the update of the counter used in the jackpot lottery be performed well. For example, by grasping | ascertaining the update timing etc. of the counter used by a big hit lottery, the timing from which the value of the said counter turns into a value corresponding to a big hit may be grasped | ascertained. Then, it is conceivable that the fraudulent act of intentionally generating a jackpot by outputting an illegal signal to the regular control board in accordance with the timing.

  Also, for example, from the viewpoint of reducing the capacity required for the counter, it is preferable that the possible range of the counter used in the jackpot lottery is narrow. However, if the range of the counter used in the jackpot lottery narrows, the probability of winning derived from the range and the winning value becomes high, which may cause inconvenience that the desired probability of winning can not be set.

  In addition, the above-mentioned problem is the same also in other gaming machines which make a lottery using a counter.

  The present invention has been made in view of the above-described circumstances and the like, and it is an object of the present invention to provide a gaming machine capable of satisfactorily updating numerical information.

The present invention
Gaming signal output means for outputting a gaming clock signal;
Control means for controlling the progress of the game based on the game clock signal being input from the game signal output means;
Numerical information updating means for sequentially updating numerical information within a predetermined numerical range each time an update timing is reached;
Acquisition means for acquiring the numerical information from the numerical information update means when predetermined acquisition conditions are satisfied;
Equipped with
In a gaming machine which is in a specific state based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined specific information,
The game signal output means is provided separately from the game signal output means, and includes update signal output means for outputting an update clock signal so as not to be synchronized with the game clock signal.
The numerical information update means sequentially updates the numerical information based on the input of the update clock signal, using a predetermined place from the rise to the fall of the update clock signal as a trigger.
A variable means for changing an interval to be updated from the numerical information of 1 to the next numerical information;
The variation means varies the period required for the numerical information to make one revolution in response to the numerical information making one revolution by changing the period in which the numerical information becomes the specific information. The period in which the numerical information is the specific information is sequentially transitioned to any of a plurality of types of periods, and the unit period for the plurality of specific cycles of the numerical information is required to be specified. The ratio of the period in which the numerical information is the specific information is the same or substantially the same for each unit period,
The numerical value information updating means is configured to repeat the updating of the numerical value information corresponding to the update group having a plurality of update timings and having a plurality of types of update intervals, in the unit of the update group.
The numerical range and the update timing are set such that the number of terms in the numerical sequence constituted by the numerical values that can be acquired by the numerical information is not a multiple of the number of update timings included in the update group. Do.

  According to the present invention, numerical information can be updated well.

It is a front view showing a pachinko machine in a 1st embodiment. It is a perspective view which expands and shows the main composition of a pachinko machine. It is a perspective view which expands and shows the main composition of a pachinko machine. It is a rear view which shows the structure of a pachinko machine. It is a rear view which shows the structure of a front door frame. It is a front view which shows the structure of a main body frame. It is a front view which shows the structure of a game board. It is a rear view which shows the structure of a main body frame. It is a perspective view showing the back composition of a game board. It is a rear view which shows the state which removed the main control unit from the game board. It is a perspective view showing the composition of the main control unit. It is a front view which shows the structure of a back pack unit. It is an exploded perspective view of a back pack unit. It is a block diagram which shows the electric constitution of a pachinko machine. Explanatory drawing which shows the outline | summary of the various counters used for game control. It is a flowchart which shows NMI interrupt processing by MPU of a main control board. It is a flowchart which shows the timer interruption process by MPU of a main control board. It is a flow chart which shows starting winning a prize processing. It is a flowchart which shows main processing. It is a flowchart which shows normal processing. It is a block circuit diagram showing composition of a clock circuit for hard random numbers. It is a timing chart for explaining the operation of the hard random number clock circuit. It is a timing chart for explaining the relation between a pulse signal group and a big hit random number counter. It is a flowchart which shows the timer interruption process in 2nd Embodiment. It is a timing chart for explaining the relation between the pulse signal group and the big hit random number counter in a 3rd embodiment. It is a part of block diagram which shows the electric constitution of the pachinko machine in 4th Embodiment. It is a block diagram which shows the electric constitution of the pachinko machine in 5th Embodiment. It is an explanatory view showing an outline of various counters used for game control. It is a flowchart which shows timer interruption processing. It is a flow chart which shows starting winning a prize processing. It is a block circuit diagram for demonstrating the structure regarding an irregular delay circuit. It is a timing chart for explaining the operation of the irregular delay circuit when the power is turned on. It is a block circuit diagram for demonstrating the structure regarding the irregular delay circuit in 6th Embodiment. It is a block diagram which shows the electric constitution of the pachinko machine in 7th Embodiment. It is a block circuit diagram for demonstrating the structure regarding an irregular delay circuit. It is a timing chart for explaining the operation of the irregular delay circuit when the power is turned on. It is a block circuit diagram for demonstrating the structure regarding the irregular delay circuit in 8th Embodiment. FIG. 21 is a timing chart for explaining the operation of the irregular delay circuit when the power is turned on in the eighth embodiment. It is a block circuit diagram for demonstrating the structure regarding the irregular delay circuit in 9th Embodiment. In 9th Embodiment, it is a timing chart for demonstrating the operation | movement of the irregular delay circuit at the time of power supply being switched on. It is a block circuit diagram for demonstrating the structure regarding the irregular delay circuit in 10th Embodiment. In 10th Embodiment, it is a timing chart for demonstrating the operation | movement of the irregular delay circuit at the time of power supply being switched on. It is a block circuit diagram for demonstrating the structure regarding the irregular delay circuit in 11th Embodiment. In 11th embodiment, it is a timing chart for explaining the operation of the irregular delay circuit when the power is turned on. It is a block diagram which shows the electric constitution of the pachinko machine in 12th Embodiment. It is a flowchart which shows main processing. It is a block diagram which shows the electric constitution of the pachinko machine in 13th Embodiment. It is a block circuit diagram for demonstrating the structure regarding an irregular delay circuit. It is a flowchart which shows the normal processing in 14th Embodiment. It is a block diagram which shows the electric constitution of the pachinko machine in 15th Embodiment. It is a block circuit diagram for demonstrating the structure regarding a power transfer circuit. It is a block diagram which shows the electric constitution of the pachinko machine in 16th Embodiment. It is a block circuit diagram for demonstrating the structure regarding a power transfer circuit. It is a timing chart for explaining the operation of the irregular delay circuit. It is a block diagram which shows the electric constitution of the pachinko machine in 17th Embodiment. It is a block circuit diagram for demonstrating the structure regarding a power transfer circuit. It is a flow chart which shows jackpot judging processing. It is a flow chart which shows a modification of timer interrupt processing in a 2nd embodiment. It is a block diagram which shows the modification of 17th Embodiment.

First Embodiment
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as "pachinko machine"), which is a type of gaming machine, will be described in detail based on the drawings. FIG. 1 is a front view of a pachinko machine 10, FIGS. 2 and 3 are exploded perspective views showing main components of the pachinko machine 10, and FIG. 4 is a rear view of the pachinko machine 10. In addition, in FIG. 2, the structure in the game area of the pachinko machine 10 is abbreviate | omitted for convenience.

  The pachinko machine 10 has an outer frame 11 forming an outer shell of the pachinko machine 10 and a gaming machine main unit 12 rotatably attached to the outer frame 11 in a forward direction. The outer frame 11 is configured by connecting wooden plate members to four sides, and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by fixing the outer frame 11 to the island facility.

  The gaming machine main part 12 includes a main body frame 13 as a base body, a front door frame 14 disposed in front of the main body frame 13, and a back pack unit 15 disposed rearward of the main body frame 13. . The main body frame 13 of the gaming machine main portion 12 is rotatably supported relative to the outer frame 11. In detail, the main body frame 13 is pivotable forward with the left side as a pivoting base end and the right side as a pivoting tip side in a front view.

  As shown in FIG. 2, the front door frame 14 is rotatably supported by the main body frame 13, and can be rotated forward with the left side as the rotation base end side and the right side as the rotation tip end side in front view It is assumed. Further, as shown in FIG. 3, the back pack unit 15 is rotatably supported by the main body frame 13, and the front side views the left side as the rotation base end side and the right side as the rotation tip end side. It is made movable.

  Next, the front door frame 14 will be described. In the following description, FIG. 1 to FIG. 3 will be referred to, and FIG. 5 will be referred to for the configuration of the back surface of the front door frame 14. FIG. 5 is a rear view of the front door frame 14.

  The front door frame 14 is provided so as to cover the entire front surface side of the main body frame 13. The front door frame 14 is formed with a window portion 21 which enables the player to visually recognize substantially the entire game area, which will be described later, from the front. The window portion 21 has a substantially elliptical shape, and a transparent glass 22 is inserted therein. Around the window 21, light emitting means such as various lamps are provided. For example, along the peripheral edge of the window portion 21, an annular lamp portion 23 incorporating light emitting means such as an LED is provided. The annular lamp unit 23 is lighted or blinked according to a change in the gaming state at the time of a jackpot or a predetermined reach. In addition, an error display lamp unit 24 is provided at the center of the annular lamp unit 23 and at the top of the pachinko machine 10 and is lighted at the time of a predetermined error. A lamp unit 25 is provided. In addition, a speaker unit 26 is provided at a position close to the right and left prize ball lamp units 25 to which sound effects and the like according to the game state are output.

  Below the window portion 21 of the front door frame 14, an upper bulging portion 31 and a lower bulging portion 32 bulging toward the front side are vertically arranged in parallel. An upper plate 33 opened upward is provided inside the upper bulging portion 31, and a lower plate 34 opening similarly upward is provided inside the lower bulging portion 32. The upper tray 33 has a function for temporarily storing game balls paid out from the later described payout device and guiding the game balls to the game ball launch mechanism side described later while aligning them in a line. Further, the lower tray 34 has a function of storing the game balls which become surplus in the upper tray 33.

  A game ball emission handle 41 is provided on the right side of the lower side bulging portion 32 so as to protrude to the front side. By operating the game ball emission handle 41, a game ball is emitted from a game ball emission mechanism described later.

  As shown in FIGS. 2 and 5, a passage forming unit 50 is attached to the back of the front door frame 14. The passage forming unit 50 is formed of a synthetic resin, and a front door upper tray passage 51 communicating with the upper tray 33 and a front door lower tray passage 52 communicating with the lower tray 34 are formed. In the passage forming unit 50, a receiving portion 53 which protrudes rearward and is opened upward is formed at the upper corner portion, and the receiving portion 53 is divided into right and left portions by a partition wall 54, thereby front door side upper plate A passage 51 and an inlet portion of the front door side lower countersink passage 52 are formed. The front door side upper plate passage 51 and the front door side lower plate passage 52 communicate with the game ball distribution unit, the upstream side of which is described later, and the game balls entering the front door side upper plate passage 51 are guided to the upper plate 33 The gaming balls having entered the door side lower plate passage 52 are guided to the lower plate 34.

  Protruding shafts 61 and 62 are provided on the upper end portion and the lower end portion of the rotation base end side (right side in FIG. 5) on the back surface of the front door frame 14. The projection shafts 61 and 62 constitute an assembly mechanism with respect to the main body frame 13. In addition, as shown in FIG. 2, a plurality of rivets 63 extending rearward is juxtaposed in the vertical direction on the pivoting tip side (left side in FIG. 5) on the back surface of the front door frame 14. These hooks 63 constitute a locking mechanism for the main body frame 13.

  Next, the main body frame 13 will be described in detail. FIG. 6 is a front view of the main body frame 13.

  The main body frame 13 mainly includes a resin base 71 having an outer shape substantially the same as that of the outer frame 11. Support metal fittings 72 and 73 are attached to the upper end portion and the lower end portion of the rotation base end side (left side in FIG. 6) on the front surface of the resin base 71. Although illustration is omitted, shaft holes are formed in the support fittings 72 and 73, and the projection shafts 61 and 62 of the front door frame 14 are inserted into these shaft holes, whereby the front door relative to the main body frame 13 is formed. The frame 14 is rotatably supported.

  In the front end of the resin base 71 on the rotating tip side (right side in FIG. 6), an insertion hole 74 for inserting a hook fitting 63 provided on the back of the front door frame 14 is provided. In the pachinko machine 10, a locking device for locking the main body frame 13 and the front door frame 14 is disposed so as to be hidden behind the rear side of the main body frame 13. Therefore, the front door frame 14 is locked to the main body frame 13 so as not to be opened by the hook fitting 63 being locked to the locking device through the insertion hole 74.

  At the lower right corner of the resin base 71, a cylinder lock 75 for unlocking the locking device is installed. The cylinder lock 75 is integrated with the locking device, and when the key inserted into the key hole of the cylinder lock 75 is turned to the right, the lock of the front door frame 14 with respect to the main body frame 13 is unlocked. When the key inserted into the key hole of the cylinder lock 75 is turned to the left, the locking of the main body frame 13 with respect to the outer frame 11 is released.

  A substantially elliptical window hole 76 is formed in the central portion of the resin base 71. A game board 81 is detachably attached to the resin base 71. The game board 81 is made of plywood, and the game area formed on the front face of the game board 81 is exposed to the front side of the main body frame 13 through the window hole 76 of the resin base 71.

  Here, the configuration of the game board 81 will be described based on FIG. The gaming board 81 is formed with a plurality of large and small openings penetrating in the front-rear direction by being subjected to router processing. At each opening, a general winning opening 82, a variable winning device 83, an operation opening 84, a through gate 85, a variable display unit 86 and the like are provided. There are four general winning openings 82, two each on the left and right respectively. When the game ball enters the general winning opening 82, the variable winning device 83 and the operation opening 84, it is detected by a detection switch described later, and a predetermined number of payouts are executed based on the detection result. In addition, an out port 87 is provided at the lowermost portion of the game board 81, and game balls which have not entered the various winning ports etc. are discharged from the game area through the out port 87. Further, on the game board 81, a large number of nails 88 are implanted in order to appropriately disperse and adjust the falling direction of the game ball, and various members (features) such as a windmill are disposed.

  The variable display unit 86 is provided with a symbol display device 91 that variably displays symbols by using a winning on the operation opening 84 as a trigger. Further, a center frame 92 is disposed on the variable display unit 86 so as to surround the symbol display device 91. At an upper portion of the center frame 92, a first specific lamp unit 93 and a second specific lamp unit 94 are provided. In addition, holding lamp portions 95 and 96 are provided at the upper and lower portions of the center frame 92, respectively. The lower holding lamp unit 95 corresponds to the symbol display device 91 and the first specific lamp unit 93, and the number of times the game ball passes through the operation opening 84 is held up to four times by lighting of the holding lamp unit 95 The pending number is displayed. The upper holding lamp unit 96 corresponds to the second specific lamp unit 94, and the number of times the game ball passes through the through gate 85 is held up to four times, and the number of holding units is displayed by lighting the holding lamp unit 96. It has become so.

  The symbol display device 91 is configured as a liquid crystal display device provided with a liquid crystal display, and the display content is controlled by a display control device described later. On the symbol display device 91, for example, symbols are displayed side by side on the left, in the middle, and in the right, and these symbols are displayed so as to be scrolled in the vertical direction. Then, when symbols of a predetermined combination are stopped and displayed on an effective line set in advance, a special gaming state (hereinafter referred to as a jackpot) will occur.

  In the first specific lamp unit 93, the emission color is switched in a predetermined order triggered by the winning of the operation port 84, and when the stop display is performed in a predetermined color, a big hit occurs. Further, in the second specific lamp unit 94, the light emission color is switched in a predetermined order triggered by the passage of the through gate 85 of the game ball, and when it is stopped and displayed in a predetermined color, The accompanying motorized part is open for a predetermined time.

  The variable winning device 83 is normally in a closed state in which the gaming ball can not win or is difficult to win, and is switched to a predetermined open state in which the gaming ball can easily win in the case of a big hit. As an opening aspect of the variable winning device 83, the variable winning device 83 repeatedly repeats a predetermined number of times (for example, 30 seconds) or a predetermined number (for example, 10) of winnings as one round and a plurality of rounds (for example, 15 rounds) as the upper limit. It is common to be open.

  The inner rail portion 101 and the outer rail portion 102 are attached to the game board 81, and the inner rail portion 101 and the outer rail portion 102 constitute a guide rail, which is fired from the game ball launch mechanism described later. The game ball is guided to the top of the game area.

  As shown in FIG. 6, the game ball firing mechanism 110 is attached below the window hole 76 in the resin base 71. The game ball firing mechanism 110 is composed of an electromagnetic solenoid 111, a firing rail 112, and a ball feeding mechanism 113, and the output shaft of the solenoid 111 is moved in the expansion and contraction direction by the input of an electrical signal to the solenoid 111. The ball feeding mechanism 113 strikes the game ball placed on the firing rail 112 toward the game area.

  There is a gap with a predetermined interval between the firing rail 112 and the inner and outer rail portions 101 and 102 attached to the game board 81, and the gap is formed in the passage forming unit 50 of the front door frame 14 below this gap. A foul ball passage 55 is provided. Therefore, if the game ball fired from the game ball firing mechanism 110 does not reach the upper part of the game area, and the guide rail formed by the inner and outer rail portions 101 and 102 is reversed, the far ball is It enters into the ball ball passage 55. The foul ball passage 55 leads to the lower door passage 52 on the front door side, and the gaming ball entering the far ball passage 55 is discharged to the lower plate 34.

  A passage forming portion 121 is provided on the left side of the firing rail 112 in the resin base 71 by penetrating the resin base 71 in the front-rear direction. In the passage forming portion 121, as shown in FIG. 3, a main body side upper countersink path 122 and a main body side lower countersink path 123 are formed. The upstream sides of the main body upper tray passage 122 and the main body lower tray passage 123 communicate with a game ball distribution unit described later. In the lower part of the passage forming part 121, the receiving part 53 of the passage forming unit 50 attached to the front door frame 14 is inserted, and in the lower part of the main body side upper plate passage 122, the front door side upper plate passage 51 is The front door side upper plate passage 51 is disposed below the main body lower plate passage 123.

  Below the passage forming portion 121 in the resin base 71, an opening / closing member 124 for opening / closing the main body side upper countersink passage 122 and the main body side lower countersink passage 123 is attached. The opening and closing member 124 is rotatably supported in the back and forth direction by a support shaft 125 provided at its lower end, and further urges the main body upper disc passage 122 and the main body lower disc passage 123 to a forward position closing them. A biasing member is provided. Therefore, when the front door frame 14 is opened with respect to the main body frame 13, the opening and closing member 124 ascends as shown in the drawing to close the main body upper countersink passage 122 and the main body lower countersink passage 123. Thereby, when the front door frame 14 is opened in a state where game balls are stored in the main body side upper plate passage 122 or the main body side lower plate passage 123, it is possible to prevent such a problem that the storage balls spill out. On the other hand, when the front door frame 14 is closed, the opening / closing member 124 is pushed and opened against the biasing force by the receiving portion 53 provided in the passage forming unit 50 of the front door frame 14. In this state, the main body side upper plate passage 122 and the front door side upper plate passage 51 communicate with each other, and the main body side lower plate passage 123 and the front door side lower plate passage 52 communicate with each other.

  Next, the rear face configuration of the main body frame 13 will be described. FIG. 8 is a rear view of the main body frame 13.

  A locking device 131 is provided on the rotating tip end side (left side in FIG. 8) on the back surface of the resin base 71, and the locking device 131 interlocks with the key operation of the cylinder lock 75, and the main body frame 13 and the front door Unlocking of the frame 14 is performed.

  A bearing fitting 132 is attached to the rotation base end side (right side in FIG. 8) on the back surface of the resin base 71. A bearing portion 133 is formed on the bearing fitting 132 so as to be vertically separated, and the back pack unit 15 is rotatably attached to the main body frame 13 by the bearing portion 133. Further, on the back surface of the resin base 71, a fastening hole 134 for fastening the back pack unit 15 to the main body frame 13 is provided.

  A plurality of locking brackets 135 are provided on the back surface of the resin base 71, and the game board 81 is attached to the resin base 71 by the locking brackets 135 as described above. Here, the configuration of the back of the game board 81 will be described. FIG. 9 is a perspective view of the game board 81 as viewed from the rear, and FIG. 10 is a rear view showing a state where the main control unit 160 is removed from the game board 81. As shown in FIG.

  The variable display unit 86 disposed at the center of the game board 81 is provided with a frame cover 141 made of synthetic resin to cover the center frame 92 from behind and provided to project backward. While the above-mentioned symbol display device 91 is attached, a display control device for driving the symbol display device is attached (illustration is omitted). The symbol display device 91 and the display control device are arranged so as to overlap in the front-rear direction (the symbol display device is in front, the display control device is in back), and the voice lamp control device unit 142 is mounted behind it. The voice lamp controller unit 142 is configured to include a voice lamp controller 143 and a mount 144, and the voice lamp controller 143 is mounted on the mount 144.

  The voice lamp control device 143 comprises a voice lamp control board for controlling voice and lamp display and display control according to an instruction from the main control device described later, and the voice lamp control board is made of a transparent resin material or the like. It is accommodated in the board | substrate box 145, and is comprised.

  On the back of the game board 81, as shown in FIG. 10, a collecting board unit 150 is provided below the variable display unit 86. The collecting plate unit 150 is provided with a game ball collecting mechanism for collecting game balls that have won in various winning openings, and a winning detection mechanism for detecting winning of gaming balls in various winning openings and the like. .

  The game ball collecting mechanism will be described. In the collecting plate unit 150, a collecting passage 151 which corresponds to the gaming board opening of the general winning opening 82, the variable winning device 83, and the operating opening 84 and is gathered in one place downstream. Is formed. Therefore, all the game balls that have won in the general winning opening 82 and the like gather under the game board 81 via the recovery passage 151. Below the game board 81 is a discharge passage, which will be described later. The game balls gathered below the game board 81 by the collection passage 151 are led out into the discharge passage. The out-port 87 is similarly communicated to the discharge passage, and game balls that have not won any of the winning openings are also led out into the discharge path through the out-port 87.

  The winning combination detection mechanism will be described. The collective plate unit 150 is provided with winning opening switches 152a to 152d at positions corresponding to the general winning openings 82 on the front side of the gaming board 81, respectively. Further, a count switch 153 is provided at a position corresponding to the variable winning device 83, and an operation port switch 154 is provided at a position corresponding to the operation port 84. The switches 152 to 154 detect the winning of the game balls, respectively. Further, on the right side of the variable display unit 86 outside the collective plate unit 150, a gate switch 155 for detecting a game ball passing through the through gate 85 is provided. In detail about detection of these switches 152-155, each switch 152-155 is electrically connected to the main control apparatus mentioned later, and in the state which has not detected the game ball, it is a LOW level signal with respect to the main control apparatus. Is outputted, and in the state of detecting the game ball, the HI level signal is outputted to the main control device.

  A main controller unit 160 is mounted on the back of the game board 81 so as to cover the group board unit 150 from the rear side. The configuration of main controller unit 160 will be described with reference to FIG. FIG. 11 is a perspective view showing the configuration of the main controller unit 160. As shown in FIG.

  The main controller unit 160 has a mount 161 made of synthetic resin, and the main controller 162 is mounted on the mount 161. The main control device 162 is provided with a main control board having a function (main control circuit) which controls the main control of the game, and the main control board is accommodated in a substrate box 163 made of transparent resin material or the like. It is done.

  The substrate box 163 is provided with a substantially rectangular parallelepiped box base (front case body) and a box cover (back case body) that covers the opening of the box base. The box base and the box cover are unopenably connected by a sealing unit 164 as sealing means, whereby the substrate box 163 is sealed. Five sealing portions 164 are provided on the long side of the substrate box 163, and at least one of them is used to perform the sealing process.

  The sealing unit 164 may have any configuration as long as a trace remains when the box base and the box cover are opened. However, the locking claw is inserted into the elongated hole constituting the sealing unit 164 to form a box. The base and the box cover are connected unopenably. The sealing process by the sealing unit 164 prevents unauthorized opening after the sealing, and even if unauthorized opening is performed, such a situation can be detected early and easily, and it is possible to temporarily open the opening. It is possible to perform the sealing process again even after the That is, the sealing process is performed by inserting the locking claw into at least one elongated hole of the five sealing portions 164. Then, when the substrate box 163 is opened, such as when a defect occurs in the main control substrate accommodated or when the main control substrate is inspected, the connecting portion between the sealing portion in which the locking claw is inserted and the other sealing portion is Disconnect. Thus, the box base and the box cover of the substrate box 163 are separated, and the main control substrate inside can be taken out. Thereafter, when the sealing process is performed again, the locking claw is inserted into the long hole of the other sealing portion. If a history indicating that the substrate box 163 has been opened is left in the substrate box 163, it is possible to easily find that unauthorized opening has been performed by looking at the substrate box 163.

  A plurality of coupling pieces 165 are provided on one short side of the substrate box 163 so as to protrude laterally. The coupling pieces 165 correspond to the plurality of coupled pieces 166 formed on the mounting base 161 in a one-to-one relationship, and between the substrate box 163 and the mounting pedestal 161 by the coupling pieces 165 and the coupled pieces 166. A sealing process is performed.

  Next, the back pack unit 15 will be described. 12 is a front view of the back pack unit 15, and FIG. 13 is an exploded perspective view of the back pack unit 15. As shown in FIG.

  The back pack unit 15 includes a back pack 201, and a delivery mechanism unit 202, a discharge passage board 203, and a control device assembly unit 204 are attached to the back pack 201. The back pack 201 is molded of a synthetic resin having transparency, and has a base portion 211 to which the dispensing mechanism portion 202 and the like are attached, and a protective cover portion 212 which protrudes rearward of the pachinko machine 10 and has a substantially rectangular parallelepiped shape. The protective cover portion 212 has a shape in which the left and right side surfaces and the upper surface are closed and only the lower surface is open, and at least has a size sufficient to surround the variable display unit 86.

  The external terminal board 213 is provided in the upper right portion of the base portion 211. The external terminal board 213 is provided with various output terminals, and various signals are output to the management control device on the game hall side through these output terminals. Further, the base portion 211 is provided with a pair of upper and lower retaining pins 214 at the right end when viewed from the rear of the pachinko machine 10, and the retaining pin 214 is inserted into the bearing portion 133 provided in the main body frame 13. The back pack unit 15 is rotatably supported on the main body frame 13. In addition, the base portion 211 is provided with a fastener 215 for fastening to the to-be-fastened hole 134 provided in the main body frame 13, and the body 215 is fitted into the to-be-fastened hole 134. The back pack unit 15 is fixed to the frame 13.

  A dispensing mechanism unit 202 is disposed on the base unit 211 so as to bypass the protective cover unit 212. That is, a tank 221 opened upward is provided at the top of the back pack 201, and gaming balls supplied from an island facility of the game hall are successively supplied to the tank 221. Below the tank 221, a tank rail 222 which is gently inclined toward the downstream side is connected, and to the downstream side of the tank rail 222, a case rail 223 which extends in the vertical direction is connected. At the most downstream portion of the case rail 223, a dispensing device 224 is provided. The game balls paid out from the payout device 224 are supplied to the game ball distribution unit 225 provided in the base portion 211 of the back pack 201 through a payout passage (not shown) provided on the downstream side of the payout device 224.

  The game ball distribution unit 225 has a function to distribute the game balls paid out from the payout device 224 to any of the upper tray 33, the lower tray 34 or a discharge passage described later, and the inner opening 226 is described above. The upper opening 33 communicates with the upper plate 33 through the main upper plate passage 122 and the upper door passage 51, and the central opening 227 is connected to the lower plate 34 through the lower plate passage 123 and the lower lower plate passage 52. An outer opening 228 is formed in communication with the discharge passage.

  A back pack substrate 229 is installed in the dispensing mechanism unit 202. For example, an AC 24 volt main power supply is supplied to the back pack substrate 229, and the power is turned on or off by switching the power switch 229a.

  At a lower end portion of the base portion 211, a discharge passage board 203 and a control device aggregation unit 204 are attached so as to sandwich the lower end portion in the front and rear direction. In the discharge passage board 203, a discharge passage 231 opened rearward is formed on the surface facing the control device collection unit 204, and the open portion of the discharge passage 231 is closed by the control device collection unit 204. The discharge passage 231 is formed to discharge the game ball to the island facility of the game hall, and the game ball led out to the discharge passage 231 from the above-mentioned collection passage 151 or the like passes through the discharge passage 231. The machine 10 is discharged to the outside.

  The control device assembly unit 204 has a mounting base 241 having an oblong shape, and the mounting base 241 is mounted with the payout control device 242 and the power supply and emission control device 243. The payout control device 242 and the power supply and emission control device 243 are disposed so as to be stacked back and forth so that the payout control device 242 is located behind the pachinko machine 10.

  The payout control device 242 accommodates a payout control board for controlling the payout device 224 in the substrate box 244. The signal of the dispensing command from the dispensing control device 242 to the dispensing device 224 is relayed by the back pack substrate 229 described above. Further, the payout control device 242 is provided with a state recovery switch 245. For example, when the state recovery switch 245 is pressed when a dispensing error occurs such as a ball clogging in the dispensing device 224, the ball clogging is eliminated.

  In the power supply and emission control device 243, the power supply and emission control substrate are accommodated in the substrate box 246, and the substrate generates and outputs predetermined electric power required for various control devices etc. Further, the game ball by the player Control of the launch of the game ball accompanying the operation of the firing handle 41 is performed. Further, the power supply and emission control device 243 is provided with a RAM erase switch 247. The pachinko machine 10 has a memory holding function of various data, and can maintain the state at the time of the power failure even if the power failure occurs, and can return to the state at the time of the power failure when recovering from the power failure. It has become. Therefore, when the power is shut off in the normal procedure, for example, as in the case of business closing of the game hall, the state before shutting off is stored and stored. It is supposed to be.

  The RAM erase switch 247 is not limited to the configuration provided in the power supply and emission control device 243, and may be, for example, a configuration provided in the main control device 162.

<Electric Configuration of Pachinko Machine 10>
Next, the electrical configuration of the pachinko machine 10 will be described based on the block diagram of FIG. In FIG. 14, the power supply line is indicated by a double arrow and the signal line is indicated by a solid arrow.

  The main control device 162 is provided with a main control board 301 and a power failure monitoring board (power failure monitoring board) 302. The MPU 311, the system clock circuit 312, the hard random number clock circuit 313, and the modulation circuit 314 are mounted on the main control board 301. In the MPU 311, a ROM (nonvolatile storage means) 315 storing various control programs executed by the MPU 311 and fixed value data, and various data etc. temporarily when executing the control program stored in the ROM 315 A RAM (volatile storage means) 316, which is a memory for storing data, a counter circuit 317, and various circuits such as an interrupt circuit, a timer circuit, and a data input / output circuit are incorporated. Note that part or all of the MPU 311, the ROM 315, and the RAM 316 may be provided as separate chips.

  The MPU 311 is provided with an input port 311 a and an output port. Note that an input / output port may be provided, and the input / output may be appropriately changed in the MPU 311. The same applies to other MPUs described later.

  To the input port 311 a of the MPU 311, a disconnection monitor substrate 302, a payout control substrate 322 provided in the payout control device 242, and a sensor group (not shown) are connected. In this case, the power and monitoring control substrate 321 is connected to the power failure monitoring substrate 302, and power is supplied to the MPU 311 through the power failure monitoring substrate 302.

  As part of the switch group, a plurality of detection sensors provided in the ball entry unit such as the operation opening 84 and the variable winning device 83 are connected, and the MPU 311 of the main control unit 162 performs the ball entry determination of the ball entry unit. It will be. Further, the MPU 311 executes the jackpot occurrence determination based on the entry of the ball into the operation opening 84 in the ball entry portion.

  The system clock circuit 312, the hard random number clock circuit 313 and the modulation circuit 314 will be described later.

  Here, an electrical configuration when performing control relating to a game in the MPU 311 will be described with reference to FIG.

  In the RAM 316, various counter areas are provided, and the MPU 311 uses the various counter information stored in the counter area and the counter information of the counter circuit 317 to play a big hit lottery, the first specific lamp unit 93 in the game. The setting of the luminescent color, the setting of the symbol display of the symbol display device 91, and the like are performed.

  Specifically, a jackpot random number counter C1 used for lottery of jackpot, jackpot type counter C2 used when determining jackpot type such as probability variation jackpot or normal jackpot, and reach when the symbol display device 91 is out of fluctuation A reach random number counter C3 used for lottery, and a variation type counter CS for determining a period in which the color displayed on the first specific lamp unit 93 is switched and a variation display time of the symbol in the symbol display device 91 are used.

  Here, the counter circuit 317 is a circuit dedicated to updating the big hit random number counter C1, and the big hit random number counter C1 is updated by inputting a clock signal to the counter circuit 317. On the other hand, the counters C2, C3 and CS other than the big hit random number counter C1 are stored in the various counter areas of the RAM 316, and the other counters C2, C3 and CS are subjected to an update instruction from the MPU 311. Based on, updated.

  Describing the other counters C2, C3 and CS in detail, the other counters C2, C3 and CS become loop counters which are incremented by 1 to the previous value each time they are updated and return to 0 after reaching the maximum value. There is. Each counter is updated by a process necessary for advancing a game, and the updated value is appropriately stored in a counter buffer set in a predetermined area of the RAM 316. The RAM 316 is provided with a storage ball storage area consisting of one execution area and four storage areas (storage first to fourth areas), and each of these areas is for the game ball to the operation port 84. Each value of the jackpot type counter C2 and the reach random number counter C3 is stored in time series according to the ball entry history.

  Specifically, the jackpot type counter C2 is configured to be sequentially incremented by one within a range of 0 to 49, for example, and returned to 0 after reaching the maximum value (that is, 49). Then, in the present embodiment, it is decided by the jackpot type counter C2 whether to be in the positive change state or in the normal state after the jackpot is finished.

  For example, the reach random number counter C3 is configured to be sequentially incremented by one within the range of 0 to 238 and to return to 0 after reaching the maximum value (that is, 238). And in this embodiment, when a game result is out of the reach random number counter C3, it is decided to determine whether or not to execute the reach.

  For example, the fluctuation type counter CS is sequentially incremented by one within the range of 0 to 240, and returns to 0 after reaching the maximum value (i.e., 240). The change display time as a period in which the color displayed on the first specific lamp unit 93 is switched is determined by the variation type counter CS. The switching display time corresponds to the fluctuation display time of the symbol of the symbol display device 91. The fluctuation type counter CS is updated once each time a normal process to be described later is executed once, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the variation type counter CS is acquired at the time of the start of color switching displayed on the first specific lamp unit 93 and the determination of the variation pattern at the start of variation of the symbol by the symbol display device 91.

  The jackpot random number counter C1 will be described in detail. The jackpot random number counter C1 is configured to be sequentially incremented by one within a range of 0 to 676, for example, and returned to zero after reaching the maximum value (ie, 676). When the gaming ball enters the operation opening 84, the MPU 311 accesses the counter circuit 317, acquires the value of the big hit random number counter C1 at that time, and further suspends the value of the obtained big hit random number counter C1 in the RAM 316. Store in the ball storage area.

  In addition, at the start of one game cycle, the MPU 311 of the main control board 301 uses the values of the counters C1 to C3 and CS stored in the holding ball storage area to make a big hit lottery or a first specific lamp unit 93. Although the switching time of the color to be displayed is determined, the information of the lottery result and the information of the switching time which are determined here are transmitted to the voice lamp control device 143 as the game turn command. In the sound lamp control device 143, based on the game turn command, the effect contents of the corresponding game times such as the fluctuation pattern in the symbol display device 91 and the presence or absence of the reach occurrence are determined.

  In addition to the above counters, the RAM 316 is also provided with a second specific lamp random number counter used for lottery whether or not the motorized combination provided in the operation port 84 is to be opened. At the timing when the winning on the gate 85 occurs, the value of the second specific lamp random number counter at that time is acquired, and based on the acquired value, a lottery is performed to determine whether or not to open the motorized combination. .

  Returning to the description of FIG. 14, the disconnection monitor substrate 302, the payout control substrate 322, and the relay terminal plate 323 are connected to the output port of the MPU 311. Various commands such as a winning ball command are output to the payout control board 322. The game control command or the like is output from the main control board 301 to the sound lamp control board 324 provided in the sound lamp control device 143 via the relay terminal board 323.

  The power failure monitoring board 302 relays the main control board 301 and the power supply and emission control board 321, and monitors the voltage of the DC stable 24 volts which is the maximum voltage output from the power supply and emission control board 321. Then, when this voltage is 22 volts or more, an HI level signal as a non-power-off signal (first information) is output (sent) to the main control board 301, and when this voltage is less than 22 volts, the power is shut off. And outputs (transmits) a LOW level signal as a power failure signal (second information) to the main control board 301. The main control board 301 confirms the input of the LOW level signal in a predetermined manner, and executes a power interruption process (power failure process) described later based on the confirmation result.

  The payout control board 322 performs payout control of a winning ball and the like by the payout device 224. The MPU 331, which is an arithmetic device, includes a ROM 332 storing a control program executed by the MPU 331, fixed value data, and the like, and a RAM 333 used as a work memory or the like. Note that part or all of the MPU 331, the ROM 332, and the RAM 333 may be provided as separate chips.

  The MPU 331 of the payout control board 322 is provided with an input port and an output port. A main control board 301, a power supply and emission control board 321, and a back pack board 229 are connected to the input side of the MPU 331. The main control board 301 and the back pack board 229 are connected to the output side of the MPU 331.

  The power supply and emission control board 321 includes a power-on unit for power-on 321 a and an emission control unit 321 b. The power-on time power supply unit 321a is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power supply, the main control substrate 301, the payout control substrate 322, etc. generate necessary operation power for each, and the generated operation power is indicated by a double-line arrow. The main control substrate 301, the payout control substrate 322, and the like are supplied through the path. The outline is that the power-on unit for power-on 321a takes in the 24-volt AC power supplied via the back pack substrate 229, and drives +12 V DC for driving various sensors, motors, etc., +5 V DC for logic. Power and the like are generated, and the direct current +12 V power and the direct current +5 V power are supplied to the main control board 301, the payout control board 322, and the like.

  The launch control unit 321b is responsible for controlling the launch of the game ball launch mechanism 110 according to the operation of the game ball launch handle 41 by the player, and the game ball launch mechanism 110 is driven when a predetermined launch condition is established. Ru.

  Further, on the power supply and emission control board 321, a power supply unit for power interruption 321c is mounted. The power-off time power supply unit 321c is a capacitor, and when the power of the pachinko machine 10 is in the ON state (when power is supplied from the external power supply), the power supplied from the power-on time power supply unit 321a Be charged. In addition, when the power of the pachinko machine 10 is off or when the power is cut off in the commercial power supply (when the power supply from the external power supply is cut off), the power is cut off from the power supply unit 321 c Storage holding power is supplied to the RAM 316 of the main control board 301. Therefore, even in such a situation, the information stored in the RAM 316 is stored without being deleted while the storage power is supplied from the power-off state power supply unit 321 c.

  Incidentally, the capacity of the power supply unit for power interruption 321 c is secured relatively large, and the information stored in the RAM 316 before the power interruption is held within a predetermined period (for example, one day or two days). Further, the power-off time power supply unit 321 c is not limited to a capacitor, and may be a battery or a non-rechargeable battery. In the case of a non-rechargeable battery, it is not necessary to charge the power-off means for power interruption when the pachinko machine 10 is powered on, but it needs to be replaced periodically.

  Further, the power supply and discharge control board 321 is provided with a power supply unit for processing at power off which is different from the power source unit for power off 321c. In the power supply and discharge control board 321, even after the DC stable 24 volt power supply is less than 22 volts, the power supply for power off processing discharges from the power off processing time, which is sufficient time for execution of power off processing described later In the meantime, the output of 5 volts, which is the drive power supply of the control system, is maintained at a normal value. As a result, the main control board 301 or the like can normally execute and complete the power-off process.

  Furthermore, the power supply and emission control board 321 is provided with an AC power supply section 321 d for outputting an AC voltage. The AC power supply unit 321 d outputs the +24 V AC voltage supplied from the commercial power supply as it is.

  Note that the AC power supply unit 321 d is not limited to the above configuration, and may include a full-wave rectification circuit as a waveform shaping unit that adjusts the waveform of the voltage. In this case, the output waveform of the +24 V AC voltage supplied from the commercial power supply is rectified in one direction.

  The sound lamp control board 324 controls the various lamp units 23 to 25 (specifically, the annular lamp unit 23, the error display lamp unit 24 and the award ball lamp unit 25), the speaker unit 26, and the display control device 325. . The MPU 341, which is an arithmetic device, includes a ROM 342 storing a control program executed by the MPU 341, fixed value data, and the like, and a RAM 343 used as a work memory or the like.

  The MPU 341 of the audio lamp control board 324 is provided with an input port and an output port. The main control board 301 is relayed to the relay terminal board 323 and connected to the input side of the MPU 341, and based on various commands output from the main control board 301, various lamp parts 23 to 25, speaker parts 26, and The display control device 325 is controlled. The display control device 325 controls the symbol display device 91 based on the display command input from the audio lamp control board 324.

<Processing Configuration of MPU 311 of Main Control Board 301>
Next, each control process executed by the MPU 311 of the main control board 301 will be described. The processing of the MPU 311 can be roughly classified into main processing activated upon power-on, timer interrupt processing activated periodically by interrupting normal processing of the main processing, and power failure to the NMI terminal (non-maskable terminal). There are NMI interrupt processing activated by the input of a signal, and for convenience of explanation, NMI interrupt processing and timer interrupt processing will be described first, and then main processing will be described.

  FIG. 16 shows NMI interrupt processing, which is executed when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like. That is, when the power of the pachinko machine 10 is cut off due to a power failure or the like, a power failure signal is output from the power failure monitoring board 302 to the NMI terminal of the MPU 311, and the MPU 311 interrupts the control under execution to process the NMI interrupt. To start. In the NMI interrupt process, the power failure flag is set in the power failure flag storage area provided in the RAM 316 in step S101, and the present process ends. Thereafter, it is confirmed that the power failure flag is set in the normal processing described later, whereby the power failure processing is executed.

<Timer interrupt processing>
FIG. 17 is a flowchart showing timer interrupt processing. The timer interrupt process is periodically activated as described above. In this case, although the system is configured to be activated in a cycle of 2 msec in this embodiment, this cycle is arbitrary. However, since processing to be repeatedly executed in a short cycle, such as confirmation of a power failure signal or fraud detection signal, confirmation of various winnings, etc., is set in the timer interrupt processing, processing other than these is set. It is preferable to be set shorter than the repetition period of the normal processing described later.

  In the timer interrupt process, first, in step S201, a signal reading process is executed. In the signal reading process, the information input to the input port 311a from the ball detection sensors individually provided for the general winning opening 82, the variable winning device 83, the operation opening 84 and the through gate 85 is confirmed, and the confirmation result Identify the presence or absence of ball entry to each ball entry section from. Specifically, the input of a signal (for example, a LOW level signal) corresponding to the fact that the game ball is not detected in any one process is confirmed, and the game ball is detected in the subsequent two processes. When the input of the signal (for example, HI level signal) corresponding to what is done is confirmed continuously, it specifies with the ball entering part of the game ball having occurred in the ball entering part corresponding to the detection sensor.

  After the signal reading process is performed, in the subsequent step S202, the jackpot type counter C2 and the reach random number counter C3 are updated. Specifically, the value of each random number counter is incremented by one, and it is determined whether the added value is the upper limit value. Then, when the added value exceeds the upper limit value, the value of the counter is set to the initial value.

  In the process, the jackpot random number counter C1 is not updated. The update of the jackpot random number counter C1 will be described later.

  Thereafter, in step S203, the start winning process is executed. In the start winning process, as shown in the flow chart of FIG. 18, the game ball is first operated at step S301 by determining whether or not the operation port flag is stored in the operation port flag storage area of the RAM 316. It is determined whether or not a winning (starting winning) has been made. The operation opening flag is stored when the winning of the game ball to the operation opening 84 is confirmed in the signal reading process of step S201.

  If it is determined that the gaming ball has won the operation opening 84, then in step S302, whether or not the number N of operation reserved balls of the first specific lamp unit 93 and the symbol display device 91 is less than the upper limit (4 in this embodiment) Determine if The process proceeds to step S303 on the condition that there is a winning on the operation port 84 and the number of operation reserved balls N <4, and the number of operation reserved balls N is incremented by one. Note that the operation port flag is erased after the process of step S303.

  In the subsequent steps S304 to S306, a process of acquiring the value of the jackpot random number counter C1 at that time is executed. The process will be described together with the explanation on the update of the jackpot random number counter C1.

  Thereafter, in step S307, each value of the jackpot random number counter C1 acquired in step S305, the jackpot type counter C2 updated in step S202, and the reach random number counter C3 is the first of the free storage areas of the holding sphere storage area of the RAM 316. Store in the area. Then, after the start winning process, the MPU 311 once ends the timer interrupt process.

<Main processing>
Next, the main processing activated upon reset upon power-on will be described using the flowchart of FIG.

  First, in step S401, a start-up process is performed upon power-on. Specifically, in order to wait for the slave-side control board (the payout control board 322 or the like) to become operable, for example, about 500 msec is waited.

  In the following step S402, it is determined whether or not 1 sec which is a permission prohibition period has elapsed after the start-up process of step S401. If 1 sec has not elapsed, the process of step S402 is executed again. The measurement of this time is performed by counting the number of times of processing in step S402. For example, when the time required to execute the process of step S402 again after the negative determination in step S402 is 0.1 msec, the count value becomes 10000 times, and after the start-up process of step S401. It is determined that 1 sec has elapsed since the In addition, the specific structure of measurement of time is arbitrary, for example, you may make it measure time using a real-time clock. If it is determined in step S402 that 1 sec has elapsed, the process proceeds to step S403.

  In step S403, access to the RAM 316 is permitted. Thereafter, in step S404, it is determined whether the RAM erase switch 247 provided in the power supply and emission control device 243 is turned on or not, and in the subsequent step S405, it is determined whether the power failure flag is stored in the RAM 316. In step S406, a RAM determination value is calculated. In the following step S407, it is determined whether the RAM determination value matches the RAM determination value stored at the time of power shutoff, that is, the validity of stored data. The RAM determination value is, for example, a checksum value at a work area address of the RAM 316. It is also possible to judge the validity of the stored data depending on whether or not the keyword written in the predetermined area of the RAM 316 is correctly stored.

  As described above, in the pachinko machine 10, the power is turned on while pressing the RAM erase switch 247 when initializing the RAM data when the power is turned on, for example, at the time of opening the hall. Therefore, if the RAM erase switch 247 is pressed, the process proceeds to steps S408 to S409. Also, when the occurrence information of the power-off is not set or when the abnormality of the stored data is confirmed by the RAM determination value (checksum value etc.), the process similarly shifts to the processes of steps S408 to S409.

  In step S408, the use area of the RAM 316 is cleared to 0 (initialization), and in step S409, the initialization process of the RAM 316 is executed. After that, in step S410, interrupt permission is set, and the process proceeds to the normal processing described later.

  On the other hand, when the RAM erase switch 247 is not pressed, the power failure is output from the RAM 316 in step S411 on condition that the power failure flag is stored and the RAM determination value (checksum value etc.) is normal. The flag is erased and the RAM determination value stored in the RAM 316 is erased in step S412. After that, in step S410, interrupt permission is set, and the process proceeds to the normal processing described later. As a result, the state before power off is restored.

<Normal processing>
Next, normal processing will be described with reference to the flowchart of FIG.

  In the normal processing, in step S501, the variation type counter CS is updated. In the subsequent step S502, a first specific lamp unit control process for switching the color displayed on the first specific lamp unit 93 is executed. In the first specific lamp unit control process, on / off control of the light source switch of the LED lamp disposed in the jackpot determination or the first specific lamp unit 93 is performed. Further, in the first specific lamp unit control process, the setting of the variable display of the first symbol by the symbol display device 91 is also performed.

  Specifically, it is determined based on the value of the jackpot random number counter C1 whether or not it is a jackpot. More specifically, it is determined whether or not the value of the jackpot random number counter C1 matches a predetermined jackpot winning value. Further, the type of jackpot is determined based on the value of the jackpot type counter C2 (so-called, whether or not it is a probability variation jackpot) is determined. Further, based on the value of the reach random number counter C3 and the value of the fluctuation type counter CS, the switching display time of the color displayed on the first specific lamp unit 93 and the fluctuation display time of the first symbol are determined. In addition, whenever on-off control of the 1st specific lamp part 93 is started by the said 1st specific lamp part control processing, the operation pending ball number N is decremented by 1, and when the operation pending ball number N is 0, it is on-off control Does not start.

  After the first specific lamp unit control process, the special winning opening / closing process is executed in step S503. In the big winning opening / closing process, the big winning opening of the variable winning device 83 is opened or closed in the case of a big hit state. That is, the big winning opening is opened for each round of the jackpot state, and it is determined whether the maximum opening time of the big winning opening has passed or whether the gaming ball has won the specified number in the big winning opening. The determination as to whether or not the predetermined number of winnings have been made is made by checking the special winning opening counter. Then, when any of these conditions is established, the special winning opening is closed.

  Thereafter, in step S504, a second specific lamp unit control process is performed to switch the color displayed on the second specific lamp unit 94. In the second specific lamp unit control process, switching of the display color in the second specific lamp unit 94 is started on the condition that the gaming ball has won in the through gate 85. At this time, the switching time of the display color is also set. Further, the color to be stopped and displayed is set based on the value of the second specific lamp random number counter acquired when the gaming ball has won on the through gate 85. When a predetermined color is set as the color to be displayed for stop display, after the stop display for the color, the motorized accessory attached to the operation port 84 is opened for a predetermined time.

  After step S504, game ball emission control processing is executed in step S505. In the game ball emission control process, the game ball emission mechanism 110 is performed once in a predetermined period (for example, 0.6 sec) on condition that the emission permission signal is input from the emission control unit 321b of the power supply and emission control substrate 321. Energize the solenoids of As a result, the gaming balls on the firing rails of the gaming ball firing mechanism 110 are launched toward the gaming area. More specifically, the MPU 311 repeats “0” output and “1” output to the launch output port in a predetermined cycle on condition that the launch permission signal is input. While “0” is output to the emission output port, a non-emission signal is output to the power and emission control board 321, and the emission control unit 321b deenergizes the solenoid. On the other hand, while "1" is output to the emission output port, the emission signal is output to the power and emission control board 321, and the emission control unit 321b causes the solenoid to be in an excited state.

  That is, the MPU 311 outputs a firing pulse signal to the power supply and firing control board 321. The launch control unit 321b of the power supply and launch control board 321 outputs a solenoid drive signal (drive voltage) obtained by amplifying the voltage of the launch pulse signal to the solenoid and moves the output shaft of the solenoid to the launch position and the storage position. Control the firing of the game ball.

  Thereafter, in step S506, it is determined whether the power failure flag is stored in the RAM 316 or not. If the power failure flag is not stored, the process proceeds to step S507, and it is determined whether or not the execution timing of the next normal processing has been reached, that is, the interrupt criteria set in advance as a plurality of times of timer interrupt processing from the start of the previous normal processing. It is determined whether the number of occurrences (specifically, twice) has occurred. Specifically, to grasp the number of times of timer interruption, an interruption number counter is provided in the RAM 316, and the value of the counter is incremented by one each time the timer interruption is activated, and the process of step S501 is executed. The value of the counter is cleared to 0 (initialized) immediately before the If the timer interrupt process has not generated the interrupt reference number of times, the process proceeds to step S508.

  In step S508, the variation type counter CS is updated. Specifically, the fluctuation type counter CS is incremented by one, and when the value of the fluctuation type counter CS thus added exceeds the upper limit value, it is cleared to 0 (initialized). Then, the updated value of the fluctuation type counter CS is stored in the corresponding buffer area of the RAM 316.

  Thereafter, the process proceeds to step S506. Thereafter, the above processing is repeated from the start of the previous normal processing until the timer interrupt processing generates the interrupt reference number of times, and when the interrupt reference number of times is reached, the processing returns to step S501. That is, when the power failure flag is not stored, the processing of step S501 to step S505 is repeatedly executed in a cycle of 4 msec. In addition, the said period is not limited to 4 msec, if progress of a game can be controlled favorably.

If the power failure flag is stored, the power failure processing after step S509 is executed. That is, in step S509, the generation of timer interrupt processing is prohibited, and then the RAM determination value is calculated and stored in step S510, and after the access to RAM 316 is prohibited in step S511, the power is completely shut off and processing is performed. Continues an infinite loop until it can not execute.
<About the update of the jackpot random number counter C1>
Next, updating of the jackpot random number counter C1 will be described with reference to FIGS. 14 and 21. FIG. FIG. 21 is a block circuit diagram showing configurations of the hard random number clock circuit 313 and the modulation circuit 314. As shown in FIG.

  As shown in FIG. 14, a system clock circuit 312 for outputting a system clock signal and a hard random number clock circuit for outputting a hard random number clock signal used for updating the big hit random number counter C1 to the main control board 301. And 313 are provided. Both are electrically connected to the power supply and emission control substrate 321 via the power failure monitoring substrate 302. Furthermore, both are electrically connected to the MPU 311, respectively.

  The system clock circuit 312 is an oscillation circuit provided with a quartz oscillator, and outputs a system clock signal to the MPU 311 in a situation where power is supplied from the power supply and emission control board 321. The MPU 311 simultaneously operates a plurality of elements on the basis of the input of the system clock signal to execute processing necessary for proceeding with the game and synchronizes with other hardware.

  The hard random number clock circuit 313 outputs a hard random number clock signal to the MPU 311 in a state where power is supplied from the power supply and the emission control board 321. The jackpot random number counter C1 is updated based on the input of the hard random number clock signal to the MPU 311.

  Specifically, the jackpot random number counter C1 is set to be updated in synchronization with the input of the hard random number clock signal to the MPU 311 without being synchronized with the input of the system clock signal to the MPU 311. Specifically, the counter circuit 317 is configured to receive only the hard random number clock signal, and when the counter circuit 317 is synchronized with the rising of the hard random number clock signal, the value of the big hit random number counter C1 is One is added. That is, while the other counters C2, C3 and CS are updated by the timer interrupt process or the normal process executed by the MPU 311, the big hit random number counter C1 is not updated by the software process in the MPU 311 but a dedicated counter. It is updated by the circuit 317. The system clock signal that triggers the operation of the MPU 311 and the hard random number clock signal that triggers the operation of the counter circuit 317 are independently input to the MPU 311. As a result, the process of updating the jackpot random number counter C1 and the processes related to the progress of other games are executed in parallel. Thus, the processing load of the MPU 311 can be reduced. In addition, since the jackpot random number counter C1 is updated without being affected by the software processing, a fraudulent act such as specifying the value of the jackpot random number counter C1 in synchronization with execution of predetermined software processing and rewriting the update program You can suppress the act.

  Here, the update timing of the jackpot random number counter C1 is the rise timing of the hard random number clock signal. The hard random number clock signal is set to have a cycle different from that of the system clock signal and not synchronized with the system clock signal.

  As shown in FIG. 21, the hard random number clock circuit 313 includes a frequency conversion circuit 401 that converts the frequency of an alternating voltage, and a signal conversion circuit 402 that converts an alternating waveform into a pulse signal.

  The frequency conversion circuit 401 is electrically connected to the AC power supply unit 321 d via the power failure monitoring substrate 302. When the AC voltage is input from the AC power supply unit 321 d, the frequency conversion circuit 401 converts the frequency of the AC voltage into a specific frequency (for example, 300 Hz) and directs the converted AC voltage to the signal conversion circuit 402. It is configured to output.

  Specifically, the frequency conversion circuit 401 includes a local oscillation circuit 401a and a mixer circuit 401b. The local oscillation circuit 401a is composed of, for example, a CR oscillation circuit having a resistor and a variable capacitor (hereinafter, simply referred to as a varicon), and an AC voltage of a frequency corresponding to the resistance value and the capacitance of the varicon is mixed with the mixer circuit 401b. It is configured to output toward the end.

  The mixer circuit 401b includes a first input terminal to which an AC voltage from the CR oscillation circuit is input, a second input terminal to which an AC voltage supplied from the AC power supply unit 321d is input, and an output terminal. The alternating voltage of the frequency of the difference between the two is output based on the fact that alternating voltages having different frequencies are input to the terminals of the first input terminal and the second input terminal.

  Here, the CR oscillation circuit has a switch for changing the capacitance of the varicon in response to changes in the frequency of the AC voltage (50 Hz for East Japan, 60 Hz for West Japan) supplied from the commercial power supply. It is provided. By operating the switch, the frequency of the AC voltage output from the CR oscillation circuit is configured to be switched to 350 Hz or 360 Hz. Thus, when the frequency of the AC voltage supplied from the commercial power supply is 50 Hz, the switch is controlled so that the AC voltage of 350 Hz is output from the CR oscillation circuit, and the frequency of the AC voltage supplied from the commercial power supply In the case of 60 Hz, by controlling the switch so that the AC voltage of 360 Hz is output from the CR oscillation circuit, the AC output from the mixer circuit 401 b regardless of the frequency of the AC voltage supplied from the commercial power supply. The frequency of the voltage is unified to 300 Hz.

  The signal conversion circuit 402 is configured to output a pulse signal corresponding to the frequency of the alternating voltage to the modulation circuit 314 based on the input of the frequency-converted alternating voltage. Specifically, the signal conversion circuit 402 includes two resistors 411 and 412 as amplitude adjustment means for adjusting the amplitude of the AC voltage output from the frequency conversion circuit 401, and the AC which is adjusted by the amplitude adjustment means A Schmitt trigger 413 (Schmitt inverter) is provided as conversion means for converting an AC voltage into a pulse signal based on the comparison between the voltage and a predetermined threshold voltage. The two resistors 411 and 412 are connected in series to the frequency conversion circuit 401. One end of the resistor 412 is grounded. In addition, a Schmitt trigger 413 is disposed at a position parallel to the resistor 412. The input terminal of the Schmitt trigger 413 is connected on the wiring connecting the two resistors 411 and 412, and the output terminal of the Schmitt trigger 413 is connected to the modulation circuit 314. With such a configuration, the alternating voltage output from the frequency conversion circuit 401 is converted into a pulse signal of + 5V.

  That is, the magnitude (amplitude) of the AC voltage applied to the Schmitt trigger 413 is determined by the ratio of the resistance values of the two resistors 411 and 412. Specifically, when the resistance values of the two resistors 411 and 412 are R1 and R2, respectively, and the amplitude of the AC voltage output from the frequency conversion circuit 401 is +24 V, the voltage applied to the Schmitt trigger 413 Becomes 24V × R2 / (R1 + R2). Therefore, for example, the voltage applied to the Schmitt trigger 413 can be adjusted to +5 V by setting the resistance value of R1 to 47 kΩ and the resistance value of R2 to 10 kΩ.

  The Schmitt trigger 413 is electrically connected to the power supply and emission control board 321 via an electrical path (not shown) and receives power supply. The Schmitt trigger 413 outputs a LOW level signal if it is equal to or higher than a predetermined upper limit threshold voltage Vth, and outputs a HI level signal if it is less than a predetermined lower limit threshold voltage Vtl. Specifically, when the AC voltage becomes higher than or equal to the upper threshold voltage Vth (for example +4.3 V), the LOW level signal is thereafter reduced until the AC voltage becomes lower than or equal to the lower threshold voltage Vtl (for example +3.5 V) lower than the upper threshold voltage Vth. When the AC voltage becomes lower than the lower limit threshold voltage Vtl, the HI level signal is output until the AC voltage becomes the upper limit threshold voltage Vth. Thereby, a pulse signal of a predetermined pulse width is obtained. The pulse signal is used as a hard random number clock signal.

  In addition, although the Schmitt trigger 413 used the thing of an inverter type, it is not restricted to this, You may use the thing of a buffer type.

  Next, the modulation circuit 314 will be described. The modulation circuit 314 is provided on a path connecting the hard random number clock circuit 313 and the MPU 311, and the hard random number clock signal output from the hard random number clock circuit 313 (specifically, an output from the Schmitt trigger 413 The modulated pulse signal is modulated to a pulse signal having two output intervals and two pulse widths.

  Specifically, the modulation circuit 314 includes a first D flip flop 422, a second D flip flop 423, a third D flip flop 424, a first XOR circuit 425 and a second XOR circuit 426. The respective D flip-flops 422, 423 and 424 have the same configuration, and thus the first D flip-flop 422 will be described by way of example. The first D flip-flop 422 has a D1 terminal as an input terminal and a CLK1 terminal and an output The Q1 terminal is provided as a terminal, and in synchronization with the rise of the signal input to the CLK1 terminal from the LOW level to the HI level, the signal corresponding to the signal state input to the D1 terminal at that point is the Q1 terminal And the output state is held until the next rise.

  Here, since the CLK terminals of the respective D flip-flops 422, 423, and 424 are connected to the signal conversion circuit 402, the same signal is input to each of the CLK terminals. That is, the D flip-flops 422, 423, 424 operate at the same timing. Hereinafter, the timing at which the D flip-flops 422, 423, and 424 synchronize (the timing at which the signal input to the CLK terminal of the D flip-flop rises from the LOW level to the HI level) is referred to as the synchronization timing.

  Each of the XOR circuits 425 and 426 has two input terminals and one output terminal. When the signal states input to the two input terminals are the same, LOW from the output terminal is used. While the level signal is output, the HI level signal is output from the output terminal if the signal states input to the two input terminals are different.

  The output terminal of the first XOR circuit 425 is connected to the D1 terminal of the first D flip-flop 422, and one input terminal of the second XOR circuit 426 is connected to the Q1 terminal of the first D flip-flop 422. The output terminal of the second XOR circuit 426 is connected to the D2 terminal of the second D flip flop 423, and the D3 terminal of the third D flip flop 424 is connected to the Q2 terminal of the second D flip flop 423. The Q3 terminal of the third D flip-flop 424 is connected to the MPU 311 and is connected to the other input terminal of the first XOR circuit 425 and one input terminal of the second XOR circuit 426. The power and emission control board 321 is connected to the other input terminal of the first XOR circuit 425 via the power failure monitoring board 302, and a +5 V voltage corresponding to the HI level signal is supplied.

  According to this configuration, the output from the Q1 terminal changes in accordance with the signal output from the Q3 terminal. Specifically, in the situation where the HI level signal is output from the Q3 terminal, the LOW level signal is output from the first XOR circuit 425 to the D1 terminal. Low level signal is output from the terminal. On the other hand, in the situation where the LOW level signal is output from the Q3 terminal, the HI level signal is output from the first XOR circuit 425 to the D1 terminal. A level signal is output.

  Further, the output from the Q2 terminal changes in accordance with the signals output from the Q1 terminal and the Q3 terminal. Specifically, in the situation where the signals output from the Q1 terminal and the Q3 terminal are the same, the LOW level signal is output from the second XOR circuit 426 to the D2 terminal. Low level signal is output from the Q2 terminal. On the other hand, in the situation where signals outputted from the Q1 terminal and the Q3 terminal are different, the HI level signal is outputted from the second XOR circuit 426 to the D2 terminal. HI level signal is output.

  The output from the Q3 terminal changes in accordance with the signal output from the Q2 terminal. Specifically, when synchronous timing is reached in the situation where the LOW level signal is output from the Q2 terminal, the LOW level signal is output from the Q3 terminal while the HI level signal is output from the Q2 terminal. When synchronous timing is reached in the situation, the HI level signal is output from the Q3 terminal.

  Next, the operation of the modulation circuit 314 will be described using the timing chart of FIG. The timing of t1 to the timing of t9 are synchronization timings. That is, at these timings, the hard random number clock signal output from the hard random number clock circuit 313 is input. Specifically, at these timings, the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level, and each D flip-flop 422, 423, and 424 synchronizes with the respective rising edges to the respective D terminals (D1 A signal corresponding to the signal input to the terminal, D2 terminal, D3 terminal) is output from each Q terminal (Q1 terminal, Q2 terminal, Q3 terminal). In the characteristics of the D flip-flop, as shown in FIG. 22, when the signal state outputted from each Q terminal changes, the change form (from rising to transition to high level or from high level to low level) Fall) is output slightly behind the synchronization timing.

  At the timing of t1, since the LOW level signal is output from the Q3 terminal, the HI level signal is output from the first XOR circuit 425. In this case, the output state from the Q1 terminal rises from the LOW level to the HI level at a timing slightly delayed from the timing of t1. Further, at the timing of t1, since the LOW level signal is output from both the Q1 terminal and the Q3 terminal, the LOW level signal is output from the second XOR circuit 426. In this case, a low level signal is output from the Q2 terminal. At the timing of t1, the output state from the Q3 terminal is maintained at the LOW level.

  At the following timing t2, since the LOW level signal is output from the Q3 terminal, the HI level signal is output from the first XOR circuit 425. In this case, the HI level signal is output from the Q1 terminal. Also, while the HI level signal is output from the Q1 terminal, the LOW level signal is output from the Q3 terminal, so the HI level signal is output from the second XOR circuit 426. In this case, the output state from the Q2 terminal rises from the LOW level to the HI level at a timing slightly delayed from the timing of t2. At time t2, the output state from the Q3 terminal is maintained at the LOW level.

  At timing t3, since the LOW level signal is output from the Q3 terminal, the HI level signal is output from the first XOR circuit 425. In this case, the HI level signal is output from the Q1 terminal. Further, at timing t3, while the HI level signal is output from the Q1 terminal, the LOW level signal is output from the Q3 terminal, so the HI level signal is output from the second XOR circuit 426. In this case, the HI level signal is output from the Q2 terminal. Furthermore, at the timing of t3, the HI level signal is output from the Q2 terminal. In this case, the output state from the Q3 terminal rises from the LOW level to the HI level at a timing slightly later than the timing of t3. The counter circuit 317 synchronizes with the rise and the jackpot random number counter C1 is updated.

  At timing t4, since the HI level signal is output from the Q3 terminal, the LOW level signal is output from the first XOR circuit 425. In this case, the output state from the Q1 terminal falls from the HI level to the LOW level at a timing slightly delayed from the timing of t4. Further, at the timing of t4, since the HI level signal is output from both the Q1 terminal and the Q3 terminal, the second XOR circuit 426 outputs the LOW level signal. In this case, the output state from the Q2 terminal falls from the HI level to the LOW level at a timing slightly delayed from the timing of t4. At time t4, the output state from the Q3 terminal is maintained at the HI level.

  At timing t5, the HI level signal is output from the Q3 terminal, so the LOW level signal is output from the first XOR circuit 425. In this case, a low level signal is output from the Q1 terminal. Further, at the timing of t5, while the LOW level signal is output from the Q1 terminal, the HI level signal is output from the Q3 terminal, so the HI level signal is output from the second XOR circuit 426. In this case, the output state from the Q2 terminal rises from the LOW level to the HI level at a timing slightly delayed from the timing of t5. Furthermore, since the LOW level signal is output from the Q2 terminal at the timing of t5, the output state from the Q3 terminal falls from the HI level to the LOW level at a timing slightly delayed from the timing of t5.

  At timing t6, since the LOW level signal is output from the Q3 terminal, the HI level signal is output from the first XOR circuit 425. In this case, the output state from the Q1 terminal rises from the LOW level to the HI level at a timing slightly delayed from the timing of t6. Further, at the timing of t6, since the LOW level signal is output from both the Q1 terminal and the Q3 terminal, the LOW level signal is output from the second XOR circuit 426. In this case, the output state from the Q2 terminal falls from the HI level to the LOW level at a timing slightly delayed from the timing of t6. Furthermore, since the HI level signal is output from the Q2 terminal at the timing of t6, the output state from the Q3 terminal rises from the LOW level to the HI level at a timing slightly delayed from the timing of t6. The counter circuit 317 synchronizes with the rising edge, and the big hit random number counter C1 is updated.

  Here, the period Ta from the timing t3 to the timing t6 (specifically, the period from the timing slightly delayed from the timing t3 to the timing slightly delayed from the timing t6) is the update interval of the random number counter C1. ing. The period Ta is three times the period T1 of the pulse signal output from the Schmitt trigger 413 (the period T1 of the hard random number clock signal output from the hard random number clock circuit 313). That is, the update interval (period Ta) of the big hit random number counter C1 and the cycle T1 of the pulse signal output from the signal conversion circuit 402 are different. As a result, even when the cycle T1 of the pulse signal output from the Schmitt trigger 413 is grasped, it is difficult to grasp the update timing of the jackpot random number counter C1.

  At timing t7, the HI level signal is output from the Q3 terminal, so the LOW level signal is output from the first XOR circuit 425. In this case, the output state from the Q1 terminal falls from the HI level to the LOW level at a timing slightly delayed from the timing of t7. Further, at the timing of t7, since the HI level signal is output from both the Q1 terminal and the Q3 terminal, the LOW level signal is output from the second XOR circuit 426, so the LOW level signal is output from the Q2 terminal. At the timing of t7, the output state from the Q3 terminal is maintained at the LOW level.

  At timing t8, the output states of the terminals Q1 and Q2 and Q3 are the same as at timing t1, so the terminal Q1 is slightly delayed from timing t8 as at timing t1. The output state from the low level rises to the high level while the outputs from the Q2 and Q3 terminals are maintained at the low level. In this case, a period T2 from the timing t1 to the timing t8 is one cycle, and the operation from the timing t1 to the timing t8 is repeatedly executed. That is, a pulse signal group including two pulse signals having different pulse widths is repeatedly output with a period T2. Then, the pulse signal group is input to the MPU 311 as a hard random number clock signal.

  Thereafter, at a timing slightly delayed from the timing of t9, the signal output from the Q3 terminal rises from the LOW level to the HI level, and the big hit random number counter C1 is updated at the timing. That is, the period Tb from the timing of t6 to the timing of t9 is the update interval of the jackpot random number counter C1. In other words, since the pulse signal is output alternately from the Q3 terminal at two types of rising edge intervals, the update interval of the big hit random number counter C1 also changes alternately. In other words, based on the input of the pulse signal from the signal conversion circuit 402, the modulation circuit 314 has pulses at different rising intervals different from the period T1 of the input pulse signal, and alternately pulses at two different rising intervals. It can be said that the output is a signal. Then, the update of the jackpot random number counter C1 according to the pulse signal group is repeated in units of the pulse signal group. As a result, since there are two types of update intervals at which the jackpot random number counter C1 is updated, it is difficult to grasp the update intervals of the jackpot random number counter C1.

  Also, focusing on the fact that the big hit random number counter C1 is updated in synchronization with the rise of the pulse signal, the rise of the pulse signal can be regarded as the trigger. In this case, the modulation circuit 314 modulates the pulse signal input from the signal conversion circuit 402 and outputs a pulse signal group including a plurality of pulse signals as one cycle, thereby triggering update of the big hit random number counter C1. It can be said that the trigger interval is set to two types, and the two trigger intervals are set to be different from the cycle T1 of the input pulse signal.

  In practice, the delay period from the synchronization timing until the output state from each Q terminal changes is sufficiently smaller than the cycle T1 of the hard random number clock signal, and in the following description, the synchronization timing And the timing at which the output state changes are described as being the same timing.

  Next, the relationship between the update interval of the big hit random number counter C1 and the numerical range of the big hit random number counter C1 will be described with reference to FIG. Here, among the update intervals of the big hit random number counter C1, one period Ta is simply referred to as Ta, the other period Tb is simply referred to as Tb, and the pulse signal to be output earlier in the pulse signal group (the pulse width is larger The rising timing of the pulse signal) is referred to as a first timing, and the rising timing of the pulse signal (a pulse signal with a smaller pulse width) to be output later is referred to as a second timing. FIG. 23 (a) is a timing chart showing how the big hit random number counter C1 is updated when the big hit random number counter C1 becomes “0” at the first timing, and FIG. 23 (b) is a second timing It is a timing chart which shows a situation of updating of big hit random number counter C1 when big hit random number counter C1 is set to "0".

  Furthermore, for convenience of explanation, it is assumed that the numerical range of the jackpot random number counter C1 is “0 to 4” and the winning value is “2”. Note that the number of terms in the numerical sequence composed of the values that can be taken by the big hit random number counter C1 is referred to as the counter term number. For example, when the numerical range of the jackpot random number counter C1 is "0 to 4", the numerical sequence composed of the values that the jackpot random number counter C1 can take is "0, 1, 2, 3, 4" The number is "5". If it expands to a general formula, if the numerical range of big hit random number counter C1 is set to "0-N", a counter term number will be "N + 1."

  As shown in FIG. 23 (a), when the big hit random number counter C1 becomes “0” at the first timing, the period required for the big hit random number counter C1 to make one revolution is 3Ta + 2Tb, and within that time period The period during which the winning value is “2” is Ta. That is, the big hit random number counter C1 holds the value of “2” only for Ta in the period of 3Ta + 2Tb, and if the value of the big hit random number counter C1 is acquired during the period, the big hit is won. In other words, in terms of the period, the jackpot winning probability is Ta / (3Ta + 2Tb).

  When the big hit random number counter C1 becomes “0” at the first timing, the timing at which the big hit random number counter C1 becomes “4” is the first timing. Then, the big hit random number counter C1 becomes “0” at the second timing, and the update is sequentially performed. In this case, a period required for the jackpot random number counter C1 to make one revolution is 2Ta + 3Tb as shown in FIG. 23B, and a period during which the value of “2” which is the winning value is within the period is It is Tb. Therefore, the jackpot winning probability in this case is Tb / (2Ta + 3Tb).

  That is, the period in which the value of the jackpot random number counter C1 is the winning value fluctuates depending on whether the jackpot random number counter C1 is updated from "0" at the first timing or the second timing. At the same time, the period in which the jackpot random number counter C1 makes a round also fluctuates. In other words, among the pulse signals included in the pulse signal group, the pulse signal corresponding to the update in which the value of the big hit random number counter C1 becomes the initial value fluctuates, and the value of the big hit random number counter C1 becomes the winning value. And the period in which the jackpot random number counter C1 makes one turn fluctuate. Thus, each time the big hit random number counter C1 makes one revolution, the value of the big hit random number counter C1 becomes the winning value, the period until the value of the big hit random number counter C1 changes from the initial value to the win value, and the big hit random number The period until the counter C1 makes one revolution fluctuates. Therefore, it is made more difficult to grasp the timing at which the value of the jackpot random number counter C1 is the winning value.

  For example, when the period until the big hit random number counter C1 makes one turn is known, there is a possibility that the update interval of the big hit random number counter C1 may be obtained. In such a situation, when the winning value is grasped, there is a possibility that the timing when the value of the jackpot random number counter C1 becomes the winning value may be specified. On the other hand, in the present embodiment, the trigger interval of the hard random number clock signal that triggers the update of the big hit random number counter C1 is set to two types, and the number of counter terms of the big hit random number counter C1 becomes odd. By setting the numerical range of the big hit random number counter C1, the timing at which the big hit random number counter C1 becomes “0” is alternately switched between the first timing and the second timing. As a result, the period in which the value of the jackpot random number counter C1 is the winning value and the period required for the jackpot random number counter C1 to make one turn fluctuate, so grasping the timing when the value of the jackpot random number counter C1 becomes the elected value It is difficult. Therefore, by specifying the period in which the big hit random number counter C1 makes one turn, it is possible to suppress the fraudulent act of grasping the timing when the value of the big hit random number counter C1 becomes the winning value.

  In this case, a random number initial value counter is separately provided, the counter updating process is performed separately from the update of the big hit random number counter C1, and if the big hit random number counter C1 makes one revolution, the value of the random number initial value counter at that time is A configuration may also be considered in which the jackpot random number counter C1 is read as the initial value. However, in the configuration, it is necessary to separately provide a random number initial value counter in the counter area of the RAM 316, and to perform update processing of the random number initial value counter and initial value setting processing of the big hit random number counter C1. Then, there is a concern that the capacity increase, the configuration complexity, and the processing load increase caused by providing the random number initial value counter.

  On the other hand, according to the present embodiment, it is possible to change the timing at which the value of the jackpot random number counter C1 becomes the winning value without applying a processing load to the MPU 311. Furthermore, since the update of the jackpot random number counter C1 is executed independently of the various software processes executed by the MPU 311, it is possible to suppress an unauthorized action on software processes such as rewriting a program.

  Further, considering the substantial winning probability, the substantial winning probability is an average of the jackpot winning probability when the update is started from the first timing and the second timing, respectively, so (Tb / (2Ta + 3Tb). ) + Ta / (3Ta + 2Tb)) / 2. In this case, when Ta = 3T1 and Tb = 4T1 are substituted, the actual winning probability is 19.93%, which is substantially the same as the theoretical probability of 20.00% calculated from the value of the jackpot random number counter C1. That is, although the big hit winning probability fluctuates each time the big hit random number counter C1 makes one revolution, since the overall winning probability is substantially the same as the theoretical probability, the fairness of the game and easy management of the game in the game hall Sex is secured.

  Specifically, if the range of values that can be taken by the big hit random number counter C1 is “0 to 5”, the number of counter terms is even, so the timing when the big hit random number counter C1 becomes “0” is the first timing Or fixed at one of the second timings. Further, the actual winning probability when fixed at the first timing is calculated to be 17.65% from Ta / (3Ta + 2Tb). On the other hand, if the timing at which the jackpot random number counter C1 is "0" is always the second timing, the actual winning probability is calculated to be 22.22% from Tb / (2Ta + 3Tb).

  As described above, the substantial jackpot winning probability fluctuates depending on whether the timing when the jackpot random number counter C1 becomes “0” is fixed to the first timing or the second timing. For this reason, the fairness of the game can not be maintained, and management of the game in the game hall becomes difficult.

  On the other hand, when the numerical range of the big hit random number counter C1 is "0 to 4", the number of counter terms is odd, and the big hit random number counter C1 becomes "0" every time the big hit random number counter C1 makes one revolution. The timing fluctuates between the first timing or the second timing. Thereby, since the substantial winning probability is an average of the winning probability at the first timing and the winning probability at the second timing, the above-mentioned inconvenience is avoided.

  The larger the difference between Ta and Tb, the larger the difference between the actual probability of winning and the theoretical probability, while the greater the fluctuation that occurs with each round of the large-hit random number counter C1, the more the difference between Ta and Tb increases. From the viewpoint, the difference between Ta and Tb may be increased.

  In addition, focusing on the fact that the big hit random number counter C1 makes a plurality of rounds, “Ta, Tb” is repeated as a unit period and the big hit random number counter C1 is repeated during the period when the big hit random number counter C1 is the winning value. It can be said that the period required to make one revolution is repeated with “2Ta + 3Tb, 3Ta + 2Tb” as a unit period.

  Here, for convenience of explanation, the possible numerical range of the big hit random number counter C1 is set to "0 to 4", and the value of "2" is assumed to be the winning value, but it is not limited thereto. It may be set to 0 to 676 ". In this case, a plurality of winning values may be set to achieve a desired jackpot winning probability. The point is that the numerical range of the jackpot random number counter C1 should be set so that the number of counter terms is an odd number.

  If three pulse signals are included in the pulse signal group output from the modulation circuit 314, the numerical range of the big hit random number counter C1 may be set so that the number of counter terms is not a multiple of three. . As a result, in the pulse signal group, the pulse signal corresponding to the update in which the value of the big hit random number counter C1 becomes the initial value fluctuates.

  That is, it is preferable to configure the modulation circuit 314 and the numerical range of the jackpot random number counter C1 so that the number of counter terms is not a multiple of the number of pulse signals included in the pulse signal group output from the modulation circuit 314. Assuming that the number of pulse signals included in the pulse signal group is “m” and the possible range of the jackpot random number counter C1 is “0 to N”, N + 1 ≠ K × m (K: It is preferable to set the numerical range “0 to N” of the jackpot random number counter C1 and the number “m” of pulse signals included in the pulse signal group so as to be a natural number relationship.

  In particular, assuming that N + 1 = K × m ± 1 (K: a natural number), a pulse corresponding to the update in which the value of the big hit random number counter C1 becomes the initial value in the pulse signal group each time the big hit random number counter C1 makes one revolution. The signal is shifted by one. Then, all the pulse signals included in the pulse signal group can be a trigger when updating is performed in which the value of the big hit random number counter C1 becomes the initial value.

  In this case, if the jackpot winning probability corresponding to each of the pulse signals included in the pulse signal group is P1, P2,..., Pm, the actual winning probability takes their average to obtain (P1 + P2 +... + Pm) / It will be m. Thus, each time the big hit random number counter C1 makes one revolution, the period from the timing when the value of the big hit random number counter C1 becomes the initial value to the timing when the win value is reached, the period when the value of the big hit random number counter C1 becomes the win value, While the period required for the jackpot random number counter C1 to make one revolution and the jackpot winning probability fluctuate, the substantial winning probability does not fluctuate. Therefore, it is possible to secure the fairness of the game while changing the timing at which the value of the jackpot random number counter C1 becomes the winning value.

  Next, acquisition of the jackpot random number counter C1 will be described using the flowchart of FIG.

  First, in step S304, processing for prohibiting update of the jackpot random number counter C1 is executed. Specifically, processing for blocking the input of the hard random number clock signal to the MPU 311 is executed. Although not shown in detail, a MOSFET is provided as a switching element for permitting or blocking the input of the hard random number clock signal to the MPU 311, and the MOSFET responds to the signal from the MPU 311 to the MPU 311. It is configured to allow or block the input of the hard random number clock signal.

  In the following step S305, processing for acquiring the value of the jackpot random number counter C1 at that time is executed, and thereafter, in step S306, the update prohibition cancellation processing is executed. Specifically, the input of the hard random number clock signal to the MPU 311 is resumed. As a result, the update of the jackpot random number counter C1 is resumed.

  Here, since the update of the big hit random number counter C1 and the timer interrupt process are independently performed in parallel, the update of the big hit random number counter C1 is performed in the situation where the big hit random number counter C1 is acquired. May be In this case, the consistency of the value of the jackpot random number counter C1 may be lost, or the acquisition of the value of the jackpot random number counter C1 may fail. In particular, the clock signal for hard random numbers used as a reference clock signal in updating the big hit random number counter C1 and the system clock signal used as a reference clock signal in operation of the MPU 311 that executes timer interrupt processing do not synchronize with each other. The above-mentioned inconvenience is likely to occur because it is set.

  On the other hand, in the present embodiment, since the input of the hard random number clock signal to the MPU 311 is cut off during the acquisition process of the big hit random number counter C1, the big hit random number counter is generated during the period. There is no update of C1. Thereby, the above-mentioned inconvenience can be avoided.

  According to the embodiment described above, the following excellent effects can be obtained.

  In addition to the system clock circuit 312 that outputs the system clock signal, a hard random number clock circuit 313 that outputs a hard random number clock signal that triggers updating of the big hit random number counter C1 is provided. The hard random number clock signal and the system clock signal are set so that their cycles are different from each other. Thus, even if the cycle of the system clock signal is specified, the update interval of the jackpot random number counter C1 is difficult to specify. Therefore, by grasping the update timing of the big hit random number counter C1, an illegal signal can be output at the timing when the value of the big hit random number counter C1 becomes the winning value, and it is possible to suppress an act of causing a big hit illegally.

  Further, since the hard random number clock signal and the system clock signal are not synchronized with each other, the timing at which the value of the big hit random number counter C1 becomes the winning value is specified in synchronization with the input of the system clock signal. Cheating can be suppressed.

  A signal conversion circuit 402 for converting an AC voltage into a pulse signal is provided. Thereby, since a pulse signal is obtained using a commercial power supply, the configuration can be simplified.

  Here, since the frequency of the AC voltage from the commercial power source is known (50 Hz or 60 Hz), the cycle of the pulse signal is specified from the frequency, and the update timing of the big hit random number counter C1 may be specified from the cycle. is there.

  On the other hand, according to the present embodiment, the frequency conversion circuit 401 is provided to convert the frequency of the AC voltage into a specific frequency. As a result, it is difficult to specify the frequency of the AC voltage input to the signal conversion circuit 402, so it becomes difficult to specify the update interval of the big hit random number counter C1.

  Furthermore, for the hard random number so that the cycle T1 of the hard random number clock signal output from the hard random number clock circuit 313 and the trigger interval (Ta or Tb) of the pulse signal that triggers the update of the large hit random number counter C1 are different. A modulation circuit 314 is provided to modulate the clock signal. As a result, even if the cycle T1 of the pulse signal is grasped, it is difficult to grasp the update timing of the jackpot random number counter C1. Therefore, by grasping the cycle T1 of the pulse signal, it is possible to suppress a cheating attempt to specify the update timing of the big hit random number counter C1.

  The modulation circuit 314 outputs a pulse signal group including a plurality of pulse signals as one cycle, and the update of the jackpot random number counter C1 according to the pulse signal group is repeated in units of the pulse signal group. Here, the numerical range of the jackpot random number counter C1 and the number of pulse signals were set so that the number of counter terms would not be a multiple of the number of pulse signals included in the pulse signal group. Thus, it is difficult to specify the timing at which the value of the jackpot random number counter C1 becomes the winning value, since the timing at which the value of the jackpot random number counter C1 becomes the winning value fluctuates each time the jackpot random number counter C1 makes one revolution. Can.

  Also, by changing the update interval, the period required for one round of the big hit random number counter C1 is sequentially transitioned to one of two types of periods, while a unit period including these two types of periods However, the jackpot random number counter C1 is repeated every two revolutions. Thereby, a unit period (a period required for the big hit random number counter C1 to make one rotation when started from the first timing, and a period required for the big hit random number counter C1 to make one rotation when started from the second timing And the winning probability is constant. Therefore, since the substantial winning probability does not change, the fairness of the game and the ease of management of the game hall are secured.

  Furthermore, every time the big hit random number counter C1 makes one revolution, while the period for which the big hit random number counter C1 is the winning value is sequentially transitioned to any one of two types of periods (Ta or Tb), The period occupied in the unit period is constant (Ta + Tb). As a result, if attention is focused on a unit period as one unit, the winning probability is constant. Therefore, since the substantial winning probability does not change, the fairness of the game and the ease of management of the game hall are secured.

  It should be noted that if focusing on the large per round random number counter C1 going around multiple times, the period in which the large per round random number counter C1 is the winning value and the time required for the large per round random number counter C1 to make one turn are units having multiple types of periods. It can be said that it is preferable that the period is sequentially transitioned to any of a plurality of types of periods included in the unit period in the period, and the winning probability is substantially constant for each unit period.

Second Embodiment
In the first embodiment, the big hit random number counter C1 is configured to return to a predetermined value (“0”) when the big hit random number counter C1 makes one revolution. On the other hand, in the present embodiment, the processing in the case where the big hit random number counter C1 makes one turn is different from that of the first embodiment. The difference will be described. In addition, about the same structure as 1st Embodiment, while attaching | subjecting the same code | symbol, description is abbreviate | omitted.

  In the present embodiment, a random number initial value counter CINI is provided in various counter areas of the RAM 316. In the random number initial value counter CINI, the possible numerical range is determined corresponding to the big hit random number counter C1, for example, when the possible numeric range of the big hit random number counter C1 is "0 to 4", the random number The initial value counter CINI is also set to be "0 to 4".

  Next, timer interrupt processing in the present embodiment will be described using the flowchart of FIG.

  First, in step S601, a signal reading process is performed. In the signal reading process, the information input to the input port 311a from the ball detection sensors individually provided for the general winning opening 82, the variable winning device 83, the operation opening 84 and the through gate 85 is confirmed, and the confirmation result Identify the presence or absence of ball entry to each ball entry section from. Specifically, the input of a signal (for example, a LOW level signal) corresponding to the fact that the game ball is not detected in any one process is confirmed, and the game ball is detected in the subsequent two processes. When the input of the signal (for example, HI level signal) corresponding to what is done is confirmed continuously, it specifies with the ball entering part of the game ball having occurred in the ball entering part corresponding to the detection sensor.

  After the signal reading process is performed, the random number initial value counter CINI is updated in step S602. Specifically, the random number initial value counter CINI is incremented by 1 and cleared to 0 (initialized) when the value reaches the maximum value.

  After that, the update prohibition process is executed in step S603. In the processing, processing for prohibiting the update of the jackpot random number counter C1 is executed. Specifically, the input of the hard random number clock signal to the MPU 311 is cut off.

  In the subsequent step S604, processing for acquiring the value of the jackpot random number counter C1 is executed, and the process proceeds to step S605.

  In step S605, based on the value of the jackpot random number counter C1 acquired in step S604, it is determined whether or not the jackpot random number counter C1 has made one revolution. Specifically, it is determined whether or not the value of the obtained jackpot random number counter C1 matches the initial value set when the previous jackpot random number counter C1 makes one revolution. If it is determined that the big hit random number counter C1 has not made one revolution, the process proceeds to step S607, while if it is determined that the big hit random number counter C1 has made one round, the process proceeds to step S606 and the initial value setting process is performed. Run. Specifically, the value of the random number initial value counter CINI at that time is read, and the value is written as the initial value of the big hit random number counter C1.

  The random number initial value counter CINI is a counter that is updated by timer interrupt processing, and fluctuates according to the read timing. As a result, the initial value of the jackpot random number counter C1 fluctuates. Therefore, even if the number of counter terms is a multiple of the number of clock signals included in the clock signal group, the value of the big hit random number counter C1 becomes an initial value every time the big hit random number counter C1 makes one revolution. During a period from the timing when the jackpot value is reached to the timing when the jackpot value is reached, the period when the value of the jackpot random number counter C1 is the winner value, and the jackpot winning probability fluctuate, the substantial winning probability does not fluctuate.

  Here, the update interval of the jackpot random number counter C1 is set to be longer than 2 msec, which is a period required for one process of the timer interrupt process. Specifically, since the frequency of the AC voltage output from the frequency conversion circuit 401 is 300 Hz, the period of the pulse signal output from the signal conversion circuit 402 is 1/300 sec. Then, since the trigger interval is modulated by the modulation circuit 314 so that Ta = 3T1 or Tb = 4T1, the update interval of the big hit random number counter C1 is 10 msec or about 13 msec. Thereby, after the update of the jackpot random number counter C1 is executed, the timer interrupt process is executed at least once until the next update of the jackpot random number counter C1 is executed. Therefore, in the timer interrupt process, it can be reliably specified that the big hit random number counter C1 is making a round.

  After the process of step S606 is completed, the process proceeds to step S607, and the update prohibition release process is performed. In the update prohibition cancellation process, the input of the hard random number clock signal to the MPU 311 is resumed. As a result, the update of the jackpot random number counter C1 is resumed.

  That is, the update of the big hit random number counter C1 is prohibited over the period from the acquisition process of the big hit random number counter C1 to the initial value setting process. As a result, while the MPU 311 is accessing the big hit random number counter C1 in the timer interrupt process, updating of the big hit random number counter C1 is prohibited. Therefore, an error that may occur due to different processes being simultaneously performed on the jackpot random number counter C1 is avoided.

  Thereafter, in step S609, the start winning process is executed. Since the said process is the same as the process shown in FIG. 18, description is abbreviate | omitted.

  According to the present embodiment described above, the random number initial value counter CINI is provided, and when the big hit random number counter C1 makes one turn, the value of the random number initial value counter CINI at that time is taken as the initial value of the big hit random number counter C1. Execute the process to set. Thus, even if the number of counter terms is a multiple of the number of pulse signals included in the pulse signal group, the value of the big hit random number counter C1 becomes the initial value every time the big hit random number counter C1 makes one revolution. During a period from the timing when it becomes to the timing to become the winning value, the period when the value of the big hit random number counter C1 becomes the winning value, and the big hit winning probability fluctuate, the substantial winning probability does not fluctuate. Therefore, it is difficult to specify the timing when the value of the jackpot random number counter C1 becomes the winning value. Therefore, by specifying the timing when the value of the big hit random number counter C1 becomes the winning value, and outputting an illegal signal at the relevant timing, the numerical range of the big hit random number counter C1 is suppressed while intentionally suppressing the fraud that causes the big hit. And the number of signals of the pulse signal group can be increased.

  Further, in the case of such a configuration, in order to grasp the value of the big hit random number counter C1, it is necessary to grasp the update timing of the big hit random number counter C1 and the update timing of the random number initial value counter CINI. Here, the update of the random number initial value counter CINI is performed by software processing by the MPU 311, while the update of the big hit random number counter C1 is performed uniquely based on the hard random number clock signal. Thereby, the update timing of the random number initial value counter CINI and the update timing of the big hit random number counter C1 are different from each other. Therefore, since it is necessary to grasp each timing of both, it is difficult to specify the value of the jackpot random number counter C1. Therefore, it can be made difficult to specify the timing when the value of the jackpot random number counter C1 becomes the winning value.

  Furthermore, the update process of the jackpot random number counter C1 is prohibited before and after the process so that the jackpot random number counter C1 is not updated during the process of setting the initial value. This makes it possible to prevent the occurrence of an error that may occur due to the update of the jackpot random number counter C1 in a situation where the MPU 311 accesses the jackpot random number counter C1.

Third Embodiment
In the first embodiment, the big hit random number counter C1 is updated based on the input of the hard random number clock signal output from the hard random number clock circuit 313, and the hard random number clock signal is: It was modulated so as to be alternately output at two types of output intervals of Ta and Tb. Then, the difference between Ta and Tb is set small so that the substantial probability approaches the theoretical probability. On the other hand, in the present embodiment, the jackpot random number counter C1 is updated using the hard random number clock signal having a large difference between Ta and Tb. Hereinafter, the difference will be described. For convenience of explanation, it is assumed that the numerical value range that can be taken by the jackpot random number counter C1 is set to “0 to 1”, and the winning value is set to “0”.

  As shown in the timing chart of FIG. 25, the output interval of the hard random number clock signal output from the modulation circuit 314 is set such that Tb is five times that of Ta. Then, assuming that the rising timing of the preceding pulse signal (the pulse signal with the smaller pulse width) is the first timing, and the rising timing of the subsequent pulse signal (the pulse signal with the larger pulse width) is the second timing. At the timing, the big hit random number counter C1 is set to "0", and at the second timing, the big hit random number counter C1 is set to "1".

  In this configuration, the period until the jackpot random number counter C1 makes one revolution is 6Ta, and the period during which the winning value is "0" is Ta, so the actual winning probability is 1 It is / 6. The said probability is smaller than the theoretical probability 1/2 calculated from the numerical range which big hit random number counter C1 can take. That is, by adjusting the difference between Ta and Tb, the actual winning probability is adjusted.

  According to the present embodiment described above, the modulation circuit 314 is provided to modulate the pulse signal so that the hard random number clock signal is output at two types of intervals. Thus, by adjusting the difference between the two, it is possible to adjust the actual winning probability. Therefore, the update frequency of the jackpot random number counter C1 can be reduced while setting the jackpot winning probability to a predetermined probability. Thus, the processing load can be reduced.

  In particular, when the output interval of the hard random number clock signal is two types, the substantial win probability is lower than the theoretical probability calculated from the numerical range that can be taken by the big hit random number counter C1 by increasing the difference between the two. can do. As a result, since the value of the counter necessary for setting the predetermined winning probability can be small, the capacity required for the jackpot random number counter C1 can be reduced.

  Also, in this case, since the period in which the value of the jackpot random number counter C1 is the winning value is shorter than the period in which the other numbers are, the value of the jackpot random number counter C1 is the winning value It has become difficult to adjust to the period. As a result, it is possible to output an unauthorized signal in accordance with the timing at which the value of the jackpot random number counter C1 is the winning value, and to suppress the fraudulent act of intentionally generating a jackpot.

  In the present embodiment, the output interval of the hard random number clock signal is set to two types. However, the present invention is not limited to this. For example, three or four types may be used.

Fourth Embodiment
In the above embodiments, the hard random number clock circuit 313 is configured to generate a hard random number clock signal by converting an alternating voltage supplied from the alternating current power supply unit 321 d. On the other hand, in the present embodiment, the configuration relating to the hard random number clock circuit 313 is different from each of the above embodiments, and the difference will be described with reference to FIG. FIG. 26 is a block diagram showing a part of the electrical configuration of the pachinko machine 10 in the present embodiment. In addition, about the same structure as 1st Embodiment, while attaching | subjecting the same code | symbol, description is abbreviate | omitted.

  In the present embodiment, as shown in FIG. 26, a signal line LN1 and a signal line LN2 are provided as signal paths connecting the system clock circuit 312 and the MPU 311. The system clock circuit 312 outputs a system clock signal to the MPU 311 via both the signal line LN1 and the signal line LN2.

  Here, a clock conversion circuit 501 is provided on the signal line LN2. The clock conversion circuit 501 converts the system clock signal input from the system clock circuit 312 into a hard random number clock signal and outputs the hard random number clock signal to the MPU 311.

  Specifically, the clock conversion circuit 501 includes a divider circuit 502 that divides the frequency of the input clock signal, and a phase shift circuit 503 that shifts the phase of the clock signal by a predetermined amount.

  Divider circuit 502 is connected to system clock circuit 312 via signal line LN2, and divides the frequency of the system clock signal output from system clock circuit 312 into 1 / N (N is a natural number). At the same time, the divided clock signal is output to the phase shift circuit 503. The cycle of the divided clock signal is different from the cycle of the system clock signal. The frequency of the divided clock signal corresponds to the specific frequency in the first embodiment.

  The phase shift circuit 503 shifts the phase of the divided clock signal output from the divider circuit 502 by a predetermined amount, and outputs the shifted clock signal toward the MPU 311 as a hard random number clock signal. Accordingly, when the hard random number clock signal and the system clock signal are compared, the cycles are different from each other and the phases are different from each other. Therefore, the hard random number clock signal and the system clock signal are not synchronized.

  The modulation circuit 314 is provided on the signal line LN2 that connects the clock conversion circuit 501 and the MPU 311. The modulation circuit 314 modulates the hard random number clock signal output from the clock conversion circuit 501, and outputs a pulse signal group including a plurality of pulse signals as one cycle, thereby triggering update of the big hit random number counter C1. The trigger is to be at two types of intervals. As a result, the update interval of the jackpot random number counter C1 fluctuates.

  According to the present embodiment described above, the clock conversion circuit 501 is provided which generates a clock signal for hard random numbers having a cycle and a phase different from that of the system clock signal by changing the system clock signal. As a result, there is no need to independently provide a circuit for outputting a hard random number clock signal (hard random number clock circuit 313 and AC power supply unit 321 d in the first embodiment), so that the configuration can be simplified.

  Also in this case, by providing the modulation circuit 314 on the signal line LN2 connecting the clock conversion circuit 501 and the MPU 311, the update interval of the big hit random number counter C1 can be varied.

  The frequency of the hard random number clock signal can be set so that the trigger interval becomes longer than the cycle of the timer interrupt processing by adjusting the dividing ratio of the dividing circuit 502. Thereby, it is determined whether or not the configuration of the second embodiment, specifically, the big hit random number counter C1 makes one turn, and it is determined that the big hit random number counter C1 makes one turn, the big hit A configuration for executing the process of setting the initial value of the random number counter C1 can be applied.

Fifth Embodiment
In the present embodiment, the configuration relating to the update of the jackpot random number counter C1 is different from that in each of the above embodiments. The difference will be described. In addition, while attaching | subjecting the code | symbol same about the structure same as said each embodiment, description is abbreviate | omitted.

  In this embodiment, as shown in FIGS. 27 and 28, the hard random number clock circuit 313 is not provided, and a large hit random number counter C1 is provided in the counter area of the RAM 316 instead of the counter circuit 317. The points are different from the above embodiments. The jackpot random number counter C1 is configured to be updated by the MPU 311, similarly to the other counters (the jackpot type counter C2 and the reach random number counter C3).

  Further, a random number initial value counter CINI is provided in the counter area, and the random number initial value counter CINI is also updated in the control of the progression of the game in the MPU 311.

  The main control board 301 is provided with a reset circuit 601 and an irregular delay circuit 602. The reset circuit 601 is electrically connected to the MPU 311 via the irregular delay circuit 602. The reset circuit 601 switches the output state of the signal directed to the MPU 311 to the HI level or the LOW level in accordance with the voltage supplied from the power failure monitoring substrate 302. In detail, when the voltage of the power supply supplied from the power supply and emission control board 321 is equal to or higher than the reference voltage when the external power supply is supplied to the power supply and emission control board 321, the HI level is set to operate. A signal is output, and a LOW level is output to stop the operation of the MPU 311 in a state of being less than the reference voltage (ie, a state in which the pachinko machine 10 is in a power-off state). The HI level signal corresponds to a reset signal as an operation signal. The MPU 311 performs update processing and the like of the jackpot random number counter C1 based on the input of the reset signal. Here, a state in which the external power is supplied to the power supply and the emission control board 321 is referred to as a power-on state of the pachinko machine 10, and a state in which the power is not supplied is referred to as a power-off state of the pachinko machine 10. That is, the power-on state means a state in which the operating power is supplied to the pachinko machine 10, and the power-off state means a state in which the operating power is not supplied to the pachinko machine 10.

  The irregular delay circuit 602 varies the input timing of the reset signal to the MPU 311 with respect to the output timing of the reset signal output from the reset circuit 601. This will be described later.

<Timer interrupt processing>
FIG. 29 is a flowchart showing timer interrupt processing in the present embodiment.

  In the timer interrupt process, first, in step S701, a signal reading process is executed. In the signal reading process, the information input to the input port 311a from the ball detection sensors individually provided for the general winning opening 82, the variable winning device 83, the operation opening 84 and the through gate 85 is confirmed, and the confirmation result Identify the presence or absence of ball entry to each ball entry section from.

  After the signal reading process is performed, the random number initial value counter CINI is updated in step S702. In the subsequent step S703, the jackpot random number counter C1, the jackpot type counter C2 and the reach random number counter C3 are updated. Such update corresponds to the update by the numerical information update means. Specifically, the value of each random number counter is incremented by one, and it is determined whether the added value is the upper limit value. Then, when the added value exceeds the upper limit value, the value of the counter is set to the initial value. Here, regarding the jackpot random number counter C1, the value of the random number initial value counter CINI at that time is read as the initial value of the jackpot random number counter C1. Since the random number initial value counter CINI is a random number value, the initial value of the jackpot random number counter C1 fluctuates. Therefore, since the timing at which the value of the big hit random number counter C1 matches the winning value differs every time the big hit random number counter C1 makes one revolution, it is difficult to grasp the timing at which the value of the big hit random number counter C1 becomes the winning value It has become.

  Thereafter, in step S704, the start winning process is executed. Specifically, as shown in the flowchart of FIG. 30, the presence or absence of a prize in the operation port 84 is confirmed in S801, and it is determined whether or not the number N of operation pending balls is smaller than 4 in step S802. If it is, N is incremented by one in step S803. Then, in step S804, the various counters C1, C2, and C3 are stored in the holding ball storage area corresponding to the operation holding ball number N.

  Here, in the present embodiment, the jackpot random number counter C1 is updated by the MPU 311. Therefore, in the start winning process, the processing for prohibiting the update of the jackpot random number counter C1 when acquiring the jackpot random number counter C1 (FIG. The process of step S304 to step S306 in step 18 is omitted.

<About Irregular Delay Circuit 602>
As described above, in the pachinko machine 10, the jackpot lottery is performed by the game ball entering the operation opening 84. Specifically, when a game ball enters the operating opening 84, it is detected by the operating opening switch 154, and an entrance detection signal is output from the operating opening switch 154. When the ball entry detection signal is input to the MPU 311, the value of the jackpot random number counter C1 at that time is acquired. Then, it is determined based on the value of the jackpot random number counter C1 whether or not it is a jackpot.

  Here, there is a case where a fraudulent act using a fraudulent board called "hanging board" is performed. The fraud is to cause the jackpot condition to occur illegally by hanging the wrong substrate against the regular control substrate. Specifically, a counter synchronized with the big hit random number counter C1 is provided on the “hanging board”, and the value of the counter is reset to “0” in accordance with the power on of the pachinko machine 10, etc. The occurrence timing of the jackpot state, that is, the timing at which the value of the jackpot random number counter C1 matches the winning value predetermined as the jackpot winning, is grasped. And according to the generation | occurrence | production timing of this big hit state, an incorrect entering detection signal is output from a "hanging board | substrate", and a big hit state is generated illegally.

  On the other hand, in this embodiment, the irregular delay circuit 602 is provided at an intermediate position in the signal path from the reset circuit 601 to the MPU 311, and it is difficult to grasp the timing of the big hit by the irregular delay circuit 602. doing.

  The irregular delay circuit 602 will be described in detail based on the block circuit diagram of FIG.

  The irregular delay circuit 602 is hardware including an integrating circuit 611 and a NAND circuit 612. The NAND circuit 612 has two input terminals and an output terminal that outputs a signal corresponding to the input signal of the two input terminals. The two input terminals of the NAND circuit 612 and the reset circuit 601 are electrically connected via the signal line LN3 and the signal line LN4. An integration circuit 611 is provided at an intermediate position of the signal line LN4. That is, as a supply path from the reset circuit 601 to the NAND circuit 612, a signal line LN3 not passing the integration circuit 611 and a signal line LN4 passing the integration circuit 611 are provided.

  The integration circuit 611 includes a capacitor 613 as charge / discharge means for storing and discharging electric charge, and a resistor 614. The capacitor 613 is connected in parallel to the resistor 614. More specifically, one end of the resistor 614 is connected to the reset circuit 601, and the other end is connected to the input terminal of the NAND circuit 612 and also connected to one end of the capacitor 613. The other end of the capacitor 613 is grounded. When the reset signal is output from the reset circuit 601, that is, when the pachinko machine 10 is turned on, a voltage is applied to the capacitor 613 to be in a charged state. On the other hand, when the reset signal is not output, that is, when the pachinko machine 10 is in the power-off state, the capacitor 613 is discharged, and the charge stored in the capacitor 613 is gradually released.

  A resistor 614 is connected on a path connecting the capacitor 613 and the reset circuit 601 in the signal line LN4. The resistor 614 has an electrical resistance, and a charge period in which the charge of the capacitor 613 is started by the resistance value of the resistor 614 and the capacitance of the capacitor 613 and then the charge is accumulated up to a predetermined amount, and The period of time from the start of charge release to the loss of accumulated charge is determined. Specifically, if the time constant which is a numerical value obtained by multiplying the electric capacity of the capacitor 613 by the resistance value of the resistor 614 is large, the charge period and the discharge period become long. On the other hand, if the time constant is small, the charging and discharging period becomes short. Note that the resistor 614 is not essential, and any resistor may be used as long as it has an electrical resistance.

  The NAND circuit 612 is electrically connected to the reset circuit 601 by the signal line LN4 passing through the integration circuit 611 and the signal line LN3 not passing through the integration circuit 611, and the reset circuit 601 outputs a reset signal. Ru. Further, the output terminal of the NAND circuit 612 and the MPU 311 are electrically connected. The NAND circuit 612 is connected to the disconnection monitoring substrate 302 via an electrical path (not shown) and is supplied with operating power.

  The NAND circuit 612 outputs the LOW level signal to the MPU 311 when the reset signal which is the HI level signal from both the signal line LN3 and the signal line LN4 is input. When the signal is input, the MPU 311 operates (becomes operating). Thereby, the update of the jackpot random number counter C1 is started. That is, the LOW level signal output from the NAND circuit 612 corresponds to the update start signal. On the other hand, when the reset signal which is the HI level signal is not input from at least one of the signal line LN3 or the signal line LN4, the NAND circuit 612 outputs the HI level signal. In this situation, the MPU 311 is inoperative and the update of the jackpot random number counter C1 is stopped. That is, the HI level signal output from the NAND circuit 612 corresponds to the stop signal. From the above, when the LOW level signal is not input from the NAND circuit 612, the MPU 311 does not operate. Therefore, even if a voltage is applied to the MPU 311 due to noise or the like, the MPU 311 does not operate. Therefore, the malfunction of the MPU 311 due to noise can be prevented.

  Next, the operation of the integration circuit 611 when the pachinko machine 10 is powered on will be described based on the timing chart of FIG.

  With the pachinko machine 10 in the power-on state at time t10, generation of the +5 V voltage is started in the power-on unit for power-on 321a, and the reset circuit 601 outputs a reset signal that is HI level . The reset signal is input to the NAND circuit 612 through the signal line LN3 and the signal line LN4. Here, while the reset signal input to the NAND circuit 612 through the signal line LN3 has the same waveform as that output from the reset circuit 601, the reset signal input to the NAND circuit 612 through the signal line LN4 is The input timing is delayed by the transient phenomenon of the integration circuit 611.

  Specifically, when a reset signal having a HI level is output from the reset circuit 601, a voltage corresponding to the HI level signal is applied to the integration circuit 611. Then, the capacitor 613 of the integration circuit 611 is charged, and charge is accumulated in the capacitor 613. In such a state, the voltage corresponding to the HI level signal is applied to the capacitor 613, and the voltage applied to the NAND circuit 612 is at the LOW level. Then, as time passes, the amount of charge accumulated in the capacitor 613 increases, and the input voltage applied to the NAND circuit 612 rises.

  Thereafter, at the timing of t11, the input voltage from the signal line LN4 of the NAND circuit 612 becomes equal to or higher than the reference voltage Va which is a voltage that the NAND circuit 612 recognizes as the HI level signal. Thereby, the NAND circuit 612 recognizes that the HI level signal is input from the signal line LN4. Then, a low level signal, which is an update start signal, is output to the MPU 311 by the NAND circuit 612, and the MPU 311 starts operating accordingly. In other words, when a predetermined amount of charge is accumulated, the output state of the NAND circuit 612 is switched. Furthermore, in other words, when a predetermined amount of charge is stored, the state of the signal supplied to NAND circuit 612 is shifted to the operable state. Then, random number counter update processing such as the jackpot random number counter C1 is executed. That is, the output timing of the LOW level signal from the NAND circuit 612 with respect to the output timing of the HI level signal from the reset circuit 601 is delayed by the integration circuit 611 by a delay period DT1 from the timing of t10 to the timing of t11.

  After that, when the power supply from the external power supply in the pachinko machine 10 is turned off at time t12, that is, when the pachinko machine 10 is switched off, the reset signal from the reset circuit 601 is not output. That is, the reset signal output from the reset circuit 601 switches from the HI level to the LOW level. In response to the switching, the input signal from the signal line LN3 of the NAND circuit 612 immediately switches from the HI level to the LOW level. As a result, the NAND circuit 612 outputs the HI level which is the stop signal, and the MPU 311 specifies that the input signal is switched to the HI level, so that the MPU 311 becomes inoperative. Thereby, the operation of the MPU 311 can be immediately stopped regardless of the integration circuit 611.

  On the other hand, when the output of the reset signal which is the HI level is stopped, the capacitor 613 in the integration circuit 611 is discharged, and the charge stored in the capacitor 613 is gradually released with time. Thus, the voltage due to the residual charge accumulated in the capacitor 613 is applied to the NAND circuit 612 from the signal line LN4. The voltage gradually decreases as the charge stored in the capacitor 613 is released. Therefore, the timing when the LOW level signal output from the reset circuit 601 via the signal line LN4 is input to the NAND circuit 612 is delayed as in the case of the reset signal.

  That is, while the NAND circuit 612 does not output the LOW level signal for operating the MPU 311 until the reset signal which is the HI level delayed by the integration circuit 611 is input, the reset circuit 601 does not output the reset signal. That is, when the output from the reset circuit 601 is switched from the HI level to the LOW level, the HI level signal as the stop signal is immediately output to the MPU 311 based on the LOW level signal regardless of the integration circuit 611. It has become. Accordingly, when the reset signal is output, the integration circuit 611 delays the start timing of the operation of the MPU 311, and when the reset signal is not output, the operation of the MPU 311 can be rapidly stopped. it can.

  Thereafter, when the pachinko machine 10 is turned on again at the timing of t13, the capacitor 613 is charged again, and charges are accumulated. Then, when the input voltage from the signal line LN4 of the NAND circuit 612 becomes equal to or higher than the reference voltage Va at the timing of t14, the HI level signal is input from the signal line LN4 to the NAND circuit 612, along with which the NAND circuit 612 A LOW level signal is output to the MPU 311.

  Here, the reset signal which is HI level is output from the reset circuit 601, and the delay time during which the input voltage to the NAND circuit 612 is higher than the reference voltage Va, that is, the HI level signal is input to the NAND circuit 612 is HI level. It fluctuates depending on the residual charge amount of the capacitor 613 at the time when a certain reset signal is output. Specifically, the period for completing the charging of the capacitor 613 is shortened by the amount of residual charge at the time when the reset signal which is the HI level is output, and the timing when the MPU 311 starts the operation becomes earlier. Here, at the timing of t10 and t13 when the reset signal is output, at the timing of t10, the voltage from the signal line LN4 is not applied to the NAND circuit 612, so the charge remains in the capacitor 613. It can be said that On the other hand, at the timing of t13, since a voltage is applied to the NAND circuit 612 from the signal line LN4, it can be said that electric charge remains in the capacitor 613. Therefore, a delay period DT1 from the timing of t10 to the timing of t11, which is the timing when the signal input to the NAND circuit 612 switches from the LOW level signal to the HI level signal, is input to the NAND circuit 612 from the timing of t13. Is longer than the delay period DT2 until the timing of t14, which is the timing when the signal to be switched from the LOW level signal to the HI level signal.

  A series of operations from the timing of t15 to the timing of t17 is similar to the operation from the timing of t12 to the timing of t14. However, since the period from t15 when the pachinko machine 10 is in the power-off state to the timing at t16 switching to the power-on state is shorter than the period from t15 to t16, the residual charge is The quantity is increasing. Therefore, the delay period DT3 from the timing of t16 when the pachinko machine 10 enters the on state to the timing when the input voltage from the signal line LN4 becomes the reference voltage Va for the NAND circuit 612 has other delay periods DT1 and DT2. It is shorter than that.

  From the above, the delay period from the output timing of the reset signal from the reset circuit 601 to the output timing of the LOW level signal from the NAND circuit 612 varies depending on the amount of residual charge at the time when the pachinko machine 10 is turned on. doing. Specifically, the delay period is shorter as the residual charge amount is larger. Further, the residual charge amount depends on the period from when the pachinko machine 10 is turned off to when it is turned on. Specifically, the residual charge amount is gradually reduced after the power-off state. That is, the output timing of the LOW level signal from the NAND circuit 612 fluctuates depending on the period from when the pachinko machine 10 is turned off to when it is turned on.

  According to the fifth embodiment described above, the following excellent effects can be obtained.

  An irregular delay circuit 602 is provided in the middle of the supply path from the reset circuit 601 to the NAND circuit 612. The irregular delay circuit 602 delays the output timing of the LOW level signal from the NAND circuit 612 with respect to the output timing of the reset signal from the reset circuit 601. The delay period fluctuates depending on the output timing of the reset circuit 601. As a result, since the delay period varies, the period from the power supply start timing to the pachinko machine 10 to the update start timing of the jackpot random number counter C1 is irregular. Therefore, even when the update process of the jackpot random number counter C1 is started from a predetermined initial value when the power supply to the pachinko machine 10 is started, it is difficult to grasp the timing of the jackpot winning. Therefore, it is possible to prevent fraudulent acts using the "hanging board" or the like. Note that the irregular delay circuit 602 may be a “circuit for non-periodical operation” or “a non-periodical circuit” if it is focused on the function of changing the period from the output timing of the reset signal to the operation start timing of the MPU 311 It can also be called "periodic delay circuit".

  Specifically, an integration circuit 611 is provided as the irregular delay circuit 602, and the capacitor 613 of the integration circuit 611 is charged by the reset signal. The reset signal is input to the NAND circuit 612 when the amount of charge stored in the capacitor 613 becomes equal to or more than a predetermined amount. Thereby, the input of the reset signal to the NAND circuit 612 is delayed from the output timing of the reset signal from the reset circuit 601 until the charge of a predetermined amount or more is accumulated in the capacitor 613. Therefore, the LOW from the NAND circuit 612 The output timing of the level signal is delayed. The delay period fluctuates depending on the amount of residual charge at the time when the reset signal is output. In addition, the residual charge amount fluctuates depending on the period from when the pachinko machine 10 is turned off to when it is turned on. That is, the delay period fluctuates according to the output timing of the reset signal. Therefore, the period from the output timing of the reset signal from the reset circuit 601 to the output timing of the LOW level signal from the NAND circuit 612 is irregular. This makes it difficult to grasp the timing of winning the jackpot. Therefore, the integration circuit 611 can prevent fraudulent acts using a “hanging board” or the like.

  In particular, the integration circuit 611 in the present embodiment is a simple circuit including one capacitor 613 and one resistor 614. Even with the simple configuration, the period from the output timing of the reset signal from the reset circuit 601 to the output timing of the LOW level signal from the NAND circuit 612 can be irregular. This makes it possible to prevent fraudulent acts using a “hanging board” or the like with a simple configuration.

  Moreover, when performing the fraudulent activity using a "hanging board" etc. continuously, in the pachinko machine 10, it is assumed that a power-on state and a power-off state switch in a relatively short time. On the other hand, the residual charge amount of the capacitor 613 in the integration circuit 611 changes more greatly as the period from when the pachinko machine 10 is turned off to when the pachinko machine 10 is turned on is shorter. This is particularly effective when the fraudulent acts using “etc.” are continuously performed.

  Further, the charging period and discharging period of the capacitor 613 are determined by the electric resistance of the resistor 614 and the capacitance of the capacitor 613. Thus, the range of variation of the delay period can be increased by extending the charge period and the discharge period. Therefore, since the variation of the delay period can be increased, the delay period can be made more irregular. Therefore, it is possible to make it difficult to grasp the timing of winning the jackpot.

  Furthermore, the amount of charge accumulated in the capacitor 613 changes according to the number of times the capacitor 613 is charged and the number of times the charge accumulated in the capacitor 613 is discharged. Specifically, it is conceivable that the insulating film is degraded by the electric field applied to the insulating film of the capacitor 613. Then, since the maximum charge amount and capacitance stored in the capacitor 613 change, the residual charge amount fluctuates. As a result, since the delay period becomes more irregular, it is possible to make it difficult to grasp the timing of the jackpot winning.

  As a supply path from the reset circuit 601 to the NAND circuit 612, a signal line LN3 not passing through the integration circuit 611 and a signal line LN4 passing through the integration circuit 611 are provided. The NAND circuit 612 outputs the LOW level signal for operating the MPU 311 when the reset signal which is the HI level is input from both the signal line LN3 and the signal line LN4, and outputs at least one of the signal line LN3 or the signal line LN4. When the reset signal which is the HI level is not input from the above, the HI level signal which is a stop signal for stopping the operation of the MPU 311 is output. As a result, when the reset signal is not output while ensuring the delay of the reset signal by the integration circuit 611, the stop signal is output from the NAND circuit 612 to the MPU 311 regardless of the integration circuit 611. As a result, by delaying the output timing of the stop signal, it is possible to prevent the MPU 311 from malfunctioning.

  Note that the resistance value of the resistor 614 and the capacitor 613 may be changed for each gaming machine. According to this configuration, since the discharge period and the charge period are different for each gaming machine, it is possible to make it more difficult to grasp the timing of the jackpot winning.

Sixth Embodiment
In the present embodiment, the configuration regarding the irregular delay circuit 602 is different from that of the fifth embodiment. Therefore, the configuration will be described in detail below. In the following description, differences from the fifth embodiment are mainly described, and the description of the same configuration is basically omitted. In the sixth embodiment, the irregular delay circuit 602 is configured as shown in FIG. 33 instead of the configuration shown in FIG. 31 to make the charge period and the discharge period different.

  The irregular delay circuit 602 is provided with a switching circuit 621. The switching circuit 621 is disposed on a path connecting the reset circuit 601 and the integration circuit 611. The reset signal output from the reset circuit 601 is input to the NAND circuit 612 through the switching circuit 621 and the integration circuit 611.

  The switching circuit 621 includes a diode 622 as rectifying means, and an adjustment resistor 623 for adjusting the discharge period with respect to the charge period. The diode 622 is connected in such a manner that the direction from the reset circuit 601 to the integration circuit 611 is a forward direction. Specifically, the anode side of the diode 622 is connected to the reset circuit 601, and the cathode side is connected to one end of the resistor 614 of the integration circuit 611. Also, the adjustment resistor 623 is connected in parallel to the diode 622. Specifically, one end of the adjustment resistor 623 is connected to the anode side of the diode 622, and the other end is connected to the cathode side of the diode 622. With this configuration, since the charge period and the discharge period of the capacitor 613 of the integration circuit 611 are different from each other, the MPU 311 can be quickly started up while securing the variation of the delay period.

  Specifically, when a reset signal is output from the reset circuit 601, a forward voltage is applied to the diode 622, so that a forward current flows. Then, a voltage corresponding to the reset signal is applied to the integration circuit 611, and the capacitor 613 is charged. As a result, the output timing of the LOW level signal from the NAND circuit 612 with respect to the output timing of the reset signal from the reset circuit 601 is delayed. Here, the delay period, that is, the charging period until the charge of a predetermined amount is accumulated in the capacitor 613 depends on the resistance value of the resistor 614 and the capacitance of the capacitor 613.

  On the other hand, when the output of the reset signal from the reset circuit 601 is stopped, that is, when the reset signal is switched from the HI level signal to the LOW level signal, the capacitor 613 is discharged and the charge stored in the capacitor 613 is released. Ru. Here, the charge stored in the capacitor 613 does not pass through the diode 622. Thus, the charge stored in the capacitor 613 is released via the resistor 614 of the integration circuit 611 and the adjustment resistor 623 connected in parallel to the diode 622. That is, the discharge period depends on the resistance value of the adjustment resistor 623 in addition to the resistor 614 and the capacitor 613. Therefore, the charging period and the discharging period of the capacitor 613 will be different. In detail, since the time constant in the discharge is larger than the time constant in the charge by the amount depending on the adjustment resistor 623, the discharge period is later than the charge period. That is, by connecting the diode 622 as the rectifying means and the adjustment resistor 623 in parallel to the diode 622, the discharge period is made relatively long with respect to the charge period.

  According to the embodiment described above, the following excellent effects can be obtained.

  The switching circuit 621 is provided to make the discharge period relatively long with respect to the charging period of the capacitor 613 in the integration circuit 611. Thereby, the start timing of the operation of the MPU 311 can be irregularly and quickly while securing the variation of the delay period.

  In order to widen the range of variation of the delay period and to increase the variation of the delay period, it is preferable to extend the charge period and the discharge period. In particular, it is preferable that the discharge period contributing to the variation of the residual charge amount be longer. In addition, in order to cause variations in the delay period even in a long-term power failure state, it is preferable that the discharge period be longer. Then, in order to extend the discharge period, it is conceivable to increase the resistance value of the resistor 614 of the integration circuit 611 or the electrostatic capacitance of the capacitor 613. However, since the charge period and the discharge period are the same in the integration circuit 611 alone, the charge period is also extended. Then, the start timing of the operation of the MPU 311 may be delayed excessively. On the other hand, in the present embodiment, the discharge period is longer than the charge period by the switching circuit 621. As a result, it is suppressed that the start timing of the operation of the MPU 311 is excessively delayed while securing the variation of the delay period.

  Note that, instead of or in addition to the adjustment resistor 623, the adjustment circuit and the adjustment capacitor are connected in series with the adjustment capacitor 611, and the capacitor 613 and the adjustment capacitor are connected in series under the charge condition, and the capacitor 613 and the adjustment capacitor under the discharge condition. It is good also as composition provided with the switching means connected in parallel. According to this configuration, since the combined capacitance of the capacitor 613 and the adjustment capacitor under the discharge state becomes larger than that under the charge state, the discharge period can be made longer than the charge period.

  In addition, although the diode 622 is used as the rectifying unit, the present invention is not limited thereto. For example, instead of the diode 622, the diode 622 is turned on when the reset signal is output from the reset circuit 601, and the reset signal is not output. A switching element which is turned off may be provided. The point is that the current should flow in one direction.

Seventh Embodiment
In the present embodiment, the configuration regarding the irregular delay circuit 602 is different from that of the fifth embodiment. Therefore, the configuration will be described in detail below. In the following description, differences from the fifth embodiment are mainly described, and the description of the same configuration is basically omitted. In the seventh embodiment, the configuration shown in FIGS. 34 to 36 is used instead of the configuration shown in FIGS.

  The power supply and emission control substrate 321 is provided with an AC power supply unit 631 for outputting an AC voltage. The AC power supply unit 631 is different from the AC power supply unit 321 d according to the first embodiment and the like, and includes a full-wave rectification circuit as a waveform shaping unit for adjusting a voltage waveform, and +24 V AC voltage supplied from a commercial power supply The output waveform of is rectified in one direction. The AC power supply unit 631 is always supplied with power from a commercial power supply regardless of the power-on state or power-off state of the pachinko machine 10.

  Further, the power failure monitoring substrate 302 includes a power failure monitoring circuit 632 that monitors a voltage, and a signal conversion circuit 402 that converts an AC voltage into a pulse signal. The power failure monitoring circuit 632 monitors the DC stable +24 V voltage which is the maximum voltage output from the power supply and emission control board 321. When the voltage is higher than a predetermined voltage, an HI level signal is output to the main control substrate 301, and when the voltage is lower than the predetermined voltage, it is determined that the power is shut off. Output a LOW level signal as a power failure signal.

  The signal conversion circuit 402 is a circuit that converts the AC voltage output from the AC power supply unit 631 into a pulse signal as described in the first embodiment. The pulse signal is output to the irregular delay circuit 602.

  The connection relationship of the signal conversion circuit 402, the irregular delay circuit 602, and the MPU 311 will be described in detail based on the block diagram of FIG.

  Here, the Schmitt trigger 413 is electrically connected to the power and discharge control board 321 via an electric path (not shown), and the pachinko machine 10 is powered by the power-on at power-on 321a and the power-on at power-off 321c. Power is supplied regardless of whether the power is on or off. As described above, the Schmitt trigger 413 outputs a LOW level signal if it is higher than a predetermined upper threshold voltage Vth, and outputs an HI level signal if it is lower than a predetermined lower threshold voltage Vtl. Specifically, when the AC voltage becomes higher than or equal to the upper threshold voltage Vth (for example +4.3 V), the LOW level signal is thereafter reduced until the AC voltage becomes lower than or equal to the lower threshold voltage Vtl (for example +3.5 V) lower than the upper threshold voltage Vth. When the AC voltage becomes lower than the lower limit threshold voltage Vtl, the HI level signal is output until the AC voltage becomes the upper limit threshold voltage Vth. Thereby, a pulse signal of a predetermined pulse width is obtained. In other words, by converting an alternating voltage into a pulse signal, a specific signal in which the HI level signal and the LOW level signal are alternately output is generated. Further, since the alternating voltage is rectified in one direction by the full wave rectification circuit, the frequency of the pulse signal is doubled as compared with the case of converting a normal alternating voltage into a pulse signal. Therefore, the operation process of the irregular delay circuit 602 using a pulse signal can be suitably performed.

  Also, the pulse width of the pulse signal can be adjusted by adjusting the upper threshold voltage Vth and the lower threshold voltage Vtl of the Schmitt trigger 413. Specifically, a pulse signal with a narrow pulse width can be obtained by narrowing the ranges of the upper limit threshold voltage Vth and the lower limit threshold voltage Vtl while bringing the upper limit threshold voltage Vth and the lower limit threshold voltage Vtl close to zero. That is, the Schmitt trigger 413 is a conversion unit that converts an AC voltage into a pulse signal, and a pulse width adjustment unit that adjusts the pulse width of the pulse signal.

  Further, the AC power supply unit 631 is connected to a commercial power supply and constantly supplied with electric power, and outputs an AC voltage. That is, the AC voltage is not affected by the power-on state and the power-off state of the pachinko machine 10. The Schmitt trigger 413 is supplied with power regardless of whether the pachinko machine 10 is turned on or off. Therefore, the pulse signal obtained by converting the AC voltage is also not affected by the on / off state of the pachinko machine 10. In other words, the form of the pulse signal is random with respect to the output timing of the reset signal.

  When the reset signal is output from the reset circuit 601, the irregular delay circuit 602 outputs a signal for operating the MPU 311 based on the form of the pulse signal input from the Schmitt trigger 413. The configuration will be described in detail.

  The irregular delay circuit 602 includes a synthesis circuit 641 and a D flip flop 642 in place of the integration circuit 611. The synthesis circuit 641, the D flip flop 642 and the NAND circuit 612 are connected to the power supply and emission control substrate 321 through an electric path and a disconnection monitor substrate 302 (not shown), respectively, and receive power supply from the power supply and emission control substrate 321. ing.

  The synthesis circuit 641 is formed of an AND circuit, and has two input terminals and an output terminal for outputting a signal based on the signals from the two input terminals. One input terminal of the synthesis circuit 641 and the output terminal of the Schmitt trigger 413 are connected. The pulse signal output from the Schmitt trigger 413 is supplied to the synthesis circuit 641. Further, the other input terminal of the synthesis circuit 641 and the reset circuit 601 are connected. The reset signal output from the reset circuit 601 is supplied to the combining circuit 641. The synthesis circuit 641 inputs the reset signal which is the HI level from the reset circuit 601 and the synthesis reset signal of the HI level to the D flip flop 642 only when the HI level signal is input from the Schmitt trigger 413. Output. On the other hand, when the reset signal is not input or when the signal input from the Schmitt trigger 413 is not the HI level signal, the combining circuit 641 does not output the combined reset signal. Thus, the output timing of the combined reset signal is delayed until the HI level signal is output.

  The D flip flop 642 has a data terminal (D terminal) and a clock terminal (CLK terminal) as input terminals, and has a positive logic output terminal (Q terminal) as an output terminal. The reset circuit 601 is connected to the D terminal, and the output terminal of the combining circuit 641 is connected to the CLK terminal. In addition, a NAND circuit 612 is connected to the Q terminal.

  The D flip-flop 642 outputs the reset signal which is HI level to the NAND circuit 612 while securing the delay generated by the synthesis circuit 641, and holds the reset signal output once without using the synthesis circuit 641. Have a function to Thus, even if the combined reset signal output from the combining circuit 641 fluctuates after the reset signal is output from the combining circuit 641 once, the output to the NAND circuit 612 is held. Therefore, it is possible to suppress the inconvenience that the operation of the MPU 311 is stopped due to the fluctuation of the synthesis reset signal.

  Specifically, the D flip-flop 642 receives a reset signal that is at the HI level at the timing when the combined reset signal is input from the combining circuit 641 to the CLK terminal (more specifically, the rising timing of the combined reset signal). If it is, it outputs a HI level signal to the NAND circuit 612. The HI level signal is continuously output until the reset signal is not input at the timing when the combined reset signal is input to the CLK terminal. In other words, it can be said that the D flip flop 642 holds the input state of the reset signal until the combined reset signal is input to the CLK terminal.

  Here, the operation of the synthesis circuit 641 and the D flip flop 642 will be described based on the timing chart of FIG.

  When the power of the pachinko machine 10 is turned on, that is, when the pachinko machine 10 is turned on at timing t18, the reset circuit 601 outputs a reset signal. More specifically, the reset circuit 601 outputs the HI level signal. Then, the reset signal is input to the D terminal of the D flip flop 642, and the reset signal is input to the combining circuit 641. On the other hand, since the output signal from the Schmitt trigger 413 is a LOW level signal, the combining circuit 641 outputs a LOW level signal. In such a state, the D flip flop 642 holds the LOW level signal. Therefore, the MPU 311 does not start the operation.

  When the output signal from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t19, the HI level signal is output from the synthesis circuit 641. Then, the signal input to the CLK terminal of the D flip flop 642 rises from the LOW level to the HI level. In such a case, the D flip flop 642 outputs a signal corresponding to the input state of the signal input to the D terminal at that time from the Q terminal. Here, since the reset signal which is HI level is input to the D terminal, the HI level signal is output from the Q terminal. Then, the reset signal is input to the NAND circuit 612. As a result, a low level signal is output from the NAND circuit 612, and the operation of the MPU 311 is started.

  That is, the start timing of the operation of the MPU 311 is delayed by the combining circuit 641 by the delay period DT4 from when the pachinko machine 10 is turned on to when the signal output from the Schmitt trigger 413 becomes the HI level signal. There is. Here, since the pulse signal fluctuates regardless of whether the pachinko machine 10 is switched on or off, the form of the pulse signal fluctuates according to the timing at which the pachinko machine 10 is switched on. Therefore, a delay period DT4 which is a period from the timing when the pachinko machine 10 enters the on state to the timing when the hi level state is one of the pulse signal forms takes place according to the timing when the pachinko machine 10 enters the on state. Change. Therefore, the delay period DT4 is irregular.

  Thereafter, when the output signal from the Schmitt trigger 413 switches from the HI level to the LOW level at the timing of t20, the combined reset signal output from the combining circuit 641 also switches from the HI level to the LOW level, and the CLK terminal of the D flip flop 642 The signal input to is also switched from HI level to LOW level. However, the D flip-flop 642 is a signal that is input to the D terminal in synchronization with the timing when the synthesis reset signal that is HI level is input to the CLK terminal, that is, the timing when the synthesis reset signal switches from LOW level to HI level. A signal corresponding to the input state of is output from the Q terminal, and synchronization is not performed at the timing when the combined reset signal switches from the HI level to the LOW level. Thus, the signal state output from the Q terminal is maintained.

  When the signal output from the Schmitt trigger 413 switches from the LOW level to the HI level at the timing of t21, the combining circuit 641 outputs a combining reset signal which is the HI level. Specifically, the signal output from the synthesis circuit 641 switches from the LOW level to the HI level. Then, since the signal input to the CLK terminal is also switched from the LOW level to the HI level, the D flip flop 642 outputs a signal corresponding to the signal input to the D terminal at that time from the Q terminal. In such a case, since the reset signal which is the HI level is input to the D terminal, the signal output from the Q terminal is also the HI level signal. Thus, the signal output from the NAND circuit 612 holds the LOW level. That is, once the HI level signal is output from the Q terminal, the synthetic reset signal is alternately switched to the HI level and the LOW level by the signal output from the Schmitt trigger 413 alternately switching to the HI level and the LOW level thereafter. Even when switched, the HI level signal output from the Q terminal does not change unless the signal input to the D terminal changes. Therefore, the malfunction of the MPU 311 due to the change of the signal output from the Schmitt trigger 413 is suppressed by the D flip flop 642.

  When the pachinko machine 10 is turned off at the timing of t22, a low level signal is immediately input from the signal line LN3 to the NAND circuit 612, and an HI level signal is output from the NAND circuit 612 to the MPU 311. Therefore, the MPU 311 falls immediately. On the other hand, the AC power supply unit 631 is connected to a commercial power supply and receives the power supply regardless of the power-off state of the pachinko machine 10 and outputs an AC voltage of a full wave waveform. The pulse signal, which is the converted AC voltage, is output regardless of the power interruption state. Since the D flip flop 642 has a volatile configuration, the output state from the Q terminal is not held. In this case, the output state from the Q terminal may be undefined. In this state, when the output state from the Q terminal is HI level, the signal output from the NAND circuit 612 becomes LOW level, and the operation of the MPU 311 may not end. On the other hand, according to the present embodiment, since the LOW level signal is input from the signal line LN3, the operation of the MPU 311 can be ended regardless of the output state from the signal line LN4. As a result, the process of stopping the MPU 311 can be reliably performed. When the output state from the Q terminal is at the LOW level, the MPU 311 immediately falls.

  When the pachinko machine 10 is turned on again at the timing of t23, the reset signal which is HI level is output similarly to the timing of t27, and accordingly, one end of the input side of the synthesis circuit 641 and D of the D flip flop 642 A reset signal which is HI level is input to the terminal. In such a case, since the signal output from the Schmitt trigger 413 to the combining circuit 641 is a LOW level signal, the combining circuit 641 outputs a LOW level signal. Since the D flip flop 642 is not synchronized with the output of the signal, the current output state is maintained. Therefore, the MPU 311 does not start the operation.

  When the signal output from the Schmitt trigger 413 switches from the LOW level to the HI level at the timing of t24, the output signal from the combining circuit 641 rises from the LOW level to the HI level as in the case of the timing of t19. In synchronization with the rise, the D flip flop 642 outputs a signal according to the input state. Specifically, since the reset signal which is HI level is input to the D terminal, the HI level signal is output from the Q terminal. Then, a low level signal is output from the NAND circuit 612 to the MPU 311, and the MPU 311 receives the signal and starts operation. Therefore, the start timing of the operation of the MPU 311 is delayed by the delay period DT5 from the timing t23 to the timing t24.

  Here, in the delay periods DT4 and DT5, the timing when the pachinko machine 10 enters the on state, that is, the output timing of the reset signal from the reset circuit 601 until the signal output from the Schmitt trigger 413 becomes the HI level signal. Since it is a period, the period until the output signal from the Schmitt trigger 413 changes from the HI level signal to the next HI level signal is within the range of the delay period variation. That is, the period of the LOW level signal falls within the range of variation of the delay period. Then, within the period of the LOW level signal, when the reset signal is output, that is, when the pachinko machine 10 is turned on, the timing at which the LOW level signal is output from the NAND circuit 612 is the timing at which the power on state is entered. It is delayed based on. As a result, since the delay period is irregular, it is difficult to grasp the start timing of the random number counter update processing. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

  When the pachinko machine 10 is turned off at the timing of t25, the MPU 311 immediately falls, as in the case of the timing of t22.

  According to the embodiment described above, the following excellent effects can be obtained.

  The synthesis circuit 641 is provided as the irregular delay circuit 602, and when the reset signal which is the HI level is input from the reset circuit 601, the synthesis circuit 641 more specifically includes the signal conversion circuit 402, more specifically, the Schmitt trigger 413. Based on the specific form of the pulse signal to be output, it is configured to output a synthesis reset signal which is HI level. Specifically, based on the fact that the signal output from the signal conversion circuit 402 is at the HI level, the combining circuit 641 outputs the combining reset signal that is the HI level. As a result, when the reset signal is output while the signal output from the signal conversion circuit 402 is at the LOW level, the output of the combined reset signal is delayed until the HI level signal is output, The output of the HI level signal to NAND circuit 612 is delayed. Then, in response to the input of the HI level signal, the NAND circuit 612 outputs a LOW level signal to the MPU 311. In response to the input of the LOW level signal, the MPU 311 starts operation. In other words, the state of the signal supplied to the NAND circuit 612 shifts to the operable state based on the signal output from the signal conversion circuit 402 becoming the HI level. Furthermore, in other words, when the signal output from the Schmitt trigger 413 becomes HI level, the state of the signal supplied to the MPU 311 is switched to the operable state.

  Here, the form of the pulse signal fluctuates according to the timing at which the pachinko machine 10 is turned on. As a result, the period from the timing when the pachinko machine 10 enters the on state to the output timing of the combined reset signal from the combining circuit 641 fluctuates depending on the timing when the pachinko machine 10 enters the incoming state. Therefore, the output timing of the LOW level signal from the NAND circuit 612 is irregular. Therefore, since it is difficult to grasp the start timing of the update of the jackpot random number counter C1, it is difficult to grasp the timing of winning the jackpot. This makes it possible to suppress fraudulent acts using the “hanging board” or the like.

  Further, in the case of the configuration in which the integration circuit 611 is provided as the irregular delay circuit 602, the charge does not remain in the capacitor 613 of the integration circuit 611 if the period of the interruption state of the pachinko machine 10 is longer than the discharge period. There is a disadvantage that does not occur. On the other hand, according to the configuration in which the NAND circuit 612 outputs the LOW level signal based on the form of the signal output from the signal conversion circuit 402, the delay period does not depend on the period of the interruption state of the pachinko machine 10. Therefore, the above-mentioned inconvenience can be avoided.

  A signal conversion circuit 402 is provided which converts the AC voltage supplied from the AC power supply unit 631 into a pulse signal. As a result, it is possible to obtain a specific signal in which the HI level signal and the LOW level signal are alternately output from the commercial power supply, so that the configuration can be simplified.

  In the above embodiment, when the signal output from the signal conversion circuit 402 is at the HI level, the synthesis circuit 641 outputs the reset signal at the HI level. However, the present invention is not limited to this. When the signal output from 402 is at the LOW level, the HI level signal may be output.

  Also, when the pachinko machine 10 is turned on again at the timing of t26, the reset signal is output, and accordingly, the reset signal which is HI level at one end of the input side of the synthesis circuit 641 and the D terminal of the D flip flop 642 Is input. Further, since the signal input to the synthesis circuit 641 is at the HI level, the synthesis circuit 641 outputs a synthesis reset signal at the HI level. Therefore, the HI level signal is output from the Q terminal of the D flip flop 642 in synchronization with the signal. In such a case, a delay does not occur.

  On the other hand, the Schmitt trigger 413 has a function of adjusting the pulse width of the pulse signal. Specifically, by adjusting the upper and lower threshold voltages of the Schmitt trigger 413, the pulse width is adjusted. In particular, by bringing the upper threshold voltage and the lower threshold voltage of the Schmitt trigger 413 closer to 0 and narrowing the ranges of the upper threshold voltage and the lower threshold voltage, the HI level in one cycle of the pulse signal is compared to the LOW level. Period is relatively short. Then, the period in which the delay does not occur becomes shorter than the period in which the delay occurs. Therefore, it is possible to avoid the problem that the delay does not occur. In other words, since the HI level signal becomes a relatively short period compared to the LOW level signal in one cycle of the pulse signal, the range of variation of the delay period becomes wide, and the variation of the delay period is increased, Irregularities in the delay period can be improved.

  When the signal output from the signal conversion circuit 402 is configured to output the HI level signal under the LOW level state, the LOW level state is adjusted to be longer than the HI level state. Good.

Eighth Embodiment
In the present embodiment, the configuration relating to the irregular delay circuit 602 is different from that of the seventh embodiment. Therefore, the configuration will be described in detail below. In the following description, differences from the seventh embodiment are mainly described, and the description of the same configuration is basically omitted. In the eighth embodiment, the configuration shown in FIGS. 37 and 38 is used instead of the configuration shown in FIGS.

  In the seventh embodiment, when the reset signal is output from the reset circuit 601 and the signal output from the signal conversion circuit 402 is the HI level signal, the combining circuit 641 outputs the HI level signal, The MPU 311 is configured to operate, but instead, the MPU 311 is configured to operate in synchronization with the rising of the pulse signal.

  The irregular delay circuit 602 has a D flip flop 651 as a transition means. The D flip flop 651 has a data terminal (D terminal) and a clock terminal (CLK terminal) as input terminals, and has a positive logic output terminal (Q terminal) as an output terminal. A reset circuit 601 is connected to the D terminal, and a Schmitt trigger 413 is connected to the CLK terminal. In addition, a NAND circuit 612 is connected to the Q terminal.

  The D flip flop 651 outputs, from the Q terminal, a signal corresponding to the input state of the signal input to the D terminal at the same time as the signal input to the CLK terminal rises from the LOW level to the HI level. . That is, in synchronization with the rising of the pulse signal converted by the Schmitt trigger 413, the signal corresponding to the signal state output from the reset circuit 601 at that time is output from the Q terminal, and the signal is output until the next rising of the pulse signal. Hold the output state.

  The operation of the irregular delay circuit 602 will be described based on the timing chart of FIG.

  When the pachinko machine 10 is turned on at timing t27, the reset circuit 601 outputs a reset signal. More specifically, the reset circuit 601 outputs the HI level signal. Then, a reset signal which is HI level is input to the D terminal of the D flip flop 651. On the other hand, since the output signal from the Schmitt trigger 413 is a LOW level signal, that is, no output state, the D flip flop 651 holds the current output state without synchronization. Therefore, the reset signal which is HI level is not output to the NAND circuit 612. Therefore, the MPU 311 does not start the operation.

  When the output signal from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t28, the D flip flop 651 outputs a signal according to the input state in synchronization with the rise. Here, since the reset signal which is HI level is input to the D terminal, the HI level signal is output from the Q terminal. Then, the HI level signal is input to the NAND circuit 612. In other words, the state of the signal supplied to the NAND circuit 612 has shifted to the operable state. As a result, the LOW level signal is output from the NAND circuit 612, the operation of the MPU 311 is started, and the update of the random number counter update processing such as the big hit random number counter C1 is started.

  That is, the timing of starting the operation of the MPU 311 is delayed by a delay period DT6 from when the pachinko machine 10 is turned on to when the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level. Here, since the pulse signal fluctuates regardless of whether the pachinko machine 10 is switched on or off, the form of the pulse signal fluctuates according to the timing at which the pachinko machine 10 is switched on. Therefore, in the delay period DT6, which is a period from the timing when the pachinko machine 10 enters the on state to the rise timing from the LOW level signal to the HI level signal, which is one of pulse signal forms, the pachinko machine 10 enters the on state. Vary according to the timing of Therefore, the output timing of the LOW level signal from NAND circuit 612 is irregular. Therefore, since the period from when the pachinko machine 10 is turned on to when the update of the big hit random number counter C1 is started becomes irregular, it is difficult to grasp the timing of the big hit.

  When the pachinko machine 10 is switched off at the timing of t29, the LOW level signal is immediately input from the signal line LN3 to the NAND circuit 612 as in the seventh embodiment, and the HI to the MPU 311 is performed. Since the level signal is output, the MPU 311 falls immediately. On the other hand, the AC power supply unit 631 is connected to a commercial power supply, receives power supply regardless of the power-on state and power-off state of the pachinko machine 10, and outputs an AC voltage of a full wave waveform. In addition, the Schmitt trigger 413 is supplied with power from the power-off-time power supply unit 321 c even in the power-off state. Therefore, the pulse signal which is what converted the alternating voltage from the alternating current power supply part 631 is output irrespective of the interruption state. Note that, since the D flip flop 651 has a volatile configuration, the output state from the Q terminal is not held in the power-off state.

  When the pachinko machine 10 is turned on again at the timing of t30, the reset signal rises at the same time as the timing of t27, and accordingly, the reset signal which is the HI level is input to the D terminal of the D flip flop 651. On the other hand, the signal input to the CLK terminal is the HI level signal, not the rise timing. Thus, the D flip flop 651 holds the LOW level signal.

  When the signal output from the Schmitt trigger 413 switches from the LOW level to the HI level at the timing of t31, the D flip flop 651 receives the reset signal which is the HI level at the D terminal, so the HI level from the Q terminal A signal is output. Then, a low level signal is output from the NAND circuit 612 to the MPU 311, and the MPU 311 receives the signal and starts operation. Therefore, the start timing of the operation of the MPU 311 is delayed by the delay period DT7 from the timing of t30 to the timing of t31.

  Here, since the delay periods DT6 and DT7 are the timing from when the pachinko machine 10 enters the on state, that is, from the output timing of the reset signal from the reset circuit 601 to the rise timing of the pulse signal, the rising period is the delay period. It becomes a range of variation. That is, the cycle of the pulse signal falls within the range of variation of the delay period. The delay period fluctuates in the range according to the output timing of the reset signal from the reset circuit 601. Specifically, the period from the timing of t30 to the timing of t31 is longer than the period from the timing of t27 to the timing of t28 since the period from the timing of output of the reset signal to the timing of rising of the pulse signal is t27. Is longer than the delay period DT6. Thereby, the delay period is irregular.

  According to the eighth embodiment described above, the following excellent effects can be obtained.

  As the irregular delay circuit 602, a D flip flop 651 is provided which outputs a signal corresponding to the reset signal output from the reset circuit 601 to the NAND circuit 612 in synchronization with the rise of the pulse signal. Thus, when the reset signal is output from the reset circuit 601, the output timing of the LOW level signal from the NAND circuit 612 is delayed until the rise of the pulse signal. Then, in response to the input of the LOW level signal, the MPU 311 starts operation. In other words, when the reset signal is output from the reset circuit 601, the state of the signal supplied to the NAND circuit 612 shifts to the operable state based on the rise of the pulse signal. Furthermore, in other words, when the reset signal is output from the reset circuit 601, the state of the signal supplied to the MPU 311 is switched to the operable state based on the rise of the pulse signal.

  Here, the form of the pulse signal fluctuates depending on the timing at which the pachinko machine 10 is turned on. As a result, the period from the timing when the pachinko machine 10 enters the on state to the rise of the pulse signal fluctuates depending on the timing when the pachinko machine 10 enters the on state. Therefore, the timing at which the D flip flop 651 synchronizes, that is, the output timing of the LOW level signal from the NAND circuit 612 becomes irregular. Therefore, since it is difficult to grasp the start timing of the update of the jackpot random number counter C1, it is difficult to grasp the timing of winning the jackpot. This makes it possible to suppress fraudulent acts using the “hanging board” or the like.

  Further, in the pulse signal, the period from the rising timing to the next rising timing is the range of the variation of the delay period. That is, the cycle of the pulse signal becomes the range of variation of the delay period. Therefore, based on the fact that either one of the HI level signal and the LOW level signal is output from the signal conversion circuit 402, compared to the configuration in which the composite reset signal which is the HI level is output, The range of variation is wide. Therefore, it is more difficult to grasp the output timing of the LOW level signal from the NAND circuit 612.

  In other words, as long as the rising edge of the pulse signal does not coincide with the timing at which the pachinko machine 10 is turned on, a delay occurs. That is, as compared with the configuration in which the signal output from the signal conversion circuit 402 is synchronized when the signal is at the HI level or the LOW level, the period in which no delay occurs is shortened. Therefore, it is possible to suppress a failure that does not cause a delay.

The ninth embodiment
In the present embodiment, the configuration relating to the irregular delay circuit 602 is different from that of the eighth embodiment. Therefore, the configuration will be described in detail below. In the following description, differences from the eighth embodiment are mainly described, and the description of the same configuration is basically omitted. In the ninth embodiment, the configuration shown in FIGS. 39 and 40 is used instead of the configuration shown in FIGS.

  In the present embodiment, the rising period of the pulse signal used to define the synchronization timing is changed.

  The irregular delay circuit 602 includes a first D flip flop 661 and a modulation circuit 662. Similar to the D flip flop 651 described in the seventh embodiment, the first D flip flop 661 has a D1 terminal as an input terminal and a CLK1 terminal, and has a Q1 terminal as an output terminal. Further, similarly to the D flip flop 651, the Q 1 terminal is connected to the input terminal of the NAND circuit 612, and the D 1 terminal is connected to the reset circuit 601. The modulation circuit 662 is provided on a path connecting the first D flip flop 661 and the Schmitt trigger 413 that converts an AC voltage into a pulse signal. The pulse signal output from the Schmitt trigger 413 is input to the CLK1 terminal of the first D flip flop 661 via the modulation circuit 662. The modulation circuit 662 includes a second D flip flop 663, a third D flip flop 664, and an XOR circuit 665. The second D flip flop 663, the third D flip flop 664, and the XOR circuit 665 are connected to the power source section 321a for power on and off of the power and discharge control board 321 via the electric path and the disconnection monitoring board 302 respectively. Connected. Therefore, while the power supply unit for power-on 321a is supplying power, that is, while the pachinko machine 10 is in the power-on state, the second D flip flop 663, the third D flip flop 664, and the XOR circuit 665. Works.

  The XOR circuit 665 has two input terminals and an output terminal that outputs a signal corresponding to the signal input to the input terminal. Similar to the first D flip flop 661, the second D flip flop 663 has a D2 terminal as an input terminal and a CLK2 terminal, and has a Q2 terminal as an output terminal. Similar to the first D flip flop 661, the third D flip flop 664 also has a D3 terminal as an input terminal and a CLK3 terminal, and has a Q3 terminal as an output terminal. The output terminal of the XOR circuit 665 is connected to the D2 terminal of the second D flip flop 663, and the output terminal of the Schmitt trigger 413 is connected to the CLK2 terminal. The D3 terminal of the third D flip-flop 664 is connected to the Q2 terminal of the second D flip-flop 663. The output terminal of the Schmitt trigger 413 is connected to the CLK3 terminal of the third D flip flop 664 similarly to the second D flip flop 663. The Q3 terminal of the third D flip flop 664 is connected to the CLK1 terminal of the first D flip flop 661 and is connected to one of the two input terminals of the XOR circuit 665. The other input terminal of the XOR circuit 665 is connected to the power supply and emission control board 321, and is supplied with a +5 V voltage which is an HI level signal. The output terminal of the XOR circuit 665 is connected to the D2 terminal of the second D flip flop 663 as described above.

  Thus, the pulse signal output from the Schmitt trigger 413 is modulated by the modulation circuit 662 and input to the CLK1 terminal of the first D flip-flop 661. The modulated pulse signal is called a modulated pulse signal.

  The operation of the modulation circuit 662 and the associated NAND circuit 612 will be described based on the timing chart of FIG.

  When the pachinko machine 10 is turned on at timing t32, the reset circuit 601 outputs a reset signal. More specifically, the reset circuit 601 outputs the HI level signal. Then, a reset signal which is HI level is input to the D1 terminal of the first D flip-flop 661. On the other hand, a voltage of +5 V is generated from the power-on time power supply section 321a of the power supply and emission control board 321, and a +5 V voltage, ie, an HI level signal is input to the XOR circuit 665. In addition, since the rising of the pulse signal is not generated at this timing, the signals output from the Q2 terminal and the Q3 terminal do not change.

  When the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t33, the second D flip-flop 663 and the third D flip-flop 664 output the signal according to the input state in synchronization with the rise. . Specifically, the HI level signal is input from the power supply and emission control board 321 to one end of the input terminal of the XOR circuit 665 connected to the D2 terminal. Further, since the LOW level signal is output from the Q2 terminal of the third D flip flop 664, the LOW level signal is input to the other end of the input terminal of the XOR circuit 665. Therefore, the HI level signal is output from the XOR circuit 665, and the HI level signal is input to the D2 terminal of the second D flip flop 663. Therefore, the HI level signal is output from the Q2 terminal. On the other hand, since the LOW level signal is output to the D3 terminal of the third D flip-flop 664 at the timing of t33, the LOW level signal is output from the Q3 terminal. The output states of the second D flip flop 663 and the third D flip flop 664 are held until the next rise of the pulse signal.

  When the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t34, the second D flip-flop 663 and the third D flip-flop 664 output the signal according to the input state in synchronization with the rise. Do. Since the signal output from the XOR circuit 665 does not change, the second D flip-flop 663 outputs an HI level signal. Further, since the HI level signal is input to the D3 terminal from the Q2 terminal, the signal output from the Q3 terminal of the third D flip-flop 664 rises from the LOW level to the HI level. In synchronization with the rise, the first D flip-flop 661 outputs the HI level signal from the Q1 terminal in response to the reset signal which is the HI level input to the D1 terminal. Then, a low level signal is output from the NAND circuit 612 to the MPU 311, and the MPU 311 starts operation by the input of the signal.

  That is, the start of the operation of the MPU 311 is delayed by a delay period DT8 from the timing of t32 when the pachinko machine 10 enters the on state to the timing of t34 when the rising edge of the pulse signal is input to the first D flip flop 661. . Here, the delay period DT8 is a period in which the period of the pulse signal is added to the period from the timing when the pachinko machine 10 enters the on state to the rise of the first pulse signal. The delay period DT8 is different from the delay period DT6 in the eighth embodiment in that the period of the pulse signal is added to the period from the output of the reset signal to the rise of the first pulse signal. That is, the timing of synchronization by the modulation pulse signal and the timing of synchronization by the pulse signal are different by one cycle of the pulse signal.

  When the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t35, the second D flip flop 663 and the third D flip flop 664 output the signal according to the input state in synchronization with the rise Do. Specifically, since the HI level signal is output from the Q2 terminal, the HI level signal is input to the two input terminals of the XOR circuit 665. Therefore, the LOW level signal is output from the XOR circuit 665. Therefore, the signal output from the Q terminal of the second D flip flop 663 switches from the HI level to the LOW level. Further, since the HI level signal is input to the D3 terminal from the Q2 terminal, the signal output from the Q3 terminal of the third D flip flop 664 is the HI level. Therefore, since the rising edge of the signal is not input to the CLK1 terminal of the first D flip flop 661, the first D flip flop 661 holds the output state.

  Thereafter, when the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t36, two HI level signals are input to the XOR circuit 665, and the LOW level signal is output. Therefore, the second D flip flop 663 outputs a LOW level signal. Further, since the LOW level signal is output from the Q2 terminal, the output signal from the Q3 terminal of the third D flip-flop 664 falls from the HI level to the LOW level. Since the first D flip-flop 661 is not synchronized with the fall, the output state from the Q1 terminal is held.

  When the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t37, the HI level signal and the LOW level signal are input to the XOR circuit 665 as at the timing of t33. Since the signal is output, the second D flip flop 663 outputs the HI level signal from the Q2 terminal. In addition, since the LOW level signal is output from the Q2 terminal, the third D flip-flop 664 outputs the LOW level signal from the Q3 terminal. Since the first D flip flop 661 is not synchronized, the output state from the Q1 terminal is held.

  That is, the period T4 from the timing of t33 to the timing of t37 is the period of the pulse signal output from the second D flip flop 663 and the third D flip flop 664, that is, the period of the modulation pulse signal. The period is four times the period T3 of the pulse signal. The pulse width of the modulation pulse signal is also four times the pulse width of the pulse signal. As a result, after the pachinko machine 10 is turned on, at the timing of t33, which is the first rise timing of the pulse signal, the output signal from the Q3 terminal does not rise, and the Q3 terminal at the next rise timing of the pulse signal. The output signal from is rising.

  When the pachinko machine 10 is switched off at the timing of t38, the LOW level signal is immediately input from the signal line LN3 to the NAND circuit 612, and the HI level signal is output to the MPU 311. I will go down immediately. Also, the +5 V voltage supply of the power-on during power-on 321a is also stopped, and the first D flip-flop 661, the second D flip-flop 663, and the second D-flip-flop 661, which were driven by receiving power supply from the power-on during power-on 321a. The 3D flip flop 664 stops its operation. In such a case, the output state of each D flip flop 661, 663, 664 is not held.

  Thereafter, when the pachinko machine 10 is turned on again at the timing of t39, the reset signal rises at the same time as the timing of t32, and accordingly, the reset signal which is HI level is input to the D1 terminal of the first D flip flop 661. Ru. Thereafter, the operation of the MPU 311 is started at the timing of t40. That is, the operation start timing of the MPU 311 is delayed with respect to the output timing of the reset signal from the reset circuit 601 by the delay period DT9 from the timing of t39 to the timing of t40.

  According to the embodiment described above, the modulation circuit 662 is provided to modulate the cycle of the pulse signal, and the first D flip-flop 661 is synchronized based on the rising of the modulation pulse signal which is the modulated pulse signal. did. Thus, since the timing at which the pulse signal rises and the timing at which the modulation pulse signal rises are different, the timing at which the first D flip-flop 661 synchronizes is different from the timing at which the first D flip-flop 661 synchronizes based on the rising of the pulse signal. Therefore, the output timing of the LOW level signal from the NAND circuit 612 is different from the configuration for outputting based on the pulse signal. Therefore, it is possible to prevent a fraudulent act of grasping the start timing of the operation of the MPU 311 from the rising timing of the pulse signal and the output timing of the reset signal.

  In particular, since the pulse signal is obtained by converting an AC voltage from a commercial power supply, the period of the pulse signal may be identified. On the other hand, the modulation pulse signal modulated by the modulation circuit 662 has a rising edge after the first rising edge of the pulse signal output from the Schmitt trigger 413 after the output timing of the reset signal from the reset circuit 601. It is supposed to stand up synchronously. That is, after the output timing of the reset signal from the reset circuit 601, the first D flip flop 661 is not synchronized with the first rise of the pulse signal output from the Schmitt trigger 413. Thus, at the first rising timing of the pulse signal output from the Schmitt trigger 413, the NAND circuit 612 does not output the LOW level signal. Therefore, even if the period from the output of the reset signal to the first rise of the pulse signal is grasped by temporarily grasping the output timing of the reset signal and the rising timing of the pulse signal, the first D flip-flop 661 It is difficult to understand when to synchronize.

  Although the modulation pulse signal has a configuration in which the pulse width and the output interval are both modulated to signals different from the pulse signal, the present invention is not limited thereto, and either one of the pulse width or the output interval is different from that of the pulse signal. It may be a signal. The point is that at least one of the pulse width and output interval of the pulse signal may be modulated to a different signal.

Tenth Embodiment
In the present embodiment, the configuration relating to the power supply of the irregular delay circuit 602 is different from that of the ninth embodiment. Therefore, the configuration will be described in detail below. In the following description, differences from the ninth embodiment will be mainly described, and the description of the same configuration will be basically omitted. In the tenth embodiment, instead of the configuration shown in FIGS. 39 and 40, the configuration shown in FIGS. 41 and 42 is used.

  In the ninth embodiment, since the power supply to the second D flip flop 663 and the third D flip flop 664 is stopped after the pachinko machine 10 is turned off, the second D flip flop 663 and the third D flip flop 664 The information held is erased and the second D flip flop 663 and the third D flip flop 664 do not operate. However, in the present embodiment, the second D flip flop 663 and the third D flip flop 664 are changed and operate even when the pachinko machine 10 is turned off. Configuration.

  Specifically, a power supply line ELN1 electrically connecting the second D flip flop 663, the third D flip flop 664, the XOR circuit 665, and the power-off time power supply portion 321c of the power supply and discharge control board 321 is provided. There is. Since the second D flip flop 663, the third D flip flop 664, and the XOR circuit 665 are also supplied with power through the power supply line ELN1 even in the power-off state of the pachinko machine 10, Works regardless. Thereby, the range of variation of the delay period can be made larger than that of the ninth embodiment.

  Note that a capacitor or the like may be separately provided as a charging unit in place of the power supply unit for power interruption 321c. In addition, although the power supply line ELN1 is connected via the power failure monitoring substrate 302, the present invention is not limited to this. The power supply unit 321c for power failure and the D flip-flops may be directly connected. The point is that the configuration may be such that the operating power is supplied regardless of whether the pachinko machine 10 is turned on or off. However, it is better to use the power supply unit for power interruption 321 c from the viewpoint of simplification of the configuration.

  The operation of the modulation circuit 662 will be described based on FIG. In addition, since the operation itself of each D flip flop 661, 663, 664 is as having mentioned above, it abbreviate | omits about these description.

  When the pachinko machine 10 is switched on at the timing of t41, the reset circuit 601 outputs a reset signal as in the case of the timing of t32. At this timing, since the rising of the pulse signal has not occurred, the output states of the second D flip flop 663 and the third D flip flop 664 are held.

  When the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t42, the signal output from the Q3 terminal of the third D flip-flop 664 is from the LOW level as in the case of the timing of t34. In order to rise to the HI level, the HI level signal is output from the Q1 terminal. That is, the start timing of the operation of the MPU 311 is delayed after the pachinko machine 10 is turned on by the delay period DT10 from the timing of t41 to the timing of t42. The delay period DT10 is a period obtained by adding one cycle of the pulse signal to the period from the output timing of the reset signal to the rising timing.

  When the pachinko machine 10 is turned off at the timing of t43, the reset signal is not output immediately, and the output signal from the NAND circuit 612 immediately switches from the LOW level to the HI level. Thus, the MPU 311 immediately executes a predetermined stop process. On the other hand, since power is supplied to the D flip-flops 663 and 664 and the XOR circuit 665 even in the disconnected state, the output states of the D flip-flops 663 and 664 and the XOR circuit 665 are held. In the power-off state, power is not supplied to the first D flip-flop 661, so the output state is not maintained.

  Thereafter, when the pachinko machine 10 is turned on again at the timing of t44, HI level signals are output from the Q2 terminal and the Q3 terminal. Then, the start timing of the operation of the MPU 311 is delayed with respect to the timing at which the pachinko machine 10 enters the on state by the delay period DT11 until the timing of t45 when the output from the Q3 terminal switches from LOW level to HI level. The delay period DT11 is a period obtained by adding the period of the pulse signal for two cycles to the period from the output timing of the reset signal to the rising timing.

  According to the embodiment described above, the following excellent effects can be obtained.

  A modulation circuit 662 is provided which modulates a pulse signal output from the Schmitt trigger 413 into a modulation pulse signal having a period longer than that of the pulse signal, and the first D flip-flop 661 is synchronized based on the modulation pulse signal. did. The D flip-flops 663 and 664 of the modulation circuit 662 are configured to operate regardless of the on / off state of the pachinko machine 10. Thus, the output states of the D flip-flops 663 and 664 fluctuate with respect to the timing when the reset signal is output from the reset circuit 601, that is, the timing when the pachinko machine 10 is turned on. The range of corresponds to the rise period of the modulation pulse signal.

  That is, when the D flip-flops 663 and 664 do not operate in the power-off state, the D flip-flops 663 and 664 output the predetermined state, that is, the LOW level signal after the pachinko machine 10 is switched on. Start operation from the state. In such a case, the delay period from the output of the reset signal to the start of the operation of the MPU 311 is obtained by adding one cycle of the pulse signal to the period from the output of the reset signal to the rise of the first pulse signal. . That is, since each D flip flop 663, 664 starts operation from a predetermined state with respect to the timing at which the pachinko machine 10 enters the on state, a period from when the reset signal is output until the first pulse signal rises. The period of the pulse signal to be added to is constant. Then, the period which fluctuates according to the output timing of the reset signal is the period from the output of the reset signal to the rise of the first pulse signal, and the entire delay period is a predetermined pulse with respect to the fluctuation period. It is a period offset by one cycle of the signal. In other words, the range of variation of the delay period corresponds to the period of the pulse signal.

  On the other hand, when the D flip-flops 663 and 664 are operating regardless of the power-on state and the power-off state of the pachinko machine 10, the D flip-flops with respect to the timing at which the pachinko machine 10 is in the power-on state. The output states of 663 and 664 are fluctuating. That is, the output state of the signal output from the Q3 terminal does not depend on the timing at which the pachinko machine 10 is turned on. In other words, the range of variation of the delay period corresponds to the period of the signal output from the Q3 terminal. Further, since the period of the signal is longer than the period of the pulse signal, the variation range of the delay period is wider as compared with the configuration not operating in the power-off state. Therefore, the delay period is more irregular because the variation of the delay period is also large. Therefore, since the update start timing of the jackpot random number counter C1 is difficult to be grasped, it is difficult to grasp the timing of the jackpot winning. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

  Although the D flip-flops 663 and 664 are configured to operate regardless of whether the pachinko machine 10 is turned on or off, the present invention is not limited to this, and information of the D flip-flops 663 and 664 is held. The above-described effects can also be obtained as a configuration. Specifically, the pulse signal output from the Schmitt trigger 413 may be cut off. With this configuration, power consumption can be suppressed.

  In addition, although the modulation pulse signal has a configuration in which both the pulse width and the output interval are made larger than the pulse width and the output interval of the pulse signal, the present invention is not limited to this. It may be The point is that at least one of the pulse width of the modulation pulse signal and the output interval may be larger than that of the pulse signal.

Eleventh Embodiment
In the present embodiment, the configuration relating to the modulation circuit in the irregular delay circuit 602 is different from that of the tenth embodiment. Therefore, the configuration will be described in detail below. In the following description, differences from the tenth embodiment will be mainly described, and the description of the same configuration will be basically omitted. In the eleventh embodiment, instead of the configurations shown in FIGS. 41 and 42, configurations shown in FIGS. 43 and 44 are used.

  In this embodiment, the pulse signal output from the Schmitt trigger 413 is modulated into a signal having two different output intervals and alternately output at two output intervals. Then, based on the rising of the modulated signal, the first D flip-flop 661 outputs a signal according to the input state.

  Specifically, in place of the modulation circuit 662, the irregular delay circuit 602 includes a modulation circuit 671 that modulates the pulse signal so that signals having different rise intervals of the pulse signal are output. Similar to the modulation circuit 314 in the first embodiment, the modulation circuit 671 includes a fourth D flip flop 672, a fifth D flip flop 673, a sixth D flip flop 674, a first XOR circuit 675, and a second XOR circuit 676. ,have. When these components are electrically connected to the power supply portion 321a of the power supply and discharge control board 321 via the electric path and the disconnection monitoring board 302 (not shown), and the pachinko machine 10 is in the power on state The operating power is supplied from the power-on unit for power-on 321a. The D flip-flops 672, 673, and 674 and the XOR circuits 675 and 676 are electrically connected to the power supply unit for disconnection 321c through the power supply line ELN2. When the pachinko machine 10 is in the power-off state, the operating power is supplied from the power-off-time power supply unit 321 c. That is, each D flip flop 672, 673, 674 and each XOR circuit 675, 676 operate regardless of the on / off state of the pachinko machine 10.

  In addition, it is good also as a structure which provides charging means, such as a capacitor | condenser, separately instead of the power supply part 321c at the time of power failure. In addition, although the power supply line ELN2 is connected via the power failure monitoring substrate 302, the present invention is not limited to this. The power supply unit 321c for power failure and the D flip-flops and the like may be directly connected. The point is that the configuration may be such that the operating power is supplied regardless of whether the pachinko machine 10 is turned on or off. However, it is better to use the power supply unit for power interruption 321 c from the viewpoint of simplification of the configuration.

  The connection of each D flip-flop 672, 673, 674 and each XOR circuit 675, 676 is the same as that of the modulation circuit 314 in the first embodiment, and thus the description thereof is omitted.

  The operation of the modulation circuit 671 will be described based on the timing chart of FIG. At the timing of t46, t48, t49, t50, 52, t53, t55, t56, t57, the D flip-flops 672, 673, 674 synchronously output the signals input to the D terminals from the Q terminal. . The outputs of terminals Q4 to Q6 at these timings are the same as the outputs from terminals Q1 to Q3 in the first embodiment (FIG. 22), and thus detailed description will be omitted. A pulse signal having different pulse widths and output intervals is repeatedly output, with a period T5 from the timing of t46 to the timing of t56 as one cycle.

  When the power of the pachinko machine 10 is turned on, that is, when the pachinko machine 10 is turned on at timing t47, the reset circuit 601 outputs a reset signal. More specifically, the reset circuit 601 outputs the HI level signal. Then, a reset signal which is HI level is input to the D1 terminal of the first D flip-flop 661.

  Thereafter, when the signal output from the Schmitt trigger 413 rises from the LOW level to the HI level at the timing of t49, the signal output from the Q6 terminal rises from the LOW level to the HI level. The HI level signal is output from the Q1 terminal in synchronization with the rise. Then, since two HI level signals are input to the NAND circuit 612, a LOW level signal is output from the NAND circuit 612. The MPU 311 starts operation by the input of the signal. That is, the start timing of the operation of the MPU 311 is delayed with respect to the output timing of the reset signal by the delay period DT12 from the timing t47 to the timing t49.

  When the pachinko machine 10 is turned off at the timing of t51, the reset signal is not output immediately, and the output signal from the NAND circuit 612 immediately switches from the LOW level to the HI level. On the other hand, since the power is supplied to the D flip-flops 672, 673, and 674 even in the disconnected state, the output states of the D flip-flops 672, 673, and 674 are maintained. Note that the first D flip flop 661 is not supplied with operating power in the power-off state of the pachinko machine 10, and thus the output state is not maintained.

  When the pachinko machine 10 is turned on again at the timing of t54, the reset circuit 601 outputs a reset signal of HI level. Since the timing is not the rise timing of the pulse signal input to each CLK terminal of each D flip flop 672, 673, 674, each D flip flop 672, 673, 674 holds the output state.

  Thereafter, since the signal output from the Q6 terminal rises from the LOW level to the HI level at the timing of t57, the HI level signal is output from the first D flip flop 661 to the NAND circuit 612 in synchronization with the rise. As a result, a low level signal is output from the NAND circuit 612. That is, the output timing of the LOW level signal from the NAND circuit 612 is delayed with respect to the output timing of the reset signal from the reset circuit 601 by the delay period DT13 from the timing of t54 to the timing of t57.

  Here, the period Tc from the timing of t49 which is the rising interval of the signal outputted from the Q6 terminal to the timing of t53 and the period Td from the timing of t53 to the timing of t57 which is the next rising timing are different. ing. In detail, the period Tc is three times the period T3 of the pulse signal, and the period Td is four times the period T3 of the pulse signal. That is, pulse signals are output alternately from the Q6 terminal at two types of output intervals.

  In the embodiment described above, pulse signals are alternately output from the Q6 terminal of the sixth D flip-flop 674 at two types of output intervals. The first D flip-flop 661 synchronizes based on the rising of the pulse signal. Thus, there are two types of timing intervals at which the first D flip-flop 661 synchronizes. This makes it difficult to grasp the timing at which the first D flip-flop 661 synchronizes.

  In the present embodiment, the rising intervals of the pulse signal are two types of the period Tc and the period Td. However, the rising intervals are not limited to this and may be three or more types. The point is that the configuration may be such that the HI level signal is output at at least two types of output intervals.

  Further, in the present embodiment, although the signal output from the modulation circuit 671 is a signal in which the HI level signal is output at at least two types of output intervals, the present invention is not limited thereto. It may be a signal to be output. Also in this configuration, the rising intervals of the pulse signal can be made two types. The point is that the modulation circuit 671 may be a circuit that generates at least one of a signal in which HI level signals are output in at least two types of output intervals or a signal that is output in at least two types of pulse widths. Configuration is optional.

  Further, the composite pulse signal used in the present embodiment may be applied to the seventh embodiment. In the signal output from the Q6 terminal, there are two kinds of LOW level periods and two kinds of HI level periods. Therefore, also in the seventh embodiment, the same effects as the effects described above can be obtained.

Twelfth Embodiment
Hereinafter, a twelfth embodiment of the pachinko machine 10 in which the jackpot lottery is performed using the jackpot random number counter C1 will be described based on FIGS. 45 and 46. FIG. FIG. 45 is a diagram showing an electrical configuration of the pachinko machine 10 in the present embodiment, and FIG. 46 is a flowchart showing main processing. In the following description, differences from the above-described embodiments will be described, and the description of the same configuration will be basically omitted.

  In this embodiment, as shown in FIG. 45, a counter updating circuit 701 having an initial value random number counter CF and a big hit random number counter C1 is different from the MPU 311, instead of the configuration in which the MPU 311 is provided with the counters CINI and C1. It is provided on the main control board 301 by the body. The counter updating circuit 701 is electrically connected to the power and discharge control board 321 via the power failure monitoring substrate 302, and the counter updating circuit 701 is a power source unit for powering on 321a or a power source unit for powering off 321c. Power is always supplied from.

  The counter updating circuit 701 includes a circuit that outputs a pulse signal at a predetermined cycle, and the big hit random number counter C1 and the initial value random number counter CF are 0 to 676 in synchronization with the pulse signal output from the circuit. Within the range, one is added sequentially, and after reaching the maximum value (i.e., 676), it returns to zero. That is, independently of the MPU 311, the values of the big hit random number counter C1 and the initial value random number counter CF are updated, and are further updated regardless of the on / off state of the pachinko machine 10.

  Here, the counter updating circuit 701 is additionally provided with a pulse signal input frequency counter, and the initial frequency random number counter CF has a case where the input frequency counter reaches a predetermined value (for example, “5”). Then, the value of the initial value random number counter CF is updated. As a result, the update frequency of the initial value random number counter CF is different from the update frequency of the big hit random number counter C1. Therefore, the initial value random number counter CF and the big hit random number counter C1 are not completely synchronized with each other.

  Furthermore, the counter updating circuit 701 is additionally provided with a counter that determines the initial value of the input number counter. The counter is uniquely updated in the numerical range (for example, within the range of “0” to “4”) that can be taken by the input number counter, and when the value of the initial value random number counter CF is updated, The value of the input number counter at the time is acquired. As a result, the value of the initial value random number counter CF is updated at irregular timing. Therefore, it is difficult to grasp the value of the initial value random number counter CF.

  Next, the main processing in the present embodiment will be described using FIG. The processing of step S901 to step S909 and the processing of step S911 to step S913 in the main processing are the same as the processing of step S401 to step S409 and the processing of step S410 to step S412 in the main processing of FIG. Here, the clear target in the clear processing of the used RAM area is the RAM 316 of the MPU 311, and the value of the counter of the counter update circuit 701 is excluded from the target of the clear processing.

  In this embodiment, before the process of setting the interrupt permission in step S911 (after the execution of the initial setting of the RAM 316 in step S909 or after the process of erasing the RAM determination value in step S913), the initial process is performed in step S910. The point which performs value setting processing differs from other embodiments. In the initial value setting process, the MPU 311 acquires the value of the initial value random number counter CF at that time, and the acquired value is set as the initial value of the big hit random number counter C1. Then, the value of the jackpot random number counter C1 is sequentially updated in the counter updating circuit 701 from the value of the initial value random number counter CF.

  That is, the values of the big hit random number counter C1 and the initial value random number counter CF are updated independently of the MPU 311 and the pachinko machine 10 is powered on regardless of the power-off state or the power-on state of the pachinko machine 10 In this case, the MPU 311 acquires the value of the initial value random number counter CF, and the value of the jackpot random number counter C1 is updated with the acquired value as the initial value.

  Further, the irregular delay circuit 602 is provided on the path connecting the reset circuit 601 and the MPU 311 in the same manner as each of the above-described embodiments. The start timing of the operation of the MPU 311 is irregularly delayed. The said reset signal is a signal output based on power being supplied to the pachinko machine 10. The initial value setting process is a process that is executed when the MPU 311 starts the operation. Therefore, the execution timing of the initial value setting process is irregularly delayed with respect to the timing at which the pachinko machine 10 is powered on. That is, in the present embodiment, the target of the process delayed by the irregular delay circuit 602 is the initial value setting process, and the timing at which the power of the pachinko machine 10 is turned on is delayed by delaying the execution of the process. The acquisition timing of the initial value will be delayed.

  Under the condition that the pachinko machine 10 is in the power-on state, when the value of the big hit random number counter C1 makes one rotation, a notification signal to notify that is output to the MPU 311. In the RAM 316, a flag storage area corresponding to the notification signal is provided, and when the notification signal is input to the MPU 311, a flag corresponding to the notification signal is stored in the storage area. There is. Then, after the process of step S508 of the normal process (see FIG. 20), a process of determining whether a flag corresponding to the signal is stored is executed. When the corresponding flag is stored, the MPU 311 reads the value of the initial value random number counter CF at that time, and sets the value as the initial value of the large hitting random number counter C1. Thereafter, the value of the jackpot random number counter C1 is updated from the initial value. Thus, the initial value random number counter CF is also used as the random number initial value counter CINI.

  For the start winning process, as shown in the flowchart of FIG. 18, the MPU 311 reads the value of the big hit random number counter C1 at that time from the counter updating circuit 701 in step S305, and the read value is transferred to step S307. And store in the holding ball storage area.

  According to the embodiment described above, the following excellent effects can be obtained.

  A counter updating circuit 701 having a jackpot random number counter C1 and an initial value random number counter CF periodically updated regardless of the power-on state and the power-off state of the pachinko machine 10 is provided. Then, when the MPU 311 is operating and the gaming ball enters the operation port 84, the MPU 311 reads the big hit random number counter C1 at that time. In such a configuration, in the main processing executed when the MPU 311 starts operation, the value of the initial value random number counter CF at that time is set as the initial value of the big hit random number counter C1, and the value of the big hit random number counter C1 is set. It is configured to be sequentially updated from the initial value. Here, since the value of the initial value random number counter CF is updated regardless of whether the pachinko machine 10 is turned on or off, the value of the initial value random number counter CF corresponds to the timing when the MPU 311 starts operation. Are fluctuating. As a result, the initial value of the jackpot random number counter C1 when the MPU 311 starts operation becomes irregular, so it is difficult to grasp the initial value. Therefore, based on the start timing of the operation of the MPU 311, it is difficult to grasp the timing at which the value of the big hit random number counter C1 becomes the winning value. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like.

  The initial value random number counter CF and the big hit random number counter C1 are prevented from being completely synchronized. Even if the initial value random number counter CF is obtained as the initial value of the big hit random number counter C1 if both are completely synchronized, the obtained value is the value of the big hit random number counter C1 at that time, By grasping the value of the jackpot random number counter C1, it is possible to grasp the initial value of the jackpot random number counter C1 after the execution of the initial value acquisition processing, and cheating using the “hanging board” etc. by the execution of the initial value acquisition processing Can not get enough of the suppression effect. On the other hand, if the configuration is such that the big hit random number counter C1 and the initial value random number counter CF do not completely synchronize, it is difficult to grasp the value of the initial value random number counter CF from the big hit random number counter C1. Cheating can be suitably suppressed.

  Further, since the value of the initial value random number counter CF is updated regardless of the on / off state of the pachinko machine 10, the value of the initial value random number counter CF constantly fluctuates. As a result, when the pachinko machine 10 is in the power-off state, the value of the initial value random number counter CF is hard to be grasped as compared with the configuration in which the pachinko machine 10 is in the power-off state. Therefore, it is possible to more preferably suppress fraudulent acts using the “hanging board” or the like.

  The counter value of the counter update circuit 701 is excluded from the target of initialization. If the counter values of the counter update circuit 701 are to be initialized, these values are set to predetermined values by the RAM data initialization process, and are acquired after the initialization process. The value of the initial value random number counter CF does not change. On the other hand, as described above, since the counter value of the counter update circuit 701 is excluded from the target of initialization of the initialization process of the RAM data, the counter value is affected by the initialization process of the RAM data. I do not receive it. As a result, the value of the initial value random number counter CF acquired after the initialization process fluctuates according to the acquisition timing. That is, the fluctuation of the initial value after the initialization process is secured.

  Here, if the output timing of the reset signal is grasped temporarily by "hanging board" etc. and the value of the initial value random number counter CF is grasped further, the value of the initial value random number counter CF at the reset signal output timing is grasped There is a risk of Then, since the initial value of the big hit random number counter C1 at the output timing of the reset signal is grasped, there is a possibility that the timing at which the value of the big hit random number counter C1 becomes the winning value may be grasped. On the other hand, since the irregular delay circuit 602 is provided on the path connecting the reset circuit 601 which outputs the reset signal and the MPU 311 which executes the initial value setting process, the output timing of the reset signal is set. The operation start timing of the MPU 311 is irregularly delayed. Since the execution timing of the initial value setting process is irregularly delayed with respect to the output timing of the reset signal, the acquisition timing of the initial value random number counter CF becomes irregular with respect to the output timing of the reset signal. Therefore, based on the output timing of the reset signal, it is difficult to grasp the initial value of the jackpot random number counter C1. Therefore, it is possible to make it difficult to grasp the timing at which the value of the jackpot random number counter C1 becomes the winning value, and therefore, it is possible to preferably suppress fraudulent acts using a "hanging board" or the like.

  In the present embodiment, any of the irregular delay circuits 602 of the fifth to eleventh embodiments may be used.

  Further, although the counter updating circuit 701 is provided on the main control board 301, the present invention is not limited to this. However, it is preferable to provide the main control board 301 in view of crime prevention and wiring.

The thirteenth embodiment
In the present embodiment, targets to be delayed by the irregular delay circuit 602 are different. Therefore, the target to be delayed in the present embodiment will be described below. In the following description, the description of the same configuration as that of the fifth to twelfth embodiments is basically omitted.

  As shown in FIG. 47, the power supply and emission control device 243 is provided with a power on RAM erase switch 801 instead of the RAM erase switch 247. During power-on, the RAM erasing switch 801 is a switch that can be pressed from the outside. During power-on, the RAM erase switch 801 is electrically connected to the RAM erase signal output circuit 802 provided on the main control board 301.

  The RAM erase signal output circuit 802 is electrically connected to the MPU 311. The RAM erase signal output circuit 802 is configured to output a RAM erase signal based on the fact that the RAM erase switch 801 is operated during power on. When the RAM erase signal is input to the MPU 311, the MPU 311 is configured to execute the process of initializing the RAM data, specifically, the process of step S408 and step S409 of the main process (FIG. 19). There is. Thus, the RAM data can be initialized without the power ON / OFF operation. That is, in the above embodiments, the process of initializing the RAM data is executed by turning on the power while pressing the RAM erase switch 247. However, in the present embodiment, the RAM data is not required to be turned on. Can be initialized. Thus, the RAM data can be easily initialized.

  Here, as shown in FIGS. 47 and 48, the irregular delay circuit 602 is provided on the path connecting the RAM erase signal output circuit 802 and the MPU 311. The RAM erase signal output from the RAM erase signal output circuit 802 is input to the MPU 311 via the irregular delay circuit 602. Specifically, when the RAM erase switch 801 is operated during power on, the RAM erase signal output circuit 802 outputs a HI level signal which is a RAM erase signal. The HI level signal is input to the NAND circuit 612 through the signal line LN3 and the signal line LN4. In this case, the signal state input from signal line LN3 to NAND circuit 612 immediately becomes HI level.

  On the other hand, the input of the HI level signal from signal line LN 4 to NAND circuit 612 is delayed by integration circuit 611 of irregular delay circuit 602. The said delay period is fluctuate | varied by the residual charge amount accumulate | stored in the capacitor | condenser 613 as mentioned above. Then, when the HI level signal is input to the NAND circuit 612 from the signal line LN 3 and the signal line LN 4, the LOW level signal is output from the NAND circuit 612. When the LOW level signal is input to the MPU 311, the MPU 311 executes a process of initializing RAM data.

  In the embodiment described above, the irregular delay circuit 602 is provided on the path connecting the RAM erase signal output circuit 802 and the MPU 311. As a result, the period from the output timing of the RAM erase signal output from the RAM erase signal output circuit 802 to the execution timing when the initialization process of the RAM data is executed fluctuates. Therefore, the period becomes irregular. Therefore, even if the value of the big hit random number counter C1 is started to be updated from a predetermined fixed value when the RAM data initialization process is executed, the RAM erase signal output circuit 802 is used. It is difficult to grasp the timing at which the value of the jackpot random number counter C1 becomes the winning value based on the timing at which the RAM erase signal is output (or the timing at which the RAM erase switch 801 is operated during charging). Therefore, it is possible to suppress the fraudulent acts using the “hanging board” or the like while securing the ease of the initialization process of the RAM data.

  In addition, although the power on / off RAM erase switch 801 is provided in the power supply and emission control device 243, the present invention is not limited to this, and may be provided in, for example, the main control device 162.

  Further, although the configuration of the fifth embodiment is used as the irregular delay circuit 602 in the present embodiment, the present invention is not limited to this, and any configuration of the sixth to eleventh embodiments may be used.

Fourteenth Embodiment
In the present embodiment, the configuration relating to the jackpot random number counter C1 and the like is different from that of the thirteenth embodiment. Therefore, the difference will be described in detail. In the following description, the description of the same configuration as that of the thirteenth embodiment is basically omitted.

  In the present embodiment, the counter updating circuit 701 shown in the twelfth embodiment is provided. As described above, the counter updating circuit 701 is provided with the big hit random number counter C1 and the initial value random number counter CF, and the values of the counters C1 and CF do not matter whether the pachinko machine 10 is turned on or off. , And independently from the MPU 311. Then, when the gaming ball enters the operation opening 84, the MPU 311 reads the value of the big hit random number counter C1 at that time, and determines whether the value is equal to the winning value.

  The normal processing in this configuration will be described with reference to FIG. First, in step S1001, it is determined whether the RAM erase flag is present. Here, a RAM erase flag storage area is provided in the RAM 316, and the RAM erase flag is stored in the RAM erase flag storage area in the timer interrupt process (FIG. 17) when the RAM erase signal is input to the MPU 311. Is a flag that That is, the fact that the RAM erase flag is stored means that the RAM erase switch 801 is operated during power on. In this case, the process proceeds to step S1002.

  The processes of steps S1002 to S1004 are the same as the processes of steps S908 to S910. In other words, the used RAM area is cleared and the RAM 316 is initialized. Then, the value of the initial value random number counter CF is acquired, and the acquired value is set as the initial value of the jackpot random number counter C1.

  Thereafter, in step S1005, a process of clearing the RAM erase flag is executed. In this process, the RAM erase flag is erased. After the process is performed, the process proceeds to step S1006.

  The processes of step S1006 to step S1012 are the same as the processes of step S501 to step S507 of FIG.

  In the processes of step S1013 and step S1014, an initial value setting process of the big hit random number counter C1 is executed when the value of the big hit random number counter C1 makes one turn. Specifically, first, in step S1013, it is determined whether the value of the jackpot random number counter C1 has made one revolution. In detail, when the value of the jackpot random number counter C1 makes one rotation, a signal to that effect is output from the counter updating circuit 701. The RAM 316 is provided with a flag storage area corresponding to the signal, and when the signal is input to the MPU 311, the flag corresponding to the signal is stored in the storage area. Then, in step S1013, it is determined whether the corresponding flag is stored.

  If the value of the jackpot random number counter C1 does not make one revolution, the process proceeds to step S1015, while if the value of the jackpot random number counter C1 makes one revolution, the process proceeds to step S1014 to execute initial value setting processing. The process proceeds to step S1015. The initial value setting process is the same as step SS 1004 (step S 910). The process of step S1015 to step S1018 is the same as the process of step S508 to step S511.

  According to the present embodiment described above, the counter update having the big hit random number counter C1 and the initial value random number counter CF in the pachinko machine 10 provided with the RAM erase switch 801 during charging and the RAM erase signal output circuit 802 is updated. A circuit 701 was provided. When the RAM erase switch 801 is operated during power on, the RAM data initialization process is executed, and the value of the initial value random number counter CF of the counter update circuit 701 is acquired, and the acquired value is obtained. Is set as the initial value of the jackpot random number counter C1. Thereby, when the RAM erase switch 801 during power on is operated, the value of the random value counter CF for initial value obtained by the initial value setting process fluctuates according to the operation timing of the RAM erase switch 801 during power on. The initial value of the big hit random number counter C1 when the RAM erase switch 801 is operated during power on is difficult to be grasped. Therefore, it is possible to suppress fraudulent acts such as "hanging board".

  In addition, since the value of the big hit random number counter C1 and the value of the initial value random number counter CF are updated independently in the counter updating circuit 701, and the MPU 311 only reads the updated numerical value, the processing load of the MPU 311 is It is reduced. In particular, when the RAM erase switch 801 during power on is provided and the initialization process of the RAM data based on the RAM erase switch 801 during power on is executed in the normal process, there is a concern that the processing load may increase. Then, the random number initial value updating process is not sufficiently performed, and there is a possibility that the numerical value of the random number initial value counter CINI may be biased. As a result, a bias occurs in the possible values of the jackpot random number counter C1. On the other hand, in the present embodiment, regardless of the processing status of the MPU 311, the value of the jackpot random number counter C1 and the value of the initial value random number counter CF are updated. That is, it is possible to avoid the inconvenience that may occur due to the initialization of the RAM erase switch 801 and the RAM data based on the switch during power-on.

The fifteenth embodiment
Hereinafter, a fifteenth embodiment of the pachinko machine 10 in which the jackpot lottery is performed using the jackpot random number counter C1 will be described based on FIG. 50 and FIG. FIG. 50 is a view showing a part of the electrical configuration of the pachinko machine 10 in the present embodiment. In the following description, differences from the above-described embodiments will be described, and the description of the same configuration will be basically omitted.

  In the first embodiment and the like, the hard random number clock circuit 313 generates the clock signal from the AC voltage. However, in the present embodiment, the clock circuit 313 has a crystal oscillator instead and supplies the operating power. The jackpot random number counter C1 is updated using the hard random number clock circuit 900 that generates a hard random number clock signal based on the above.

  Specifically, the main control board 301 is provided with a hard random number clock circuit 900 for outputting a hard random number clock signal. The hard random number clock circuit 900 is an oscillation circuit provided with a quartz oscillator, and is electrically connected to the power supply and emission control substrate 321 via the power failure monitoring substrate 302. When the pachinko machine 10 is in the power-on state, the operating voltage Vcc of the DC voltage is supplied from the power supply and emission control board 321 to the hard random number clock circuit 900 as the operating power. The hard random number clock circuit 900 is configured to output a hard random number clock signal in a state where the operating power is supplied from the power supply and the emission control board 321. The hard random number clock signal is set to be a clock signal having a cycle different from that of the system clock signal.

  The hard random number clock circuit 900 is electrically connected to the MPU 311, and the hard random number clock signal is output to the MPU 311. In part of the ROM 315 of the MPU 311, a jackpot random number counter C1 that updates numerical information based on an input of a hard random number clock signal is provided. The jackpot random number counter C1 is set to be updated in synchronization with the input of the hard random number clock signal without being synchronized with the input of the system clock signal. The jackpot random number counter C1 is configured to be sequentially incremented by 1 within the range of 0 to 676, and returned to 0 after reaching the maximum value (i.e., 676). Then, when the gaming ball enters the operating port 84, the value of the jackpot random number counter C1 at that time is acquired, and the determination of whether or not it is performed.

  When the pachinko machine 10 is in the power-off state, the counter value of the big hit random number counter C1 is not held. Then, in the start-up process executed when the pachinko machine 10 is in the power-on state, the counter value of the big hit random number counter C1 is configured to be reset to a predetermined value (for example, “0”).

  Here, as shown in FIGS. 50 and 51, a power transfer circuit 901 for transferring operating power is provided on a path connecting the hard random number clock circuit 900 and the disconnection monitor substrate 302. The power transfer circuit 901 will be described with reference to the block circuit diagram of FIG.

  The power transfer circuit 901 has its operating power for hard random numbers based on the signal outputted from the irregular delay circuit 602, the adjustment resistor 911 for adjusting voltage and current to the irregular delay circuit 602, and the irregular delay circuit 602. And an amplifier circuit 912 for supplying the clock circuit 900.

  First, the amplifier circuit 912 will be described. The amplifier circuit 912 is composed of an NPN transistor 913 and a PNP transistor 914. These two transistors 913 and 914 are connected in a so-called inverted Darlington connection. Specifically, the collector of the NPN transistor 913 is connected to the base of the PNP transistor 914, the emitter of the NPN transistor 913 is grounded, and the base of the NPN transistor 913 is connected to the output terminal of the irregular delay circuit 602. The collector of the PNP transistor 914 is connected to the hard random number clock circuit 900, and the emitter of the PNP transistor 914 is connected to the power and emission control board 321. An operating voltage Vcc of direct current is applied to the emitter of the PNP transistor 914 from the power supply and emission control board 321 in a state where the pachinko machine 10 is in the power-on state.

  According to this configuration, in the situation where the low level signal is output from the irregular delay circuit 602, no current flows to the base of the NPN transistor 913, so the NPN transistor 913 is in the off state. In this case, no current flows between the collector and the emitter of the NPN transistor 913. Since the current between the collector and the emitter of the NPN transistor 913 is the base current of the PNP transistor 914, no current flows in the base of the PNP transistor 914. Thus, the PNP transistor 914 is in the off state. As a result, no current flows between the collector and the emitter of the PNP transistor 914, so no operating power is supplied to the hard random number clock circuit 900.

  On the other hand, when a high level signal is output from the irregular delay circuit 602, a base current of a predetermined magnitude flows in the NPN transistor 913, and the NPN transistor 913 is turned on. In this case, a base current flows to the base of the PNP transistor 914. The current value of the base current is a value obtained by multiplying the current value of the base current flowing through the NPN transistor 913 by the amplification factor of the NPN transistor 913. Then, the PNP transistor 914 is turned on, and a predetermined current (collector current) flows between the emitter and the collector of the PNP transistor 914. The collector current is a value obtained by multiplying the current value of the base current of the PNP transistor 914 by the amplification factor of the PNP transistor 914. That is, the current value of the collector current is a value obtained by multiplying the amplification factor of the NPN transistor 913 and the amplification factor of the PNP transistor 914 by the current value of the base current of the NPN transistor 913.

  Further, since the inverted Darlington connection of the NPN transistor 913 and the PNP transistor 914 is made, the voltage lost in the amplifier circuit 912 is the saturation voltage (the voltage between the collector and the emitter) of the PNP transistor 914.

  For example, in the case of a Darlington connection consisting of two NPN transistors, the amplification factor is the same as that of the inverted Darlington connection, while the voltage lost due to its configuration is between the base and emitter of the first stage NPN transistor. It is a voltage obtained by combining the voltage and the saturation voltage of the second stage NPN transistor. That is, when the inverted Darlington connection is used, the voltage loss by the amplifier circuit 912 is reduced while securing the same amplification factor as compared with the case where the Darlington connection is used.

  From the above, when the random delay circuit 602 outputs the HI level signal, the hard random number clock circuit 900 is supplied with a current higher than the current flowing from the irregular delay circuit 602 and is high. The voltage in which the voltage drop accompanying the current is suppressed is applied. Thereby, when the HI level signal is output from the irregular delay circuit 602, the hard random number clock circuit 900 supplies operable power to the hard random number clock circuit 900 while suppressing the circuit loss. Can. That is, on / off of the amplification circuit 912 is switched according to the output state from the irregular delay circuit 602, and on / off of power supply to the hard random number clock circuit 900 is switched according to the switching.

  Each of the NPN transistor 913 and the PNP transistor 914 is provided with input resistors 913 a and 914 a for converting a voltage input to the base into a current. Thus, the NPN transistor 913 and the PNP transistor 914 are controlled based on the base current instead of the input voltage. In particular, generally in a transistor, the collector current changes exponentially with changes in input voltage relative to the base, while changing linearly with changes in base current. Therefore, base current control can realize more stable collector current supply than control based on the input voltage to the base. Thus, stable operation power can be supplied to the hard random number clock circuit 900.

  Each of the NPN transistor 913 and the PNP transistor 914 is provided with a bypass wiring for connecting the base and the emitter, and resistors 913 b and 914 b are provided on the wiring. Thus, a leakage current (including one generated due to noise or the like) flows on the bypass wiring through the resistor 913 b or 914 b, so the leakage current does not easily flow to the base of the transistor. Therefore, malfunction of each of the transistors 913 and 914 is suppressed.

  In particular, in the case of the inverted Darlington connection, the base of the PNP transistor 914 is in a floating state when the NPN transistor 913 is in the off state, and the input voltage to the base is likely to be unstable. Therefore, the power supply to the hard random number clock circuit 900 becomes unstable, and the hard random number clock signal may not be output in a predetermined cycle. On the other hand, in the present embodiment, the base of the PNP transistor 914 is pulled up by the bypass wiring and the resistor 914 b. Thereby, the above-mentioned inconvenience can be avoided, and the stability of the circuit in the amplifier circuit 912 is enhanced. That is, the disadvantages that may be caused by using inverted Darlington connections can be avoided.

  Furthermore, when the output from the irregular delay circuit 602 or the application of the operating voltage Vcc is stopped, the carrier accumulated in each of the transistors 913 and 914 is released through the bypass wiring, so that the turn-off can be speeded up. It has been realized. Thus, the supply of the operating power to the hard random number clock circuit 900 can be stopped quickly.

  The irregular delay circuit 602 that performs on / off control of the amplifier circuit 912 and the adjustment resistor 911 will be described.

  First, the adjustment resistor 911 will be described. The adjustment resistor 911 is arranged in series on the path connecting the irregular delay circuit 602 and the power supply and emission control board 321. When the operating voltage Vcc is applied from the power supply and emission control board 321, the operating voltage Vcc is input to the irregular delay circuit 602 through the adjustment resistor 911. Thus, the resistance value of the adjustment resistor 911 adjusts the input voltage and input current input to the irregular delay circuit 602. Specifically, when the operating voltage Vcc is applied from the power supply and emission control board 321, the irregular delay circuit 602 is set to receive a voltage that can be recognized as an HI level signal. Therefore, excessive voltage application and current flow to the irregular delay circuit 602 are suppressed, so that normal operation and power consumption of the irregular delay circuit 602 can be reduced. .

  Next, the irregular delay circuit 602 will be described. The irregular delay circuit 602 is configured to output an HI level signal or a LOW level signal based on the input voltage from the power supply and emission control board 321 and the pulse signal from the signal conversion circuit 402. Specifically, the irregular delay circuit 602 is composed of a D flip flop 915 and an AND circuit 916. The power and emission control board 321 is connected to the D terminal of the D flip-flop 915 through the adjustment resistor 911, and the output terminal of the signal conversion circuit 402 (the output terminal of the Schmitt trigger 413) is connected to the CLK terminal. One input terminal of an AND circuit 916 is connected to the Q terminal. The power and emission control board 321 is connected to the other input terminal of the AND circuit 916 via the adjustment resistor 911.

  Here, the operation of the irregular delay circuit 602 will be described. When the pachinko machine 10 is turned on, the operating voltage Vcc is applied from the power and emission control board 321, and the HI level signal is input to the D terminal of the D flip flop 915 and one end of the input terminal of the AND circuit 916. In this case, a low level signal is output from the Q terminal, and a low level signal is output from the AND circuit 916.

  Thereafter, as described in the eighth embodiment, when the pulse signal from the Schmitt trigger 413 rises, the HI level signal is output from the Q terminal in synchronization with the rise. Then, since the HI level signal is output from the AND circuit 916, the amplification circuit 912 operates as described above. The operation of the amplification circuit 912 supplies operating power to the hard random number clock circuit 900.

  Here, the period from when the operating voltage Vcc is applied until the AND circuit 916 outputs the HI level signal fluctuates according to the form of the pulse signal at the time when the operating voltage Vcc is applied. The form of the pulse signal fluctuates according to the timing at which the pachinko machine 10 is turned on. That is, it can be said that the period from when the pachinko machine 10 is turned on to when the HI level signal is output from the AND circuit 916 fluctuates according to the timing at which the pachinko machine 10 is turned on. As a result, the period until the operating power is supplied to the hard random number clock circuit 900 is irregular after the pachinko machine 10 is turned on.

  When the pachinko machine 10 is in the power-off state, the application of the operating voltage Vcc from the power supply and emission control board 321 is stopped. In this case, the LOW level signal is input to the irregular delay circuit 602, more specifically, to the D terminal of the D flip flop 915 and the other input terminal of the AND circuit 916. As a result, the LOW level signal is immediately output from the AND circuit 916, and the amplification circuit 912 is turned off. Therefore, the amplifier circuit 912 can be turned off without waiting for the output of the LOW level signal from the Q terminal.

  Here, in the situation where the operating voltage Vcc is not supplied from the power supply and emission control substrate 321, no voltage is applied between the collector and the emitter of the PNP transistor 914 of the amplifier circuit 912. The amplifier circuit 912 does not operate. However, the amplifier circuit 912 may operate due to the influence of carriers stored in the transistor. In particular, since the saturation voltage is lower than the voltage between the base and the emitter required to turn on the transistor, the NPN transistor 913 is off when the NPN transistor 913 is on. Compared to the situation, the PNP transistor 914 is prone to malfunction.

  On the other hand, in the present embodiment, when the pachinko machine 10 is in the power-off state, the irregular delay circuit 602 immediately sends the amplifier circuit 912 to the amplifier circuit 912 without waiting for the input of the LOW level signal from the D terminal. The LOW level signal is output, and the NPN transistor 913 of the amplification circuit 912 is turned off based on the input of the LOW level signal. Thus, malfunction of the amplifier circuit 912 is less likely to occur. Therefore, it is suppressed that the operation power is supplied to the hard random number clock circuit 900 even though the pachinko machine 10 is turned off.

  According to the present embodiment described in detail above, the pachinko machine 10 enters the on state from the timing when the pachinko machine 10 enters the on state until the operating power is supplied to the hard random number clock circuit 900. An irregular delay circuit 602 is provided which varies according to the timing. As a result, the period until the operation timing of the hard random number clock circuit 900 (the output start timing of the hard random number clock signal) changes after the pachinko machine 10 is turned on. Then, it is difficult to grasp the update timing of the jackpot random number counter C1 that performs the update based on the input of the hard random number clock signal. Therefore, even if the jackpot random number counter C1 is reset when the pachinko machine 10 is in the ON state, it is difficult to know the update start timing of the jackpot random number counter C1. Cheating can be suitably prevented.

  Further, even when the operation timing of the hard random number clock circuit 900 fluctuates, the operation timing of the system clock circuit 312 is constant, so the operation of the hard random number clock circuit 900 is delayed by the irregular delay circuit 602. Even in the case where this is done, the MPU 311 can be operated normally.

  Further, the cycle of the hard random number clock signal is set to be different from the cycle of the system clock signal. As a result, even if the cycle of the system clock signal is grasped, the update timing of the jackpot random number counter C1 to be updated according to the hard random number clock signal is not grasped. Therefore, it is possible to prevent an unfair act of grasping the update timing of the big hit random number counter C1 from the cycle of the system clock signal and finding the timing when the big hit random number counter C1 matches the winning information.

Sixteenth Embodiment
The present embodiment is different from the fifteenth embodiment in the configuration relating to data erasure, and is different from the fifteenth embodiment in the object to be irregularly delayed. Thus, the configuration relating to data erasure in the present embodiment will be described below. In the following description, the description of the same configuration as the fifteenth embodiment is basically omitted.

  As shown in FIG. 52, the power supply and emission control device 243 is provided with a data erase switch 1001 in place of the RAM erase switch 247. The data erasing switch 1001 is a switch that can be operated from the outside of the pachinko machine 10. The data erase switch 1001 is electrically connected to a data erase signal output circuit 1002 provided on the main control substrate 301.

  The data erase signal output circuit 1002 is connected to the MPU 311 via the signal line LN5. The data erase signal output circuit 1002 is configured to output a data erase signal to the MPU 311 based on the operation of the data erase switch 1001. When the data erase signal is input to the MPU 311, the MPU 311 executes a process of initializing the RAM data, and more specifically, executes the processes of step S408 and step S409 of the main process (FIG. 19). It is comprised so that the process which initializes the counter value of the big hit random number counter C1 may be performed. Thus, the data initialization process can be performed without the power ON / OFF operation. Therefore, data initialization processing can be easily performed.

  The data erase signal output circuit 1002 is connected to the power transfer circuit 901 via a signal line LN6 different from the signal line LN5. The data erasing signal output circuit 1002 outputs the HI level signal or the LOW level signal to the power transfer circuit 901 in a situation where the pachinko machine 10 is in the power-on state. The power transfer circuit 901 supplies operating power to the hard random number clock circuit 900 based on the input of the HI level signal from the data cancellation signal output circuit 1002.

  Describing in detail, as shown in the block circuit diagram of FIG. 53, the power transfer circuit 901 is provided with a reset transistor 1003 on the upstream side with respect to the adjustment resistor 911 and the amplifier circuit 912. The reset transistor 1003 is an NPN transistor, the collector is connected to the power and emission control substrate 321 via the power failure monitoring substrate 302, and the emitter is connected to each of the adjustment resistor 911 and the amplifier circuit 912, The base is connected to the data erase signal output circuit 1002.

  In the situation where the HI level signal is output from data erase signal output circuit 1002, reset transistor 1003 is in the ON state, so that operating voltage Vcc from power supply and discharge control substrate 321 (more specifically, operating voltage Vcc). Of the reset transistor 1003) is applied to the irregular delay circuit 602 and the amplifier circuit 912. In this case, the operating power is supplied to the hard random number clock circuit 900 through the amplifier circuit 912 on condition that the HI level signal is output from the irregular delay circuit 602 to the amplifier circuit 912.

  On the other hand, in the situation where the LOW level signal is output from the data erase signal output circuit 1002, the reset transistor 1003 is in the OFF state, so the operating voltage Vcc from the power and emission control substrate 321 is irregularly delayed. It is not applied to the circuit 602 and the amplifier circuit 912. In this case, as described in the fifteenth embodiment, the low level signal is output from the irregular delay circuit 602 to the amplifier circuit 912, and the voltage between the collector and the emitter of the PNP transistor 914 of the amplifier circuit 912 is Not applied. Therefore, since the amplification circuit 912 does not operate, no operating power is supplied to the hard random number clock circuit 900.

  Here, when the data erase switch 1001 is operated, the data erase signal output circuit 1002 is configured to output a LOW level signal over a predetermined stop period Ts. The specific stop period Ts is set to be longer than one cycle of the pulse signal output from the Schmitt trigger 413.

  The operation of the power transfer circuit 901 based on the operation of the data erase switch 1001 will be described based on the timing chart of FIG. The timing of t59, the timing of t60, and the timing of t62 indicate the rising timing of the pulse signal from the Schmitt trigger 413, and at this timing, the D flip flop 915 is input to the D terminal at that time. Output the signal from the Q terminal. That is, the cycle T3 of the pulse signal output from the Schmitt trigger 413 is a cycle in which the D flip-flop 915 is synchronized.

  When the data erase switch 1001 is operated at timing t58, the signal state from the data erase signal output circuit 1002 to the power transfer circuit 901 falls from the HI level to the LOW level. Then, a voltage is not applied between the collector and the emitter of the PNP transistor 914 of the amplification circuit 912, and the AND circuit 916 outputs a LOW level signal. Thereby, the supply of operating power to the hard random number clock circuit 900 is stopped.

  A low level signal is input to the D terminal of the D flip flop 915 based on the fact that the signal state from the data erase signal output circuit 1002 has become the low level. On the other hand, since the timing of t58 is not the timing at which the D flip-flop 915 synchronizes, the output state from the Q terminal is maintained at the HI level.

  After that, at the timing of t59, since the LOW level signal is input to the D terminal, the LOW level signal is output from the Q terminal. Also at the timing of t60, since the LOW level signal is input to the D terminal, the LOW level signal is output from the Q terminal.

  Thereafter, at time t61 when the specific stop period Ts has elapsed since the data erase switch 1001 was operated, the signal state output from the data erase signal output circuit 1002 is switched from the LOW level to the HI level. As a result, a voltage is applied between the collector and the emitter of the PNP transistor 914 of the amplification circuit 912, and a HI level signal is input to the D terminal. On the other hand, since the timing is not the synchronization timing of the D flip flop 915, the output state from the Q terminal is maintained at the LOW level state.

  Thereafter, at the timing of t62, the D flip-flop 915 is synchronized to output the HI level signal from the Q terminal. Thus, the HI level signal is output from the AND circuit 916. Thus, the amplifier circuit 912 operates, and the supply of operating power to the hard random number clock circuit 900 is resumed. In this case, the operation power supply start timing (timing t62) is delayed by a delay period DT14 with respect to the timing (timing t61) at which the data erase signal output circuit 1002 outputs the HI level signal.

  From the above, when the data erase switch 1001 is operated, the supply of the operating power to the hard random number clock circuit 900 is temporarily stopped. Then, when the period obtained by combining the specific suspension period Ts and the delay period DT14 has elapsed from the supply suspension timing of the operating power, the supply of the operating power is resumed. Since the delay period DT14 is a period that fluctuates according to the timing at which the pachinko machine 10 enters the on state, as described in the eighth embodiment etc. The timing of resumption is variable. As a result, since it is difficult to grasp the restart timing of the power supply to the hard random number clock circuit 900, it is possible to suppress the fraudulent act by the “hanging board” or the like.

  Here, the specific stop period Ts is set to be longer than the period T1 of the pulse signal output from the Schmitt trigger 413. As a result, the synchronization timing of the D flip flop 915 is at least once during the specific stop period Ts, and a LOW level signal is output from the Q terminal. Therefore, the LOW level signal is output from the Q terminal at the elapsed timing of the specific stop period Ts. In other words, when the specific stop period Ts has elapsed, the D flip flop 915 is reliably reset.

  According to the present embodiment described in detail above, the data erase switch 1001 and the data erase signal output circuit 1002 that outputs the HI level signal to the power transfer circuit 901 when the pachinko machine 10 is in the on state, Provided. The data erase signal output circuit 1002 outputs a data erase signal to the MPU 311 based on the operation of the data erase switch 1001, and outputs a LOW level signal to the power transfer circuit 901 for the specific stop period Ts. It was set up. In such a configuration, in the situation where the HI level signal is input from data erase signal output circuit 1002, a voltage is applied to irregular delay circuit 602 and amplifier circuit 912 while the LOW level from data erase signal output circuit 1002 is applied. In the situation where a signal is input, the reset transistor 1003 is provided to stop the application of the operating voltage Vcc to the irregular delay circuit 602 and the amplifier circuit 912. Thus, the period from the operation timing of the data erase switch 1001 to the output timing of the hard random number clock signal becomes irregular. Therefore, even when the operation timing of the data erase switch 1001 is known, the output timing of the hard random number clock signal is difficult to specify. Therefore, in synchronization with the operation of the data erasing switch 1001, it is possible to suppress the fraudulent act of specifying the timing when the value of the big hit random number counter C1 becomes the winning value.

  In particular, according to this configuration, the update start timing of the big hit random number counter C1 is irregularly delayed with respect to each of the power on timing and the operation timing of the data erasing switch 1001. As a result, it becomes difficult to grasp the update timing of the big hit random number counter C1 for each of the power on timing and the operation timing of the data erase switch 1001. You can suppress the act.

  The specific stop period Ts is set longer than the period T3 of the pulse signal output from the Schmitt trigger 413 (period in which the D flip-flop 915 is synchronized). Thus, in the situation where the specific stop period Ts has elapsed, the output state from the Q terminal of the D flip flop 915 is at the LOW level.

  That is, if the specific stop period Ts is shorter than the cycle T3, the D flip-flop 915 may not be synchronized during the specific stop period Ts. In this case, the HI level signal is output from the Q terminal at the elapse of the specific stop period Ts. Then, when the HI level signal is output from the data erase signal output circuit 1002, the supply of the operating power to the hard random number clock circuit 900 is immediately resumed without being delayed.

  On the other hand, in the present embodiment, since the specific stop period Ts is set to be longer than the cycle T3 of the pulse signal output from the D flip flop 915, the D flip flop 915 is surely set within the specific stop period Ts. It is supposed to synchronize. Thus, the D flip-flop 915 is reliably reset until the specific stop period Ts elapses after the data erase switch 1001 is operated. Thus, when the data erase signal output circuit 1002 outputs the HI level signal, irregular delay of the delay period DT14 occurs.

Seventeenth Embodiment
In the fifteenth and sixteenth embodiments, the irregular delay circuit 602 is provided on the path connecting the disconnection monitor substrate 302 and the hard random number clock circuit 900, and the irregular delay circuit 602 causes the pachinko machine 10 to The supply start timing of the power to the hard random number clock circuit 900 with respect to the timing when it enters the state fluctuates. On the other hand, in the present embodiment, targets of delay are different. The differences are described below. In addition, while attaching | subjecting the code | symbol same about the structure same as the said 15th Embodiment, description is abbreviate | omitted.

  As shown in the block diagram of FIG. 55, a clock signal transfer circuit 1101 is provided on the path connecting the hard random number clock circuit 900 and the MPU 311. The clock signal transfer circuit 1101 is electrically connected to the hard random number clock circuit 900 via the two signal lines LN7 and LN8. The hard random number clock circuit 900 outputs the hard random number clock signal via the signal line LN7 and the signal line LN8 when operating power is supplied.

  The clock signal transfer circuit 1101 will be described with reference to the block circuit diagram of FIG.

  The clock signal transfer circuit 1101 is composed of an irregular delay circuit 602 and a thyristor 1102. In the thyristor 1102, the anode is connected to the hard random number clock circuit 900 via the signal line LN 7, the cathode is connected to the MPU 311, and the gate is connected to the output side of the irregular delay circuit 602.

  According to this configuration, when the HI level signal is input to the gate, the hard random number clock signal is output from the cathode of the thyristor 1102 to the MPU 311. On the other hand, when the LOW level signal is input to the gate, the hard random number clock signal is not output to the MPU 311. Thus, transmission of the hard random number clock signal to the MPU 311 is controlled according to the signal state input to the gate. A signal input to the gate is supplied from the hard random number clock circuit 900 via the signal line LN8. The irregular delay circuit 602 is provided on the signal line LN8.

  The irregular delay circuit 602 is an integrating circuit, and when the hard random number clock circuit 900 outputs an HI level signal, as described in the fifth embodiment, it is delayed by a predetermined period and the HI level signal is output to the gate. It is input. Since the delay period fluctuates according to the timing at which the HI level signal is output, the timing at which the thyristor 1102 turns on changes with respect to the output timing of the hard random number clock signal. Thus, the timing at which the hard random number clock signal is output from the thyristor 1102 fluctuates with respect to the timing at which the hard random number clock signal is output from the hard random number clock circuit 900.

  When the output state from the hard random number clock circuit 900 falls from the HI level to the LOW level, the state where the HI level signal is input to the gate is predetermined due to the discharge effect of the charge stored in the capacitor 613. Only for a period of time. That is, a clock signal having a pulse width different from the pulse width of the hard random number clock signal is input to the gate. Then, a shift occurs between a period in which the HI level signal is input to the gate and a period in which the HI level signal is input to the anode. Thus, a clock signal having a plurality of types of pulse widths and a plurality of types of output intervals is output from the thyristor 1102 to the MPU 311. In this case, since the big hit random number counter C1 is updated based on the input of the clock signal, the update interval of the big hit random number counter C1 fluctuates. Therefore, it is more difficult to specify the timing at which the value of the jackpot random number counter C1 becomes the winning value. In this case, the electrostatic capacitance of the capacitor 613 and the resistance value of the resistor 614 may be set so that the clock signal input to the gate and the clock signal for hard random number are not synchronized.

  According to the present embodiment described above, the clock signal transfer circuit 1101 for transferring the hard random number clock signal is provided on the path connecting the hard random number clock circuit 900 and the MPU 311. The clock signal transfer circuit 1101 outputs a clock signal corresponding to the hard random number clock signal to the MPU 311 based on the fact that the hard random number clock signal is input from the hard random number clock circuit 900 and also outputs a hard random number. The period from the input timing of the clock signal to the output timing of the corresponding clock signal is varied according to the input timing. As a result, the period from the output timing of the hard random number clock signal to the input timing when the clock signal corresponding to the hard random number clock signal is input to the MPU 311 is irregular. Therefore, it is possible to suppress the fraudulent acts due to the “hanging board” and the like. That is, in the fifteenth embodiment, the target to be irregularly delayed is "the period from when the pachinko machine 10 is turned on to when the operating power is supplied to the hard random number clock circuit 900". On the other hand, in the present embodiment, the target to be irregularly delayed is that the clock signal corresponding to the hard random number clock signal after the hard random number clock signal is output from the hard random number clock circuit 900 is the MPU 311 It is "period until it is input to".

<Other Embodiments>
In addition, it is not limited to the description content of embodiment mentioned above, For example, you may implement as follows. Incidentally, the following configurations may be applied to the configuration of the above embodiment alone, or may be applied to the configuration of the above embodiment in a predetermined combination. In addition, the following configurations may be applied to an embodiment that is not illustrated as an application target of the configuration.

  (1) In the first to fourth embodiments, it is determined whether the winning value of the big hit random number counter C1 is a predetermined fixed value and whether the value of the big hit random number counter C1 matches the winning value. However, the present invention is not limited thereto. For example, a predetermined predetermined range is set as a winning range out of the range that can be taken by the big hit random number counter C1, and the value of the big hit random number counter C1 is the winning It may be determined whether or not it is within the range. Even in this case, the present invention can be applied.

  The said structure is demonstrated using the flowchart of FIG. FIG. 57 is a flowchart showing a jackpot determination process of determining whether the value of the acquired jackpot random number counter C1 corresponds to the winning value. In the present modification, the numerical range that can be taken by the big hit random number counter C1 is set to “0 to 65535”. Specifically, the counter circuit 317 includes two 8-bit shift registers, and each shift register is updated based on the input of the hard random number clock signal. Then, when the game ball enters the operation port 84, the MPU 311 acquires the information of each shift register, generates the value of the jackpot random number counter C1 from the acquired information, and stores it in the holding ball storage area Do.

  In this case, if the configuration is such that the big hit random number counter C1 is generated by combining the bits of each shift register arbitrarily, the value of the big hit random number counter C1 is hard to be identified from the information of each shift register. Excellent from.

  First, in step S1101, a process of setting a winning value PV is executed. Specifically, the ROM 315 is provided with a storage area in which is stored a success / failure table in which the gaming state and the winning value PV are set in one-to-one correspondence, and by referring to the success / failure table A winning value PV corresponding to the game state of is set. For example, in the definite change state, the winning value PV is set to “1310”, and in the normal state, the winning value PV is set to “655”.

  Thereafter, in step S1102, in the present jackpot determination process, the winning value PV is added to the value of the jackpot random number counter C1 which is the target of the jackpot determination to set a new jackpot random number counter C1.

  In the following step S1103, it is determined whether the value of the new jackpot random number counter C1 updated in step S1102 exceeds "65535". If it is determined in the determination process that the value of the jackpot random number counter C1 does not exceed "65535", it means that the current game result is out. In this case, the outlier information is stored in the outlier information storage area provided in the RAM 316 in step S1104. On the other hand, when it is determined that the value of the jackpot random number counter C1 exceeds “65535”, it means that the present game result is a jackpot winning. In this case, in step S1105, the jackpot winning information is stored in the jackpot winning information storage area provided in the RAM 316.

  Here, if the winning value PV is set to “655”, if the value of the jackpot random number counter C1 is any value within the numerical range of “64881 to 65535”, the jackpot is won. In this case, since the numerical range that can be taken by the jackpot random number counter C1 is “0 to 65535”, the winning probability is about 1/100.

  In addition, if the winning value PV is set to “1310”, the jackpot is won if the value of the jackpot random number counter C1 is any value within the numerical range of “64226 to 65535”. In this case, the winning probability is 1/50.

  From the above, the numerical value of the big hit random number counter C1 which is the big hit is in a predetermined numeric range, and the winning probability is set to the predetermined probability by changing the winning value PV added to the big hit random number counter C1. can do.

  Even with this configuration, by changing the output interval of the hard random number clock signal, the value of the big hit random number counter C1 is the period until the big hit random number counter C1 makes one turn each time the big hit random number counter C1 makes one turn. Since the period in which the winning value is the winning value and the winning probability fluctuate, a jackpot is generated intentionally by outputting a signal illegally in accordance with the period in which the value of the big hit random number counter C1 is the winning value. It is possible to suppress cheating.

  (2) In the first to third embodiments, the frequency conversion circuit 401 is composed of the local oscillation circuit 401a and the mixer circuit 401b. However, the present invention is not limited to this. What is necessary is to convert into an alternating voltage of a fixed frequency, for example, a combination of an AC / DC converter and a DC / AC inverter may be used. In this case, an alternating voltage having a constant frequency can be obtained regardless of the frequency of the alternating voltage input from the commercial power supply. However, focusing on the simplification of the configuration and the viewpoint of the amount of heat generation, the combination of the local oscillation circuit 401a and the mixer circuit 401b is better.

  In addition, for example, as the frequency conversion circuit 401, a 6 × circuit and a 5 × circuit may be provided. In this case, when an alternating voltage of 50 Hz is input, the frequency is converted using a 6-fold circuit, while when an alternating voltage of 60 Hz is input, a frequency is converted using a 5-fold circuit. Make it This makes it possible to obtain an AC voltage of 300 Hz, regardless of which frequency of AC voltage is input.

  (3) In the first to third embodiments, the CR oscillation circuit is used as the local oscillation circuit 401a. However, the present invention is not limited to this. For example, a clapping oscillation circuit may be used. However, when the oscillation frequency is a low frequency, the shape of the coil used in the clapp oscillation circuit becomes large, and therefore, the CR oscillation circuit is superior in terms of space saving.

  Further, a voltage control oscillation circuit (VCO) may be used as the local oscillation circuit 401a. The point is that any oscillation circuit that can change the frequency to be output can be used.

  (4) In the first embodiment, the numerical range of the big hit random number counter C1 is set so that the number of counter terms of the big hit random number counter C1 does not become a multiple of the number of pulse signals included in the pulse signal group. However, the present invention is not limited to this. For example, the numerical range of the jackpot random number counter C1 may be set such that the number of counter terms is a prime number larger than the number of signals. As a result, the degree of freedom of the number of signals can be enhanced, so that even if the number of signals is to be changed temporarily, the change can be easily coped with.

  (5) In the second embodiment, the random number initial value counter CINI is provided as the initial value of the big hit random number counter C1, and the random number initial value counter CINI is updated in the timer interrupt process. For example, instead of the random number initial value counter CINI, a count-up counter may be provided which is incremented by one each time the big hit random number counter C1 makes one revolution. Even in this case, every time the big hit random number counter C1 makes one revolution, a period from when the value of the big hit random number counter C1 becomes the initial value to when it becomes the winning value, and the value of the big hit random number counter C1 becomes the winning value. Since the period in which the value is changed fluctuates, it is difficult to grasp the timing at which the value of the jackpot random number counter C1 becomes the winning value.

  The details of this modification will be described using the flowchart of FIG. The process of step S1201 in FIG. 58 is the same as the process of step S601, the processes of steps S1202 to S1204 are the same as those of steps S603 to S605, and the processes of steps S1206 to S1209 are steps S606 to S606. Since the process is the same as the process of step S609, the description is omitted.

  In this modification, the process of updating the pulse shift counter SC in step S1205 is executed instead of the process of updating the random number initial value counter CINI (the process of step S602 in FIG. 24). It is different. The pulse shift counter SC has a numerical range corresponding to the number of signals, and is added one by one in order within the numerical range each time the update timing is reached, and after reaching the maximum value, returns to "0". There is. Specifically describing the numerical range, when the number of pulse signals included in the pulse signal group is “m”, the numerical range of the pulse shift counter SC is set to “0 to m−1”. The pulse shift counter SC is updated when it is determined that the big hit random number counter C1 has made one revolution.

  According to this configuration, even if it is assumed that the numerical range of the big hit random number counter C1 is "0 to N" and N + 1 = K × m (K: natural number), the round hit number of the big hit random number counter C1 While the initial value fluctuates, the value of the jackpot random number counter C1 corresponding to the pulse signal contained in the pulse signal group fluctuates. Thus, each time the big hit random number counter C1 makes one revolution, a period from when the value of the big hit random number counter C1 becomes the initial value to when it becomes the winning value, and a period when the value of the big hit random number counter C1 becomes the win value Changes.

  Further, when the numerical value range of the number of signals is smaller than the numerical value range of the jackpot random number counter C1 (N> m), the capacity required for the pulse shift counter SC can be reduced compared to the random number initial value counter CINI. Furthermore, while the pulse shift counter SC is updated only when the big hit random number counter C1 makes one revolution, the random number initial value counter CINI is updated each time the timer interrupt process is executed. Thus, the update frequency of the pulse shift counter SC is smaller than the update frequency of the random number initial value counter CINI. Thus, the processing load is reduced.

  However, since the random number initial value counter CINI is superior to the pulse shift counter SC in terms of irregularity, the second embodiment is superior from the viewpoint of fraud suppression.

  (6) In the first to fourth embodiments, the counter circuit 317 is configured to update the big hit random number counter C1 in synchronization with the rise of the pulse signal. However, the present invention is not limited to this. The jackpot random number counter C1 may be updated in synchronization with the falling edge. Further, the counter circuit 317 may be configured to update the big hit random number counter C1 in synchronization with both rising and falling of the pulse signal. In this case, the update frequency of the big hit random number counter C1 is increased and the number of types of update intervals is increased, as compared with the configuration in which the update is performed synchronously with only one of the rising or falling of the pulse signal. Identification can be made more difficult.

  (7) In the second embodiment, although the random number initial value counter CINI is updated in the timer interrupt process, the present invention is not limited to this. For example, the random number initial value counter CINI is updated in the variation counter update process of step S508 in the normal process. It is good also as composition. Thereby, the randomness of the random number initial value counter CINI can be improved.

  Further, the random number initial value counter CINI is not limited to the configuration updated by software processing related to the progress of the game, and for example, a dedicated counter circuit is provided and based on the hard random number clock signal or the system clock signal being input. Alternatively, the random number initial value counter CINI may be updated.

  Furthermore, in this case, a determination circuit that determines whether or not the big hit random number counter C1 has made one turn, and if it is determined by the determination circuit that it has made one turn, the big random number counter C1 is set as the big random number initial value counter CINI at that time. And a circuit for writing as an initial value of. As a result, the jackpot random number counter C1 operates independently without depending on the MPU 311, including the setting of the initial value, so that the value of the jackpot random number counter C1 is identified through software processing, etc. You can suppress the act. However, focusing on the simplification of the configuration, the second embodiment is superior.

  (8) In the first to third embodiments, the specific frequency of the AC voltage output from the frequency conversion circuit 401 is set such that the trigger interval is longer than the cycle of timer interrupt processing. For example, the specific frequency may be set such that the trigger interval is shorter than the cycle of the timer interrupt process. In this case, since the update interval of the big hit random number counter C1 becomes short, the period in which the value of the big hit random number counter C1 becomes the winning value becomes short, and it becomes difficult to output the fraudulent signal in that period.

  However, in the second embodiment, when the specific frequency is set such that the trigger interval is shorter than the cycle of the timer interrupt process, it may not be possible to specify that the jackpot random number counter C1 has made one rotation. In this case, a stop circuit is provided to temporarily stop updating the big hit random number counter C1 when the big hit random number counter C1 makes one rotation, and in the timer interrupt process, updating of the big hit random number counter C1 is stopped by the stop circuit. It is good to judge whether it is. However, since the period which is the value of the jackpot random number counter C1 according to the stop state may be longer than the period when it is other values, pay attention to the aspect of fraud suppression and the viewpoint of stabilization of jackpot probability For example, the specific frequency may be set such that the trigger interval is longer than the period of the timer interrupt process.

  Note that as shown in (7), the determination circuit that determines whether or not the big hit random number counter C1 has made one rotation, and the random number initial value at that time when it is determined by the determination circuit that it has made one rotation. When a circuit for writing the counter CINI as the initial value of the big hit random number counter C1 is separately provided, the specific frequency is set so that the trigger interval becomes shorter than the timer interrupt processing cycle while avoiding the above inconvenience. be able to.

  In the fourth embodiment, the division ratio of the divider circuit 502 may be determined so that the trigger interval is shorter than the cycle of timer interrupt processing.

  (9) In each of the first to third embodiments, the hard random number clock circuit 313 converts the hard random number clock signal by converting the alternating voltage of the commercial power source supplied from the power source and the emission control board 321. However, the present invention is not limited to this. For example, a clock circuit that has a dedicated crystal oscillator and independently outputs a clock signal of a predetermined frequency may be used. In this case, the frequency conversion circuit 401 and the signal conversion circuit 402 become unnecessary. However, in terms of simplification of the configuration and the manufacturing cost, the configuration for converting the AC voltage from the commercial power supply is better.

  (10) In the first to fourth embodiments, the update interval of the big hit random number counter C1 is changed by changing the rising interval of the input pulse signal. However, the present invention is not limited to this. A programmable counter for counting the number of times of signal input may be separately provided, and when the pulse signal is input a predetermined number of times, the big hit random number counter C1 may be updated, and the predetermined number of times may fluctuate. As a result, even if the rise interval of the pulse signal that triggers the update of the big hit random number counter C1 does not change, the update interval of the big hit random number counter C1 can be changed. Therefore, it is difficult to specify the update timing of the jackpot random number counter C1. However, focusing on the simplification of the configuration of the counter circuit 317, the first embodiment is superior.

  (11) In the first to fourth embodiments, the output interval of the pulse signal is modulated to be two types. However, the present invention is not limited to this. For example, three types or four types may be used. As the number of types of output intervals of the pulse signal increases, the number of types of periods in which the big hit random number counter C1 is the winning value and the time required for the big hit random number counter C1 to make one revolution increase. In this case, it is preferable for these periods to sequentially transition each time the jackpot random number counter C1 makes one revolution. This makes it more difficult to specify the update timing of the jackpot random number counter C1. However, focusing on simplification of the configuration of the modulation circuit 314, it is preferable that the number of types of output intervals of pulse signals be small.

  In addition, as a specific configuration for changing the output interval of the pulse signal to three or four types, in addition to the configuration further including a D flip flop and an XOR circuit, a D flip flop having a preset input terminal (PR input terminal) is used. Thus, a configuration may be considered in which a signal is input to the PR input terminal at a predetermined timing.

  Although the D flip flop is used as the modulation circuit 314 for changing the output interval of the pulse signal, the present invention is not limited to this. For example, any of various flip flops such as a JK flip flop may be used. Furthermore, not limited to the XOR circuit, any of various logic circuits such as an AND circuit may be used.

  (12) In the first to fourth embodiments, the big hit random number counter C1 is updated based on the input of the hard random number clock signal. However, the present invention is not limited to this. Based on the above, update of counters other than the jackpot random number counter C1 may be performed.

  (13) In the first to fourth embodiments, the game progress control is performed based on the system clock signal being input, and the jackpot is performed based on the hard random number clock signal being input. Although the configuration is such that updating of the random number counter C1 is performed, the present invention is not limited thereto. For example, in the first mode in which the updating mode of the big hit random number counter C1 is performed based on the input of the system clock signal In the second mode performed based on the input, it may be configured to be alternately switched. This makes it more difficult to specify the update timing of the jackpot random number counter C1.

  Note that, as a specific configuration of these, for example, a configuration in which a switching element for switching between the input of the hard random number clock signal and the input of the system clock signal can be considered.

  (14) Although the modulation circuit 314 is provided in the first to fourth embodiments, the modulation circuit 314 may be omitted. Thereby, simplification of a structure and speeding-up of a process can be achieved.

  Even in this case, since the hard random number clock signal and the system clock signal are set to have different cycles, the cycle of the hard random number clock signal should be specified from the cycle of the system clock signal. Is becoming difficult. This makes it difficult to specify the update timing of the jackpot random number counter C1, so it is possible to make it difficult to specify the timing at which the value of the jackpot random number counter C1 becomes the winning value.

  However, since it is more difficult to identify the update timing of the big hit random number counter C1 in the configuration in which the modulation circuit 314 is provided, the configuration in which the modulation circuit 314 is provided is preferable from the viewpoint of preventing a fraud.

  (15) In the first to fourth embodiments, the counter circuit 317 for updating the big hit random number counter C1 is provided based on the input of the hard random number clock signal. However, the present invention is not limited to this. A program may be provided to update the jackpot random number counter C1 based on the input of the clock signal. In this case, it is preferable that the frequency of the hard random number clock signal is set so that the program operates normally and smooth processing with other processing is performed. As a result, update processing is performed at a predetermined frequency, and in order to synchronize the acquisition processing of the big hit random number counter C1 and the update processing of the big hit random number counter C1, the start timing of the acquisition processing is delayed excessively. Can be avoided.

  In this case, the hard random number clock signal may be a signal output from the modulation circuit 314. As a result, the processing period of the program fluctuates, and as a result, the update interval of the jackpot random number counter C1 fluctuates.

  (16) In the first to fourth embodiments, the counter circuit 317 for updating the big hit random number counter C1 is provided. However, the present invention is not limited to this. For example, the big hit random number counter C1 in timer interrupt processing, normal processing, etc. It may be configured to update the In this case, the update interval of the jackpot random number counter C1 may be varied in software processing. This makes it difficult to specify the update timing of the jackpot random number counter C1.

  In addition, as a specific configuration, a loop counter that is updated whenever the timer interrupt process is executed is separately provided, and when the value of the loop counter is a predetermined value, the jackpot random number counter C1 is updated and the loop counter is updated. A configuration is conceivable in which the predetermined value is varied.

  (17) In the first to third embodiments, the frequency conversion circuit 401 and the modulation circuit 314 are mounted on the main control board 301. However, the present invention is not limited thereto. And may be mounted on the emission control substrate 321. However, it is better to be mounted on the main control board 301 in terms of preventing physical cheating against these.

  (18) In the first to third embodiments, the AC power supply 321d, the frequency conversion circuit 401, and the signal conversion circuit 402 are attached to the pachinko machine 10. However, the present invention is not limited to this. It is good also as composition attached to the exterior of ten.

  (19) In the first to third embodiments described above, the AC power supply unit 321d is provided on the power supply and emission control board 321. However, the present invention is not limited to this. It may be provided independently. However, the configuration in which the AC power supply unit 321 d is integrated into the power supply and emission control substrate 321 is better in terms of simplification of the configuration in the power supply system.

  (20) In the first to third embodiments, the Schmitt trigger 413 is used as the signal conversion circuit 402. However, the present invention is not limited to this. A comparator with the same upper limit threshold voltage and lower limit threshold voltage may be used. The point is that any comparison circuit may be used as long as it compares the input voltage with at least one reference voltage and outputs a signal based on the comparison result. However, a configuration having both the upper threshold voltage and the lower threshold voltage such as the Schmitt trigger 413 is better from the viewpoint of the stability of the output waveform. Although the reference voltage and the input voltage are compared, the signal control may be performed based on the comparison between the reference current and the current actually flowing.

  (21) In the first to third embodiments, the system clock circuit 312, the hard random number clock circuit 313, and the modulation circuit 314 are provided on the main control board 301. However, the present invention is not limited to this. It may be incorporated inside. In this case, these circuits are connected to the ROM 315 and the like through the wiring in the MPU 311.

  Also in the fourth embodiment, the system clock circuit 312, the clock conversion circuit 501, and the modulation circuit 314 may be incorporated in the MPU 311 in the same manner.

  (22) In the first to fourth embodiments, the period in which the jackpot random number counter C1 is the winning value is repeated with “Ta, Tb” as the unit period, but is not limited to this. "Ta, Tb, Tb, Ta" may be repeated as a unit period. Even in this case. The overall winning probability does not change. However, in this case, every time the big hit random number counter C1 makes two rounds, the period in which the big hit random number counter C1 is the winning value fluctuates. For this reason, the first to fourth embodiments in which the period of the winning value fluctuates every time the jackpot random number counter C1 makes one revolution are superior from the viewpoint of fraudulent behavior suppression.

  Note that the same applies to the period required for the big hit random number counter C1 to make one revolution.

  (23) In the fourth embodiment, the divider circuit 502 is used as the frequency conversion means. However, the present invention is not limited to this. For example, a multiplier circuit may be used. Even in this case, since the system clock signal and the hard random number clock signal have different cycles, the effect of the fourth embodiment can be obtained.

  (24) In the first to fourth embodiments, the jackpot random number counter C1 is not updated in a state (power-off state) where the pachinko machine 10 is not powered on. However, the present invention is not limited thereto. The jackpot random number counter C1 may be updated in a situation where it has not been input. As a result, the value of the big hit random number counter C1 fluctuates according to the timing when the power is turned on, so that it is possible to make it difficult to specify the value of the big hit random number counter C1.

  As a specific configuration, it is preferable that operating power be supplied to the hard random number clock circuit 313, the modulation circuit 314, and the counter circuit 317 from the power-off state power supply unit 321c in the power-off state.

  (25) In the first to fourth embodiments, each time the big hit random number counter C1 makes one turn, the period required for the big hit random number counter C1 to make one turn is varied, but the present invention is limited thereto. For example, the period required for the big hit random number counter C1 to make one turn may be changed every time the big hit random number counter C1 makes two turns. The point is that the period required for the jackpot random number counter C1 to make one revolution may be varied, triggered by the one round of the jackpot random number counter C1.

  (26) In the fifth to twelfth embodiments, the reset signal is delayed by the irregular delay circuit 602. However, the present invention is not limited to this. The start timing of the power supply to the MPU 311 may be delayed. Good.

  (27) In the fifth to twelfth embodiments, the MPU 311 operates with the LOW level signal. However, the present invention is not limited to this. The MPU 311 may operate with the HI level signal. In such a case, it is necessary to use an AND circuit instead of the NAND circuit 612. However, the configuration that operates with the LOW level signal is better from the viewpoint of noise suppression.

  (28) In any of the seventh to eleventh embodiments, each D flip-flop is configured to be synchronized with the rising of the pulse signal. However, the present invention is not limited to this, and may be configured to be synchronized with the falling. In such a case, it is necessary to change the input / output of the reset circuit 601 etc. correspondingly. Further, a flip flop synchronized with the rising edge and a flip flop synchronized with the falling edge may be combined. In this way, it is possible to generate pulse signals having different output intervals, as in the eleventh embodiment. Further, it may be configured to be synchronized with both rising and falling. However, it is preferable to have a configuration in which synchronization is made only to the rising or falling, from the viewpoint of the variability of the delay period, because the range of the delay period becomes wider.

  (29) In any one of the seventh to eleventh embodiments, an AC power supply unit 631 for outputting an AC voltage from a commercial power supply to obtain a desired pulse signal, and a signal for converting the AC voltage into a pulse signal. Although the conversion circuit 402 is provided, the invention is not limited to this, and a pulse generation circuit for generating a pulse signal of an oscillation circuit or the like using a quartz oscillator may be provided. However, the configuration provided with the AC power supply unit 631 and the signal conversion circuit 402 is superior in terms of simplification of the configuration because the commercial power supply is used as it is.

  Further, although the AC power supply unit 631 and the signal conversion circuit 402 are attached to the pachinko machine 10, the present invention is not limited to this, and the pachinko machine 10 may be attached to the outside.

  Moreover, although the Schmitt trigger 413 used the thing of the inverter type, it is not restricted to this, You may use the thing of a buffer type.

  (30) In any of the seventh to eleventh embodiments, the AC power supply unit 631 is configured to have the full wave shaping circuit. However, the present invention is not limited to this. May be output as it is.

  (31) In any of the seventh to eleventh embodiments, the pulse signal is a rectangular wave having a predetermined pulse width, but it may be a sawtooth wave, a triangular wave or the like. The shape of the waveform is arbitrary. Also, the pulse signal may be inverted. In such a case, it is necessary to set each D flip flop and logic circuit correspondingly.

  (32) In any one of the seventh to eleventh embodiments, the pulse signal output from the Schmitt trigger 413 of the signal conversion circuit 402 is output regardless of whether the pachinko machine 10 is turned on or off. However, it is not limited to this. For example, at least one of the AC power supply unit 631 and the signal conversion circuit 402 may not be operated. Specifically, power may not be supplied to the Schmitt trigger 413 of the signal conversion circuit 402 under a power-off state, or power may not be supplied to the AC power supply unit 631. Further, power may not be supplied to both the Schmitt trigger 413 and the AC power supply unit 631. In such a case, it is possible to reduce the power consumption in the power-off state of the pachinko machine 10, so it is possible to reduce the charge capacity of the power-off state power supply 321c or to maintain the standby state for a long time. However, when the pachinko machine 10 enters the on state when the AC voltage is equal to or higher than the upper limit threshold voltage of the Schmitt trigger 413, the output of the pulse signal may rise from the LOW level to the HI level simultaneously. Then, since the D flip-flops are synchronized at the same time as the power on state, there is a possibility that delay will not occur. Therefore, in such a case, each D flip-flop may be configured to be synchronized with the switching from the HI level signal to the LOW level signal. Thereby, the above-mentioned inconvenience can be avoided.

  When power is not supplied to AC power supply unit 631 and Schmitt trigger 413 in the power-off state, in the tenth and eleventh embodiments, no pulse signal is output. , 673, and 674, but since the output state in the power-off state is maintained, the effects described in the tenth and eleventh embodiments can be obtained.

  Further, in the tenth embodiment and the eleventh embodiment, the AC power supply unit 631 is configured to always be supplied with power from the commercial power regardless of whether the pachinko machine 10 is turned on or off. However, the present invention is not limited to this, and in the power-off state, power may be supplied from the power-off-time power supply unit 321 c. Even in this case, the effects of the present invention can be exhibited.

  (33) In the eighth embodiment, the D flip flop 651 outputs the signal corresponding to the input state of the signal input to the D1 terminal from the Q1 terminal in synchronization with the rise of the pulse signal. A pulse signal delay unit may be further provided which outputs the pulse signal with a delay of a predetermined period after the pulse signal is input. Specifically, a pulse signal delay means is provided on a path connecting the Schmitt trigger 413 and the D flip flop 651, and the pulse signal output from the Schmitt trigger 413 is transmitted to the D flip flop 651 via the pulse signal delay means. It is preferable that the signal be input to the CLK terminal.

  As the pulse signal delay means, for example, the integration circuit described in the fifth embodiment can be considered. Further, a monostable multivibrator may be provided instead of the integration circuit. In such a case, it is necessary to provide an electrical path for electrically connecting the monostable multivibrator and the disconnection monitoring substrate 302 and to separately provide an integrating circuit on the electrical path. The monostable multivibrator has an A terminal as an input terminal, and has a positive logic output terminal (Q terminal) and a negative logic output terminal (Q bar terminal) as output terminals. The output terminal of the Schmitt trigger 413 may be connected to the A terminal, and the CLK terminal of the D flip flop 651 may be connected to the Q bar terminal. According to this configuration, when the pulse signal is input to the monostable multivibrator, that is, when the signal input to the A terminal rises from the LOW level to the HI level, the signal is output from the Q bar terminal with a delay of a predetermined period. Signal goes from low level to high level. Thus, the timing at which the D flip flop 651 synchronizes with the rising of the pulse signal is delayed. Therefore, it is difficult to grasp the output timing of the LOW level signal from the NAND circuit 612.

  Here, since the D flip flop 651 is configured to be synchronized with the rising of the signal input to the CLK terminal, that is, the abrupt change of the input voltage, it may not be synchronized with the gradual change of the input voltage. Then, there is a possibility that the D flip flop 651 may not synchronize in the delay due to the gradual voltage change of the integration circuit. On the other hand, in the case of a monostable multivibrator, the D flip-flop 651 is likely to be synchronized because the output signal is switched from LOW level to HI level immediately after a predetermined period has elapsed since the input of the pulse signal. Therefore, the D flip flop 651 can be preferably synchronized while delaying the pulse signal. That is, the monostable multivibrator has a function of delaying and outputting a pulse signal having an edge that can be synchronized by the D flip flop 651 to the D flip flop 651 as the transition means based on the input of the pulse signal. In addition, since the monostable multivibrator uses an integration circuit, the delay time due to the monostable multivibrator also varies depending on the residual charge amount. It is possible to prevent fraudulently using the "hanging board" more preferably.

  This configuration may be applied to the above ninth to eleventh embodiments. In such a case, a monostable multivibrator as a pulse signal delay means is provided on the path connecting the modulation circuit 662 and the first D flip flop 661 or on the path connecting the modulation circuit 671 and the first D flip flop 661. It is good.

  (34) In the eighth embodiment described above, the Schmitt trigger 413 is configured to operate even when the pachinko machine 10 is disconnected, but the present invention is not limited to this. For example, when the pachinko machine 10 is in the power-off state, no operating power is supplied to the Schmitt trigger 413, and the operation start timing of the Schmitt trigger 413 and the output start timing of the reset signal from the reset circuit 601 are shifted. With the configuration, the same operation and effect as those of the eighth embodiment can be obtained.

  (35) In the fifth to twelfth embodiments, the reset circuit 601 and the irregular delay circuit 602 receive the supply of the operating power from the power supply and the firing control board 321 via the power failure monitoring board 302, The present invention is not limited to this, and the reset circuit 601 and the irregular delay circuit 602 may be directly connected to the power supply and emission control substrate 321 to receive power supply.

  In addition, although the power failure monitoring substrate 302 and the main control substrate 301 are separately provided, the present invention is not limited to this. For example, the power failure monitoring circuit 632 mounted on the power failure monitoring substrate 302 It may be configured to be mounted on 301.

  (36) In the fifth to seventeenth embodiments, the irregular delay circuit 602 is mounted on the main control board 301, but the present invention is not limited to this. For example, the irregular delay circuit 602 may be provided on the disconnection monitoring substrate 302. Further, the configuration may be provided on the power supply and the emission control substrate 321 or the like. However, the configuration mounted on the main control substrate 301 is better from the viewpoint of simplification of the configuration because it is not necessary to separately provide a wiring or the like. Further, the main control substrate 301 is accommodated in the substrate box 163, and the substrate box 163 is fixed by the sealing unit 164 in an unopenable or difficult state. Therefore, by mounting the irregular delay circuit 602 on the main control substrate 301, it is possible to prevent the fraudulent action on the irregular delay circuit 602.

  (37) In the fifth embodiment or the sixth embodiment, one capacitor 613 is connected in parallel to the resistor 614. However, the present invention is not limited to this. A plurality of capacitors having different electrostatic capacitances may be used. It may be configured to be connected in parallel. In this case, a switch may be provided on the path connecting the respective capacitors 613 and the resistor 614. As a result, since the capacitance changes due to the on / off control of the switch, the charge period and the discharge period change. Then, since the delay period fluctuates, it is possible to make the delay period irregular more suitably. Therefore, it is possible to make it difficult to grasp the timing of winning a big hit. Note that a plurality of capacitors having the same capacitance may be connected in parallel. In such a case, it is preferable to execute on / off control of the switch so as to change the combined capacitance.

  (38) In any of the fifth to ninth embodiments, the power supply and discharge control substrate 321 is provided with the power supply unit 321c for power interruption, and in the power interruption state of the pachinko machine 10, the power supply unit for power interruption 321c. Although the configuration is such that the storage holding power is supplied to the RAM 316 of the main control board 301, the present invention is not limited to this, and the power supply unit for power interruption 321c may be omitted. In this case, the RAM data is erased each time the pachinko machine 10 is turned off, and the RAM data initialization process is executed each time the pachinko machine 10 is turned on. Even in this case, the effects of the present invention can be exhibited.

  (39) In the fifth to eleventh embodiments described above, the signal line LN3 connecting the reset circuit 601 and the NAND circuit 612 and the signal line LN4 are provided. However, the present invention is not limited to this. It is also good. However, in this case, since the output timing of the HI level signal from the NAND circuit 612 is delayed with respect to the timing when the power is cut off, the fifth to eleventh embodiments are performed from the viewpoint of rapid drop processing of the MPU 311. Embodiment is better.

  (40) In the twelfth embodiment, although the value of the initial value random number counter CF is constantly updated regardless of whether the pachinko machine 10 is turned on or off, the present invention is not limited to this. It may be configured to update only to the on state. In such a case, it is preferable to separately provide storage means for storing the value of the initial value random number counter CF in the power-off state, and read out the value stored in the storage means in the initial value setting process. Even in this configuration, since the value of the initial value random number counter CF fluctuates according to the timing when the power is cut off, the initial value of the jackpot random number counter C1 set in the initial value setting process fluctuates It will be done. Thereby, the same effect as that of the twelfth embodiment can be obtained. However, when the value of the initial value random number counter CF is constantly updated, the value of the initial value random number counter CF is hard to be grasped as compared to the configuration in which the value of the initial value random number counter CF is stored. It is excellent from the viewpoint of prevention of fraudulent activity using a hanging board or the like.

  (41) Although the update frequency of the values of the initial value random number counter CF and the big hit random number counter C1 is different in the twelfth embodiment, the present invention is not limited thereto. For example, update of the value of the initial value random number counter CF The interval and the update interval of the value of the jackpot random number counter C1 may be different. Specifically, the counter updating circuit 701 is provided with two circuits each outputting a pulse signal at different cycles, and the value of the big hit random number counter C1 is a pulse signal output from one of the two circuits. Synchronously, the values are sequentially added one by one within the range of 0 to 676 and return to 0 after reaching the maximum value (that is, 676), while the value of the initial value random number counter CF is output from other circuits In synchronism with the pulse signal, similarly to the large hit random number counter C1, one may be sequentially added one by one within the range of 0 to 676 and returned to zero after reaching the maximum value (that is, 676). As a result, since the cycle of the pulse signal synchronized with the big hit random number counter C1 is different from the cycle of the pulse signal synchronized with the initial value random number counter CF, the update interval of the value of the big hit random number counter C1 and the random number for the initial value The update interval of the value of the counter CF will be different. Even in this case, the initial value random number counter CF and the big hit random number counter C1 can be prevented from being completely synchronized.

  (42) In the twelfth embodiment, the irregular delay circuit 602 is provided on the path connecting the reset circuit 601 and the MPU 311. However, the present invention is not limited to this. For example, the irregular delay circuit 602 is not provided. It is also good. Even with this configuration, since the value of the initial value random number counter CF is constantly updated, the initial value of the jackpot random number counter C1 acquired in the initial value setting process fluctuates according to the acquisition timing. As a result, since it is difficult to grasp the initial value of the jackpot random number counter C1, it is possible to suppress fraudulent acts using a "hanging board" or the like.

  Further, in this case, a storage area storing different fixed values (for example, serial numbers) for each pachinko machine 10 is further provided, and in the initial value setting process, initial values based on the value of the initial value random number counter CF and the fixed values. May be set. Thereby, identification of the initial value can be made difficult, and the initial value set for each pachinko machine 10 will be different. Therefore, it is possible to more preferably suppress fraudulent acts using the “hanging board” or the like.

  (43) In the twelfth embodiment, although the initial value random number counter CF is also used as the random number initial value counter CINI, the present invention is not limited to this, and may be provided. However, the twelfth embodiment is preferable from the viewpoint of processing load, manufacturing cost, and space saving.

  (44) In the twelfth embodiment described above, the initial value random number counter CF is provided to determine the initial value of the big hit random number counter C1 when the power is turned on. However, the present invention is not limited to this. For example, instead of the initial value random number counter CF, a timer counter circuit may be separately provided. Then, the timer counter starts operation (updating) based on the output of the reset signal from the reset circuit 601, and the initial value of the big hit random number counter C1 based on the value of the timer counter at the timing when the reset signal is input to the MPU 311 The configuration may be determined. In this case, since the period from the output timing of the reset signal from the reset circuit 601 to the input timing to the MPU 311 fluctuates by the irregular delay circuit 602, the timing at which the reset signal is output is temporarily grasped by the "hanging board" or the like. Even in the case where it is determined, it is difficult to grasp the value of the timer counter. Therefore, since it becomes difficult to grasp the initial value of big hit random number counter C1 determined based on the value of a timer counter, it can be made difficult to grasp the timing when the value of big hit random number counter C1 becomes a winning value. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like. In this case, any of the irregular delay circuits 602 of the fifth to eleventh embodiments may be applied. The initial value information used as the initial value may be a parameter that changes according to the period from the output timing of the reset signal to the execution timing of the initial value setting process.

  (45) In the twelfth embodiment, the counter updating circuit 701 having the big hit random number counter C1 and the initial value random number counter CF is provided. However, the present invention is not limited thereto. Counter updating with the initial value random number counter CF The circuit 701 may be provided, and the jackpot random number counter C1 may be provided as a part of the RAM 316. In this case, it is preferable that the value of the initial value random number counter CF be constantly updated. The value of the big hit random number counter C1 is updated when the MPU 311 is operating, and the counter updating circuit is executed when the initial value setting processing is executed or when the value of the big hit random number counter C1 makes one turn. It is preferable that the initial value random number counter CF 701 is read. In this configuration as well, the same effects as those of the twelfth embodiment can be obtained, and the configuration of the counter update circuit 701 can be simplified.

  Furthermore, both the big hit random number counter C1 and the initial value random number counter CF may be provided as part of the RAM 316. In this case, the value of the initial value random number counter CF is updated under the situation where the MPU 311 is operating, and is held under the situation where the MPU 311 is not operating. It is preferable that the initial value random number counter CF be excluded from the target of conversion. As a result, the value of the initial value random number counter CF is not affected by the initialization process and fluctuates according to the timing when the MPU 311 stops its operation, so the initial value of the jackpot random number counter C1 after the initialization process Fluctuations in value are secured.

  (46) In the thirteenth embodiment, the execution timing of the initialization process of the RAM data is delayed by the irregular delay circuit 602 with respect to the output timing of the RAM erase signal. However, the present invention is not limited to this. The output timing of the RAM erase signal of the RAM erase signal output circuit 802 may be delayed by the irregular delay circuit 602 with respect to the operation timing of the RAM erase switch 801 during power on. Specifically, an operation signal output circuit is provided which outputs a signal notifying that effect by the operation of the RAM erase switch 801 during power on, and the RAM erase signal output circuit 802 receives the operation signal. Based on this, the RAM erase signal is output. In such a configuration, the irregular delay circuit 602 is provided on the path connecting the operation signal output circuit and the RAM erase signal output circuit 802. Even in this case, the same effect as that of the thirteenth embodiment can be obtained. In this case, the irregular delay circuit 602 may be provided between both the operation signal output circuit and the RAM erase signal output circuit 802 and between the RAM erase signal output circuit 802 and the MPU 311.

  The random delay circuit 602 may be mounted on the RAM erase signal output circuit 802, and the output timing of the RAM erase signal may be delayed with respect to the input timing of the operation signal by the irregular delay circuit 602. The point is that the period from the operation of the RAM erase switch 801 during power on to the initialization of the RAM data may be varied.

  (47) In the fifth to eleventh embodiments, the value of the jackpot random number counter C1 is updated when the pachinko machine 10 is in the ON state, and is not updated when the pachinko machine 10 is in the OFF state. Although the configuration is described, the present invention is not limited to this, and the configuration may be such that the value of the jackpot random number counter C1 is updated even in the power-off state.

  (48) In the fifth to twelfth embodiments described above, the hardware as the irregular delay circuit 602 is provided in which the operation start timing of the MPU 311 is varied with respect to the output timing of the reset signal. The timing at which the value of the jackpot random number counter C1 becomes the winning value may be varied in software processing. For example, a waveform grasping circuit for grasping an AC waveform from a commercial power supply is provided, and a process for grasping the waveform by the waveform grasping circuit is provided after the process of initializing the RAM in step S409 of the main process of the MPU 311 (FIG. 19). When the alternating current waveform exceeds a predetermined threshold value, processing may be performed to set the interrupt permission. In this case, it is preferable to provide a changing means for changing a predetermined threshold. Also in this configuration, it is possible to make it difficult to grasp the timing when the jackpot random number counter C1 starts updating. The point is that the execution timing of at least one process may be changed during a plurality of processes from when the pachinko machine 10 is turned on until the value of the jackpot random number counter C1 becomes the winning value. The specific content of the process for changing the timing is optional, and the changing means is not limited to hardware but may be software.

  (49) The output timing of the reset signal in the fifth to twelfth embodiments, the output timing of the RAM erase signal in the thirteenth to fourteenth embodiments, the application timing of the operating voltage Vcc in the fifteenth embodiment, the sixteenth In the seventeenth embodiment, the update start timing of the big hit random number counter C1 with respect to the output timing of the data erase signal is changed, but the invention is not limited thereto. Any configuration may be used as long as the start timing is varied.

  (50) In the fifteenth and sixteenth embodiments, the counter value of the big hit random number counter C1 is not held when the pachinko machine 10 is switched off, and the pachinko machine 10 Although the present invention is configured to be reset to a predetermined value when it enters the on state, the present invention is not limited to this. When the pachinko machine 10 enters the power-off state, the counter value of the big hit random number counter C1 at that time is held It is good also as composition. In this case, in the start-up process executed when the pachinko machine 10 is in the power-on state, the value of the jackpot random number counter C1 may be excluded from being reset. As a result, since it is difficult to grasp the counter value of the jackpot random number counter C1 when the pachinko machine 10 is in the power-on state, it is possible to suppress fraudulent acts using the “hanging board” or the like more suitably.

  As a specific configuration for realizing the above configuration, a flash memory is provided in at least a part of the ROM 315, an update program for the flash memory is provided, and the update of the jackpot random number counter C1 is performed using the flash memory. The configuration to be implemented is conceivable.

  (51) In the fifteenth and sixteenth embodiments, the big hit random number counter C1 is provided in the ROM 315. However, the present invention is not limited to this, and may be provided in the RAM 316. In this case, it is necessary to set the circuit for updating the jackpot random number counter C1 not to be synchronized with the system clock signal. In such a configuration, while the pachinko machine 10 is in the power-off state, backup power is supplied to the RAM 316 so as to hold the counter value of the big hit random number counter C1. In the raising process, the value of the jackpot random number counter C1 may be excluded from the reset target.

  (52) In the seventeenth embodiment, the clock signal transfer circuit 1101 is provided on the path connecting the hard random number clock circuit 900 and the MPU 311. However, the present invention is not limited to this. For example, as shown in FIG. The system clock circuit 312 and the MPU 311 may be connected via the two signal lines LN9 and LN10, and the clock signal transfer circuit 1101 may be provided only on one of the signal lines LN10. In this case, the signal line LN11 connecting the system clock circuit 312 and the clock signal transfer circuit 1101 is provided separately from the signal line LN10, and the system clock circuit 312 is provided for each of the three signal lines LN9, LN10 and LN11. The clock signal is output. According to this configuration, the clock signal transmission circuit 1101 is disposed using the clock signal input to the MPU 311 via the signal line LN9 not provided with the clock signal transmission circuit 1101 as the system clock signal. By using the clock signal input to the MPU 311 as a clock signal for hard random numbers through the above, the configuration can be simplified without interfering with the progress of the game.

  In particular, in the configuration for obtaining the hard random number clock signal by converting the system clock signal, the fifteenth or sixteenth embodiment is shown on the power line connecting the system clock circuit 312 and the disconnection monitoring board 302. When the power transfer circuit 901 is provided, the input of the system clock signal to the MPU 311 is also delayed, which may hinder the progress of the game. On the other hand, with the above configuration, only the input of the update clock signal to the MPU 311 is irregularly delayed, while the input of the game clock signal to the MPU 311 is not delayed. That is, the inconvenience caused by the configuration in which the hard random number clock signal is obtained by converting the system clock signal is avoided.

  However, in this case, since the cycle of the system clock signal and the cycle of the hard random number clock signal become the same, by grasping the cycle of the system clock signal, the cycle of update timing of the big hit random number counter C1 can be grasped. There is a case. To address this, the clock signal transfer circuit 1101 may be provided with a circuit that modulates the cycle of the clock signal.

  (53) Although the clock signal is input to the gate of the thyristor 1102 in the seventeenth embodiment, the present invention is not limited to this, and a constant HI level signal may be output. Even with this configuration, the period from the output timing of the hard random number clock signal from the hard random number clock circuit 900 to the input timing of the signal to the MPU 311 becomes irregular. As a configuration for outputting a constant HI level signal, a circuit for converting a hard random number clock signal into an HI level signal is provided on signal line LN 8 connecting hard random number clock circuit 900 and irregular delay circuit 602. A configuration provided is conceivable.

  Further, the clock signal transfer circuit 1101 is not limited to the thyristor 1102, and for example, the hard random number clock circuit 900 and the MPU 311 are connected, and switches (for example, piezo elements) are provided on signal lines transmitting the hard random number clock signal. When the operation signal delayed from the irregular delay circuit 602 is input, the switch may be set to be in the ON state. However, the seventeenth embodiment is superior in that a clock signal having a plurality of types of output intervals is output.

  Furthermore, in the seventeenth embodiment, although the one in the fifth embodiment is used as the irregular delay circuit 602, the present invention is not limited to this, and any configuration in the sixth to eleventh embodiments may be applied. .

  (54) In the fifteenth and sixteenth embodiments, in each of the transistors 913 and 914 of the amplifier circuit 912, the bypass wiring for connecting the gate and the emitter is provided, and the resistors 913b and 914b are provided. May be omitted. In this case, since the amplification factor of each of the transistors 913 and 914 is improved, the operating voltage Vcc can be lowered while securing the operating power of the hard random number clock circuit 900. However, focusing on the stability of the circuit, the fifteenth and sixteenth embodiments are superior.

  (55) Although the amplification circuit 912 is provided in the fifteenth and sixteenth embodiments, the present invention is not limited to this. The power supply and emission control board 321 and the clock circuit 900 for hard random numbers are not provided without the amplification circuit 912. , And the output of the AND circuit 916 may be directly input to the hard random number clock circuit 900. In this case, the operating voltage Vcc needs to be a high voltage, and the resistance value of the adjustment resistor 911 needs to be changed. However, the configuration in which the amplifier circuit 912 is provided is superior from the viewpoint of circuit loss and circuit deterioration.

  Although the NPN transistor 913 and the PNP transistor 914 are connected in an inverted Darlington connection, the present invention is not limited to this, as long as the output current from the irregular delay circuit 602 is amplified. For example, two NPN transistors may be connected in Darlington connection. In this case, the amplifier circuit 912 operates more stably than in the inverted Darlington connection. However, since the inverted Darlington connection has less loss voltage in the amplifier circuit 912, it is better from the viewpoint of reducing the operating voltage Vcc.

  (56) In the fifteenth and sixteenth embodiments, the D flip flop 915 is used as the irregular delay circuit 602. However, the present invention is not limited to this, and any of the fifth to eleventh embodiments may be used. . In this case, the NAND circuit 612 is replaced with an AND circuit 916.

  Further, the AND circuit 916 may not be provided. Even in this case, when the application of the operating voltage Vcc from the power supply and emission control board 321 is stopped, the application of the voltage between the collector and the emitter of the amplifier circuit 912 is stopped, so the operation to the hard random number clock circuit 900. Power supply stops. Thereby, the configuration can be simplified. However, focusing on the viewpoint of preventing malfunction of the amplifier circuit 912, the configuration provided with the AND circuit 916 is better.

  (57) In the sixteenth embodiment, the power transfer circuit 901 is provided with the irregular delay circuit 602. However, the present invention is not limited to this. For example, a path connecting the data erase signal output circuit 1002 and the reset transistor 1003 The irregular delay circuit 602 may be provided on the upper side. In this case, the timing at which the HI level signal is input to the power transfer circuit 901 is irregularly delayed with respect to the timing at which the output of the HI level signal from the data erase signal output circuit 1002 is resumed. That is, an object to be irregularly delayed is "a period from the output timing of the HI level signal from the data erase signal output circuit 1002 to the input timing of the HI level signal to the power transfer circuit 901". Thereby, the supply start timing of the operation power to the hard random number clock circuit 900 is irregularly delayed with respect to the operation timing of the data erase switch 1001. Therefore, since it becomes difficult to specify the output timing of the hard random number clock signal from the operation timing of the data erase switch 1001, it is difficult to grasp the update timing of the big hit random number counter C1. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like.

  (58) In the sixteenth embodiment, the specific stop period Ts is a predetermined period. However, the present invention is not limited to this, and the specific stop period Ts may be varied. According to this configuration, since the irregular delay circuit 602 can be omitted from the power transfer circuit 901, the configuration can be simplified. However, the specific stop period Ts is preferably at least longer than the period T3 of the pulse signal output from the Schmitt trigger 413, and under such conditions, if the specific stop period Ts is varied, the range of the varied period may be narrowed. In addition, the construction of the system will be complicated. Focusing on these points, the sixteenth embodiment is preferable.

  Note that, as a specific configuration for changing the specific stop period Ts, a configuration using an integration circuit of a monostable multivibrator can be considered.

  (59) In the sixteenth embodiment, the specific stop period Ts is at least longer than the period T3 of the pulse signal output from the Schmitt trigger 413. However, the present invention is not limited thereto. For example, the clear terminal of the D flip flop 915 The D flip flop 915 may be reset using In this case, the clear terminal and the data erase signal output circuit 1002 are electrically connected. According to this configuration, the D flip flop 915 is reset based on the fact that the LOW level signal is input from the data erase signal output circuit 1002 to the clear terminal, and the LOW level signal is output from the Q terminal. As a result, the D flip flop 915 can be reliably reset. Therefore, the specific stop period Ts can be omitted. Further, in this case, the D flip flop 915 can be reset without waiting for the input of the pulse signal, so that the AND circuit 916 can be omitted.

  (60) In the sixteenth embodiment, the reset transistor 1003 is provided, and the data erase signal output circuit 1002 generates the HI level signal to the gate of the reset transistor 1003 in a state where the pachinko machine 10 is in the on state. While the data erase switch 1001 is operated, the low level signal is once output and then the HI level signal is output again. However, the present invention is not limited to this. For example, instead of the reset transistor 1003. An inverter circuit (inversion circuit) may be provided to electrically connect the input terminal of the inverter circuit to the data erasing signal output circuit 1002. In this case, the data erase signal output circuit 1002 outputs a LOW level signal to the inverter circuit in a state where the pachinko machine 10 is in the power-on state and the Schmitt trigger when the data erase switch 1001 is operated. It is preferable that a one-shot pulse having a pulse width larger than the period T3 of the pulse signal output from 413 is output.

  According to such a configuration, the inverter circuit outputs the HI level signal (operating voltage) to the irregular delay circuit 602 and the amplifier circuit 912 in the situation where the LOW level signal is input from the data erase signal output circuit 1002. On the other hand, when the HI level signal is input from the data erase signal output circuit 1002, the LOW level signal is output to the irregular delay circuit 602 and the amplifier circuit 912. Then, the LOW level signal is output to the irregular delay circuit 602 and the amplifier circuit 912 based on the input of the one-shot pulse. In this case, since the voltage is not applied between the collector and the emitter of the PNP transistor 914 of the amplification circuit 912 and the irregular delay circuit 602 outputs a low level signal to the amplification circuit 912, the operation of the amplification circuit 912 Will stop. Thereby, the supply of operating power to the hard random number clock circuit 900 is temporarily stopped.

  Here, since the pulse width of the one-shot pulse is set larger than the period T3 of the pulse signal output from the Schmitt trigger 413, the D flip-flop is performed at least once in the state where the one-shot pulse is input. 915 synchronizes. In this case, since the LOW level signal is input to the D terminal, the LOW level signal is output from the Q terminal, and the LOW level state is maintained.

  After that, the HI level signal (operating voltage) is output to the irregular delay circuit 602 and the amplifier circuit 912 based on the completion of the input of the one-shot pulse (the input signal changes from HI level to LOW level). As a result, the supply of operating power to the hard random number clock circuit 900 is resumed. In this case, the irregular delay circuit 602 irregularly delays the supply start timing of the operating power to the hard random number clock circuit 900 with respect to the timing when the input of the one-shot pulse ends. Therefore, the same effect as the sixteenth embodiment can be obtained.

  In addition, as an inverter circuit, what was comprised by the NPN transistor, a CMOS inverter circuit, etc. are arbitrary.

  (61) In the sixteenth embodiment, the reset transistor 1003 may be provided only on the path connecting the irregular delay circuit 602 and the power supply and emission control board 321. In this case, the voltage applied to the amplifier circuit 912 is higher than that in the sixteenth embodiment by the voltage drop by the reset transistor 1003. Therefore, the circuit loss is reduced and the operating voltage Vcc is lowered. Can be Even in this case, when the LOW level signal is output from data erase signal output circuit 1002, the LOW level signal is immediately input to one of the input terminals of AND circuit 916. Power supply to the clock circuit 900 is immediately stopped. Therefore, a quick drop is secured. However, from the viewpoint of preventing malfunction of the amplification circuit 912, the sixteenth embodiment is superior.

  (62) In the fifteenth embodiment, the hard random number clock circuit 900 outputs the hard random number clock signal by being supplied with operating power. However, the present invention is not limited to this. For example, the reset circuit 601 And the hard random number clock circuit 900 is connected to the hard random number clock circuit 900. When the operating power is supplied to the hard random number clock circuit 900 and the reset signal is input from the reset circuit 601, It may be configured to output a clock signal for random numbers. In this case, the irregular delay circuit 602 may be provided on the path connecting the hard random number clock circuit 900 and the reset circuit 601.

  (63) Other types of pachinko machines and the like different from the above embodiments, for example, pachinko machines in which a motorized role opens a predetermined number of times when gaming balls enter a specific area of a special device The present invention can be applied to gaming machines such as pachinko machines, pachinko machines equipped with other features, arrange ball machines, ball balls, etc., in which a right is generated and a jackpot is generated.

  A non-ball-ball type game machine, for example, a plurality of reels having a plurality of kinds of symbols attached in the circumferential direction, starts the rotation of the reels by inserting medals and operating the start lever, and the stop switch is operated. Alternatively, after the reel is stopped after the predetermined period has elapsed, the player is given a privilege such as the payout of medals if a specific symbol or a combination of specific symbols is established on an effective line visible through the display window. The present invention is also applicable to slot machines.

  A pachinko machine and slot machine including a loading device and starting rotation of the reel by operating the start lever after a predetermined number of gaming balls stored in the storage unit are loaded by the loading device. The present invention can also be applied to a gaming machine in which is integrated.

<About the invention group extracted from the above embodiment>
Hereinafter, the features of the invention group extracted from the above-described embodiment will be described while showing effects and the like as necessary. In the following, for ease of understanding, the corresponding configuration in the above embodiment is appropriately shown in parentheses or the like, but the present invention is not limited to the specific configuration illustrated in the parentheses or the like.

Features A1. Numerical information updating means (counter circuit 317) for sequentially updating numerical information within a predetermined numerical range each time an update timing is reached,
Acquisition means for acquiring the numerical information from the numerical information update means when a predetermined acquisition condition is satisfied (a function for executing the processing of step S305 and step S307 in the MPU 311);
Equipped with
In a gaming machine which is in a specific state based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined specific information,
A game machine characterized by comprising variation means (a modulation circuit 314) for varying an interval updated from one numerical information to the next.

  According to the feature A1, since the update interval changes, it is difficult to grasp the update timing of the numerical information. As a result, it is difficult to specify the timing at which the numerical information becomes the specific information. Therefore, for example, it is possible to suppress the fraudulent act of causing the specific state to occur deliberately by establishing the acquisition condition illegally in accordance with the timing when the numerical information becomes the specific information.

  Further, according to the change of the update interval, the period in which the numerical information is the specific information and the period required for one round of the numerical information may change. Thus, for example, by adjusting the update interval, it is possible to adjust the actual winning probability derived from the ratio of the period in which the numerical information is the specific information to the period required for one round of the numerical information. Therefore, by changing the update interval, the actual winning probability can be made lower than the numerical range of the numerical information and the theoretical winning probability derived from the specific information. Therefore, since the numerical range of numerical information can be reduced, the capacity required for numerical information can be reduced.

  From the above, the numerical information can be updated well.

  Feature A2. The gaming machine according to feature A1, wherein the variation means varies a time period required for the numerical value information to make one revolution in response to the numerical information making a revolution.

  According to the feature A2, since the period required for one turn of the numerical information fluctuates according to one turn of the numerical information, it is difficult to specify the timing at which the numerical information becomes the initial value. Thus, it is difficult to specify the timing at which the numerical information becomes the specific information from the timing at which the numerical information becomes the initial value. Therefore, it is possible to suppress the fraudulent act of causing the specific state to occur intentionally, by making the acquisition condition illegally met at the timing when the numerical information becomes the specific information.

  Feature A3. The fluctuation means sequentially changes the period required for one round of the numerical information to one of a plurality of types of periods by changing an interval at which one numerical information is updated to the next numerical information. The gaming machine according to the feature A2, characterized in that a unit period having the plurality of types of periods is repeated for each of a plurality of turns of the numerical value information.

  According to the feature A3, since the period required for one round of numerical information transitions sequentially to any of a plurality of types of periods, one round of numerical information causes one round of numerical information. The required period fluctuates. Thereby, the effect of feature A2 is exhibited.

  Here, when the period required for one turn of the numerical information fluctuates, the actual winning probability will fluctuate. For this reason, if the period required for one round of numerical information is made irregular from the viewpoint of preventing fraudulent acts, the range in which the winning probability substantially fluctuates becomes wide, so that the fairness of the game and the management of the game hall Unfavorable from the viewpoint of ease.

  On the other hand, according to this feature, a unit period having a plurality of types of periods is repeated for each of a plurality of rounds of numerical information, so that the substantial winning probability as a whole is a plurality of types of periods included in the unit period. It becomes the average of the substantial winning probability corresponding to each. As a result, each time the numerical information makes one revolution, the time required for the numerical information to make one revolution and the actual winning probability fluctuate, while the substantial winning probability as a whole becomes a constant probability. There is. Therefore, the stability of the game and the ease of management of the game hall are secured while making it difficult to specify the timing when the numerical information becomes the specific information.

  Feature A4. In any one of the features A1 to A3, the changing unit changes the update timing such that the numerical information is updated at a plurality of types of update intervals within the numerical value range. Of gaming machines.

  According to the feature A4, since the update of numerical information is performed at a plurality of types of update intervals within the numerical range, the update timing of the numerical information fluctuates. This makes it difficult to specify the update timing of the numerical information, and thus makes it difficult to specify the timing at which the numerical information becomes specific information. Therefore, it is possible to suppress the fraudulent act of intentionally generating the specific state by making the acquisition condition illegally met in accordance with the timing when the numerical information becomes the specific information.

  Feature A5. In any one of the features A1 to A4, the variation means is configured to vary a period in which the numerical value information is the specific information in response to one round of the numerical value information. Of gaming machines.

  According to the feature A5, the period in which the numerical information is the specific information fluctuates in response to one round of the numerical information. This makes it difficult to identify the period in which the numerical information is the specific information. Therefore, it is possible to suppress the fraudulent act of establishing the acquisition condition illegally in accordance with the timing when the numerical information is the specific information.

  Feature A6. The variation means causes a period in which the numerical value information becomes the specific information to sequentially transition to any of a plurality of types of periods, and a unit period required for the plurality of specific values of the numerical information to circulate The gaming machine according to the feature A5, wherein a ratio of a period during which the numerical value information is the specific information is the same or substantially the same for each unit period.

  According to the feature A6, a period in which numerical information is specific information sequentially transitions to any of a plurality of types of periods. As a result, since the period in which the numerical information is the specific information fluctuates in response to one round of the numerical information, the effect of the feature A5 is exhibited.

  Here, when the period in which the numerical information is the specific information changes, the actual winning probability changes. For this reason, if the period in which numerical information is specified information is made irregular from the viewpoint of preventing fraudulent acts, the range in which the probability of winning a prize fluctuates becomes wide, so that the fairness of the game and the management of the game hall Unfavorable from the viewpoint of ease.

  On the other hand, according to the present feature, the ratio of the period in which the numerical information is the specific information to the unit period required for the specific plural number of turns of the numerical information is the same or substantially the same for each unit period . Thus, when focusing on the unit period, the substantial winning probability is the same or substantially the same. Therefore, every time the numerical information turns, the period in which the numerical information is the specific information and the actual winning probability fluctuate, while the substantial winning probability as a whole is a fixed probability. . Therefore, the stability of the game and the ease of management of the game hall are secured while making it difficult to specify the period in which the numerical information is the specific information.

Feature A7. The numerical information updating means comprises a plurality of update timings (pulse signals), and the updating of the numerical information in accordance with the update group (pulse signal group) having a plurality of types of update intervals is repeated for each update group. To be
The numerical range and the update timing so that the number of terms (the number of counter terms) of a numerical sequence composed of the numerical values that the numerical information can take can not be a multiple of the number of update timings (the number of signals) included in the update group. The gaming machine according to any one of the features A4 to A6, wherein

  If the number of terms is a multiple of the number of update timings (hereinafter simply referred to as the number of updates) included in the update group, and the numerical information makes one revolution, the update is started from a predetermined initial value. In the case of the configuration, while the update interval of the numerical information fluctuates, the update timing corresponding to the update in which the numerical information becomes the initial value does not change in the update group. Therefore, the period from the timing when the numerical information becomes the initial value to the timing when it becomes the specific information becomes constant, and the period when the numerical information becomes the specific information becomes constant.

  On the other hand, according to the present feature, the numerical range and the update timing of the numerical information are set such that the number of terms is not a multiple of the number of updates. As a result, even if the numerical information is sequentially updated from a fixed value determined in advance every time the numerical information goes around, the update timing corresponding to the update in which the numerical information becomes the initial value fluctuates in the update group. . As a result, the period from the timing when the numerical information becomes the initial value to the timing when the specific information becomes the variation fluctuates, and the period during which the numerical information becomes the identification information fluctuates. Therefore, it is difficult to identify these periods. Therefore, it is difficult to specify the timing at which numerical information is specific information based on these periods.

  In addition, in the update group, in response to the change of the update timing corresponding to the update in which the numerical information becomes the initial value, the substantial probability of winning changes. As a result, each time the numerical information makes one revolution, the actual winning probability fluctuates. On the other hand, since the substantial winning probability as a whole is an average of the winning probabilities as a whole corresponding to each update timing, it does not change. Thereby, the fairness of the game and the ease of management of the game hall are secured.

  The term “number of terms” means, for example, “N + 1” when the numerical value range of numerical information is “0 to N”.

Feature A8. Initial value information updating means for sequentially updating initial value information within a predetermined range (a function for updating the random number initial value counter CINI or the pulse shift counter SC in the MPU 311);
Initial value information acquiring means (function of executing the process of step S606 in the MPU 311) for acquiring the initial value information from the initial value information updating means when the numerical value information makes one rotation;
Equipped with
When the initial value information is acquired, the numerical value information updating unit is configured to update the numerical information from the acquired initial value information, in any one of the features A1 to A7. The gaming machine described.

  According to the feature A8, the initial value information of the initial value information updating means is acquired each time the numerical value information makes one revolution, and the numerical information is updated from the acquired initial value information. The initial value information fluctuates according to the timing of acquisition. Thereby, the period until numerical information becomes specific information fluctuates. Therefore, it is difficult to specify the timing when the numerical information becomes the specific information.

  In addition, even if the number of terms is a multiple of the number of updates, the initial value fluctuates and the numerical information corresponding to the update timing fluctuates in the update group each time the numerical information makes one revolution. As a result, even if the number of terms is a multiple of the number of updates, the period from the timing at which the update serving as the initial value is performed to the timing at which the numerical information becomes the specific information fluctuates. It is difficult to identify the timing of the information. Therefore, even if the number of terms is a multiple of the number of updates, it is difficult to specify the timing when the numerical information becomes the specific information.

  Note that, for example, “within the range of the number of update timings included in the update group” or “within the numerical range of the numerical information” may be considered as “within the predetermined range”.

Feature A9. The numerical value information updating means is configured to repeat the updating of the numerical value information corresponding to the update group having a plurality of update timings and having a plurality of types of update intervals, in the unit of the update group.
The numerical range and the update timing such that the number of terms (the number of counter terms) of a numerical sequence composed of the numerical values that can be acquired by the numerical information is a multiple of the number of update timings (the number of signals) included in the update group. Is set,
Furthermore, the specific information and the update timing are set such that the period in which the numerical information is the specific information does not correspond to the maximum update interval among the update intervals included in the update group. The gaming machine according to the feature A1.

  According to the feature A9, since the number of terms is a multiple of the number of update timings included in the update group, numerical information corresponding to the update timing is constant in the update group. As a result, even when the numerical information turns once, the holding period of each numerical information does not change. In such a case, the period in which the numerical information is the specific information is set not to correspond to the maximum update interval in the update group. Thus, the period in which numerical information is specific information can be made relatively shorter than the period in which other numerical information is used. Thus, the actual winning probability can be smaller than the theoretical probability. Therefore, it is possible to narrow the numerical value range of numerical information required to set a predetermined winning probability. Therefore, the capacity required for numerical information can be reduced.

  In addition, it is preferable that “the specific information and the update timing are set such that a period in which numerical information is the specific information corresponds to the minimum update interval among the update intervals included in the update group”. .

Feature A10. An update signal output unit (hard random number clock circuit 313) for outputting an update clock signal;
The numerical information update means is configured to update the numerical information using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
Any one of the features A1 to A9 characterized in that the variation means varies an interval between a trigger that triggers updating of one numerical information and a trigger that triggers updating of the next numerical information. The gaming machine described in.

  According to the feature A10, since the interval of the trigger that triggers the update of the numerical information fluctuates, the fluctuation of the update interval of the numerical information is realized. This eliminates the need for software processing for changing the update interval, thus reducing the burden of software processing.

  Further, in relation to the feature A4, “the variation means changes at least one of the pulse width or pulse interval of the update clock signal, and outputs a pulse signal group including a plurality of pulse signals as one cycle. Therefore, it is preferable to output pulse signals at a plurality of types of trigger intervals. In this case, for the feature A 7 and the feature A 9, the “update group” is replaced with the “pulse signal group”, and the “update timing” is replaced with the “trigger”.

Characteristics A11. Game signal output means (system clock circuit 312) provided separately from the update signal output means and outputting a game clock signal;
A control unit (a function of executing processing on the progress of the game in the MPU 311) that performs control related to the game based on the input of the game clock signal;
The gaming machine according to feature A10, further comprising:

  According to the feature A11, since the control regarding the game is performed based on the gaming clock signal different from the renewal clock signal, even if the timing of the renewal clock signal fluctuates, the influence of the fluctuation is Control regarding the game is performed without receiving the Thereby, the effect of the feature A10 can be obtained without affecting the control regarding the game.

  The configuration limited by any one of the features B2 to B9 or the features C1 to C3 may be applied to the configuration of the present feature. In this case, further effects can be obtained by applying each configuration.

Feature A12. A first signal path (signal line LN1) connecting the updating signal output unit and the numerical information updating unit;
A second signal path (signal line LN2) which is provided separately from the first signal path and which connects the updating signal output means and the control means for controlling the game;
Equipped with
The update signal output unit outputs the update clock signal to both the numerical information update unit and the control unit.
The control means performs control relating to a game based on the input of the update clock signal through the second signal path,
The gaming machine according to feature A10, wherein the variation means is provided only at an intermediate position of the first signal path among the first signal path and the second signal path.

  According to the feature A12, the fluctuation means is provided in the middle position of the first signal path, while the fluctuation means is not provided in the second signal path. Thus, while the input timing of the update clock signal input to the numerical information update means may fluctuate, the update clock signal input to the control means does not change. Therefore, the effect of the feature A10 can be obtained without affecting the control regarding the game.

  The configuration limited by any one of the features B2 to B9 or the features C1 to C3 may be applied to the configuration of the present feature. In this case, further effects can be obtained by applying each configuration.

  Each invention of the above-mentioned feature A group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Whether or not the jackpot state occurs is determined at the timing when the gaming ball enters the operation opening. For example, it has a counter that is regularly updated within a certain range (for example, 1 count is updated in the range of 0 to 300 every 2 ms), and acquires the value of the counter when the gaming ball enters the operation opening If the value of the counter matches a predetermined winning value such as "7", for example, a bonus is given to the player in which the gaming state shifts to the jackpot state.

  Here, it is preferable that the update of the counter used in the jackpot lottery be performed well. For example, by grasping | ascertaining the update timing etc. of the counter used by a big hit lottery, the timing from which the value of the said counter turns into a value corresponding to a big hit may be grasped | ascertained. Then, it is conceivable that the fraudulent act of intentionally generating a jackpot by outputting an illegal signal to the regular control board in accordance with the timing.

  Also, for example, from the viewpoint of reducing the capacity required for the counter, it is preferable that the possible range of the counter used in the jackpot lottery is narrow. However, if the range of the counter used in the jackpot lottery narrows, the probability of winning derived from the range and the winning value becomes high, which may cause inconvenience that the desired probability of winning can not be set.

  In addition, the above-mentioned problem is the same also in other gaming machines which make a lottery using a counter.

Feature B1. Game signal output means (system clock circuit 312) for outputting a game clock signal;
Control means for controlling the progress of the game based on the fact that the game clock signal is input from the game signal output means (a function of the MPU 311 executing a process related to the progress of the game);
Numerical information updating means (counter circuit 317) capable of sequentially updating numerical information within a predetermined numerical range;
Acquisition means for acquiring the numerical information from the numerical information update means when a predetermined acquisition condition is satisfied (a function for executing the processing of step S305 and step S307 in the MPU 311);
Equipped with
In the gaming machine, which enters a specific state based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined specific information,
An update signal output unit (hard random number clock circuit 313) for outputting an update clock signal;
A gaming machine characterized in that the numerical information updating means updates the numerical information based on the fact that the updating clock signal is inputted from the updating signal output means.

  According to the feature B1, while the progress of the game is controlled based on the game clock signal being input to the control means, the numerical value is based on the update clock signal being input to the numerical information update means Information is updated. Thus, for example, by changing the cycle of the update clock signal, it is possible to increase the freedom of setting the update timing of the numerical information without affecting the progress of the game.

  Further, for example, by making the cycle with the update clock signal different from the cycle of the gaming clock signal, even when the cycle of the gaming clock signal is grasped, the update timing of the numerical information is grasped from the cycle. Hateful. Therefore, the update timing of the numerical information is grasped from the cycle of the gaming clock signal, and the acquisition condition is illegally established in accordance with the timing at which the numerical information becomes the specific information, and the illegal act of intentionally generating the specific state is suppressed. Can.

  As described above, in the gaming machine in which the control of the game is performed based on the input of the clock signal, the control system can be made suitable.

Feature B2. Game signal output means (system clock circuit 312) for outputting a game clock signal;
Control means for controlling the progress of the game based on the fact that the game clock signal is input from the game signal output means (a function of the MPU 311 executing a process related to the progress of the game);
Numerical information updating means (counter circuit 317) capable of sequentially updating numerical information within a predetermined numerical range;
Acquisition means for acquiring the numerical information from the numerical information update means when a predetermined acquisition condition is satisfied (a function for executing the processing of step S305 and step S307 in the MPU 311);
Equipped with
In the gaming machine, which enters a specific state based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined specific information,
The game apparatus further comprises update signal output means (hard random number clock circuit 313) provided separately from the game signal output means and outputting an update clock signal.
A gaming machine characterized in that the numerical information updating means sequentially updates the numerical information based on the input of the updating clock signal.

  According to the feature B2, the progress of the game is controlled based on the input of the gaming clock signal, and the numerical information is based on the input of the updating clock signal different from the gaming clock signal. It will be updated. Thus, the frequency can be set individually for the gaming clock signal and the updating clock signal. Therefore, it is possible to increase the degree of freedom in setting the update timing of the numerical information without affecting the progress of the game.

  Further, for example, even when the cycle of the gaming clock signal is grasped by setting the gaming clock signal and the updating clock signal to have different cycles from each other, the update timing of the numerical information is It is hard to be grasped. Therefore, the update timing of the numerical information is grasped from the cycle of the gaming clock signal, and the acquisition condition is illegally established in accordance with the timing at which the numerical information becomes the specific information, and the illegal act of intentionally generating the specific state is suppressed. Can.

  As described above, in the gaming machine in which the control of the game is performed based on the input of the clock signal, the control system can be made suitable.

  Feature B3. The gaming machine according to feature B2, wherein the updating signal output unit outputs the updating clock signal so as not to be synchronized with the gaming clock signal.

  According to the feature B3, since the update clock signal is not synchronized with the gaming clock signal, it becomes difficult to grasp the output timing of the update clock signal from the output timing of the gaming clock signal, etc. There is. In this way, it is possible to suppress the fraudulent act of grasping the update timing of the numerical information by the numerical information update means from the output timing of the game clock signal or the like.

Feature B4. The numerical value information updating means is configured to update the numerical value information by using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
In the feature B2 or the feature B3, the update signal output unit outputs the update clock signal such that an output interval of a signal state corresponding to the trigger is different from the gaming clock signal. The gaming machine described.

  According to the feature B4, since the output intervals of the signal states that trigger updating of the numerical information are different between the gaming clock signal and the updating clock signal, even when the gaming clock signal is grasped. It is difficult to grasp the update timing of numerical information. Thus, it is possible to specify the update timing of the numerical information from the gaming clock signal, and to suppress the fraudulent act of specifying the timing when the numerical information becomes the specific information.

  Feature B5. The update signal output unit includes a signal conversion unit (signal conversion circuit 402) that generates the update clock signal by converting an AC voltage supplied from an external power supply into a pulse signal. The gaming machine according to any one of features B2 to B4.

  According to the feature B5, the update clock signal is obtained by converting the AC voltage supplied from the external power supply into a pulse signal. Thus, for example, by using a commercial power supply or a power supply of a game machine as an external power supply, a pulse signal can be easily obtained, and the pulse signal can be used as an update clock signal. Therefore, the configuration can be simplified.

Feature B6. The numerical value information updating means is configured to update the numerical value information by using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
The signal conversion means includes output space conversion means (frequency conversion circuit 401) for converting so that the output space of the signal state corresponding to the trigger does not correspond to the cycle of the input AC voltage. The gaming machine according to feature B5, characterized in that

  According to the feature B6, the output interval of the signal state corresponding to the trigger of the update of the numerical information is converted so as not to be an interval corresponding to the cycle of the input AC voltage. As a result, even if the cycle of the alternating voltage to be input is specified, it is difficult to specify the output interval of the signal state corresponding to the trigger for updating the numerical information. Therefore, the output interval of the signal state equivalent to the trigger of the update of numerical information is specified from the frequency of the alternating voltage input, and the fraudulent act which specifies the update timing of numerical information can be suppressed.

  Note that, as a more specific configuration of the output interval conversion means, “the output interval conversion means outputs the frequency of the update clock signal output from the update signal output means and the frequency of the AC voltage to be input. Are converted so as to have different frequencies.

Feature B7. The numerical value information updating means is configured to update the numerical value information by using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
The signal conversion means is characterized in that it generates an update clock signal of a predetermined specific frequency, regardless of whether the frequency of the AC voltage to be input is either the first frequency or the second frequency. The gaming machine according to feature B5 or feature B6.

  For example, when a commercial power supply is used as the external power supply, the frequency of the AC voltage is different between East Japan and West Japan, so the frequency of the update clock signal is also different. Then, since the output interval of the signal state corresponding to the trigger of the update of the numerical information is different, the update frequency of the numerical information is different in the use area, and the fairness of the game is hindered.

  On the other hand, according to the present feature, regardless of whether the frequency of the input AC voltage is the first frequency or the second frequency, the frequency of the update clock signal is the specific frequency. As a result, since the output interval of the signal state corresponding to the trigger of updating of the numerical information does not depend on the frequency of the AC voltage, the above-mentioned inconvenience can be avoided.

  The first frequency and the second frequency may be 50 Hz and 60 Hz, which are frequencies of a commercial power supply.

Feature B8. The control means
Initial value information updating means (the function of updating the random number initial value counter CINI or the pulse shift counter SC in the MPU 311) which sequentially updates the initial value information within the numerical range each time the update timing is reached,
Determining means (a function of executing the process of step S605 in the MPU 311) for determining whether or not the numerical value information has made one rotation;
Initial value information acquiring means (function of executing the process of step S606 in the MPU 311) for acquiring the initial value information from the initial value information updating means when it is determined by the determining means that the numerical value information has traveled one round ,
And writing means (a function of executing the process of step S606 in the MPU 311) that writes the acquired initial value information as the initial value of the numerical information when the initial value information is acquired.
Prohibiting means for prohibiting updating of the numerical value information during a period of writing by the writing means (a function of executing the processing of step S603 and step S607 in the MPU 311);
A game machine according to any one of features B2 to B7, characterized in that it comprises:

  According to the feature B8, when the numerical value information makes one revolution, the initial value information is acquired, and the updating of the numerical information is started from the initial value information. As a result, since the initial value of the numerical information fluctuates each time the numerical information makes one revolution, it is difficult to specify the timing at which the numerical information becomes specific information.

  Here, since the update of the numerical information and the control by the control means are different from each other in the clock signal which triggers the execution, the numerical information may be updated during the writing by the writing means. In particular, when the gaming clock signal and the updating clock signal are not synchronized with each other, the control by the control means and the updating by the numerical information updating means are not synchronized. This makes it easy to update numerical information during writing. Then, the consistency of the contents can not be obtained, and an error or the like is likely to occur. In this respect, according to the present feature, updating of numerical information is prohibited during writing. Thereby, the above-mentioned inconvenience can be avoided.

  Further, in relation to the feature B6, “the control means periodically performs the determination process by the determination means at a predetermined cycle, and the output interval of the signal state corresponding to the trigger is determined by the determination means. It may be set to be longer than the execution cycle. Thus, since the determination process is performed at least once between the update of the numerical information and the next update, it is possible to reliably grasp that the numerical information has made one revolution, and the numerical information has made one revolution. The condition is not to continue excessively.

Feature B9. A substrate box (substrate box 163) accommodating the numerical information updating means;
Fixing means (seal portion 164) for fixing the substrate box in a state where it can not be opened or difficult to open;
Equipped with
The gaming machine according to any one of features B2 to B8, wherein at least the updating signal output unit is accommodated in the substrate box.

  According to the feature B9, at least the updating signal output unit and the numerical information updating unit are accommodated in the substrate box. The substrate box is fixed in a state where it can not be opened or is difficult to open by the fixing means. Thus, it is possible to prevent the fraudulent action on the numerical information updating means and to prevent the fraudulent action on the updating signal output means. Therefore, while simplifying the configuration, it is possible to preferably suppress fraudulent acts on the updating signal output means such as grasping the cycle of the updating clock signal.

  Further, in relation to the feature B6, it is preferable that "the output interval conversion means is accommodated in the substrate box". Thereby, it is possible to suppress the fraudulent act on the output interval conversion means. Therefore, it is possible to specify the output interval of the signal state corresponding to the trigger of the update of the numerical information based on the analysis of the output interval conversion means, and to suppress the fraudulent act of grasping the update timing of the numerical information.

Feature B10. The numerical value information updating means is configured to update the numerical value information by using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
A signal path connecting the updating signal output means and the numerical information updating means;
Variation means (a modulation circuit 314) provided at an intermediate position of the signal path and varying a trigger interval from one trigger to the next trigger;
The gaming machine according to any one of the features B2 to B9, comprising:

  According to the feature B10, since the interval between the triggers that triggers the update of the numerical information changes, the update interval of the numerical information changes. As a result, since the update timing of the numerical information is difficult to grasp, it is difficult to specify the timing at which the numerical information becomes specific information. Therefore, for example, it is possible to suppress the fraudulent act of causing the specific state to occur deliberately by establishing the acquisition condition illegally in accordance with the timing when the numerical information becomes the specific information.

  Further, the period in which the numerical information is the specific information and the period in which the numerical information makes one revolution may vary according to the trigger interval. Thus, for example, by adjusting the trigger interval, it is possible to adjust the actual winning probability derived from the ratio of the period in which the numerical information is the specific information to the period in which the numerical information makes one revolution. Therefore, since it is possible to make the substantial winning probability lower than the numerical range of the numerical information and the theoretical winning probability derived from the specific information, it is possible to reduce the numerical range of the numerical information. Therefore, the capacity required for numerical information can be reduced.

  From the above, the numerical information can be updated well.

  The configuration limited by any one of the features A1 to A10 may be applied to the configuration of the present feature. In this case, further effects can be obtained by applying each configuration.

Feature B11. An output unit (system clock circuit 312) for outputting a clock signal;
Control means (a function of executing processing on the progress of the game in the MPU 311) that controls the progress of the game by executing a plurality of processes based on the clock signal output from the output means;
In the gaming machine provided with
The control means is configured such that a first clock signal is input through a first signal path and a second clock signal is input through a second signal path, and the first clock signal is The first processing means for executing the first process among the plurality of processes based on the input and the second process among the plurality of processes based on the input of the second clock signal And second processing means for processing the game.

  According to the feature B11, the first process is executed based on the input of the first clock signal, and the second process is executed based on the input of the second clock signal. Thus, by setting the frequency individually with the first clock signal and the second clock signal, it is possible to increase the degree of freedom in setting the execution timing of each of the first processing and the second processing.

  In this case, it is preferable that the first clock signal and the second clock signal be set to have different cycles. Thus, for example, the first process is a process that is particularly susceptible to fraud among a plurality of processes, and the second process is a process that is likely to be a fraudulent subject by a process other than the first process among a plurality of processes. Since it is difficult to specify the execution timing of the program, it is possible to suppress cheating on processing that is likely to be a target of cheating.

  Each invention of the above-mentioned feature B group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Here, the pachinko machine is provided with a storage element such as a memory in which a control program related to a game is stored, an arithmetic element for executing the control program, or a control board on which an MPU on which these are integrated is mounted. What is known. In the pachinko machine, a series of games are controlled by a control program.

  The above-mentioned gaming machine is provided with an oscillating circuit which outputs a clock signal which is a reference of operation timing of the arithmetic element. The operation element executes the control program by operating the plurality of elements in synchronization with the clock signal output from the oscillation circuit. As the control program, for example, the counter is periodically updated within a predetermined numerical range, and when the gaming ball enters the operation opening, the value of the counter at that time is acquired, and the counter For example, when the value of 一致 matches a predetermined winning value such as "7", there is one that shifts the gaming state to the jackpot state.

  Here, depending on the purpose of processing, it may be preferable to change the frequency of the clock signal. However, changing the frequency of the clock signal may affect other processes, which is not preferable.

  Further, for example, an illegal circuit is attached to a path connecting the arithmetic element and the oscillator circuit, and an illegal signal is generated in synchronization with the clock signal output from the oscillator circuit to intentionally generate a jackpot state. May be done.

  As described above, there is still room for improvement in the control system including the oscillation circuit that outputs the clock signal and the arithmetic element that performs control related to the game based on the input of the clock signal.

  The above problem is a problem common to gaming machines provided with an oscillating circuit that outputs a clock signal and a computing element that executes a control program related to gaming based on the input of the clock signal.

Feature C1. Game signal output means (system clock circuit 312) for outputting a game clock signal;
Control means for controlling the progress of the game (a function of executing processing relating to the progress of the game in the MPU 311);
Numerical information updating means (counter circuit 317) capable of sequentially updating numerical information within a predetermined numerical range;
Acquisition means for acquiring the numerical information from the numerical information update means when a predetermined acquisition condition is satisfied (a function for executing the processing of step S305 and step S307 in the MPU 311);
Equipped with
The control means controls the progress of the game based on the input of the game clock signal from the game signal output means.
In the gaming machine, which enters a specific state based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined specific information,
An update signal output unit (hard random number clock circuit 313) for outputting an update clock signal;
The numerical value information updating means is configured to update the numerical value information by using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
The updating signal output unit satisfies at least one of a condition not synchronized with the gaming clock signal and an output interval of a signal state corresponding to the trigger different from the gaming clock signal. A game machine characterized by outputting an update clock signal.

  According to the feature C1, while the progress of the game is controlled based on the gaming clock signal being input to the control means, the numerical information is triggered by the predetermined place from the rising edge to the falling edge of the update clock signal. Updates will be made.

  Here, between the gaming clock signal and the updating clock signal, at least one of the fact that both are not synchronized with each other and that the output intervals of the signal states corresponding to the trigger are different from each other. Since the condition is satisfied, even when the gaming clock signal is grasped, it is difficult to grasp the timing at which the updating clock signal becomes the output state corresponding to the trigger. Thereby, the update timing of the numerical information is grasped from the gaming clock signal, and the acquisition condition is illegally met in accordance with the timing when the numerical information becomes the specific information, and the illegal operation to intentionally generate the specific state is suppressed. it can.

Feature C2. A first signal path (signal line LN1) connecting the gaming signal output means and the control means;
A second signal path (signal line LN2) connecting the gaming signal output means and the numerical information update means;
Equipped with
The gaming signal output unit outputs the gaming clock signal to each of the control unit and the numerical information updating unit.
The update signal output unit is provided on the second signal path, and is a clock conversion unit that outputs the update clock signal based on the game clock signal being input from the game signal output unit. The gaming machine according to feature C1, comprising (a clock conversion circuit 501).

  According to the feature C2, the update clock signal is obtained by converting the gaming clock signal. Thus, the configuration can be simplified because a configuration for outputting a clock signal is not necessary.

  Further, since the gaming clock signal is input via the first signal path, control relating to the gaming is performed at a constant timing regardless of the mode of the updating clock signal. Thereby, it is possible to change the aspect of the update clock signal without affecting the control regarding the game.

Feature C3. Frequency conversion means (dividing circuit 502) for converting the frequency of the gaming clock signal by dividing or multiplying the gaming clock signal output from the gaming signal output means;
Phase shift means (phase shift circuit 503) for shifting the phase of the clock signal frequency-converted by the frequency conversion means by a predetermined amount with respect to the phase of the gaming clock signal. The gaming machine according to feature C2.

  According to the feature C3, the updating clock signal converts the frequency of the gaming clock signal by dividing or multiplying the gaming clock signal, and the phase of the converted clock signal is the phase of the gaming clock signal. It is created by shifting by a predetermined amount with respect to. Thus, the update clock signal and the gaming clock signal have different cycles from each other, and are not synchronized with each other. Therefore, the effects shown in the feature C2 can be obtained.

  The configuration limited by any one of the features A1 to A10 may be applied to the configuration of the present feature. In this case, further effects can be obtained by applying each configuration.

  Each invention of the above-mentioned feature C group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Here, in the pachinko machine, a storage element such as a memory in which a control program related to a game is stored, an arithmetic element for executing the control program, or a control board on which an MPU on which these are integrated is mounted. What is provided is known. In the pachinko machine, a series of games are controlled by a computing element.

  The above-mentioned gaming machine is provided with an oscillating circuit which outputs a clock signal which is a reference of operation timing of the arithmetic element. The operation element executes the control program by operating the plurality of elements in synchronization with the clock signal output from the oscillation circuit. As a control program, for example, the counter is periodically updated within a predetermined numerical range, and when the gaming ball enters the operation opening, the value of the counter at that time is acquired, and When the value matches, for example, a predetermined winning value such as "7", the gaming state may be shifted to the jackpot state.

  Here, the timing at which the value of the counter becomes the jackpot winning value may be grasped by grasping the update timing or the like of the counter used in the jackpot lottery. Then, it is conceivable that the fraudulent act of intentionally generating a jackpot by outputting an illegal signal to the regular control board in accordance with the timing.

  In addition, in the gaming machine, various cheating acts are assumed, and as described above, the predetermined processing timing etc. in the control entity are grasped, and the act of cheating on the basis of the grasping result is not limited to the jackpot lottery. . In addition, such fraud is not limited to the pachinko machine, and the same applies to the slot machine.

Feature D1. In a gaming machine provided with control means for performing control regarding gaming,
Signal conversion means (signal conversion circuit 402) for converting an AC voltage supplied from an external power supply into a clock signal,
A game machine characterized in that the control means performs control relating to a game based on input of a clock signal obtained by the signal conversion means.

  According to the feature D1, the clock signal is obtained by converting the AC voltage supplied from the external power supply. Thus, it is possible to easily obtain a clock signal by using, for example, a commercial power supply or a power supply of a game machine as an external power supply. Therefore, the configuration can be simplified.

Feature D2. The control means is a numerical information updating means (counter circuit 317) for sequentially updating numerical information within a predetermined numerical range, triggered by a predetermined place from rising to falling of the clock signal, and predetermined acquisition Acquisition means for acquiring the numerical information from the numerical information update means when the condition is satisfied (function for executing the processing of step S305 and step S307 in the MPU 311), and the numerical information acquired by the acquisition means Is in a specific state based on the fact that it corresponds to predetermined specific information,
The signal conversion means includes output space conversion means (frequency conversion circuit 401) for converting so that the output space of the signal state corresponding to the trigger does not correspond to the cycle of the input AC voltage. The gaming machine according to feature D1, characterized in that

  According to the feature D2, when the acquired numerical information corresponds to the specific information, the specific state is established. The numerical information is updated using a predetermined portion of the clock signal as a trigger.

  Here, the output interval of the signal state corresponding to the trigger in the clock signal is converted so as not to be the interval corresponding to the cycle of the input AC voltage. As a result, even if the cycle of the alternating voltage to be input is specified, it is difficult to specify the output interval of the signal state corresponding to the trigger for updating the numerical information. Therefore, the output interval of the signal state equivalent to the trigger of the update of numerical information is specified from the frequency of the alternating voltage input, and the fraudulent act which specifies the update timing of numerical information can be suppressed.

  As a more specific configuration of the output interval conversion means, “the frequency of the update clock signal output from the update signal output means is set to a frequency different from the frequency of the AC voltage to be input. It is considered that the configuration is “to convert”.

Feature D3. The numerical value information updating means is configured to update the numerical value information by using a predetermined place from the rise to the fall of the clock signal for update as a trigger.
The signal conversion means is configured to output an update clock signal of a predetermined specific frequency regardless of whether the frequency of the input AC voltage is any of the first frequency and the second frequency. The gaming machine according to feature D1 or D2, characterized in that

  For example, when a commercial power supply is used as the external power supply, the frequency of the AC voltage is different between East Japan and West Japan, so the frequency of the update clock signal is also different. Then, since the output interval of the signal state corresponding to the trigger of the update of the numerical information is different, the update frequency of the numerical information is different in the use area, and the fairness of the game is hindered.

  On the other hand, according to the present feature, regardless of whether the frequency of the input AC voltage is the first frequency or the second frequency, the frequency of the update clock signal is converted to the specific frequency. As a result, since the output interval of the signal state corresponding to the trigger of updating of the numerical information does not depend on the frequency of the AC voltage, the above-mentioned inconvenience can be avoided.

  The first frequency and the second frequency may be 50 Hz and 60 Hz, which are frequencies of a commercial power supply.

  Each invention of the above-mentioned feature D group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  A pachinko machine is provided with a storage element such as a memory in which a control program related to a game is stored, an arithmetic element for executing the control program, or a control board on which an MPU on which these are integrated is mounted. What is known. In the pachinko machine, a series of games are controlled by a control program.

  The above-mentioned gaming machine is provided with an oscillating circuit which outputs a clock signal which is a reference of operation timing of the arithmetic element. The operation element executes the control program by operating the plurality of elements in synchronization with the clock signal output from the oscillation circuit.

  Here, the simple configuration of the oscillation circuit is preferable, and there is still room for improvement in the oscillation circuit.

  The above problem is a problem common to gaming machines provided with an oscillating circuit that outputs a clock signal and a computing element that executes a control program related to gaming based on the input of the clock signal.

Feature E1. In a gaming machine provided with control means (main control board 301) to be in a specific state in the process of controlling the progress of the game and controlling the progress of the game,
A game machine characterized by further comprising variable means (irregular delay circuit 602 or non-periodical circuit) for changing a period from when the predetermined condition is established to when the control means becomes the specific state.

  According to the feature E1, the period from the satisfaction of the predetermined condition to the specific state of the control means is fluctuated by the fluctuation means. As a result, a variation occurs in the period from the establishment timing of the predetermined condition to the specific state of the control means. Therefore, the period from the establishment timing of the predetermined condition to the timing when the control means becomes the specific state becomes irregular. Therefore, even if it is a case where the establishment timing of a predetermined condition is grasped | ascertained temporarily by a "hanging board" etc., it is difficult to grasp the timing which a control means will be in a specific state. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

Feature E2. Numerical information updating means (a function for executing the updating process of the jackpot random number counter C1 of the step S703 in the MPU 311) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Equipped with
It is a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information,
The game is characterized by further comprising variable means (irregular delay circuit 602 or non-periodical circuit) for changing a period from establishment of a predetermined condition until numerical information of the numerical information update means becomes the win information. Machine.

  According to the feature E2, the period from when the predetermined condition is met to when the numerical information of the numerical information update means becomes the win information is fluctuated by the fluctuation means. As a result, a variation occurs in the period from the establishment timing of the predetermined condition to the timing when the numerical information becomes the winning information. Therefore, the period from the establishment timing of the predetermined condition to the timing when the numerical information becomes the win information becomes irregular. Therefore, even if it is a case where the fulfillment timing of a predetermined condition is grasped by a "hanging board" etc., it is difficult to grasp the timing when the numerical information becomes the winning information. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

Feature E3. Numerical information updating means (a function for executing the updating process of the jackpot random number counter C1 of the step S703 in the MPU 311) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Equipped with
It is a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information,
Fluctuation is caused according to the execution timing of the predetermined operation to change the period from the execution timing of the predetermined operation enabling the numerical information to be sequentially updated from the predetermined numerical value to the win information of the numerical information A game machine characterized by comprising means (irregular delay circuit 602 or non-periodic circuit).

  According to the feature E3, a period from the execution timing of the predetermined operation enabling the numerical information to be sequentially updated from the predetermined numerical value to the win information of the numerical information fluctuates according to the execution timing of the predetermined operation. ing. As a result, variation occurs in the period from the execution timing of the predetermined operation to the timing when the numerical information becomes the win information. Therefore, the period from the execution timing of the predetermined operation to the timing when the numerical information becomes the winning information becomes irregular. Therefore, since it is difficult to grasp the period from the execution timing of the predetermined operation to the timing when the numerical information becomes winning information, it is difficult to grasp the timing when the numerical information becomes winning information even if the execution timing of the predetermined operation is grasped. Therefore, it is possible to suppress fraudulent acts such as "hanging board".

Feature E4. Numeric information update means that operates in a state where operating power is supplied to control means that performs control relating to gaming, and sequentially updates numerical information within a predetermined numeric range each time an update timing is reached (big hit of step S703 in MPU 311 A function of updating the random number counter C1),
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Equipped with
It is a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information,
Variation means for varying a period from supply start timing at which operation power is supplied to the control means to update start timing at which update of the numerical information is started in the numerical information update means according to the supply start timing ( A game machine characterized by comprising an irregular delay circuit (602) or a circuit for deperiodicalization.

  According to the feature E4, since the period from the supply start timing at which the operation power is supplied to the control means to the update start timing at which the update of the numerical information is started fluctuates according to the supply start timing, the update start from the supply start timing There is a variation in the time to timing. As a result, the period from the supply start timing to the update start timing becomes irregular. Therefore, even if the numerical information updating means starts updating from a predetermined initial value, the period from the supply start timing until the numerical information matches the winning information becomes irregular, so the period is It is hard to be grasped. Therefore, it is possible to suppress the fraudulent act of outputting a signal in accordance with the timing when the numerical information coincides with the winning information by the “hanging board” or the like to obtain the privilege illegally.

Feature E5. Supply means (reset circuit 601, power supply and emission control board 321) which is in a supply state for supplying a signal or power based on the start of supply of operation power to the control means in the feature E4;
A supply path (signal line LN4) for connecting the supply means and the numerical information update means;
Equipped with
The numerical value information updating means starts updating when the supply means is in the supply state and the state of the signal or power supplied from the supply path is in a predetermined operable state.
The fluctuation means is provided at an intermediate position of the supply path, and fluctuates a period from the timing to be in the supply state to the timing to be in the operable state according to the timing to be in the supply state. A gaming machine to be.

  According to the feature E5, the numerical information update means and the supply means are connected via the supply path. The supply means is in a supply state for supplying a signal or power based on the start of the supply of the operating power to the control means. Further, when the supply means is in the supply state and the state of the signal or the power supplied from the supply path is in a predetermined operable state, the numerical information update means starts the update. Here, the fluctuation means is provided at an intermediate position of the supply path, and the period from the timing of the supply state to the timing of the operable state fluctuates according to the timing of the supply state. As a result, since the period from the timing when the supply state is reached to the availability state becomes irregular, the period from the supply start timing to the update start timing becomes irregular. Therefore, the period from the supply start timing until the numerical information coincides with the winning information becomes irregular, so it is difficult to grasp the period. Therefore, it is possible to prevent fraudulent acts using the "hanging board" or the like.

  Further, since the period from the timing when the supply state is reached to the timing when the operation possible state is irregular, it is not necessary to change the update start timing in the numerical information update means. Therefore, the configuration of the numerical information updating means can be simplified.

  Feature E6. In the feature E5, the variation means is capable of accumulating the supplied electric charge and releasing the charged electric charge, and charging / discharging means (capacitor 613) which accumulates the electric charge when the supply means is in the supply state. To shift the state of the signal or power supplied from the supply path to the numerical information update means to the operable state when the charge accumulated in the charge / discharge means is accumulated a predetermined amount or more A game machine characterized by being made to

  According to the feature E6, when the supply means is in the supply state, charges are accumulated in the charge / discharge means, and when charge is accumulated in the charge / discharge means to a predetermined amount or more, the state shifts to the operable state. As a result, the timing at which the supply unit is in the supply state is delayed with respect to the timing at which the supply unit is in the supply state by the period in which the charge and discharge unit accumulates a predetermined amount or more. On the other hand, when the supply means is not in the supply state, that is, when the operating power is not supplied to the control means, the charge stored in the charge and discharge means is gradually released. That is, the charge / discharge means is in a discharged state. When the supply means is in the supply state again under the discharge state, the charge / discharge means is switched from the discharge state to the charge state. Then, the timing at which the operation is enabled is delayed by a period until a predetermined amount of charge is accumulated again in the charge / discharge means. The said delay period is fluctuate | varied according to the residual charge amount in the charging / discharging means in the time of a supply means being in a supply state. In addition, the residual charge amount fluctuates depending on the timing at which the supply means becomes the supply state under the discharge state of the charge and discharge means. As a result, based on the timing at which the supply means is in the supply state, the period from the timing at which the supply means is in the supply state to the timing at which it is in the operable state fluctuates. Therefore, it is possible to suppress fraudulent acts using a “hanging board” or the like with a simple configuration in which charge / discharge means are provided.

  Feature E7. In the feature E6, the variation means includes an integration circuit (integral circuit 611) including at least one capacitor (capacitor 613) and at least one resistor (resistance 614) as the charge / discharge means. A gaming machine to be.

  According to the feature E7, a charge period from the start of charge accumulation to the charge accumulation to the predetermined amount and a discharge from the start of discharge of the accumulated charge to the loss of the accumulated charge Since the period is set based on the electric capacity of the capacitor of the integration circuit and the resistance value of the resistor, the charge period and the discharge period can be adjusted by adjusting both. As a result, by lengthening the charge period and the discharge period, it is possible to increase the variation of the residual charge amount that fluctuates due to the variation of the delay period and the discharge period. Therefore, the start timing of the updating of the numerical value updating means can be irregular, and it is difficult to grasp the timing.

  Feature E8. In the feature E6 or the feature E7, in the charge and discharge means, the variation means starts discharging the accumulated charge and then discharges the accumulated charge from the start of accumulation of the charge until the discharge period starts. A gaming machine comprising period changing means (switching circuit 621) for making the charging period longer than the charge period until the predetermined amount is accumulated.

  From the viewpoint of variation in delay period, a charging period from the start of charge accumulation to the accumulation of charges up to the predetermined amount, and from the start of discharge of accumulated charges to the loss of accumulated charges The discharge period is preferably longer. In particular, it is preferable that the discharge period contributing to the variation of the residual charge amount be longer. However, for example, in the case of an integration circuit, since the charge period and the discharge period are substantially the same, if the charge period is extended by prolonging the discharge period, the update start timing of the numerical information update means is excessively delayed. Problems may occur. On the other hand, according to the feature E8, the discharge period is longer than the charge period by the period changing means. As a result, it is possible to avoid the above problems while securing the variation of the delay period.

Feature E9. In the feature E5, the variation means is a transition means (synthesis circuit 641, D flip flop 651 or the like) that receives the specific signal from a specific signal output means (signal conversion circuit 402) that outputs a specific signal in a specific form at a specific timing. Equipped with
The transition means is based on the fact that the supply means is in the supply state, and the specific signal output from the specific signal output means is based on the specific form from the supply path. A gaming machine characterized in that a state of a signal or power supplied to information updating means is shifted to the operable state.

  According to the feature E9, the specific signal in the specific form at the specific timing is output to the transition means by the specific signal output means. Then, based on the fact that the supply means is in the supply state and the specific signal outputted from the specific signal output means is in the specific form, the signal or electric power supplied from the supply path to the numerical information update means The state of is transitioned to the operable state. Thus, when the supply means is in the supply state under the condition that the specific signal output from the specific signal output means is other than the specific form, the specific signal output from the specific signal output means is the specific form Transition to the ready state is delayed until Further, the delay period varies depending on the form of the specific signal with respect to the timing at which the supply means is in the supply state. As a result, based on the timing at which the supply means is in the supply state, the period from the timing at which the supply means is in the supply state to the timing at which it is in the operable state changes. Therefore, since the start timing of the update of the numerical information update means is irregular, it is difficult to grasp the timing. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like.

  Further, in the configuration in which the charge / discharge means is provided as the fluctuation means, when the period when the operation power is not supplied to the control means is longer than the discharge period, no charge remains in the charge / discharge means. It occurs. On the other hand, according to the feature E9, since the delay period does not depend on the period in which the operating power is not supplied to the control means, the above-mentioned inconvenience can be avoided.

Feature E10. In the feature E5, the variation means outputs a specific signal in a specific form at a specific timing (signal conversion circuit 402);
Based on the fact that the supply means is in the supply state and the specific signal outputted from the specific signal output means is in the specific form, the supply path supplies the numerical information updating means to the numerical information update means Transition means (combining circuit 641, D flip flop 651 or the like) for shifting the state of the signal or power to the operable state;
A game machine characterized by comprising:

  According to the feature E10, the specific signal which is in the specific form at the specific timing is supplied to the transition means by the specific signal output means. Then, based on the fact that the supply means is in the supply state and the specific signal outputted from the specific signal output means is in the specific form, the signal or electric power supplied from the supply path to the numerical information update means The state of is transitioned to the operable state. Thus, when the supply means is in the supply state under the condition that the specific signal output from the specific signal output means is other than the specific form, the specific signal output from the specific signal output means is the specific form Transition to the ready state is delayed until Further, the delay period varies depending on the form of the specific signal with respect to the timing at which the supply means is in the supply state. As a result, based on the timing at which the supply means is in the supply state, the period from the timing at which the supply means is in the supply state to the timing at which it is in the operable state fluctuates. Therefore, since the start timing of the update of the numerical information update means is irregular, it is difficult to grasp the timing. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like.

  Further, in the configuration in which the charge / discharge means is provided as the fluctuation means, when the period when the operation power is not supplied to the control means is longer than the discharge period, no charge remains in the charge / discharge means. It occurs. On the other hand, according to the feature E10, since the delay period does not depend on the period in which the operating power is not supplied to the control means, the above-mentioned inconvenience can be avoided.

Feature E11. In the feature E10, the specific signal output from the specific signal output means is a signal in which an HI level signal and a LOW level signal are alternately output,
The operation of the transition means is based on the fact that the supply means is in the supply state and any one of the HI level signal and the LOW level signal is outputted from the specific signal output means. A game machine characterized by being capable of shifting to a possible state (combination circuit 641).

  According to the feature E11, the operation is possible based on the fact that the supply means is in the supply state and one of the HI level signal and the LOW level signal is output from the specific signal output means to the transition means. It becomes a state. For example, if the transition means is brought into the operable state based on the fact that the supply means is in the supply state and the HI level signal is output from the specific signal output means, the LOW level signal is When the supply means is in the supply state under the condition of being output from the specific signal output means, the transition to the operable state is delayed until the HI level signal is output from the specific signal output means. The said delay period changes with the form of the specific signal with respect to the timing used as supply. As a result, since the start timing of the update of the numerical information update means is irregular, it is difficult to grasp the timing. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

Feature E12. In the feature E11, the specific signal output means outputs a signal in which the period of the HI level signal and the period of the LOW level signal are relatively different from each other.
The transition means is based on the fact that the supply means is in the supply state, and a signal with a relatively short period of the HI level signal and the LOW level signal is output from the specific signal output means. A game machine characterized by being shifted to the operable state.

  For example, if the transition means is brought into the operable state based on the fact that the supply means is in the supply state and the HI level signal is output from the specific signal output means, the LOW level signal is the specific signal. When the supply means is in the supply state under the condition of being output from the output means, the transition to the operable state is delayed until the HI level signal is output from the specific signal output means. However, when the supply means is supplied under the condition that the HI level signal is output from the specific signal output means, the operation state is immediately shifted to the operable state, causing a problem that no delay occurs. That is, there is a period in which no delay occurs with respect to the timing at which the supply means is in the supply state. On the other hand, according to the feature E12, the specific signal output means outputs a signal in which the period of the HI level signal and the period of the LOW level signal are different. Then, the supply means is in the supply state, and the transition to the operable state is made based on the fact that a signal with a relatively short period of the HI level signal and the LOW level signal is output from the specific signal output means. As a result, the period in which the delay does not occur becomes shorter than the period in which the delay occurs, so that the above problem can be suppressed.

Feature E13. In the feature E10, the specific signal output from the specific signal output means is a signal in which an HI level signal and a LOW level signal are alternately output,
In the transition means, the supply means is in the supply state, and the output state of the specific signal output from the specific signal output means is changed between the HI level signal and the LOW level signal. A gaming machine characterized by being based on the one to shift to the operable state (D flip flop 651).

  According to the feature E13, the supply means is in the supply state, and the operation is possible based on the change in the output state of the specific signal output from the specific signal output means between the HI level signal and the LOW level signal. Transition to the state. Thus, the transition to the operable state is delayed until the output state of the specific signal output from the specific signal output means changes between the HI level signal and the LOW level signal after the supply means becomes in the supply state. Ru. The delay period varies depending on the form of the specific signal with respect to the timing at which the supply means becomes in supply state. As a result, since the start timing of the update of the numerical information update means is irregular, it is difficult to grasp the timing. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

  Further, since the transition to the operable state is made based on the change in the output state of the specific signal between the HI level signal and the LOW level signal, the timing when the supply means becomes the supply state and the output state of the specific signal are HI As long as the timing at which the level signal and the low level signal change does not coincide, a delay occurs. That is, the period in which the delay does not occur is shorter than the configuration in which transition is made based on the fact that one of the HI level signal and the LOW level signal is output from the specific signal output means. Therefore, it is possible to suppress the problem that the delay does not occur.

  Feature E14. In any one of the features E10 to E13, the specific signal output unit converts the AC voltage supplied from the external power supply into a pulse signal with reference to a predetermined threshold voltage, thereby converting the HI level signal and the HI level signal. A game machine characterized in that the LOW level signal generates a specific signal alternately output.

  According to the feature E14, the specific signal in which the HI level signal and the LOW level signal are alternately output is obtained by converting the AC voltage supplied from the external power supply into a pulse signal. Thereby, a desired pulse signal can be easily obtained, for example, by using a commercial power supply or the power supply of a game machine as an external power supply. Therefore, the configuration can be simplified.

  Moreover, conversion from an alternating voltage to a pulse signal is performed based on a predetermined threshold voltage. Thereby, by changing the threshold voltage, it is possible to easily obtain a pulse signal of a desired pulse width. Therefore, the configuration of the feature E12 can be easily realized.

Feature E15. In any one of features E10 to E14, the specific signal output means includes pulse signal output means (signal conversion circuit 402) for outputting a pulse signal at a predetermined cycle,
The specific signal is generated using the pulse signal, and is in the specific form based on the pulse signal being in a predetermined form,
After the timing when the supply means is in the supply state, the specific signal becomes the specific form based on a predetermined form after the first predetermined form of the pulse signal output from the pulse signal output means A game machine characterized by comprising delay means (modulation circuit 662) for generating a signal.

  According to the feature E15, the specific signal is generated using the pulse signal output from the pulse signal output unit. Also, based on the pulse signal being in a predetermined form, the specific signal is in a specific form. Then, after the timing at which the supply means is in the supply state, the specific signal is not in the specific form based on the first predetermined form in the pulse signal. Thereby, when the supply means is in the supply state, the transition to the operable state based on the first predetermined form in the pulse signal after the timing when the supply means is in the supply state is not executed. Therefore, it is difficult to grasp the start timing of the updating of the numerical information updating means. Therefore, it is possible to prevent the fraudulent act of grasping the start timing of the updating of the numerical information updating means by grasping the timing when the supplying means is in the supplying state and the timing when the pulse signal becomes the predetermined form.

Feature E16. In any one of the features E13 to E15, the specific signal output means outputs a pulse signal at a predetermined cycle (signal conversion circuit 402);
By changing at least one of the repetition interval or pulse width of the pulse signal output from the pulse signal output means, at least one of the repetition interval or the pulse width as the specific signal corresponds to the HI level according to the change Signal changing means (modulation circuit 662, modulation circuit 671) for generating a signal from which the signal is output;
Equipped with
The transition means is brought into the operable state based on the fact that the supply means is in the supply state and the output state of the specific signal is changed between the HI level signal and the LOW level signal. A gaming machine characterized in that it is to be shifted.

  According to the feature E16, at least one of the repetition interval or the pulse width of the pulse signal output from the pulse signal output means and the signal to which the HI level signal as the specific signal is output are different. Then, based on the change in the output state of the specific signal between the HI level signal and the LOW level signal, the state of the signal or power supplied from the supply path to the numerical information update means shifts to the operable state. Do. As a result, the timing at which the apparatus becomes operable differs from the case where the transition is made based on the change in the output state of the pulse signal output from the pulse signal output means. Therefore, it is possible to prevent a fraudulent act of grasping the timing of becoming the operable state from the output state of the pulse signal output from the pulse signal output means and the timing when the supplying means becomes the supplying state.

  Feature E17. In the feature E16, the signal changing unit changes at least one of a repetition interval or a pulse width of the pulse signal output from the pulse signal output unit to obtain at least one of the repetition interval or the pulse width as the specific signal. A game machine characterized in that the signal generation circuit (signal conversion circuit 402) generates a signal in which an HI level signal larger than the pulse signal output from the pulse signal output means is output.

  According to the feature E17, at least one of the repetition interval or pulse width of the HI level signal as the specific signal is changed by the signal changing means to be larger than that of the pulse signal output from the pulse signal output means. Therefore, the range of the delay period, which is the difference between the timing at which the supply means enters the supply state, and the timing at which the output state of the specific signal changes, is increased. Thereby, the variation of the delay period becomes large. Therefore, since the start timing of the update of the numerical information update means becomes more irregular, it is difficult to grasp the timing. It is possible to more preferably prevent fraudulent acts using a "hanging board" or the like.

  Feature E18. In the feature E16 or the feature E17, the signal changing unit changes at least one of a repetition interval or a pulse width of the pulse signal output from the pulse signal output unit to make at least an HI level signal as the specific signal. A game machine characterized by generating at least one of a signal outputted at two kinds of repetition intervals or a signal at which pulse signals of at least two kinds of pulse widths are outputted (a modulation circuit 671).

  According to the feature E18, as the specific signal, HI level signals are output at at least two repetition intervals or HI level signals having at least two pulse widths are output. As a result, the output state of the specific signal changes at least two intervals. Therefore, it is difficult to grasp the timing at which the output state of the specific signal changes. Therefore, it is difficult to grasp the timing of becoming the operable state. Therefore, it is possible to prevent fraudulent acts using the "hanging board" or the like.

Feature E19. In the feature E17 or the feature E18, the signal changing means generates a changing signal from the standby state using the pulse signal based on the start of the supply of the operating power to the control means. And a change signal generation unit (the second D flip flop 663, the third D flip flop 664, etc.) for transitioning to the generation state,
The signal changing means outputs an HI level signal in which at least one of a repetition interval and a pulse width is changed using the change signal when the change signal generation means is in the change signal generation state. To generate a signal,
A power-off time supply means (power-off time power supply section 321c) for supplying operating power to the change signal generating means in a situation where supply of operating power to the control means is stopped;
The change signal generation unit is configured to stop the change signal generation state when the supply of the operation power to the control unit is stopped while the operation power is supplied from the power-off time supply unit. A game machine characterized by storing a state, and transitioning from the stop state to the change signal generation state based on start of supply of operation power to the control means.

  According to the feature E19, the change signal generation means shifts from the standby state to the change signal generation state for generating the change signal based on the start of the supply of the operation power to the control means. When in the change signal generation state, the signal change unit generates a signal that outputs an HI level signal in which at least one of the repetition interval or the pulse width is changed using the change signal.

  Here, while the operating power is supplied from the power-off time supply means, the stop state which is a change signal generation state when the supply of the operating power to the control means is stopped is stored. Then, on the basis of the start of the supply of the operation power to the control means, the stop state is shifted to the change signal generation state. As a result, the standby state of the change signal generation means at the start timing of supply of the operation power to the control means fluctuates. Therefore, the fluctuation of the output timing of the specific signal is large as compared with the configuration in which the standby state at the operation power supply start timing is the same state. Therefore, the range of variation of the delay period becomes large, and the variation of the delay period is large. Therefore, the start timing of the update of the numerical information update means can be made more irregular.

Feature E20. In the feature E19, a storage means (RAM 316) is provided which stores information used when the control means performs control, and stores and holds the information while power is supplied thereto.
The power-off power supply means supplies power to the storage means and supplies power to the change signal generation means in a situation where the supply of operating power to the control means is stopped. A gaming machine characterized by being one.

  According to the feature E20, the power-off-time power supply unit holds the information stored in the storage unit and stores the stop state of the change signal generation unit. Thereby, the configuration can be simplified.

Feature E21. In any one of features E5 to E20, as the supply path, a first supply path (signal line LN3) not passing through the fluctuation means, and a second supply path (signal line LN4) passing through the fluctuation means While preparing
When the state of the signal or the power supplied from both supply paths to the numerical information update means is in the operable state, an update start signal for starting the update of the numerical information update means is the numerical information A stop signal for stopping the updating of the numerical information updating means is outputted to the numerical information updating means while outputting to the updating means while the state of at least one signal or power of both supply paths is not the operable state. A game machine comprising update instruction means (NAND circuit 612) for outputting.

  According to the feature E21, the supply means and the numerical information update means are connected by the first supply path not passing through the changing means and the second supply path passing through the changing means. Then, when the state of the signal or the power supplied to the numerical information update means from both supply paths is in the operable state, the update start signal for starting the update of the numerical information update means is sent to the numerical information update means Output. In response to the input of the signal, the numerical information update means starts updating. Thereby, even if the state of the signal or the power supplied from the first supply path to the numerical information update means is in the operable state, the state from the second supply path via the fluctuation means is not in the operable state. In this case, the update start signal is not output to the numerical information update means. Therefore, the effect of the delay by the fluctuation means is secured.

  On the other hand, when the state of the signal or the power supplied from at least one of the two supply paths to the update instructing means is not in the operable state, the update instructing means outputs a stop signal to the numerical information updating means . In response to the input of the stop signal, the update of the numerical information update means is stopped. This makes it possible to stop the updating of the numerical information update means without waiting for the state of the signal or power supplied from the second supply path to the numerical information update means to transition to the operable state. Therefore, by delaying the input of the stop signal to the numerical information update means, it is possible to suppress the inconvenience that a malfunction of the numerical information update means occurs.

Feature E22. In any one of the features E5 to E21, the supply means is an operation signal output means (reset circuit 601) for outputting an operation signal (reset signal) when the supply state is established,
The variation means, based on the fact that the operation signal is outputted from the operation signal output means, relays the relay result signal which is the same as or corresponding to the operation signal through the supply path. The period from the output start timing of the operation signal from the operation signal output means to the output start timing of the relay result signal is changed according to the output start timing of the operation signal. It is
The numerical value information updating means operates when the operation power is supplied through a path different from the supply path, and the relay result signal is input through the supply path. A gaming machine to be.

  According to the feature E22, based on the fact that the operation signal is outputted from the operation signal output means, the relay result signal identical to or corresponding to the operation signal is outputted to the numerical information update means through the supply path. It is done. Then, when the relay result signal is input through the supply path and the operation power is supplied through the path different from the supply path, the update by the numerical information update means is started. Here, the period from the output start timing of the operation signal from the operation signal output means to the output start timing of the relay result signal fluctuates according to the output start timing of the operation signal. As a result, since the start timing of the update by the numerical information update unit is irregular, it is difficult to grasp the start timing of the update of the numerical information update unit. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

Feature E23. In the features E10 to E22, a substrate box (substrate box 163) accommodating the numerical value information updating means;
Fixing means (seal portion 164) for fixing the substrate box in a state where it can not be opened or difficult to open;
Equipped with
A game machine characterized in that at least the transition means is accommodated in the substrate box.

  According to the feature E23, at least the transition means and the numerical information update means are accommodated in the substrate box. The substrate box is fixed in a state where it can not be opened or is difficult to open by the fixing means. As a result, it is possible to prevent the fraudulent act on the numerical information updating means and to prevent the fraudulent action on the transition means. Therefore, it is possible to preferably suppress fraudulent acts on the transition means while simplifying the configuration.

Feature E24. In any one of the features E1 to E23, a substrate box (substrate box 163) accommodating the numerical value information updating means,
Fixing means (seal portion 164) for fixing the substrate box in a state where it can not be opened or difficult to open;
Equipped with
A game machine characterized in that the variation means is accommodated in the substrate box.

  According to the feature E24, the changing means and the numerical information updating means are accommodated in the substrate box. The substrate box is fixed in a state where it can not be opened or is difficult to open by the fixing means. As a result, it is possible to prevent the fraudulent act on the numerical information updating means and to prevent the fraudulent action on the variable means. Therefore, it is possible to preferably suppress fraudulent acts on the variable means while simplifying the configuration.

Feature E25. Numerical information updating means (a function for executing the updating process of the jackpot random number counter C1 of the step S703 in the MPU 311) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Start signal output means (RAM erase signal output circuit 802) for outputting a start signal (RAM erase signal) when a predetermined operation condition is satisfied;
Equipped with
A bonus is given to the player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information.
In the gaming machine, the numerical value information updating means starts updating the numerical value information from a predetermined initial value based on the fact that the activation signal is outputted from the activation signal output means.
The period from the establishment timing of the predetermined operation condition to the update start timing when the numerical information update means starts updating the numerical information in the numerical information update means is varied according to the establishment timing of the predetermined operation condition A game machine characterized by comprising variation means (irregular delay circuit 602 or non-periodic circuit).

  According to the feature E25, when the predetermined operation condition is satisfied (for example, the switch provided in the game machine is operated), the activation signal is output from the activation signal output means, and the predetermined signal is output according to the output of the signal. Numerical information is updated from the initial value of. Here, since the period from the establishment timing of the predetermined operation condition to the update start timing at which updating of the numerical information is started from the predetermined initial value fluctuates according to the establishment timing, the period from the establishment timing to the update start timing Variations occur. As a result, the period from the establishment timing to the update start timing becomes irregular. Therefore, even if the numerical information update means starts updating from a predetermined initial value, the period from the timing when the predetermined operating condition is met to when the numerical information matches the winning information becomes irregular. , It is difficult to grasp the relevant period. Therefore, it is possible to suppress the fraudulent act of outputting a signal in accordance with the timing when the numerical information coincides with the winning information by the “hanging board” or the like to obtain the privilege illegally.

  In addition, the technical ideas shown in the features E5 to E18 and the features E21 to E24 can be applied to this feature. In this case, “based on the start of supply of operating power to the control means” is replaced with “based on the establishment of the predetermined operating condition”.

  The "predetermined initial value" includes not only a predetermined initial value but also an initial value acquired from a means for generating predetermined initial value information.

Feature E26. Numerical information updating means (a function for executing the updating process of the jackpot random number counter C1 of the step S703 in the MPU 311) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Reception means for receiving a predetermined initial value setting operation (a power on RAM erase switch 801);
Equipped with
A bonus is given to the player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information.
In the gaming machine, the numerical value information updating means starts updating the numerical value information from a predetermined initial value based on the acceptance of the initial value setting operation by the acceptance means.
Variation means (irregular delay circuit 602) for varying a period from the acceptance of the initial value setting operation to the update start timing from the predetermined initial value according to the acceptance timing of the initial value setting operation Or a game machine characterized by comprising a circuit for non-periodicalization.

  According to the feature E26, the update of the numerical information is started from the predetermined initial value based on the reception of the initial value setting operation by the reception unit. Here, since the period from the reception timing of the initial value setting operation to the update start timing at which updating of the numerical information is started fluctuates according to the reception timing, a variation occurs in the period from the reception timing to the update start timing. As a result, the period from the reception timing to the update start timing becomes irregular. Therefore, even if the numerical information updating means starts updating from the predetermined initial value, the period from the reception timing of the initial value setting operation to the numerical information becoming equal to the winning information becomes irregular. The period is difficult to grasp. Therefore, it is possible to suppress the fraudulent act of outputting a signal in accordance with the timing when the numerical information coincides with the winning information by the “hanging board” or the like to obtain the privilege illegally.

  In addition, the technical ideas shown in the features E5 to E18 and the features E21 to E24 can be applied to this feature. In this case, “based on the start of supply of the operation power to the control means” is replaced with “based on the reception of the initial value setting operation”.

  The "predetermined initial value" includes not only a predetermined initial value but also an initial value acquired from a means for generating predetermined initial value information.

  Each invention of the above-mentioned feature E group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Whether or not the jackpot state occurs is determined at the timing when the gaming ball enters the operation opening. For example, it has a counter that is regularly updated within a certain range (for example, 1 count is updated in the range of 0 to 300 every 2 ms), and acquires the value of the counter when the gaming ball enters the operation opening Then, when the value of the counter matches a predetermined value such as "7", for example, the player is given a benefit that the gaming state shifts to the jackpot state.

  Here, there is a case where a fraudulent act using a fraudulent board called "hanging board" is performed. The fraud is to cause the jackpot condition to occur illegally by hanging the wrong substrate against the regular control substrate. Specifically, a "hanging board" is provided by providing a counter synchronized with the counter used in the jackpot lottery on the "hanging board" and resetting the value of the counter to "0" in accordance with the power on of the pachinko machine etc. Understand the occurrence timing of the jackpot state inside. And according to the generation | occurrence | production timing of this big hit state, an incorrect entering detection signal is output with respect to a regular control board from a "hanging board", and a big hit state is produced illegally.

  On the other hand, a gaming machine may be considered in which the initial value of the update of the counter is changed every time the counter is rotated in the jackpot lottery. According to the gaming machine, the initial value of the update of the counter is changed for each rotation of the counter, so it becomes difficult to grasp the timing of occurrence of the jackpot by the “hanging board”. Furthermore, apart from the periodic updating process, the updating process of the initial value random number counter is performed in the remaining time of the predetermined loop process for performing the game control, so that the changed initial value can not be grasped.

  However, even with such a configuration, when initialization of the control board is performed at the time of recovery from a power failure, RAM clearing, etc., information such as values of various counters stored in storage means such as RAM is cleared. Therefore, immediately after initialization, the value of the random number counter used in the jackpot lottery or the initial value random number counter used when determining the initial value of the random number counter is set to a predetermined value such as "0". Be done. As a result, immediately after initialization of the control substrate, there is a possibility that the occurrence timing of the jackpot may be easily grasped by the “hanging substrate”. Therefore, there is a possibility that the fraudulent activity that performs the initialization process and generates a jackpot.

  In addition, in the gaming machine, various types of fraudulent activities are assumed, and as described above, the control body determines the predetermined processing timing and the like, and acts to perform the fraud based on the grasped result is the “hanging board” as described above. Other than act by. In addition, such fraud is not limited to the pachinko machine, and the same applies to the slot machine.

Feature F1. Numerical information updating means (an updating function of the big hit random number counter C1 of the counter updating circuit 701) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Numeric information acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of the predetermined acquisition condition (performing processing to store the big hit random number counter C1 of step S804 in the MPU 311 Function),
Equipped with
In a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the numerical information acquiring means corresponds to predetermined winning information.
In the situation where operating power is supplied to the control means for controlling the game, the initial value information is sequentially updated in the numerical range each time the update timing comes, and the operating power is not supplied to the control means Initial value information updating means (an updating function of the initial value random number counter CF of the counter updating circuit 701) configured to prevent initialization of the initial value information;
Initial value information acquiring means (function of executing an initial value setting process in the MPU 311) for acquiring the initial value information from the initial value information updating means based on the operation power supplied to the control means;
Equipped with
A gaming machine characterized in that, when the initial value information is acquired, the numerical information update means updates the numerical information from the acquired initial value information.

  According to the feature F1, based on the fact that the operation power is supplied to the control unit, the initial value information acquisition unit acquires initial value information, and the numerical value information is updated from the initial value information. Since the initial value information is sequentially updated under the condition where the operating power is supplied to the control means, the initial value information fluctuates according to the timing when the operating power is not supplied to the control means. Then, the initial value information is not initialized even in a situation where no operating power is supplied to the control means. As a result, the initial value information acquired by the initial value information acquisition means fluctuates. Therefore, since it is difficult to grasp the initial value information, it is possible to make it difficult to grasp the timing when the numerical information becomes the winning information. Therefore, it is possible to suppress the fraudulent acts due to the “hanging board” and the like.

Feature F2. Numerical information updating means (an updating function of the big hit random number counter C1 of the counter updating circuit 701) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Numeric information acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of the predetermined acquisition condition (performing processing to store the big hit random number counter C1 of step S804 in the MPU 311 Function),
Equipped with
In a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the numerical information acquiring means corresponds to predetermined winning information.
In the situation where operating power is supplied to the control means for controlling the game, the initial value information is sequentially updated in the numerical range each time the update timing comes, and the operating power is not supplied to the control means Initial value information updating means (the function of updating the initial value random number counter CF of the counter update circuit 701) for sequentially updating the initial value information;
Initial value information acquiring means (function of executing an initial value setting process in the MPU 311) for acquiring the initial value information from the initial value information updating means based on the operation power supplied to the control means;
Equipped with
A gaming machine characterized in that, when the initial value information is acquired, the numerical information update means updates the numerical information from the acquired initial value information.

  According to the feature F2, based on the fact that the operation power is supplied to the control means, the initial value information acquisition means acquires the initial value information, and the numerical value information is updated from the initial value information. Since the initial value information is updated even in a situation where no operating power is supplied to the control unit, the initial value information acquired by the initial value information acquiring unit is the operating power to the control unit. It fluctuates according to the timing when it is supplied. As a result, since it is difficult to grasp the initial value information, it is possible to make it difficult to grasp the timing when the numerical information becomes the winning information. Therefore, it is possible to suppress the fraudulent acts due to the “hanging board” and the like.

  In particular, in the case where the control unit is configured to hold the initial value information in a situation where the operation power is not supplied, the stored initial value information may be grasped by the “hanging board” or the like. On the other hand, according to this feature, since the initial value information is constantly updated, it is difficult to grasp the initial value information as compared with the configuration in which the initial value information is held. As a result, it is possible to more preferably suppress fraudulent acts due to "hanging board" and the like.

Feature F3. Storage means (RAM 316) for storing information used when the control means performs control relating to a game;
An initialization execution unit (function of executing the processing of step S408 and step S409 in the main processing of the MPU 311) that initializes the information stored in the storage unit when a predetermined initialization operation is received;
Equipped with
The gaming machine according to feature F1 or F2, wherein the initialization execution means is configured to exclude the initial value information from the targets of initialization.

  According to the feature F3, the initial value information is excluded from the target of initialization. Temporarily, when initial value information is the object of initialization, initialization is performed and initial value information becomes a predetermined numerical value. Then, since the numerical value is acquired by the initial value information acquisition means, the initial value information of the numerical information update means does not change when initialization is performed. On the other hand, in this feature, since the initial value information is excluded from the target of initialization, the initial value information is not affected by the initialization. Thereby, since the initial value information in the case where initialization is performed fluctuates, the fluctuation of the initial value information of the numerical information update means in the case where initialization is performed is secured. Therefore, it is possible to suppress the fraudulent act of grasping the initial value information by intentionally executing the initialization.

  Feature F4. In any one of the features F1 to F3, when the operating power is supplied to the control unit, the initial value information acquisition unit performs one round of updating of the numerical information of the numerical information update unit. A game machine for acquiring the initial value information.

  According to the feature F4, in the situation where the operation power is supplied to the control means, the initial value information of the initial value information update means is acquired every time the numerical information of the numerical information update means makes one turn, and the acquired Numerical information is updated from the initial value information. Thus, the initial value information updating means and the initial value information acquiring means are also used as initial value determining means for determining the initial value of the numerical information every time the numerical information of the numerical information updating means makes a round. Therefore, it is possible to reduce the processing load and simplify the configuration while making it difficult to grasp the timing at which the numerical information becomes the winning information.

  Feature F5. The variation means according to any one of the features F1 to F4, wherein a period from a supply start timing at which operating power to the control means is supplied to an acquisition timing for acquiring the initial value information is varied according to the supply start timing A game machine characterized by comprising (the irregular delay circuit 602 or the circuit for non-periodicalization).

  According to the feature F5, the period from the supply start timing to the acquisition timing of the initial value information is fluctuated by the fluctuation means. As a result, since the acquired initial value information fluctuates, the initial value information fluctuates when updating of the numerical information update means is started. Therefore, it is difficult to grasp the initial value information when the numerical information update means starts the update. Therefore, even when the supply start timing and the initial value information of the initial value information updating means are grasped by the “hanging board” or the like, it is difficult to grasp the timing when the numerical information becomes the winning information. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like.

  The technical ideas shown in the features E5 to E20 and the features E22 to E24 can be applied to this feature. In this case, "numerical information update means" is "initial value information acquisition means", "start update" is "acquire initial value information", "update start timing" is "initial value acquisition timing", It shall replace.

  Further, in the configuration provided with the feature F3, “a storage unit that stores information used when the control unit performs control, and stores and holds the information while power is supplied to itself” The storage means stores information used when performing control relating to a game while power is supplied to the storage means.

Feature F6. Numerical information updating means (an updating function of the big hit random number counter C1 of the counter updating circuit 701) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Numeric information acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of the predetermined acquisition condition (performing processing to store the big hit random number counter C1 of step S804 in the MPU 311 Function),
Start signal output means (RAM erase signal output circuit 802) for outputting a predetermined start signal (RAM erase signal) when a predetermined operation condition is satisfied;
Equipped with
A bonus is given to the player based on the fact that the numerical information acquired by the numerical information acquiring means corresponds to predetermined winning information.
In the gaming machine, the numerical value information updating means starts updating the numerical value information from a predetermined initial value based on the fact that the activation signal is outputted from the activation signal output means.
Initial value information updating means (an updating function of the initial value random number counter CF of the counter updating circuit 701) for sequentially updating the initial value information in the numerical value range each time the update timing comes;
Initial value information acquiring means (function of executing an initial value setting process in the MPU 311) for acquiring the initial value information from the initial value information updating means based on the input of the start signal;
Equipped with
When the initial value information is acquired by the initial value information acquisition unit, the numerical information update unit is configured to update the numerical information from the acquired initial value information. Machine.

  According to the feature F6, the initial value information is acquired based on the input of the activation signal to the initial value information acquiring means, and the numerical information is updated from the initial value information. Since the initial value information is sequentially updated each time the update timing is reached, the initial value information obtained according to the establishment timing of the predetermined operation condition fluctuates. As a result, since it is difficult to grasp the initial value information, it is possible to make it difficult to grasp the timing when the numerical information becomes the winning information. Therefore, it is possible to suppress the fraudulent acts due to the “hanging board” and the like.

  Feature F7. A variation unit (irregular delay circuit 602 or non-periodic circuit) that varies a period from establishment timing of the predetermined operation condition to acquisition timing of acquiring the initial value information in the feature F6 according to the establishment timing. A game machine characterized by comprising:

  According to the feature F7, the period from the establishment timing of the predetermined operation condition to the initial value information acquisition timing is fluctuated by the fluctuation means. As a result, since the acquired initial value information fluctuates, the initial value information fluctuates when updating of the numerical information update means is started. Therefore, it is difficult to grasp the initial value information when the numerical information update means starts the update. Therefore, even when the timing of establishment of the predetermined operation condition and the initial value information of the initial value information updating means are grasped by "hanging board" or the like, it is difficult to grasp the timing when the numerical information becomes winning information. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like.

  It is also possible to apply the technical ideas shown in the features E5 to E18 and the features E22 to E24 to this feature. In this case, "based on the supply of operating power to the control means being started", "based on the establishment of the predetermined operating conditions", and "numerical information updating means" as "initial value information It is assumed that “acquisition means”, “start update” is replaced with “acquire initial value information”, and “update start timing” is replaced with “initial value acquisition timing”.

Feature F8. Numerical information updating means (a function for executing the updating process of the jackpot random number counter C1 of the step S703 in the MPU 311) which sequentially updates numerical information in a predetermined numerical range each time an update timing comes;
Numeric information acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of the predetermined acquisition condition (performing processing to store the big hit random number counter C1 of step S804 in the MPU 311 Function),
Reception means for receiving a predetermined initial value setting operation (a power on RAM erase switch 801);
Equipped with
A bonus is given to the player based on the fact that the numerical information acquired by the numerical information acquiring means corresponds to predetermined winning information.
In the gaming machine, the numerical value information updating means starts updating the numerical value information from a predetermined initial value based on the acceptance of the initial value setting operation by the acceptance means.
Initial value information updating means (an updating function of the initial value random number counter CF of the counter updating circuit 701) for sequentially updating the initial value information in the numerical value range each time the update timing comes;
Initial value information acquisition means (function of executing an initial value setting process in the MPU 311) for acquiring the initial value information when the reception means receives the initial value setting operation;
Equipped with
When the initial value information is acquired by the initial value information acquisition unit, the numerical information update unit is configured to update the numerical information from the acquired initial value information. Machine.

  According to the feature F8, when the initial value setting operation is accepted by the accepting unit, the initial value information is acquired, and the numerical information is sequentially updated from the acquired initial value information. Since the initial value information is updated, the initial value information acquired for each initial value setting operation fluctuates. Thus, it is difficult to grasp the timing at which the numerical information becomes the winning information based on the initial value setting operation. Therefore, it is possible to suppress fraudulent acts such as "hanging board".

  Feature F9. Fluctuation means (irregular delay circuit) for fluctuating a period from the reception of the initial value setting operation to the acquisition of the initial value information according to the reception timing of the initial value setting operation in the feature F8 A game machine characterized by comprising the circuit 602 or the circuit for non-periodicalization.

  According to the feature F9, since the period from the reception timing of the initial value setting operation to the acquisition timing of acquiring the initial value information fluctuates according to the reception timing, from the reception of the initial value setting operation to the acquisition of the initial value information There is a variation in the period of As a result, the period from the initial value setting operation acceptance timing to the initial value information acquisition timing becomes irregular. Therefore, even if the initial value information of the initial value information updating means is grasped by "hanging board" etc., the period from the initial value setting operation acceptance timing to the coincidence of the numerical information with the winning information is grasped. Hateful. Therefore, it is possible to suppress the fraudulent act of outputting a signal in accordance with the timing when the numerical information coincides with the winning information by the “hanging board” or the like to obtain the privilege illegally.

  In addition, the technical ideas shown in the features E5 to E18 and the features E22 to E24 can be applied to this feature. In this case, "based on start of supply of operation power to the control means", "based on reception of the initial value setting operation", and "initial value information updating means" “Value information acquisition means”, “start update” is replaced with “acquire initial value information”, and “update start timing” is replaced with “initial value acquisition timing”.

  Each invention of the above-mentioned feature F group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Whether or not the jackpot state occurs is determined at the timing when the gaming ball enters the operation opening. For example, it has a counter that is regularly updated within a certain range (for example, 1 count is updated in the range of 0 to 300 every 2 ms), and acquires the value of the counter when the gaming ball enters the operation opening Then, when the value of the counter matches a predetermined value such as "7", for example, the player is given a benefit that the gaming state shifts to the jackpot state.

  Here, there is a case where a fraudulent act using a fraudulent board called "hanging board" is performed. The fraud is to cause the jackpot condition to occur illegally by hanging the wrong substrate against the regular control substrate. Specifically, a "hanging board" is provided by providing a counter synchronized with the counter used in the jackpot lottery on the "hanging board" and resetting the value of the counter to "0" in accordance with the power on of the pachinko machine etc. Understand the occurrence timing of the jackpot state inside. And according to the generation | occurrence | production timing of this big hit state, an incorrect entering detection signal is output with respect to a regular control board from a "hanging board", and a big hit state is produced illegally.

  On the other hand, a gaming machine may be considered in which the initial value of the update of the counter is changed every time the counter is rotated in the jackpot lottery. According to the gaming machine, the initial value of the update of the counter is changed for each rotation of the counter, so it becomes difficult to grasp the timing of occurrence of the jackpot by the “hanging board”. Furthermore, apart from the periodic updating process, the updating process of the initial value random number counter is performed in the remaining time of the predetermined loop process for performing the game control, so that the changed initial value can not be grasped.

  However, even with such a configuration, when initialization of the control board is performed at the time of recovery from a power failure, RAM clearing, etc., information such as values of various counters stored in storage means such as RAM is cleared. Therefore, immediately after initialization, the value of the random number counter used in the jackpot lottery or the initial value random number counter used when determining the initial value of the random number counter is set to a predetermined value such as "0". Be done. As a result, immediately after initialization of the control substrate, there is a possibility that the occurrence timing of the jackpot may be easily grasped by the “hanging substrate”. Therefore, there is a possibility that the fraudulent activity that performs the initialization process and generates a jackpot.

  In addition, in the gaming machine, various types of fraudulent activities are assumed, and as described above, the control body determines the predetermined processing timing and the like, and acts to perform the fraud based on the grasped result is the “hanging board” as described above. Other than act by. In addition, such fraud is not limited to the pachinko machine, and the same applies to the slot machine.

Feature G1. When the predetermined condition defined in advance is satisfied, the update clock signal is output at a predetermined period, while the output of the update clock signal is stopped in the situation where the predetermined condition is not satisfied. Update signal output means (hard random number clock circuit 313);
Numerical information updating means (updating function of jackpot random number counter C1) for sequentially updating numerical information within a predetermined numerical range based on the input of the updating clock signal from the updating signal output means;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Equipped with
It is a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information,
Variation means (irregular delay circuit) for varying the period from the satisfaction timing of the predetermined condition to the input timing to which the clock signal for update is input to the numerical information updating device according to the satisfaction timing of the predetermined condition A game machine characterized by comprising the circuit 602 or the circuit for non-periodicalization.

  According to the feature G1, when the predetermined condition is satisfied, the update signal output unit outputs the update clock signal. Then, when the update clock signal is input to the numerical information update means, the numerical information is updated.

  Here, the period from the establishment timing of the predetermined condition to the input timing at which the update clock signal is input to the numerical information update means fluctuates according to the establishment timing of the predetermined condition. As a result, since a variation occurs in the period from the establishment timing of the predetermined condition to the input timing, the period becomes irregular. Therefore, since it is difficult to grasp the period from the establishment timing of the predetermined condition to the timing when the numerical information becomes the win information, it is difficult to grasp the timing when the numerical information becomes the win information even if the establishment timing of the predetermined condition is grasped. Therefore, it is possible to suppress fraudulent acts such as "hanging board".

Feature G2. Power means (power supply and emission control board 321) connected to an external power supply to supply power;
While outputting the update clock signal at a predetermined cycle based on the supply of power to the power means, in a situation where the supply of power to the power means is stopped, the update clock signal Updating signal output means (hard random number clock circuit 313) for stopping the output of
Numerical information updating means (updating function of jackpot random number counter C1) for sequentially updating numerical information within a predetermined numerical range based on the input of the updating clock signal from the updating signal output means;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Equipped with
It is a gaming machine in which a bonus is given to a player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information,
The period from the supply start timing at which the operation power is supplied to the power unit to the input timing at which the update clock signal is input to the numerical information update unit is varied according to the supply start timing. A game machine characterized by comprising variation means (irregular delay circuit 602 or non-periodic circuit).

  According to the feature G2, based on the fact that power is supplied to the power means, the update signal output means outputs the update clock signal, and the numerical information is updated based on the input of the update clock signal. To be done.

  Here, the period from the supply start timing of the power to the power unit to the input timing when the update clock signal is input to the numerical information update unit fluctuates according to the supply start timing. As a result, since the period varies, the period becomes irregular. Therefore, even if the numerical information update means starts updating from the predetermined initial value, it is difficult to grasp the period from the supply start timing until the numerical information becomes the winning information. Therefore, it is possible to suppress fraudulent acts due to "hanging board" and the like.

Feature G3. Supply means (a function for supplying operating power to the main control board 301 of the power supply and emission control board 321) which is in a supply state for supplying a signal or electric power based on the start of the power supply to the power means. ,
A supply path connecting the supply means and the updating signal output means;
Equipped with
The update signal output unit outputs the update clock signal when the supply unit is in the supply state and the signal or power supplied from the supply path is in a predetermined operable state. And
The fluctuation means is provided at an intermediate position of the supply path, and fluctuates a period from the timing of the supply state to the timing of the operable state according to the timing of the supply state. The gaming machine according to feature G2, which is a feature.

  According to the feature G3, the updating signal output unit and the supplying unit are connected via the supply path. The supply means is in a supply state for supplying a signal or power based on the start of the power supply to the power means. Further, when the supply means is in the supply state and the state of the signal or power supplied from the supply path is in a predetermined operable state, the update clock signal is output. Here, the fluctuation means is provided at an intermediate position of the supply path, and the period from the timing of the supply state to the timing of the operable state fluctuates according to the timing of the supply state. As a result, the period from the timing when the power is supplied to the time when the power is enabled becomes irregular, so that the update start timing when the update of the numerical information is started from the supply start timing when the power is supplied to the power unit. Until the period becomes irregular. Therefore, since the period from the supply start timing to the numerical information becoming the winning information becomes irregular, it is difficult to grasp the period. Therefore, it is possible to prevent fraudulent acts using the "hanging board" or the like.

  In addition, the technical ideas shown in the features E6 to E20 and the features E23 to E24 can be applied to this feature. In this case, "control means" is replaced with "power means".

Feature G4. A power supply path connecting the power means and the updating signal output means;
The power means is in a supply state for supplying operating power to the updating signal output means based on the start of supply of power from the external power supply,
The update signal output unit is configured to output the update clock signal based on the fact that the power unit is in the supply state and the operating power is supplied from the power supply path.
The variation means is provided at an intermediate position of the power supply path, and a period from the timing when the supply state is reached to the time when the operation signal is supplied to the updating signal output means is the timing when the supply state is reached. The gaming machine according to feature G2, characterized in that it is varied.

  According to the feature G4, the period from the timing when the power means is in the supply state to the time when the operation power is supplied to the updating signal output means fluctuates according to the timing when the supply state is. As a result, the period from the supply start timing at which power is supplied to the power unit to the update start timing of the numerical information by the numerical information update unit fluctuates, making it difficult to specify the update start timing. Therefore, since it is difficult to specify the timing at which the numerical information becomes the win information, it is possible to suppress the fraudulent acts using the “hanging board” or the like.

  In addition, the technical ideas shown in the features E6 to E20 and the features E23 to E24 can be applied to this feature. In this case, "control means" is replaced with "power means".

Feature G5. The variation means is a situation where operating power is supplied from the power means, and further, when a predetermined instruction signal is input, the operating power from the power means is used as the updating signal output means. Power transfer means (amplifying circuit 912) for transferring
Based on the fact that the power means is in the supply state, the instruction signal is output to the power transfer means, and until the instruction signal is output from the timing when the power means is in the supply state Command signal output means (irregular delay circuit 602) for changing the period of time according to the timing at which the supply state is reached;
The gaming machine according to feature G4, comprising:

  According to the feature G5, the operation power is supplied to the update signal output means by the input of the instruction signal, and the output timing of the instruction signal fluctuates with respect to the timing when the power means is in the supply state. doing. That is, the control for changing the timing at which the operation power is supplied to the updating signal output means with respect to the timing when the supply state is achieved is realized by signal control. As a result, compared to power control, fluctuating control can be easily performed, and loss of power consumption associated with the control can be suppressed.

Feature G6. A signal path connecting the update signal output unit and the numerical information update unit;
The variation means is provided at an intermediate position of the signal path, and the input signal is supplied to the numerical information update means at an output timing at which the update signal output means outputs the update clock signal. The gaming machine according to feature G2, wherein a period until timing is changed according to the output timing.

  According to the feature G6, since the input timing at which the update clock signal is input to the numerical information update unit fluctuates with respect to the output timing at which the update clock signal is output from the update signal output unit, the numerical information is changed. The update start timing of is fluctuating. Thereby, since it is difficult to grasp the update start timing of the numerical information, it is possible to suppress the fraudulent act using the “hanging board” or the like.

Feature G7. It further comprises a signal path connecting the updating signal output means and control means for controlling the game,
The control means performs control relating to a game based on the fact that the update clock signal is input via the signal path,
The update signal output unit outputs the update clock signal to the control unit based on the fact that power is supplied to the power unit, and the update of the numerical information update unit is performed. A game machine according to feature G6, characterized in that it outputs a clock signal.

  According to the feature G7, the signal path connecting the updating signal output means and the control means separately from the signal path connecting the updating signal output means and the numerical information updating means (hereinafter referred to as the first signal path) A game-related control is performed based on the fact that an update clock signal is input to the control means via the second signal path (hereinafter referred to as a second signal path). In this way, updating of the numerical information and control regarding the game are performed by the updating clock signal.

  Here, since the variation means is provided only on the first signal path and the variation means is not provided on the second signal path, the input timing of the update clock signal to the control means does not vary. As a result, even if the input timing of the update clock signal to the numerical information update means fluctuates, the control regarding the game is performed at a constant timing. Therefore, it is possible to suppress fraudulent acts using the “hanging board” or the like without affecting the control relating to the game.

Feature G8. The variation means, based on the input of the update clock signal from the update signal output means, relays the relay result signal identical to or corresponding to the update clock signal through the signal path to the numerical information update means The period from the output timing of the update clock signal to the output timing of the relay result signal is varied according to the output timing of the update clock signal,
The gaming machine according to feature G6, wherein the numerical information updating means updates the numerical information based on the fact that the relay result signal is input.

  According to the feature G8, when the update clock signal is input to the variation unit, the relay result signal that is the same as or corresponds to the update clock signal is output to the numerical information update unit. Numerical value information is updated by inputting the relay result signal to the numerical value information updating means. Here, the period from the output timing of the update clock signal to the output timing of the relay result signal fluctuates according to the output timing of the update clock signal. Thus, it is difficult to grasp the start timing of the update by the numerical information update means. Therefore, it is possible to prevent fraudulent acts using the “hanging board” or the like.

  In particular, the cycle of the relay result signal may be set to be different from the cycle of the update clock signal. In this case, the update timing of the numerical information based on the relay result signal is different from the update timing based on the update clock signal. As a result, even when the cycle of the update clock signal is grasped, it is difficult to grasp the update timing of the numerical information. Therefore, by specifying the period of the update clock signal, it is possible to suppress the cheating that specifies the update timing of the numerical information.

Feature G9. Gaming signal output means (system clock circuit 312) for outputting a gaming clock signal at a predetermined cycle based on the supply of power to the power means;
A control unit (a function of executing processing in the MPU 311 to execute the processing of the game) on the basis of the input of the game clock signal from the game signal output unit;
The gaming machine according to any one of Features G2 to G8, further comprising:

  According to the feature G9, since the control relating to the game is performed based on the gaming clock signal different from the renewal clock signal, the renewal clock with respect to the supply start timing at which the operating power is supplied to the power unit. Even when the output timing of the signal fluctuates, control regarding the game is performed at a fixed timing. Thereby, it is possible to suppress the fraudulent acts using the “hanging board” or the like without affecting the control regarding the game.

Feature G10. Update signal output means (hard random number clock circuit 313) for outputting an update clock signal at a predetermined cycle;
Numerical information updating means (updating function of jackpot random number counter C1) for sequentially updating numerical information within a predetermined numerical range based on the input of the updating clock signal from the updating signal output means;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of a predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 in step S804 in the MPU 311) When,
Start signal output means (data erase signal output circuit 1002) for outputting a start signal (data erase signal) when an operating condition is satisfied;
Equipped with
A bonus is given to the player based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined winning information.
In the gaming machine, the numerical value information updating means starts updating the numerical value information from a predetermined initial value based on the fact that the activation signal is outputted from the activation signal output means.
Start signal handling means for temporarily stopping input of the update clock signal to the numerical information update means based on the start signal output means from the start signal output means, and thereafter resuming input (data erase A signal output circuit 1002 and a reset transistor 1003),
Variation means (irregular delay circuit) for varying the period from the formation timing of the operating condition to the input timing at which the clock signal for update is input to the numerical information updating means according to the formation timing of the operating condition 602 or a circuit for non-periodical operation)
A game machine characterized by comprising:

  According to the feature G10, the activation signal is output from the activation signal output unit when the operation condition is satisfied (for example, the switch provided on the gaming machine is operated). In response to the output of the start signal, the input of the update clock signal to the numerical information update means is temporarily stopped. As a result, updating of numerical information is temporarily stopped. Thereafter, the input of the update clock signal is resumed, and the updating of the numerical information is performed from a predetermined initial value.

  Here, the period from the establishment timing of the operating condition to the input timing at which the update clock signal is input to the numerical information updating means fluctuates according to the formation timing of the operating condition. As a result, the period from the establishment timing of the operating condition to the update start timing of the numerical information fluctuates. Therefore, since it becomes difficult to specify the update start timing of the numerical information, it is possible to suppress the fraudulent acts such as the “hanging board”.

  In addition, the technical ideas shown in the features E6 to E18 and the features E23 to E24 can be applied to this feature. In this case, "based on the start of supply of operating power to the control means" is replaced with "based on the establishment of the operating condition".

  The "predetermined initial value" includes not only a predetermined initial value but also an initial value acquired from a means for generating predetermined initial value information.

Feature G11. Power means (power supply and emission control board 321) which is connected to an external power supply and is in a supply state for supplying power to the updating signal output means based on start of supply of power from the external power supply;
A power supply path connecting the power means and the updating signal output means;
Equipped with
The update signal output unit is configured to output the update clock signal based on the fact that the power unit is in the supply state and the operating power is supplied from the power supply path.
The variation means is provided at an intermediate position of the power supply path, and based on the fact that the operation power is supplied from the power means, the operation power is supplied to the updating signal output means through the power supply path. And a period from the timing when the operating power is supplied from the power unit to the timing when the operating power is supplied to the updating signal output unit according to the timing when the operating power is supplied. To change,
The start signal handling means temporarily stops the supply of the operating power from the power means to the variation means based on the fact that the start signal is outputted from the start signal output means, and then resumes the supply thereafter. The gaming machine according to feature G10, characterized in that

  According to the feature G11, when the operating power is supplied from the power unit to the varying unit, the operating power is supplied from the varying unit to the updating signal output unit. Here, since the timing at which the operating power is supplied to the updating signal output unit fluctuates with respect to the timing at which the operating power is supplied to the changing unit, the updating is performed from the timing at which the power unit is supplied. The period until the timing when the clock signal is output fluctuates. Accordingly, it is possible to suppress the cheating that specifies the update start timing of the numerical information in synchronization with the power supply unit starting the power supply.

  Furthermore, when the start signal is output, the power supply from the power unit to the variation unit is temporarily stopped. After that, when the power supply is resumed, the operating power is supplied to the updating signal output unit through the fluctuation unit. In this case, the timing at which the operating power is supplied to the updating signal output unit fluctuates with respect to the timing at which the power supply is resumed. Accordingly, it is difficult to grasp the start timing of the update of the numerical information in synchronization with the satisfaction of the operating condition.

  From the above, it is understood that the fraudulent operation of specifying the update start timing of the numerical information in synchronization with the supply state of the power unit and the update of the numerical information in synchronization with the establishment of the predetermined condition It is possible to suppress both fraudulent activities that specify the start timing.

  Moreover, it is also possible to apply the technical feature shown to the feature G6 to this feature.

Feature G12. Game signal output means (system clock circuit 312) for outputting a game clock signal at a predetermined cycle;
Control means (function to execute various processes in the MPU 311) for performing control relating to a game based on the input of a game clock signal from the game signal output means;
The gaming machine according to Feature G10 or Feature G11, further comprising:

  According to the feature G12, since the control relating to the game is performed based on the gaming clock signal different from the renewal clock signal, the output timing of the renewal clock signal fluctuates with respect to the establishment timing of the operation condition. Even if there is, control regarding the game is performed at a fixed timing. Thereby, it is possible to suppress the fraudulent acts using the “hanging board” or the like without affecting the control regarding the game.

Feature G13. Game signal output means (system clock circuit 312) for outputting a game clock signal at a predetermined cycle;
Control means (function to execute various processes in the MPU 311) for performing control relating to a game based on the game clock signal being input from the game signal output means;
Update signal output means (hard random number clock circuit 313) for outputting an update clock signal at a specific cycle;
Numerical information updating means (updating function of jackpot random number counter C1) for sequentially updating numerical information within a predetermined numerical range based on the input of the updating clock signal from the updating signal output means;
Acquisition means for acquiring the numerical information updated by the numerical information update means based on the establishment of the predetermined acquisition condition (function to execute the process of storing the jackpot random number counter C1 of the step S307 in the MPU 311) When,
Privilege giving means (function of executing the process of step S503 in the MPU 311) for giving a player a privilege based on the fact that the numerical information acquired by the acquiring means corresponds to predetermined winning information;
Equipped with
A gaming machine characterized in that the gaming clock signal and the updating clock signal have different cycles.

  According to the feature G13, since the gaming clock signal and the updating clock signal have different cycles from each other, the output timing of the updating clock signal is even when the cycle of the gaming clock signal is known. It is hard to be grasped. Thus, it is possible to specify the update timing of the numerical information from the cycle of the gaming clock signal, and to suppress the fraudulent act of specifying the timing when the numerical information becomes the winning information.

  Note that the updating signal output unit and the gaming signal output unit may be configured to individually output a clock signal, or may be configured to output its own clock signal by converting the clock signal output from one of them. It may be

  Feature G14. The gaming machine according to feature G13, wherein the gaming clock signal and the updating clock signal are set such that the other cycle is not synchronized with one cycle.

  According to the feature G14, since the period of the gaming clock signal and the period of the updating clock signal are not synchronized with each other, the synchronization timing of the updating clock signal is grasped by synchronizing with the gaming clock signal. Things are getting harder. Thus, by synchronizing with the gaming clock signal, it is possible to grasp the synchronization timing of the updating clock signal and to suppress the fraudulent act of grasping the updating timing of the numerical information by the numerical information updating means.

  Each invention of the above-mentioned feature G group is effective to the following subject.

  There is a pachinko machine as a type of gaming machine. In a pachinko machine, for example, a jackpot lottery is performed based on the game ball launched into the game area entering the operation opening. When the jackpot is won in the lottery, for example, after the symbols variably displayed on the predetermined display device are stopped and displayed in a predetermined specific combination, the opening and closing of the variable ball entry device provided in the game area is performed. To be executed. Then, a bonus is given to the player that the game ball is paid out according to the number of ball entry into the variable ball entry device.

  Whether or not the jackpot state occurs is determined at the timing when the gaming ball enters the operation opening. For example, it has a counter that is regularly updated within a certain range (for example, 1 count is updated in the range of 0 to 300 every 2 ms), and acquires the value of the counter when the gaming ball enters the operation opening Then, when the value of the counter matches a predetermined value such as "7", for example, the player is given a benefit that the gaming state shifts to the jackpot state.

  Here, there is a case where a fraudulent act using a fraudulent board called "hanging board" is performed. The fraud is to cause the jackpot condition to occur illegally by hanging the wrong substrate against the regular control substrate. Specifically, a "hanging board" is provided by providing a counter synchronized with the counter used in the jackpot lottery on the "hanging board" and resetting the value of the counter to "0" in accordance with the power on of the pachinko machine etc. Understand the occurrence timing of the jackpot state inside. And according to the generation | occurrence | production timing of this big hit state, an incorrect entering detection signal is output with respect to a regular control board from a "hanging board", and a big hit state is produced illegally.

  On the other hand, a gaming machine may be considered in which the initial value of the update of the counter is changed every time the counter is rotated in the jackpot lottery. According to the gaming machine, the initial value of the update of the counter is changed for each rotation of the counter, so it becomes difficult to grasp the timing of occurrence of the jackpot by the “hanging board”. Furthermore, apart from the periodic updating process, the updating process of the initial value random number counter is performed in the remaining time of the predetermined loop process for performing the game control, so that the changed initial value can not be grasped.

  However, even with such a configuration, when initialization of the control board is performed at the time of recovery from a power failure, RAM clearing, etc., information such as values of various counters stored in storage means such as RAM is cleared. Therefore, immediately after initialization, the value of the random number counter used in the jackpot lottery or the initial value random number counter used when determining the initial value of the random number counter is set to a predetermined value such as "0". Be done. As a result, immediately after initialization of the control substrate, there is a possibility that the occurrence timing of the jackpot may be easily grasped by the “hanging substrate”. Therefore, there is a possibility that the fraudulent activity that performs the initialization process and generates a jackpot.

  In addition, in the gaming machine, various types of fraudulent activities are assumed, and as described above, the control body determines the predetermined processing timing and the like, and acts to perform the fraud based on the grasped result is the “hanging board” as described above. Other than act by. In addition, such fraud is not limited to the pachinko machine, and the same applies to the slot machine.

  Hereinafter, basic configurations of various game machines to which the above-described features can be applied will be described.

  Pachinko gaming machine: operation means operated by a player, game ball firing means for firing game balls based on the operation of the operation means, a ball passage for guiding the fired game balls to a predetermined game area, and a game A gaming machine comprising: each gaming component arranged in an area, and providing a bonus to a player when a gaming ball passes through a predetermined passing portion of the gaming components.

  Throttle type gaming machines such as slot machines: A pattern display device for variably displaying a plurality of patterns, variable display of the plurality of patterns is started due to the operation of the start operation means, and the cause is due to the operation of the stop operation means A game machine, wherein variable display of the plurality of symbols is stopped, and a privilege is given to the player according to the symbols after the stop.

  10: Pachinko machine as a gaming machine, 162: main control device, 243: power supply and discharge control device, 301: main control board, 302: electrical disconnection monitoring board, 311: MPU, 312: system clock circuit, 313: hard Clock circuit for random number, 314: Modulation circuit, 401: Frequency conversion circuit, 402: Signal conversion circuit, 501: Clock conversion circuit, 601: Reset circuit, 602: Irregular delay circuit, 701: Counter update circuit, 802: RAM erase Signal output circuit 900: hard random number clock circuit 901: power transfer circuit 1002: data erase signal output circuit 1101: clock signal transfer circuit.

Claims (1)

Gaming signal output means for outputting a gaming clock signal;
Control means for controlling the progress of the game based on the game clock signal being input from the game signal output means;
Numerical information updating means for sequentially updating numerical information within a predetermined numerical range each time an update timing is reached;
Acquisition means for acquiring the numerical information from the numerical information update means when predetermined acquisition conditions are satisfied;
Equipped with
In a gaming machine which is in a specific state based on the fact that the numerical information acquired by the acquisition means corresponds to predetermined specific information,
The game signal output means is provided separately from the game signal output means, and includes update signal output means for outputting an update clock signal so as not to be synchronized with the game clock signal.
The numerical information update means sequentially updates the numerical information based on the input of the update clock signal, using a predetermined place from the rise to the fall of the update clock signal as a trigger.
A variable means for changing an interval to be updated from the numerical information of 1 to the next numerical information;
The variation means varies the period required for the numerical information to make one revolution in response to the numerical information making one revolution by changing the period in which the numerical information becomes the specific information. The period in which the numerical information is the specific information is sequentially transitioned to any of a plurality of types of periods, and the unit period for the plurality of specific cycles of the numerical information is required to be specified. The ratio of the period in which the numerical information is the specific information is the same or substantially the same for each unit period,
The numerical value information updating means is configured to repeat the updating of the numerical value information corresponding to the update group having a plurality of update timings and having a plurality of types of update intervals, in the unit of the update group.
The numerical range and the update timing are set such that the number of terms in the numerical sequence constituted by the numerical values that can be acquired by the numerical information is not a multiple of the number of update timings included in the update group. Gaming machine.

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