JP2019062388A - Radiation imaging system, dynamic image generation method and program - Google Patents

Abstract

To provide a technology that is advantageous to reduction in noise of a frame image.SOLUTION: A radiation imaging system for generating a dynamic image comprises: a plurality of pixels each having a signal generation unit that converts radiation into electric charges; a reading circuit that reads out from each pixel an accumulation signal outputted by the signal generation unit depending on accumulated electric charges, and a reset signal outputted by the signal generation unit that is in a reset state; a storage unit that can store data; and a signal processing unit. The signal processing unit stores in the storage unit a correction image generated on the basis of the reset signal and the accumulation signal read out from each pixel, before first radiation irradiation, and in each frame time period, generates a frame image on the basis of a radiation image generated on the basis of the accumulation signal read out from each pixel, a reset image generated on the basis of the reset signal read out from each pixel, and the correction image stored in the storage unit.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a radiation imaging system, a moving image generation method, and a program.

  In the field of radiation imaging devices, large-area flat panel radiation imaging devices of an equal-magnification optical system using photoelectric conversion elements have become widespread in order to improve resolution, reduce the volume, and suppress distortion of images. Patent Document 1 describes that a noise component caused by a dark current or the like is removed by subtracting an offset image generated without radiation irradiation from a radiation image to generate a frame image. . Also, a radiation image is generated by subtracting the noise signal held in the second sample and hold circuit from the light signal held in the first sample and hold circuit.

JP, 2016-95278, A

  Due to semiconductor elements such as an amplification transistor, a constant current source, and a switch included in the radiation imaging apparatus, 1 / f noise and noise due to temperature drift occur in the offset image and the radiation image. Since these noises fluctuate with time, if the time interval between offset image acquisition and radiation image acquisition is long, the difference between the noise included in each of the radiation image and the offset image becomes large, and the noise is sufficiently reduced from the frame image Can not. Some aspects of the present invention aim to provide an advantageous technique for reducing the noise of a frame image.

  In view of the above problems, a radiation imaging system for generating a moving image, the plurality of pixels each having a signal generation unit for converting radiation into charge, and the signal generation according to charges accumulated from each pixel A readout circuit for reading out an accumulation signal output from the storage unit and a reset signal output from the signal generation unit in a reset state; a storage unit capable of storing data; and a signal processing unit; Stores the correction image generated based on the reset signal read from each pixel and the accumulated signal before the first radiation irradiation, and reads out from each pixel in each frame period. The radiation image generated based on the accumulated signal, the reset image generated based on the reset signal read from each pixel, and the correction image stored in the storage unit Radiation imaging system is provided, characterized in that to generate the frame image based on and.

  By the above means, the noise of the frame image is reduced.

It is an equivalent circuit diagram explaining the composition of the pixel of some embodiments of the present invention. It is an equivalent circuit diagram explaining the composition of the pixel array of some embodiments of the present invention, and a signal read-out part. It is a schematic diagram explaining the structure of the radiation imaging system of the one part embodiment of this invention. It is a time chart which shows an example of the drive method at the time of video recording of some embodiments of the present invention. 5 is a flowchart illustrating an example of a process for generating a correction image according to some embodiments of the present invention. 5 is a flowchart illustrating an example of a process of generating a frame image according to some embodiments of the present invention. It is a time chart which shows an example of the drive method which reads a signal with a plurality of sensitivity of some embodiments of the present invention. 5 is a flowchart illustrating an example of a process for generating a correction image with multiple sensitivities of some embodiments of the present invention. 5 is a flowchart illustrating an example of a process for generating frame images with multiple sensitivities of some embodiments of the present invention.

  Embodiments of the invention will now be described with reference to the accompanying drawings. Like elements are given the same reference numerals throughout the various embodiments and duplicate descriptions are omitted. In addition, each embodiment can be appropriately changed and combined. Embodiments described below relate to a radiation imaging apparatus such as a digital X-ray imaging apparatus and a radiation imaging system. The radiation imaging system generates, inter alia, moving images.

First Embodiment
FIG. 1 is an equivalent circuit diagram illustrating a schematic circuit of one pixel P in a radiation imaging apparatus 100 (FIG. 3) according to some embodiments of the present invention. The pixel P includes a conversion unit CP, an amplification unit AP, a reset unit RP, holding units SH1 to SH3, and output units OP1 to OP3. In the following example, each of these configurations is comprised of a circuit. For example, the conversion unit CP is configured by a conversion circuit.

  The conversion unit CP includes a photodiode PD, a transistor M1, a floating diffusion capacitance Cfd (hereinafter referred to as an FD capacitance Cfd), and an additional capacitance Cfd 'for sensitivity switching. The photodiode PD is an example of a photoelectric conversion element, and converts light generated in response to radiation incident on a scintillator that is a wavelength converter into charge. That is, a conversion element for converting radiation into charge is constituted by the wavelength converter for converting radiation into light and the photoelectric conversion element for converting light into charge. Instead of this, as the conversion element, an element that converts radiation directly into electric charge may be used. A charge corresponding to the radiation is generated by the photodiode PD, and the voltage of the FD capacitance Cfd corresponding to the generated charge amount is output to the amplification unit AP. The sensitivity switching capacitor Cfd 'is used to switch the sensitivity of the pixel P to radiation, and is connected to the photodiode PD via the transistor M1 (switch element). As the WIDE signal is activated, the transistor M1 is turned on, and the voltage of the combined capacitance of the FD capacitance Cfd and the capacitance Cfd 'is output to the amplification unit AP. That is, by controlling the conduction state of the transistor M1, a high sensitivity signal, which is a voltage corresponding to the charges converted by the high sensitivity converter CP, and a voltage corresponding to the charges converted by the low sensitivity converter CP. The low sensitivity signal which is

  The amplification unit AP includes a control transistor M3, an amplification transistor M4, a clamp capacitance Ccl, a control transistor M6, an amplification transistor M7, and respective constant current sources. The control transistor M3, the amplification transistor M4, and the constant current source (for example, a transistor having a current mirror configuration) are connected in series so as to form a current path. The activation of the enable signal EN input to the gate of the control transistor M3 causes the amplification transistor M4 receiving the voltage from the conversion unit CP to be in the operating state. Thus, a source follower circuit is formed, and a voltage obtained by amplifying the voltage from the conversion unit CP is output from the amplification transistor M4. The voltage output from the amplification transistor M4 is input to the amplification transistor M7 via the clamp capacitance Ccl. The control transistor M6, the amplification transistor M7, and the constant current source are connected in series so as to form a current path. As the enable signal EN input to the gate of the control transistor M6 is activated, the amplification transistor M7 receiving the voltage from the amplification transistor M4 is put into operation. Thus, a source follower circuit is formed, and a voltage obtained by amplifying the voltage from the amplification transistor M4 is output from the amplification transistor M7. The clamp capacitance Ccl is disposed in series between the amplification transistor M4 and the amplification transistor M7. The clamp operation by the clamp capacitance Ccl will be described together with the reset unit RP described later.

  The reset unit RP includes a reset transistor M2 and a reset transistor M5. The reset transistor M2 supplies a predetermined potential to the photodiode PD when the reset signal PRES is activated, thereby resetting (initializing) the charge of the photodiode PD and resetting the voltage output to the amplification unit AP Do. The reset transistor M5 resets the voltage output from the amplification transistor M7 by supplying a predetermined potential to the connection node between the clamp capacitance Ccl and the amplification transistor M7. A voltage corresponding to the voltage from the conversion unit CP at the time of reset by the reset transistor M2 is input to the input terminal n1 of the clamp capacitance Ccl. Further, activation of the clamp signal PCL turns on the reset transistor M5, and the clamp voltage VCL, which is a predetermined potential, is input to the output terminal n2 of the clamp capacitance Ccl. In this manner, the potential difference generated between both terminals of the clamp capacitance Ccl is clamped as a noise component, and the voltage changed with the subsequent generation and accumulation of charges in the photodiode PD is output as a signal component. This is the clamp operation using the clamp capacitance Ccl, and the clamp operation suppresses noise components such as kTC noise generated in the conversion unit CP and an offset of the amplification transistor M4.

  The conversion unit CP and the amplification unit AP constitute a signal generation unit that converts radiation into charge and generates a signal based on the charge accumulated in the conversion unit CP. A signal corresponding to the accumulated charge is called an accumulation signal. The charge stored in the conversion unit CP includes a charge generated according to radiation and a charge generated without radiation (so-called dark charge). The accumulated signal is based on the high sensitivity signal or the low sensitivity signal described above. A signal generated by the signal generation unit is called a reset signal when the reset unit RP resets the signal generation unit to a state before charge accumulation. As described above, the signal generation unit is reset by resetting the potential of the photoelectric conversion element PD and the potential of the output terminal n2 of the clamp capacitor Ccl. The accumulation signal and the reset signal are collectively referred to as a pixel signal. The pixel signal output from the signal generation unit after the charge is accumulated in the conversion unit CP is the accumulation signal, and the pixel signal output when the signal generation unit is in the reset state is the reset signal.

  The holding unit SH1 is a portion capable of holding the pixel signal output from the amplification unit AP, and is a sample hold circuit including the transfer transistor M8 and the holding capacitance CS1. Specifically, sampling is performed to transfer and hold the pixel signal to the capacitor CS1 by switching the state (conductive state or non-conductive state) of the transfer transistor M8 using the sample hold control signal TS1. The output unit OP1 includes a signal amplification transistor M10 and an output switch SW9. The signal amplification transistor M10 is a transistor for amplifying and outputting the pixel signal held by the holding capacitance CS1, and the output switch SW9 is a switch for transferring the pixel signal outputted by the signal amplification transistor M10. Specifically, when the output switch SW9 is turned on by the vertical scanning signal VSR input to the output switch SW9, the source of the signal amplification transistor M10 and the constant current source CCSp of the subsequent stage connected by the column signal line 406 A follower circuit is formed. Accordingly, the pixel signal held in the holding unit SH1 is amplified by the output unit OP1 and output from the pixel P. Hereinafter, the amplified pixel signal output from the pixel P is referred to as a pixel signal S1. Also, when the pixel signal is an accumulation signal, it is called accumulation signal S1, and when it is a reset signal, it is called reset signal S1.

  The holding unit SH2 is a portion capable of holding the pixel signal output from the amplification unit AP, and is a sample hold circuit including the transfer transistor M11 and the holding capacitance CS2. Specifically, sampling is performed by transferring the pixel signal to the capacitor CS2 and holding the pixel signal by switching the state (conductive state or non-conductive state) of the transfer transistor M11 using the sample hold control signal TS2. The output part OP2 includes a signal amplification transistor M13 and an output switch SW12. The signal amplification transistor M13 is a transistor for amplifying and outputting the pixel signal held by the holding capacitance CS2, and the output switch SW12 is a switch for transferring the pixel signal outputted by the signal amplification transistor M13. Specifically, when the output switch SW12 is turned on by the vertical scanning signal VSR input to the output switch SW12, the source of the signal amplification transistor M13 and the constant current source CCSp of the subsequent stage connected by the column signal line 407 A follower circuit is formed. Accordingly, the pixel signal held in the holding unit SH2 is amplified by the output unit OP2 and output from the pixel P. Hereinafter, the amplified pixel signal output from the pixel P is referred to as a pixel signal S2. Also, when the pixel signal is an accumulation signal, it is called accumulation signal S2, and when it is a reset signal, it is called reset signal S2.

  The holding unit SH3 is a portion capable of holding the pixel signal output from the amplification unit AP, and is a sample hold circuit including the transfer transistor M14 and the holding capacitance CS3. Specifically, sampling is performed to transfer and hold the pixel signal to the capacitor CS3 by switching the state (conductive state or non-conductive state) of the transfer transistor M14 using the sample and hold control signal TS3. The output unit OP3 includes a signal amplification transistor M16 and an output switch SW15. The signal amplification transistor M16 is a transistor for amplifying and outputting the pixel signal held by the holding capacitance CS3, and the output switch SW15 is a switch for transferring the pixel signal outputted by the signal amplification transistor M16. Specifically, when the output switch SW15 is turned on by the vertical scanning signal VSR input to the output switch SW15, the source of the signal amplification transistor M16 and the constant current source CCSp of the subsequent stage connected by the column signal line 408 A follower circuit is formed. Accordingly, the pixel signal held in the holding unit SH3 is amplified by the output unit OP3 and output from the pixel P. Hereinafter, the amplified pixel signal output from the pixel P is referred to as a pixel signal S3. In addition, when the pixel signal is an accumulation signal, it is called accumulation signal S3, and when it is a reset signal, it is called reset signal S3.

  After the sample and hold of the capacitors CS1, CS2 and CS3, the transfer transistor M8, the transfer transistor M11 and the transfer transistor M14 are turned off, whereby the capacitors CS1, CS2 and CS3 are disconnected from the amplification unit AP of the previous stage. Therefore, the held pixel signal (stored signal or reset signal) can be read out nondestructively until it is sampled and held again.

  Next, the pixel array 120 and the readout circuit 20 of the radiation imaging apparatus 100 of the present embodiment will be described with reference to FIGS. 2 (A) and 2 (B). A plurality of pixels P in FIG. 1 are arranged in a two-dimensional array to form a pixel array 120. Then, the signal from the pixel array 120 is read out by the readout circuit 20. First, the pixel array 120 of the radiation imaging apparatus 100 according to the present embodiment will be described with reference to FIG. FIG. 2A is an equivalent circuit diagram for describing a schematic configuration of the pixel array 120 of the radiation imaging apparatus 100 of the present embodiment.

  The pixel array 120 includes a plurality of pixels P, a vertical scanning circuit 403 for driving each pixel P, and a horizontal scanning circuit 404 for performing signal readout from each pixel P. The vertical scanning circuit 403 and the horizontal scanning circuit 404 are constituted by shift registers, for example, and operate based on control signals from the control unit 109 (FIG. 3). The vertical scanning circuit 403 supplies a vertical scanning signal VSR to each pixel P via the control line 405, and drives each pixel P row by row based on the vertical scanning signal VSR. That is, the vertical scanning circuit 403 functions as a row selection unit, and selects pixels P for which signal readout is to be performed row by row. Further, the horizontal scanning circuit 404 functions as a column selection unit, selects each pixel P in units of columns based on the horizontal scanning signal HSR, and sequentially outputs signals from each pixel P (horizontal transfer). Here, the operating frequency of the row selection unit (vertical scanning circuit 403) is lower than the operating frequency of the column selection unit (horizontal scanning circuit 404), that is, the row selection unit (vertical scanning circuit 403) Operation is slower than horizontal scanning circuit 404).

  The pixel array 120 also has a terminal Es1 for reading out the pixel signal held in the capacitor CS1 of each pixel P, a terminal Es2 for reading out the pixel signal held in the capacitor CS2, and a pixel held in the capacitor CS3. And a terminal Es3 for reading out the signal. The pixel array 120 further has a select terminal Ecs, and the signal received by the terminal Ecs is activated, whereby the pixel signal of each pixel P of the pixel array 120 is read out via the terminals Es1, Es2 and Es3. Be Specifically, the pixel signal S1, the pixel signal S2, and the pixel signal S3 of each pixel P described above are supplied to the column signal lines 406 to 408 corresponding to the respective terminals.

  The control transistor SWch, the amplification transistor Av and the constant current source CCSv are connected in series to form a current path. The output of the amplification transistor Av is connected to the analog signal lines 409 to 411 via the transfer transistor SWah which becomes conductive in response to the horizontal scanning signal HSR from the horizontal scanning circuit 404. As the horizontal scanning signal HSR input to the gate of the control transistor SWch is activated, the amplification transistors Av receiving the voltages from the column signal lines 406 to 408 are activated. Thus, the source follower circuit is formed, and voltages obtained by amplifying the voltages from the column signal lines 406 to 408 become conductive in response to the horizontal scanning signal HSR via the analog signal lines 409 to 411 via the transfer transistor SWah. Output to

  The amplification transistor Aout and the constant current source CCSout are connected in series so as to form a current path, and a source follower circuit in an operating state is formed. As a result, voltages obtained by amplifying the voltages from the analog signal lines 409 to 411 are output from the terminals Es1, Es2 and Es3 via the transfer transistors SWcs which are rendered conductive in response to the signal received by the terminal Ecs.

  Pixel array 120 further includes terminals HST, CLKH, VST, and CLKV receiving control signals for controlling vertical scanning circuit 403 and horizontal scanning circuit 404. Terminal HST receives the start pulse input to horizontal scanning circuit 404. Terminal CLKH receives a clock signal input to horizontal scanning circuit 404. Terminal VST receives the start pulse input to vertical scanning circuit 403. Terminal CLKV receives a clock signal input to vertical scanning circuit 403. These control signals are input from the control unit 109 described later. The horizontal scanning circuit 404 generates and outputs a horizontal scanning signal HSR based on the input start pulse and the clock signal, and the vertical scanning circuit 403 generates the vertical scanning signal VSR based on the input start pulse and the clock signal. Generate and output. Thereby, the pixel signal S1, the pixel signal S2 and the pixel signal S3 are sequentially read out from each pixel by the XY address method. That is, in the pixel array 120, each pixel P is controlled in row units, and the signal is read by outputting (horizontally transferring) the signals held in each holding unit in column units.

  Next, the readout circuit 20 of the radiation imaging apparatus of the present embodiment will be described using FIG. 2 (B). FIG. 2B is an equivalent circuit diagram for describing a schematic configuration of the readout circuit 20 of the radiation imaging apparatus of the present embodiment. The readout circuit 20 includes, for example, a signal amplification unit 107 including a differential amplifier and the like, and an AD conversion unit 108 that performs AD conversion.

  The pixel signal S3 from the terminal Es3 is input to the non-inversion input terminal AMP + of the signal amplification unit 107. Further, the pixel signal S1 from the terminal Es1 is input to the inverting input terminal AMP− of the signal amplification unit 107 via the switch M51 which is turned on in response to the control signal TRO1 input to the control terminal. Further, the pixel signal S2 from the terminal Es2 is input to the inverting input terminal AMP- through the switch M52 which is turned on in response to the control signal TRO2 input to the control terminal. The switches M51 and M52 are controlled such that one of the signals of the terminal Es1 and the terminal Es2 is input to the inverting input terminal AMP-. Switches M51 and M52 and signal amplification unit 107 are designed to have a response characteristic that can follow the cycle of signal ADCLK.

  In the signal amplification unit 107, the difference between the signal from the terminal Es1 and the signal from the terminal Es3 or the difference between the signal from the terminal Es2 and the signal from the terminal Es3 is amplified. This difference is AD converted to digital data by the AD converter 108 based on the clock signal input via the terminal ADCLK. With such a configuration, image data (digital data) of the pixel array 120 is obtained, and is output to the control unit 109 described later via the terminal ADOUT.

  The radiation imaging apparatus 100 and the radiation imaging system SYS of the present embodiment are configured using the pixel array 120 and the readout circuit 20 as described above. Next, the radiation imaging apparatus 100 and the radiation imaging system SYS of the present embodiment will be described using FIG. 3. FIG. 3 is a schematic view for explaining a schematic configuration of the radiation imaging apparatus 100 and the radiation imaging system SYS of the present embodiment.

  The radiation imaging system SYS includes a radiation imaging apparatus 100, a radiation generation apparatus 104 for generating radiation, an irradiation control unit 103, a signal processing unit 101 for performing image processing and system control, and a display unit 102 including a display and the like. Equipped with When radiation imaging is performed, the signal processing unit 101 synchronously controls the radiation imaging apparatus 100 and the irradiation control unit 103. The radiation imaging apparatus 100 generates a signal based on the radiation (X-ray, α-ray, β-ray, γ-ray, etc.) that has passed through the subject, and this signal is processed by the signal processing unit 101 etc. After being generated, image data based on the radiation is generated. The image data is displayed on the display unit 102 as a radiation image. The radiation imaging apparatus 100 includes an imaging panel 105 having an imaging area 10, a readout circuit 20 for reading out a signal from the imaging area 10, and a control unit 109 for controlling each unit.

  The imaging panel 105 is configured by tiling a plurality of pixel arrays 120 on a plate-like base (two-dimensional array), and a large-sized imaging panel 105 is formed by such a configuration. A plurality of pixels P are arranged in each pixel array 120, and the imaging region 10 includes a plurality of pixels P arranged to form a row and a plurality of columns by the plurality of pixel arrays 120. Moreover, although the structure by which the some pixel array 120 was tiled so that 7 row x 2 rows may be formed is illustrated here, it is not restricted to this structure.

  The control unit 109 communicates control commands with, for example, the signal processing unit 101, communicates synchronization signals, and outputs image data to the signal processing unit 101. Further, the control unit 109 controls the imaging region 10 or each unit, and performs, for example, setting of a reference voltage of each pixel array 120, drive control of each pixel, and operation mode control. Further, the control unit 109 combines the image data (digital data) of each pixel array 120 AD-converted by the AD conversion unit 108 of the readout circuit 20 into one frame image data, and outputs it to the signal processing unit 101. . The control unit 109 may be configured by a processor such as a CPU and a memory such as a RAM or a ROM. The processor of the control unit 109 may execute the program stored in the memory to execute an operation of the radiation imaging apparatus 100 described later. Instead of this, the control unit 109 may be configured by a dedicated circuit such as an ASIC (application specific integrated circuit). Similarly, the signal processing unit 101 may be a computer configured by a processor such as a CPU and a memory such as a RAM or a ROM, or may be configured by a dedicated circuit such as an ASIC. Since the signal processing unit 101 generates an image as described later, it can also be called an image generation device. The signal processing unit 101 is connected to a storage unit 115 capable of storing data used in processing of the signal processing unit 101. The storage unit 115 may be configured of, for example, a magnetic disk or a semiconductor drive.

  The control unit 109 and the signal processing unit 101 exchange control commands or control signals and image data via various interfaces. The signal processing unit 101 outputs setting information such as an operation mode and various parameters or photographing information to the control unit 109 via the control interface 110. Further, the control unit 109 outputs device information such as the operation state of the radiation imaging apparatus 100 to the signal processing unit 101 via the control interface 110. The control unit 109 also outputs the image data obtained by the radiation imaging apparatus 100 to the signal processing unit 101 via the image data interface 111. Further, the control unit 109 notifies the signal processing unit 101 that the radiation imaging apparatus 100 is in a state in which imaging is possible using the READY signal 112. Further, the signal processing unit 101 uses the synchronization signal 113 to notify the control unit 109 of the timing of the start of radiation irradiation in response to the READY signal 112 from the control unit 109. In addition, the irradiation permission signal 114 is a signal for notifying the signal processing unit 101 that the imaging panel 105 is accumulating. The signal processing unit 101 outputs a control signal to the irradiation control unit 103 to start radiation irradiation while the irradiation permission signal 114 is in the enable state.

  FIG. 4 is a time chart showing an example of a driving method of the radiation imaging apparatus 100. As shown in FIG. This method is implemented by the control unit 109 controlling the operation of each component of the radiation imaging apparatus 100. The radiation imaging apparatus 100 captures a moving image composed of a plurality of frame images. The reset image is an image generated based on the reset signal read from each pixel.

  In FIG. 4, “SYNC” to “WIDE” indicate the levels of the respective signals. “CS1”, “CS2” and “CS3” indicate signals held in the capacitive elements CS1, CS2 and CS3. “Es1”, “Es2” and “Es3” indicate periods in which signals are read out from the holding units of the pixel array 120 to the readout circuit 20. The control unit 109 performs the signal read operation while “Es1” to “Es3” are at high level. “AMP−” indicates a period during which a signal is input to the inverting input terminal AMP− of the signal amplification unit 107. “AMP +” indicates a period during which a signal is input to the non-inverting input terminal AMP + of the signal amplification unit 107. A period R indicates a period in which a signal is output from the output terminal of the signal amplification unit 107. "AMP-" and "AMP +" both indicate the input period of the signal at high level.

  In the driving method of FIG. 4, the frame image rate is constant, the period Tc after the reset driving RD and the period Ts after the sample and hold driving SD are longer than the reading period R of the pixel signal, and the additional capacitance Cfd 'is not added. The case where is set will be described.

  The frame periods F1 and F2 indicate the first and second frame periods after the start of shooting. A frame period is a period repeated to generate a plurality of frame images. The accumulation period T indicates an accumulation period corresponding to the frame periods F1 and F2. The accumulation period is a period in which charge is accumulated in the photoelectric conversion element PD. During the accumulation period T, the control unit 109 notifies the signal processing unit 101 by the irradiation permission signal 114 that irradiation of radiation is possible.

  The shooting mode is set before shooting. Specifically, since the sensitivity of the pixel P is high sensitivity of only the FD capacitance Cfd to which the additional capacitance Cfd 'for sensitivity switching is not added, the control unit 109 deactivates the control signal WIDE. When detecting the rising of the pulse in the SYNC signal, the control unit 109 starts driving for generating a frame image in the frame period F1. The SYNC signal may be either an external synchronization signal or an internal synchronization signal, but in this embodiment it is an external synchronization signal. For example, the rise of a pulse in the SYNC signal starts one frame period F1, the next rise ends this frame period F1, and the next frame period F2 starts. The drive RD indicates the reset drive performed in the frame periods F1 to F2, and the drive SD indicates the sample and hold drive performed in the frame periods F1 to F2. The reset drive is a drive for performing reset of the conversion unit CP and the amplification unit AP and sample hold of the reset signal. The sample and hold drive is a drive for performing sample and hold of the accumulation signal.

  The reset drive RD in the frame period F1 will be described. The control unit 109 collectively performs reset drive RD described below on all the pixels P included in the imaging panel 105. That is, the control unit 109 controls each pixel P such that each of the plurality of pixels generates a reset signal at the same timing.

  When detecting the rising of the pulse in the SYNC signal, the control unit 109 starts driving for generating a frame image in the frame period F1. The control unit 109 activates the enable signal EN. As a result, the control transistor M3 and the control transistor M6 become conductive. When the control transistor M3 becomes conductive, the amplification transistor M4 receiving the voltage from the conversion unit CP is activated, and a voltage obtained by amplifying the voltage from the conversion unit CP is output from the amplification transistor M4. When the control transistor M6 is turned on, the amplification transistor M7 receiving the voltage from the amplification transistor M4 is activated, and a voltage obtained by amplifying the voltage from the amplification transistor M4 is output from the amplification transistor M7.

  Further, the control unit 109 activates the reset signal PRES. As a result, the reset voltage VRES which is a predetermined potential is supplied to the photodiode PD, and the charge of the photodiode PD is reset. As a result, the voltage output to the amplification unit AP is reset, and a voltage corresponding to the voltage from the conversion unit CP at the time of reset by the reset transistor M2 is input to the input terminal n1 of the clamp capacitance Ccl. The control unit 109 next activates the clamp signal PCL. As a result, a predetermined voltage VCL is supplied to the connection node between the clamp capacitance Ccl and the amplification transistor M7. As a result, the voltage output from the amplification transistor M7 is reset, and the clamp voltage VCL which is a predetermined potential is input to the output terminal n2 of the clamp capacitance Ccl.

  The control unit 109 temporarily activates control signals TS1 to TS3 until the clamp signal PCL is inactivated. As a result, the transfer transistors M8, M11, and M14 temporarily switch from the non-conductive state to the conductive state, and the reset signals S1 to S3 are transferred to and held by the holding capacitances CS1 to CS3 (that is, sampling of the reset signals is performed). ).

  The control unit 109 deactivates the reset signal PRES while temporarily activating the control signals TS1 to TS3. As a result, the reset transistor M2 becomes nonconductive. The control unit 109 deactivates the clamp signal PCL after inactivating the control signals TS1 to TS3. As a result, the reset transistor M5 becomes nonconductive, the potential difference generated between the input terminal n1 and the output terminal n2 is maintained at both terminals of the clamp capacitance Ccl, and the charge converted according to the radiation is a photoelectric conversion element The accumulation period T accumulated in PD starts. After inactivating the clamp signal PCL, the control unit 109 deactivates the enable signal EN input to the control transistor M3 and the gate of the control transistor M6. This completes the reset driving RD in the frame period F1.

  The operation of reading the reset signal S1 and the reset signal S3 in the period Tc of the frame period F1 will be described with reference to FIG. In the present embodiment, the readout circuit 20 starts readout of the reset signal S1 and the reset signal S3 after a predetermined time has elapsed from the start of holding the reset signals S1 to S3. At the end of the reset driving RD in the frame period F1, the holding capacitances CS1 to CS3 hold the reset signals S1 to S3. Therefore, the control unit 109 starts reading out the reset signal S1 and the reset signal S3 held in the storage capacitors after a predetermined time has elapsed since the end of the reset driving RD. Specifically, the control unit 109 activates the select terminal Ecs and the control signal TRO1, and deactivates the control signal TRO2. Subsequently, the control unit 109 controls the vertical scanning circuit 403 and the horizontal scanning circuit 404 to select a pixel to be read out first among the plurality of pixels P included in the pixel array 120. Thus, the reset signal S1 held in the holding unit TS1 of the selected pixel P is input to the inverting input terminal AMP− of the signal amplification unit 107, and the reset signal S3 held in the holding unit TS3 of the selected pixel P Are input to the non-inverted input terminal AMP + of the signal amplification unit 107. Thus, the read circuit 20 reads the reset signal S1 and the reset signal S3 at the same timing.

  In the above-described reset driving RD, the holding capacitance CS1 and the holding capacitance CS3 hold the reset signal of the same potential. The control unit 109 reads out the held reset signal S1 and reset signal S3 through signal paths (differential signal paths) of pixel signals of two systems in the pixel array 120, and outputs the signal to the signal amplification unit 107. The signal amplification unit 107 receiving the output from the pixel array 120 outputs a signal obtained by taking the difference between the reset signal S1 and the reset signal S3. The reset signal S1 is read from the holding unit SH1 through the first signal path, and the reset signal S3 is read from the holding unit SH3 to the readout circuit 20 through the second signal path different from the first signal path. The accumulation signal S1 and the reset signal S1 are read from each pixel P to the readout circuit 20 through the same first signal path.

  The output signal from the signal amplification unit 107 corresponds to a pixel signal in which the common offset of the two signal paths is corrected by differential input, but the difference between different noises included in the two signal paths remains. The output signal is converted into digital data by the AD converter 108 and supplied to the controller 109. The control unit 109 sequentially switches the selected pixels by controlling the vertical scanning circuit 403 and the horizontal scanning circuit 404 in a period R, acquires pixel data for generating an image, and generates a reset signal corresponding to the frame period F1. Generate a configured reset image.

  Subsequently, the sample and hold drive SD in the frame period F1 will be described. The control unit 109 collectively performs sample and hold driving SD described below on all the pixels P included in the imaging panel 105. That is, the control unit 109 controls each pixel P such that each of the plurality of pixels generates an accumulation signal at the same timing.

  The control unit 109 activates the enable signal EN after a lapse of a period Tc since the enable signal EN is deactivated by the reset driving RD in the frame period F1. As a result, the control transistor M3 and the control transistor M6 become conductive. When the control transistor M3 becomes conductive, the amplification transistor M4 receiving the voltage from the conversion unit CP is activated, and a voltage obtained by amplifying the voltage from the conversion unit CP is output from the amplification transistor M4. When the control transistor M6 is turned on, the amplification transistor M7 receiving the voltage from the amplification transistor M4 is activated, and a voltage obtained by amplifying the voltage from the amplification transistor M4 is output from the amplification transistor M7.

  Next, control unit 109 temporarily activates control signal TS1. As a result, the transfer transistor M8 switches from the non-conductive state to the conductive state, and the storage signal S1 stored in the period T is transferred to the storage capacitor CS1 and held (that is, sampling of the storage signal is performed). The control unit 109 deactivates the enable signal EN input to the gates of the control transistor M3 and the control transistor M6 after the completion of sampling. As a result, the amplification transistor M4 and the amplification transistor M7 are inactivated.

  The operation of reading out the accumulation signal S1 and the reset signal S3 in the period Ts of the frame period F1 will be described with reference to FIG. In the present embodiment, the reading circuit 20 starts reading of the accumulation signal S1 and the reset signal S3 after a predetermined time has elapsed from the start of holding the accumulation signal S1. At the end of the sample hold drive SD in the frame period F1, the storage signal CS1 holds the storage signal S1 and the holding capacitors CS2 to CS3 hold the reset signals S2 to S3. Therefore, the control unit 109 starts reading out of the accumulation signal S1 and the reset signal S3 held in the holding capacitors after a predetermined time has elapsed since the end of the sample and hold driving SD. Specifically, the control unit 109 activates the select terminal Ecs and the control signal TRO1, and deactivates the control signal TRO2. Subsequently, the control unit 109 controls the vertical scanning circuit 403 and the horizontal scanning circuit 404 to select one of the plurality of pixels P included in the pixel array 120. Thus, the storage signal S1 held in the holding portion TH1 of the selected pixel P is input to the inverting input terminal AMP- of the signal amplification portion 107, and the reset signal S3 held in the holding portion TH3 of the selected pixel P Are input to the non-inverted input terminal AMP + of the signal amplification unit 107. Thus, the read circuit 20 reads the accumulation signal S1 and the reset signal S3 at the same timing.

  The control unit 109 reads out the held accumulation signal S1 and reset signal S3 via signal paths (differential signal paths) of pixel signals of two systems in the pixel array 120, and outputs the readout signal to the signal amplification unit 107. The signal amplification unit 107 receiving the output from the pixel array 120 outputs a signal obtained by taking the difference between the accumulation signal S1 and the reset signal S3. Although the output signal of the signal amplification unit 107 corresponds to a pixel signal in which the offsets of the signal paths of the two systems are corrected by the differential input, the difference between the noises included in the signal paths of the two systems remains. The accumulation signal S1 is read from the holding unit SH1 through the first signal path, and the reset signal S3 is read from the holding unit SH3 through the second signal path.

  The output signal is converted into digital data by the AD converter 108 and supplied to the controller 109. The control unit 109 sequentially switches the selected pixel by controlling the vertical scanning circuit 403 and the horizontal scanning circuit 404 in the period R, acquires digital data for generating an image, and stores the storage signal corresponding to the frame period F1. Generate an image. Thus, an image generated based on the accumulation signal read from each pixel is referred to as an accumulation image. As described later, the processing in FIG. 4 is performed in each of a state in which the radiation imaging apparatus 100 is not irradiated with radiation and a state in which the radiation imaging apparatus 100 is irradiated with radiation. The accumulated image generated in a state where the radiation imaging apparatus 100 is not irradiated with radiation is called a dark image. A stored image generated in a state where radiation is irradiated to the radiation imaging apparatus 100 is referred to as a radiation image. The reset image generated by reading out the reset signal and the accumulated image generated by reading out the accumulated signal may have the same resolution. For example, when performing signal addition using a switch, the same signal addition is performed on the reset image and the stored image.

  Subsequently, in the frame period F2, as in the frame period F1, the reset drive RD and the sample hold drive SD are sequentially performed. The reset signals S1 to S3 are transferred to and held by the holding capacitors CS1 to CS3 by the reset driving RD. The accumulation signal S1 is transferred to the holding capacitor CS1 and held by the sample hold drive SD. During a period Tc between the end of the reset drive RD and the start of the sample-and-hold drive SD, the control unit 109 sequentially switches the selected pixels in a period R to acquire digital data for generating an image, and a frame period F2 Generates a reset image corresponding to

  During a period Ts from the end of the sample and hold drive SD to the start of the reset drive RD in the next frame period F3, the control unit 109 sequentially switches the selected pixels in a period R to digital data for generating an image. Acquire and generate a stored image corresponding to the frame period F2. Driving similar to the frame period F2 is performed also in the frame period after the frame period F3 and a reset image and a stored image are sequentially generated.

The signal paths of pixel signals in the pixel array 120 include semiconductor elements such as amplification transistors, constant current sources and switches in addition to signal lines, and different 1 / f noise and temperature drift occur due to individual semiconductor elements. Do. The 1 / f noise increases as the frequency decreases. The semiconductors of the signal amplification unit 107 and the AD conversion unit 108 that constitute the readout circuit 20 also include 1 / f noise components. That is, in the generated signal, the noise component of the readout circuit 20 is superimposed on the noise of the signal path inside the pixel array 120.
In the above example, a method is performed in which the read signal is transmitted differentially. Intrinsic offset, 1 / f noise, and temperature drift exist in the semiconductor elements of each differential transmission path. The differences between the differential signals are superimposed on the generated image and appear in the image as inherent artifacts, random noise, vertical noise, and blocky artifacts. With regard to the inherent offset, it is possible to suppress an artifact by subtracting a dark image acquired before imaging from a radiation image.
In order to correct well the 1 / f noise of the time-varying semiconductor element, it is conceivable that a dark image is generated immediately before the start of imaging. However, even if the photographing mode is limited to several types, generation of a dark image including accumulation takes time, and in particular, when generating immediately before photographing, a time lag occurs at the start of photographing.
Also, the effect of low frequency noise on the image differs at the location of the circuit where the semiconductor device is used. For example, low frequency noise of the amplification transistors M10, M13 and M16 of the storage capacitor of the pixel circuit P of the pixel array 120 affects the image as random noise. Low frequency noise of constant current source CCSp, amplification transistor Av and constant current source CCSv used for amplification of pixel signals of column signal lines 406 to 408 of pixel array 120 affects the image as vertical line noise. The low frequency noise of the amplification transistor Aout and constant current source CCSout used for amplification of the pixel signal of the analog signal lines 409 to 411, the signal amplification unit 107, and the AD conversion unit 108 is superimposed on the entire pixel array area, Affects the image as an artifact. In particular, in 3D imaging using a large area flat panel sensor, it is known that vertical line noise and block-like artifacts cause ring artifacts in a 3D reconstructed image and affect the image more than random noise.
In the present embodiment, a correction image is generated before the first radiation irradiation, and a frame image is generated based on the correction image and the reset image and radiation image generated in each frame period. By this, it is possible to correct vertical line noise and block-like artifacts generated due to 1 / f noise.

  Subsequently, a method of generating a frame image will be described with reference to FIGS. 5 and 6. FIG. 5 explains the operation for generating the correction image. The operation of FIG. 5 is performed before the start of radiography, specifically, before the first irradiation.

  In step S101, the signal processing unit 101 issues a control command to the control unit 109 of the radiation imaging apparatus 100 through the control interface 110, and sets an imaging mode. The setting of the photographing mode includes sensitivity setting, frame image rate setting, accumulation time setting, pixel addition setting, and the like. The signal processing unit 101 further causes the radiation imaging apparatus 100 to transition to the imaging enabled state by the control command.

  In S102, the signal processing unit 101 determines whether or not the radiation imaging apparatus 100 has transitioned to the imaging enabled state. If the signal processing unit 101 transitions to the imaging enabled state ("YES" in S102), the signal processing unit 101 advances the process to S103, and if not transitioning to the imaging enabled state ("NO" in S102), the signal processing unit 101 Repeat S102.

  In step S103, the signal processing unit 101 resets the imaging counter n in the signal processing unit 101 to zero. In step S104, the signal processing unit 101 increments the shooting counter n, and starts generation of a stored image and a reset image that are the source of the correction image.

  In S105, the signal processing unit 101 outputs the synchronization signal pulse SYNC to the control unit 109 through the synchronization signal 114. Since the correction image is generated based on the dark image, the radiation generator 104 does not perform radiation irradiation. In S106, when receiving the synchronization signal pulse SYNC via the synchronization signal 114, the control unit 109 drives the imaging panel 105 and the readout circuit 20 according to the time chart of FIG. The control unit 109 AD converts the reset signal held in each pixel within a frame period, and transfers the reset signal as pixel data to the signal processing unit 101 through the image data interface 111. The signal processing unit 101 generates a reset image based on the transferred pixel data, and stores the reset image in the storage unit 115.

  In step S107, the control unit 109 AD converts the accumulated signal held in each pixel within a frame period, and transfers it to the signal processing unit 101 as pixel data of a dark image. The signal processing unit 101 generates an accumulated image from sequentially transferred pixel data, and subtracts the reset image stored in the storage unit 115 in S106 from this accumulated image to generate an n-th correction image. The signal processing unit 101 stores the nth correction image in the storage unit 115.

  In step S108, the signal processing unit 101 determines whether the predetermined number N of correction images can be acquired in the shooting mode set in the shooting mode setting process. If the default number N has been acquired ("YES" in S108), the signal processing unit 101 advances the process to S110. If the default number N has not been acquired ("NO" in S108), the signal processing unit 101 advances the process to S109. In S109, the signal processing unit 101 waits for the frame period F to elapse from the output of the synchronization signal pulse SYNC, and returns the process to S104.

  Since acquisition of the predetermined number N of image data is completed, in S110, the signal processing unit 101 transmits a control command for notifying the end of image generation in the current shooting mode to the control unit 109 through the control interface 110. In S111, the signal processing unit 101 generates one image by averaging the N correction images, and stores the image in the storage unit 115 as a correction image. The correction image is based on the accumulated signal read a plurality of times and the reset signal read a plurality of times.

  In step S112, the signal processing unit 101 determines whether the radiation imaging apparatus 100 is in the imaging disable state (for example, the sleep state). The change of the state can be confirmed by the termination control command transmitted in S110. When transitioning to the imaging impossible state ("YES" in S112), the signal processing unit 101 advances the process to S113, and when not transitioning to the imaging impossible state ("NO" in S112), the signal processing unit 101 Repeat S112.

  In step S113, the signal processing unit 101 determines whether acquisition of the correction image has been completed for only the type of imaging mode used for imaging by the radiation imaging system SYS. If the process has not been completed (“NO” in S113), the signal processing unit 101 returns the process to S101 and generates correction images of the required types. When it is completed ("YES" in S113), the signal processing unit 101 ends the process.

  In addition to the offsets of the conversion unit CP and the amplification unit AP, the readout system offset is superimposed on the dark image acquired in S107 of the above processing. On the other hand, the reset image acquired in S106 includes only the reading system offset. By subtracting the reset image from the dark image in S107, the offset components of the readout system of each other are offset, and an image of only the offset of the conversion unit CP and the amplification unit AP that does not include the readout system offset is obtained. Since a correction image is obtained by averaging a plurality of images obtained in this manner, a correction image with less random noise can be obtained.

  In the example of the flowchart of FIG. 5, the generation of the frame image n in S107 is performed in the signal processing unit 101, but the control unit 109 may perform the subtraction process of the reset image from the dark image. In this case, the control unit 109 includes a storage unit for storing a reset image, and the control unit 109 transfers the image after subtraction processing to the signal processing unit 101. In the processing of the signal processing unit 101 in S107, the n-th correction image is generated based on the transferred image, and is stored in the storage unit 115.

  Subsequently, an operation for generating a radiation image will be described with reference to FIG. The operation of FIG. 6 is performed after radiation imaging is started.

  In step S201, the signal processing unit 101 issues a control command to the control unit 109, and sets a shooting mode. Thereafter, the signal processing unit 101 causes the radiation imaging apparatus 100 to transition to the imaging enabled state by the control command. In step S202, the signal processing unit 101 determines whether the radiation imaging apparatus 100 has transitioned to the imaging enabled state. When transitioning to the imaging enabled state ("YES" in S202), the signal processing unit 101 advances the process to S203, and when not transitioning to the imaging enabled state ("NO" in S202), the signal processing unit 101 Repeat S202. It can be determined whether, for example, the READY signal 112 has been activated or not, whether or not it has transitioned to the imaging enabled state. The signal processing unit 101 starts radiation imaging when determining that the radiation imaging apparatus 100 is ready for imaging.

  In S203, the signal processing unit 101 outputs the synchronization signal pulse SYNC to the control unit 109. When receiving the synchronization signal pulse SYNC, the control unit 109 starts driving the imaging panel 105 according to the time chart of FIG. 4 and outputs the irradiation permission signal 114 to the signal processing unit 101 during the accumulation period T set in S201. .

  In S204, the signal processing unit 101 determines whether the irradiation permission signal 114 is activated. If the irradiation permission signal 114 is activated ("YES" in S204), the signal processing unit 101 proceeds the process to S205, and if the irradiation permission signal 114 is not activated ("NO" in S204), The processing unit 101 repeats S204.

  In S205, the signal processing unit 101 outputs a control signal to the irradiation control unit 103 so that irradiation of radiation is performed in accordance with the period of the accumulation period T. In step S206, the control unit 109 drives the imaging panel 105 and the readout circuit 20 in accordance with the drive started from step S203. The control unit 109 AD converts the reset signal held in each pixel within a frame period, and transfers the signal to the signal processing unit 101 as pixel data of a reset image through the image data interface 111. The signal processing unit 101 generates a reset image based on the transferred pixel data, and stores the reset image in the storage unit 115.

  In step S207, the control unit 109 AD converts the accumulated signal held in each pixel within a frame period, and transfers it to the signal processing unit 101 as pixel data of a radiation image. The signal processing unit 101 generates a radiation image based on the sequentially transferred pixel data. The signal processing unit 101 generates a frame image by subtracting the reset image stored in the storage unit 115 in S206 and the correction image stored in the storage unit 115 in S111 from the radiation image. In this process, a correction image of the same imaging mode as radiation imaging such as resolution and accumulation time is selected.

  In step S208, the signal processing unit 101 transfers the frame image to the subsequent process in accordance with the shooting mode. In the post-process, image processing such as gain correction processing and sharpening processing is performed on the transferred frame image in parallel with radiation imaging by a pipeline method. In the case of radiography in which an image is observed in real time such as radioscopic radiography, the processed image is transferred to the display unit 102 and displayed. In the case of imaging for processing based on a plurality of images such as 3D imaging, a frame image after image processing is stored in the storage unit 115.

  In step S209, the signal processing unit 101 determines whether to end the imaging based on a fluoroscopic switch (not shown) or a programmed number of sheets. When imaging is continued (“NO” in S209), the signal processing unit 101 determines in step S210 that the frame period has elapsed. When it is determined that the imaging is completed ("YES" in S209), the signal processing unit 101 transmits a control command for notifying the end of image generation in the current imaging mode through the control interface 110 in S211. To the end of the shooting process.

  In S210, the signal processing unit 101 determines whether a frame period has elapsed. If it is determined that the frame period has not elapsed ("NO" in S210), the signal processing unit 101 returns the process to S209. If it is determined that the frame period has elapsed ("YES" in S210), the signal processing unit 101 returns the process to S203 and performs shooting of the next frame image.

  In step S <b> 212, the signal processing unit 101 determines whether the radiation imaging apparatus 100 is in the imaging disable state (for example, the sleep state). The change of state can be confirmed by the termination control command. The signal processing unit 101 ends the processing when transitioning to the imaging disabled state ("YES" in S212), and the signal processing unit 101 proceeds to S212 when the transition to the imaging disabled state is not performed ("NO" in S212). repeat.

  In the example of the flowchart of FIG. 6, the signal processing unit 101 performs subtraction processing of pixel data of a reset image from pixel data of a radiation image in the processing of S207, but the control processing may perform the subtraction processing. In this case, the control unit 109 includes a storage unit that stores a reset image, and stores, in the storage unit, a reset image to be read first within a frame period. Then, the control unit 109 subtracts the pixel data of the reset image read from the storage unit from the pixel data of the radiation image read out from the imaging panel 105 next, and transfers the processed pixel data to the signal processing unit 101. Do. The processing of the signal processing unit 101 in S207 generates a frame image by subtracting the pixel data of the correction image from the pixel data transferred.

  In addition to the offsets of the conversion unit CP and the amplification unit AP, the readout system offset is superimposed on the radiation image acquired in S207 of the above processing. On the other hand, the reset image includes only the readout offset. By subtracting the reset image from the radiation image, the offset components of the readout systems of the respective images are offset, and an image in which only the offsets of the conversion unit CP and the amplification unit AP are superimposed is obtained. By subtracting the offset components of the conversion unit CP of the correction image and the amplification unit AP from the image, it is possible to generate a frame image in which the offset components of the conversion unit CP and the amplification unit AP are offset. Noise and artifacts are well suppressed in this frame image. Although the differential readout method is described in the present embodiment, the readout circuit 20 may read out a signal not in differential but in single end.

Second Embodiment
A driving method of the radiation imaging apparatus 100 according to the second embodiment will be described with reference to FIG. The hardware configuration of the radiation imaging apparatus 100 may be the same as that of the first embodiment, and thus the description will not be repeated. Hereinafter, differences between the first embodiment and the second embodiment will be mainly described. A case will be described where in the driving method of FIG. 7, a photographing mode in which signals are read out with two types of sensitivity is set.

  A case where the frame image rate is constant and the period Tc and the period Ts are longer than the readout period R of the pixel signal in the driving method of FIG. 7 will be described. Furthermore, a shooting mode is set in which signals are read out for the high sensitivity to which the additional capacitance Cfd 'is not added and the low sensitivity to which the additional capacitance Cfd' is added. As in the first embodiment, SYNC is an external synchronization signal. The read-out images of the two types of sensitivity are used, for example, as an image for composition for extending the dynamic range. The shooting mode is set before shooting.

  The reset drive RD in the frame period F1 will be described. When detecting the rising of the pulse in the SYNC signal, the control unit 109 starts driving for generating a frame image in the frame period F1. First, the control unit 109 activates the enable signal EN. The control unit 109 also activates the reset signal PRES and the sensitivity switching control signal WIDE. As a result, the transistor M1 becomes conductive, and the charges of the photodiode PD of the conversion unit CP, the floating diffusion capacitance Cfd, and the sensitivity switching additional capacitance Cfd 'are reset. As a result, a voltage corresponding to the voltage from the conversion unit CP at the time of reset is input to the input terminal n1 of the clamp capacitor Ccl. The control unit 109 next activates the clamp signal PCL. Thereby, the clamp voltage VCL is input to the output terminal n2 of the clamp capacitor Ccl.

  Next, the control unit 109 deactivates the control signal WIDE. As a result, the voltage at the time of reset is held in the additional capacitance Cfd '. The control unit 109 temporarily activates control signals TS1 to TS3 until the clamp signal PCL is inactivated. As a result, the reset signals S1 to S3 are transferred to and held by the holding capacitors CS1 to CS3 (that is, sampling of the reset signal is performed).

  The control unit 109 deactivates the reset signal PRES while temporarily activating the control signals TS1 to TS3. As a result, the reset transistor M2 becomes nonconductive. The control unit 109 deactivates the clamp signal PCL after inactivating the control signals TS1 to TS3. This starts an accumulation period T in which the charge converted according to the radiation is accumulated in the photoelectric conversion element PD. The control unit 109 deactivates the enable signal EN after inactivating the clamp signal PCL. This completes the reset driving RD in the frame period F1.

  The operation of reading the reset signals S1 to S3 in the period Tc of the frame period F1 will be described with reference to FIG. In the second embodiment, the readout circuit 20 starts readout of the reset signals S1 to S3 after a predetermined time has elapsed from the start of holding of the reset signals S1 to S3. Specifically, first, the control unit 109 activates the select terminal Ecs, then activates the control signal TRO1, and deactivates the control signal TRO2. Thus, the reset signal S1 is selected. Subsequently, the control unit 109 controls the vertical scanning circuit 403 and the horizontal scanning circuit 404 to select the first pixel to be read out of the plurality of pixels P included in the pixel array 120. As a result, the reset signal S1 of the first pixel is input to the inverting input terminal AMP- of the signal amplifier 107, and the reset signal S3 is input to the non-inverting input terminal AMP + of the signal amplifier 107. Thus, the reading circuit 20 reads the difference between the reset signal S1 and the reset signal S3 at the same timing. The control unit 109 switches the selected pixels sequentially by controlling the horizontal scanning circuit 404, and reads out pixel data of one row as a difference between the reset signal S1 and the reset signal S3.

  Next, control unit 200 deactivates control signal TRO1 and activates control signal TRO2. Thus, the reset signal S2 is selected. The control unit 109 switches the selected pixels sequentially by controlling the horizontal scanning circuit 404, and reads out pixel data for one row as a difference between the reset signal S2 and the reset signal S3. That is, the control unit 109 scans the first row twice, reads the difference between the reset signal S1 and the reset signal S3 in the first scan, and reads the difference between the reset signal S2 and the reset signal S3 in the second scan.

The control unit 109 switches between the control signal TRO1 and the control signal TRO2 for each scan while controlling the vertical scanning circuit 403 and the horizontal scanning circuit 404 to generate two types of images in the reading period R of the period Tc. To generate pixel data. Based on the pixel data, a reset image based on the reset signal S1 stored in the storage capacitor CS1 of the frame period F1 and a reset image based on the reset signal S2 stored in the storage capacitor CS2 are generated. The reset image based on the reset signal S1 is called a high sensitivity reset image, and the reset image based on the reset signal S2 is called a low sensitivity reset image,
Subsequently, the sample and hold drive SD in the frame period F1 will be described. The control unit 109 activates the enable signal EN after a lapse of a period Tc since the enable signal EN is inactivated by the reset drive RD in the frame period F1. Next, the control unit 109 temporarily activates the control signal TS1 while deactivating the sensitivity switching control signal WIDE. Charge is generated in the photodiode PD in the period T, and the high sensitivity voltage of the FD capacitance Cfd corresponding to the generated charge amount is transferred to the holding capacitance CS1 as the accumulation signal S1 and held.

  Next, the control unit 109 activates the sensitivity switching control signal WIDE and the control signal TS2. As the WIDE signal is activated, the transistor M1 becomes conductive, and the capacitance of the conversion unit CP becomes a combined capacitance of the FD capacitance Cfd and the capacitance Cfd '. The output of the conversion unit CP is a low sensitivity voltage of the combined capacitance of the FD capacitance Cfd and the capacitance Cfd 'according to the charge generated in the photodiode PD in the period T.

  Next, the control unit 109 deactivates the sensitivity switching control signal WIDE. The transistor M1 becomes nonconductive, and the capacitance of the conversion unit CP becomes the FD capacitance Cfd, but the output of the conversion unit CP is maintained. Next, the control unit 109 deactivates the control signal TS2. The low sensitivity voltage is transferred to and held by the storage capacitor CS2 as the storage signal S2. The control unit 109 deactivates the enable signal EN after the sampling is completed.

  The operation of reading out the accumulation signal S1, the accumulation signal S2 and the reset signal S3 in the period Ts of the frame period F1 will be described with reference to FIG. 7 continuously. The control unit 109 switches between the control signal TRO1 and the control signal TRO2 for each scan while controlling the vertical scanning circuit 403 and the horizontal scanning circuit 404 to generate two types of images in the reading period R of the period Ts. To generate pixel data. Based on the pixel data, an accumulated image of the high sensitivity voltage signal held in the holding capacitance CS1 corresponding to the frame period F1 and an accumulated image of the low sensitivity voltage signal held in the holding capacitance CS2 are generated. The accumulated image of the high sensitivity voltage signal is called a high sensitivity accumulated image, and the accumulated image of the low sensitivity voltage signal is called a low sensitivity accumulated image.

  Subsequently, in the frame period F2, as in the frame period F1, the reset drive RD and the sample hold drive SD are sequentially performed. The reset signals S1 to S3 are transferred to and held by the holding capacitors CS1 to CS3 by the reset driving RD. The storage signal CS1 of high sensitivity is held in the holding capacitance CS1 by the sample and hold driving SD, and the storage signal S2 of low sensitivity is held in the holding capacitance CS2.

  During a period Tc between the end of the reset drive RD and the start of the sample-and-hold drive SD, the control unit 109 sequentially switches the selected pixels, acquires digital data in the period R, and the high sensitivity reset image corresponding to the frame period F2. And generate a low sensitivity reset image.

  During a period Ts from the end of the sample hold drive SD to the start of the reset drive RD in the next frame period F3, the control unit 109 sequentially switches the selected pixels in period R to acquire digital data, and the frame period F2 To generate a high sensitivity storage image and a low sensitivity storage image corresponding to Driving similar to the frame period F2 is performed also in the frame period after the frame period F3.

  In the moving image generation method according to the second embodiment, as in the first embodiment, the correction image is generated before the first radiation irradiation, the correction image, the reset image and the radiation image generated in each frame period, and Generate a frame image based on. By this, it is possible to correct vertical line noise and block-like artifacts generated due to 1 / f noise.

  FIG. 8 explains the operation for generating the correction image. The operation of FIG. 8 is performed before the start of radiation irradiation. Hereinafter, differences between the first embodiment and the second embodiment will be mainly described. The case where the imaging mode for reading out the two types of sensitivity shown in the driving method of FIG. 7 is set will be described.

  The processes of S101 to S105 in FIG. 8 are equivalent to those of the first embodiment. At S106 ', the control unit 109 drives the imaging panel 105 and the readout circuit 20. Specifically, the control unit 109 AD converts the reset signal held in each pixel within a frame period, and transfers pixel data of the high sensitivity reset image and the low sensitivity reset image to the signal processing unit 101. The signal processing unit 101 generates a high sensitivity reset image and a low sensitivity reset image based on the transferred pixel data, and stores the high sensitivity reset image and the low sensitivity reset image in the storage unit 115.

  In S <b> 107 ′, the control unit 109 AD converts the accumulated signal held in each pixel within a frame period, and transfers pixel data of the high sensitivity dark image and the low sensitivity dark image to the signal processing unit 101. The signal processing unit 101 subtracts the pixel data of the high sensitivity reset image or the low sensitivity reset image in the storage unit 115 corresponding to the pixel data from the sequentially transferred pixel data to obtain a high sensitivity correction image and a low sensitivity. A correction image is generated and stored in the storage unit 115. The processes of S108 to S110 in FIG. 8 are equivalent to those of the first embodiment.

  In S111 ′, the signal processing unit 101 obtains the image obtained by averaging the N high sensitivity correction images as the high sensitivity correction image, and is obtained by averaging the N low sensitivity correction images. The stored images are stored in the storage unit 115 as low sensitivity correction images. The process of S112 to S113 in FIG. 8 is equivalent to that of the first embodiment.

  Subsequently, an operation for generating a radiation image will be described with reference to FIG. The operation of FIG. 9 is performed after radiation imaging is started. Hereinafter, differences between the first embodiment and the second embodiment will be mainly described. The case where the imaging mode for reading out the two types of sensitivity shown in the driving method of FIG. 7 is set will be described.

  The processes of S201 to S205 in FIG. 9 are the same as those in the first embodiment. At S206 ', the control unit 109 drives the imaging panel 105 and the readout circuit 20. Specifically, the control unit 109 AD converts the reset signal held in each pixel within a frame period, and transfers pixel data of the high sensitivity reset image and the low sensitivity reset image to the signal processing unit 101. The signal processing unit 101 generates a high sensitivity reset image and a low sensitivity reset image based on the transferred pixel data, and stores the high sensitivity reset image and the low sensitivity reset image in the storage unit 115.

  In S207 ', the control unit 109 AD converts the accumulated signal held in each pixel within a frame period, and transfers it to the signal processing unit 101 as pixel data of a high sensitivity radiation image and a low sensitivity radiation image. The signal processing unit 101 subtracts the pixel data of the reset image of the sensitivity corresponding to the pixel data and the pixel data of the correction image of the corresponding sensitivity from the sequentially transferred pixel data to obtain a high sensitivity frame. Generate images and low sensitivity frame images. The correction image used here is a correction image stored in advance in the storage unit according to the shooting mode. A correction image of the same imaging mode as radiation imaging, such as resolution and accumulation time, is selected.

  In step S208 ', the signal processing unit 101 transfers frame images of a plurality of sensitivities to a post-process according to the shooting mode. In the post-process, image processing such as gain correction processing, dynamic range expansion processing, and sharpening processing is performed on the transferred frame image in parallel with radiation imaging by a pipeline method. In the case of radiography in which an image is observed in real time such as radioscopic radiography, the processed image is transferred to the display unit 102 and displayed. In the case of imaging for processing based on a plurality of images such as 3D imaging, a frame image after image processing is stored in the storage unit 115. The processes of S209 to S212 in FIG. 9 are the same as those in the first embodiment.

P pixel, SYS radiation imaging system, 100 radiation imaging apparatus, 101 signal processing unit, 102 display unit, 103 irradiation control unit, 104 radiation generator, 109 control unit

Claims (11)

A radiation imaging system for generating a moving image, comprising:
A plurality of pixels each having a signal generation unit for converting radiation into charge;
A readout circuit that reads out, from each pixel, an accumulation signal output from the signal generation unit according to the accumulated charge and a reset signal output from the signal generation unit in a reset state;
A storage unit capable of storing data;
And a signal processing unit,
The signal processing unit
Before the first radiation irradiation, the correction image generated based on the reset signal read from each pixel and the accumulation signal is stored in the storage unit.
A radiation image generated based on the accumulated signal read from each pixel during each frame period, a reset image generated based on the reset signal read from each pixel, and stored in the storage unit A radiation imaging system comprising: generating a frame image based on the correction image.   The radiation imaging system according to claim 1, wherein the accumulation signal and the reset signal are read out from each pixel to the readout circuit through the same signal path. Each of the plurality of pixels further includes a holding unit capable of holding the accumulation signal and the reset signal,
The radiation imaging system according to claim 1, wherein the readout circuit reads out the accumulated signal and the reset signal held by the holding unit.
  The radiation imaging system according to claim 3, wherein the accumulated signal is held in the holding unit after the reset signal is read out from the holding unit.   The radiation imaging system according to claim 3, wherein an accumulation period for generating the accumulation signal starts after holding the reset signal in the holding unit.   The radiation imaging system according to any one of claims 1 to 5, wherein the signal processing unit generates the frame image by subtracting the reset image and the correction image from the radiation image. . Each of the plurality of pixels further includes a first holding unit and a second holding unit,
The accumulation signal output from the signal generation unit is held in the first holding unit, and the reset signal output from the signal generation unit is held in each of the first holding unit and the second holding unit.
The signal processing unit
The first reset signal read out from the second holding unit through the second signal path is subtracted from the reset signal read out from the first holding unit through the first signal path before the first radiation irradiation. Generating the reset image based on the result,
A second result obtained by subtracting the reset signal read from the second holding unit through the second signal path from the accumulated signal read from the first holding unit through the first signal path in each frame period The radiation imaging system according to any one of claims 1 to 6, wherein the radiation image is generated based on it. The readout circuit further includes an AD converter.
The radiation imaging system according to claim 7, wherein the readout circuit supplies the first result and the second result converted into digital data by the AD conversion unit to the signal processing unit.   The signal processing unit generates the correction image based on the reset signal read a plurality of times from each pixel and the accumulated signal read a plurality of times. The radiation imaging system according to claim 1. A plurality of pixels each having a signal generation unit for converting radiation into charge, an accumulated signal output from the signal generation unit according to the charge accumulated from each pixel, and the signal generation unit in a reset state output A moving image generation method using data obtained by a radiation imaging apparatus having a reset signal for
Storing a correction image generated based on the reset signal and the accumulation signal read from each pixel before the first radiation irradiation;
A radiation image generated based on the accumulated signal read from each pixel during each frame period, a reset image generated based on the reset signal read from each pixel, and stored in the storage unit Generating a frame image based on the correction image,
A method characterized in that it comprises:   The program for making a computer perform each process of the method of Claim 10.

Images