JP2019054133A - Compound semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a compound semiconductor device capable of satisfying both conflicting characteristics such as low resistance and high resistance required between a compound semiconductor layer and each electrode.SOLUTION: The compound semiconductor device comprises: a compound semiconductor layer 2; a source electrode 4, a drain electrode 5 and a gate electrode 6 which has a work function higher than that of the source electrode 4 and the drain electrode 5, which are formed on the compound semiconductor layer 2; a pair of structures 11, 12 formed at the positions in the compound semiconductor layer 2 below the source electrode 4 and the drain electrode 5 but not formed at the position below the gate electrode 6. In the compound semiconductor layer 2, a first region 13 between the structures 11, 12 and the source electrode 4 and the drain electrode 5 has a density of dislocation defects higher than that in a second region 14 below the gate electrode 6.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN that is a nitride semiconductor is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, GaN is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As devices using nitride semiconductors, many reports have been made on field effect transistors, in particular, high electron mobility transistors (HEMTs). In addition, research into application to diodes has been actively conducted.

JP 2009-16655 A JP 2006-351794 A JP 2006-179546 A JP 2006-148015 A

  In the nitride semiconductor device, for example, two types of electrodes (first electrode and second electrode) are provided. The first electrode is required to have a low resistance between the nitride semiconductor layer. On the other hand, the second electrode is required to have high resistance between the nitride semiconductor layer. For example, if HEMT is taken as an example of the nitride semiconductor device, the first electrode is a source electrode and a drain electrode, and the second electrode is a gate electrode. In the HEMT, the first electrode is required to keep the contact resistance between the first electrode and the nitride semiconductor layer low in order to improve the operating current of the device and improve the operating efficiency. On the other hand, the second electrode is required to keep the leakage current of the nitride semiconductor layer low.

  As described above, in the nitride semiconductor device, the first electrode and the second electrode are in a relationship requiring contradictory characteristics, and it is extremely difficult to satisfy both characteristics.

  An object of the present invention is to provide a compound semiconductor device that satisfies both of the conflicting characteristics of low resistance and high resistance required between a compound semiconductor layer and a first electrode and a second electrode, and a method for manufacturing the same. .

  In one embodiment, a compound semiconductor device includes a compound semiconductor layer, a first electrode provided above the compound semiconductor layer, and a work function provided above the compound semiconductor layer, the work function being higher than that of the first electrode. A second electrode having a high height, and a structure that is provided at a position in the compound semiconductor layer below the first electrode and is absent below the second electrode, and the compound semiconductor layer Has a higher density of dislocation defects in the first region between the structure and the first electrode than in the second region below the second electrode.

  In one aspect, a method for manufacturing a compound semiconductor device includes a step of forming a structure, and a first region above the structure is embedded in the second region in which the structure is absent. A step of forming a compound semiconductor layer having a high density of dislocation defects; a step of forming a first electrode in the first region above the compound semiconductor layer; and the second region above the compound semiconductor layer. Forming a second electrode having a work function higher than that of the first electrode.

  In one aspect, a compound semiconductor device that satisfies both conflicting characteristics of low resistance and high resistance required between the compound semiconductor layer and the first electrode and the second electrode is realized.

It is a schematic sectional drawing which shows the manufacturing method of AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 3 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. It is a schematic sectional drawing for paying attention to the initial layer which grows first among compound semiconductor layers about a mode that a high-density dislocation defect is formed in a compound semiconductor layer. It is a photograph figure shown about the result of having acquired the shape image and electric current image of the surface of a compound semiconductor layer. Characteristics of the relationship between the gate-source voltage (V _gs ), the gate current (I _g ), and the drain current (I _d ) of the AlGaN / GaN HEMTs of Samples 1 and 2 as the first embodiment and the comparative example. FIG. FIG. 5 is a characteristic diagram showing the relationship between dislocation defect density (/ cm ² ) and leakage current (relative value). It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by the modification 1 of 1st Embodiment. FIG. 8 is a schematic cross-sectional view showing the main steps of the method for manufacturing the AlGaN / GaN HEMT according to Modification 1 of the first embodiment, following FIG. 7. It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by the modification 2 of 1st Embodiment. FIG. 10 is a schematic cross-sectional view illustrating main steps of the AlGaN / GaN HEMT manufacturing method according to Modification 2 of the first embodiment, following FIG. 9. It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by the modification 3 of 1st Embodiment. FIG. 12 is a schematic cross-sectional view showing main steps of the method for manufacturing the AlGaN / GaN HEMT according to Modification 3 of the first embodiment, following FIG. 11. It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by the modification 4 of 1st Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of AlGaN / GaN * HEMT by the modification 5 of 1st Embodiment. FIG. 15 is a schematic cross-sectional view showing the main steps of the method for manufacturing the AlGaN / GaN HEMT according to Modification 5 of the first embodiment following FIG. 14. It is a schematic sectional drawing which shows the manufacturing method of the diode by 2nd Embodiment to process order. FIG. 17 is a schematic cross-sectional view illustrating the manufacturing method of the diode according to the second embodiment in order of processes subsequent to FIG. 16; It is a connection diagram which shows schematic structure of the power supply device by 3rd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 4th Embodiment.

[First Embodiment]
In this embodiment, a nitride semiconductor AlGaN / GaN HEMT is disclosed as a compound semiconductor device.
1 to 2 are schematic cross-sectional views showing the method of manufacturing the AlGaN / GaN HEMT according to the first embodiment in the order of steps.

  First, as shown in FIG. 1A, structures 11 and 12 are formed on, for example, a Si substrate 1 as a growth substrate. As the growth substrate, an SiC substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the Si substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.

Specifically, for example, an insulating material on the Si substrate 1, specifically SiO _2, SiN, SiON or the like, wherein the SiO ₂ is deposited to a thickness of, for example, about 40nm by CVD. The deposited SiO ₂ is processed by lithography and etching to leave SiO ₂ with a width of, for example, about 1 μm only at a position aligned below the formation region of the subsequent source electrode and drain electrode formation region on the Si substrate 1. . Thus, the structures 11 and 12 made of SiO ₂ are formed on the Si substrate 1.

Subsequently, as illustrated in FIG. 1B, the compound semiconductor layer 2 is formed on the Si substrate 1 so as to bury the structures 11 and 12.
The compound semiconductor layer 2 includes an initial layer 2a, a buffer layer 2b, an electron transit layer 2c, an electron supply layer 2d, and a cap layer 2e. A thin spacer layer may be formed between the electron transit layer 2c and the electron supply layer 2d.

  Two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2c and the electron supply layer 2d. This 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 2c and the compound semiconductor (here, AlGaN) of the electron supply layer 2d.

Specifically, the following compound semiconductors are grown on the Si substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the Si substrate 1, AlN, Al _x Ga _1-x N having a multilayer structure (0.2 <x <0.8) with varying Al composition, i (intensive undoped) -GaN, AlGaN, and N-GaN is grown sequentially. AlN is about 160 nm thick, Al _x Ga _1-x N multilayer structure is about 500 nm in total thickness, i-GaN is about 1 μm thick, AlGaN is about 5 nm to about 20 nm thick, n -GaN grows to a thickness of about 4 nm. Thus, the initial layer 2a, the buffer layer 2b, the electron transit layer 2c, the electron supply layer 2d, and the cap layer 2e are formed.

As growth conditions for AlN, a mixed gas of trimethylaluminum (TMA) gas and ammonia (NH ₃ ) gas is used as a source gas. As a growth condition for GaN, a mixed gas of trimethylgallium (TMG) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMA gas, TMG gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of the TMA gas as the Al source and the TMG gas as the Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to about 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

During the growth of n-GaN in the cap layer 2e, for example, SiH ₄ gas containing, for example, Si as an n-type impurity is added to the source gas at a predetermined flow rate, and GaN is doped with silicon (Si). As the n-type impurity, germanium (Ge) or oxygen (O) may be used instead of Si. The cap layer 2e has a concentration profile in which the n-type impurity concentration gradually increases from the lower surface to the upper surface. In this case, Si doping to GaN is performed by gradually increasing the flow rate of the SiH ₄ gas and, for example, a predetermined value of 5 × 10 ¹⁶ / cm ³ or more in the vicinity of the upper surface, here, about 1 × 10 ¹⁸ / cm ^3. Adjust so that Note that the cap layer 2e may have a concentration profile in which the n-type impurity concentration is uniform in the film thickness direction, instead of the above-described concentration profile.

  In some cases, the cap layer 2e is not formed. In this case, the electron supply layer 2d has a concentration profile in which the n-type impurity concentration gradually increases, for example, from the lower surface to the upper surface. Si doping to AlGaN is performed by doping an n-type impurity such as Si as in the case of the cap layer 2e.

In the present embodiment, the compound semiconductor layer 2 is formed so as to embed the structures 11 and 12 on the Si substrate 1. In the second region 14 in the compound semiconductor layer 2 where the structures 11 and 12 are absent above the Si substrate 1, the generated dislocation defects are of low density. The dislocation defect is not shown in FIG. On the other hand, due to the structures 11 and 12, dislocation defects 13 a having a higher density than the dislocation density of the second region 14 are present in the first region 13 located above the structures 11 and 12 of the compound semiconductor layer 2. Generated. The density of the dislocation defects 13a is set to a predetermined value within a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² , for example, about 1 × 10 ⁹ / cm ² for the reason described later. The

FIG. 3 is a schematic cross-sectional view for explaining a state in which high-density dislocation defects are formed in the compound semiconductor layer, focusing on the initial layer grown first among the compound semiconductor layers.
First, as shown in FIG. 3A, the structures 11 and 12 made of SiO ₂ are formed on the Si substrate 1 in the same manner as described above.
Next, as shown in FIG. 3B, AlN to be the initial layer 2 a is grown on the Si substrate 1. The growth of AlN starts in the vertical direction from the region where the structures 11 and 12 on the Si substrate 1 are absent.

  Next, as shown in FIG. 3C, AlN grows beyond the thickness of the structures 11 and 12, and gradually extends from the vertical direction to the horizontal direction so as to cover the upper surfaces of the structures 11 and 12. As shown in FIG. 3D, the growth of AlN in the lateral direction continues.

  Next, as shown in FIG. 3E, the AlN grown from the left and right in the figure collide with each other and the AlN crystal is bonded. Here, the crystal orientation of the AlN crystal which has begun to grow from the right side or the left side of the structures 11 and 12 does not completely coincide with each other, and the orientation of the hexagonal column which is the basic structure of the nitride semiconductor is slightly different in the plane. . Therefore, a high-density dislocation defect is easily generated at a position where an AlN crystal grown from another region is bonded.

Then, as shown in FIG. 3 (f), the surface is flattened so as to embed the structures 11 and 12 on the Si substrate 1, and an initial layer 2a is formed as shown in FIG. 3 (g). . In the initial layer 2a, low density dislocation defects 14a are formed in the second region 14 where the structures 11 and 12 are absent above the Si substrate 1. On the other hand, due to the structures 11 and 12, dislocation defects 13a having a higher density than the dislocation defects 14a are formed in the first region 13 located above the structures 11 and 12 of the initial layer 2a.
Thereafter, the dislocation defects 13a and 14a are taken over by the buffer layer 2b, the electron transit layer 2c, the electron supply layer 2d, and the cap layer 2e formed in the initial layer 2a. As described above, as shown in FIG. 1B, the compound semiconductor layer 2 having the high density of dislocation defects 13a in the first region 13 and the density of dislocation defects lower than that of the dislocation defects 13a is formed in the second region 14. Is done.

  In the present embodiment, the uppermost layer of the compound semiconductor layer 2 is a cap layer 2e containing an n-type impurity or an electron supply layer 2d containing an n-type impurity. The reason why the uppermost layer is doped with n-type impurities will be described with reference to FIG. FIG. 4 shows the results of acquiring the shape image and current image of the surface of the compound semiconductor layer for two types of AlGaN / GaN HEMTs (samples 1 and 2) that do not have the structures 11 and 12 of the present embodiment. In Sample 1, an n-GaN cap layer is provided on the uppermost layer of the compound semiconductor layer. In sample 2, an i-GaN cap layer not containing an n-type impurity is provided on the uppermost layer of the compound semiconductor layer. (A) is a shape image of sample 1, (b) is a current image of sample 1, (c) is a shape image of sample 2, and (d) is a current image of sample 2.

  In Sample 1, minute surface pits related to high-density dislocation defects are observed on the surface of the compound semiconductor layer (FIG. 4A). Furthermore, in sample 1, it can be read that each pit works as a current leak path via screw dislocation or mixed dislocation (FIG. 4B). On the other hand, in Sample 2, as in Sample 1, pits related to dislocation defects are observed on the surface of the compound semiconductor layer (FIG. 4C). This is a natural result because it is unlikely that the dislocation density will change only by changing the conductivity type of the outermost cap layer. On the other hand, sample 2 does not work as a leakage current path serving as a current transport path despite the presence of high-density dislocation defects on the surface of the compound semiconductor layer (FIG. 4D). In Sample 1, since each electrode is formed on the surface of the compound semiconductor layer, it is necessary that a current transport path of dislocation defects exists on the surface. 4A to 4D, in order for the dislocation defect to become a current transport path, it is necessary that the dislocation defect not only reaches the surface of the compound semiconductor layer, but also that the surface is doped with an n-type impurity. I understand that.

Subsequent to FIG. 1B, the element isolation structure 3 is formed as shown in FIG.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor layer 2. Thereby, the element isolation structure 3 is formed in the surface layer portions of the compound semiconductor layer 2 and the Si substrate 1. An active region is defined on the compound semiconductor layer 2 by the element isolation structure 3.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor layer 2.

Subsequently, as shown in FIG. 2A, the source electrode 4 and the drain electrode 5 are formed as the first electrode.
Specifically, first, a resist mask for forming the source electrode and the drain electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor layer 2 to form openings that expose the formation sites of the source electrode and the drain electrode. The formation site of the source electrode which is the first electrode is the first region 13 where the high-density dislocation defects 13 a located above the structure 11 are formed on the compound semiconductor layer 2. Similarly, the formation region of the drain electrode which is the first electrode is the first region 13 in which the high-density dislocation defects 13 a located above the structure 12 are formed on the compound semiconductor layer 2. Thus, a resist mask having the opening is formed.

  Using this resist mask, the first electrode material is deposited on the resist mask including the inside of the opening exposing the formation site (first region 13) of the source electrode and the drain electrode on the surface of the compound semiconductor layer 2 by vapor deposition, for example. accumulate. As the first electrode material, a material having a work function lower than that of the second electrode material of the gate electrode, which will be described later, such as Ti, Al, In, or the like is used. Here, for example, Ti (lower layer) / Al (upper layer) is used. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated in a nitrogen atmosphere, for example, at a temperature of about 400 ° C. to 1000 ° C., for example, about 600 ° C., and the remaining Ti / Al is brought into ohmic contact with the cap layer 2e. If an ohmic contact with the Ti / Al cap layer 2e is obtained, heat treatment may be unnecessary. As described above, the source electrode 4 and the drain electrode 5 are formed on the first region 13 in which the high-density dislocation defects 13a are formed on the surface of the compound semiconductor layer 2.

Subsequently, as shown in FIG. 2B, a gate electrode 6 is formed as a second electrode.
Specifically, first, a resist mask for forming the gate electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied to the surface of the compound semiconductor layer 2 to form an opening that exposes the formation site of the gate electrode. The formation site of the gate electrode which is the second electrode is the second region 14 on the compound semiconductor layer 2 where the structures 11 and 12 are absent and the dislocation defects are lower in density than the first region 13. Thus, a resist mask having the opening is formed.

  Using this resist mask, the second electrode material is deposited on the resist mask including the inside of the opening exposing the gate electrode formation site (region where the dislocation defect 14 is formed) by, for example, vapor deposition. As the second electrode material, a material having a work function higher than that of the first electrode material of the source electrode 4 and the drain electrode 5, for example, a material appropriately selected from Ni, Pt, Pd, Au and the like is used. Here, for example, Ni (lower layer) / Au (upper layer) is used. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. As described above, the gate electrode 6 is formed on the second region 14 where dislocation defects are low density on the surface of the compound semiconductor layer 2.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 4, drain electrode 5, and gate electrode 6, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. The AlGaN / GaN HEMT according to the present embodiment is formed.

  In the present embodiment, a current leak path is formed by a high-density dislocation defect 13a immediately below the source electrode 4 and the drain electrode 5 of the compound semiconductor layer 2, so that a low contact resistance is obtained and a large current operation is realized. To do. The formation of the leakage current path due to the fact that both the high-density dislocation defects 13a and the n-type impurities on the outermost surface (cap layer 2e) of the compound semiconductor layer 2 are aligned can be understood as follows. In dislocation defects, it is known that impurities and point defects gather around them. For this reason, the n-type impurity doped on the outermost surface of the compound semiconductor layer 2 tends to gather near the dislocation line, and the n-type impurity concentration locally increases. Thereby, it is considered that the pit position on the outermost surface works as a current leak path.

  On the other hand, there are no high-density dislocation defects 13a immediately below the gate electrode 6 of the compound semiconductor layer 2 (the density of dislocation defects is lower than that of the dislocation defects 13a). Although n-type impurities are present on the outermost surface of the compound semiconductor layer 2, a large current leak path is not formed only by this. Accordingly, with respect to the gate electrode 6, a high resistance is obtained between the compound semiconductor layer 2 and a gate structure with a small gate leakage current is realized.

The results of examining the transistor operating characteristics of the AlGaN / GaN HEMT according to the present embodiment based on the comparison with the comparative example will be described with reference to FIG. FIG. 5 shows the relationship between the gate-source voltage (V _gs ), the gate current (I _g ), and the drain current (I _d ) for the AlGaN / GaN HEMTs of Samples 1 and 2 that are the present embodiment and the comparative example. FIG.

In sample 1, in order to realize a large current operation, the cap layer is formed thin so that the contact resistance at the interface between the source and drain electrodes and the compound semiconductor layer is reduced, and the surface of the cap layer, for example, 5 × 10 ¹⁹ The structure has a high concentration of n-type impurities exceeding / cm ³ . According to sample 1, the contact resistance is reduced, so that a large current operation of the transistor can be realized, but the barrier property between the gate electrode and the compound semiconductor layer is also lowered, and the gate leakage current is increased. To do. Accordingly, when the transistor is turned off, electrons flowing from the gate electrode flow toward the drain electrode, so that the off characteristics of the transistor are deteriorated.

  Sample 2 has a structure having a compound semiconductor layer with a low dislocation defect density over the entire surface in order to reduce the gate leakage current and form a good Schottky barrier. According to the sample 2, while it is possible to realize a characteristic with a small gate leakage current, in order to realize a large current operation, the contact resistance at the interface between the source electrode and the drain electrode and the compound semiconductor layer is increased. Operation cannot be realized.

  In contrast to Samples 1 and 2, according to the present embodiment, a current leak path is formed at the interface between the source and drain electrodes and the compound semiconductor layer due to the presence of high-density dislocation defects and n-type impurities. Current operation is realized. On the other hand, since a dislocation density is suppressed under the gate electrode, formation of a current leak path becomes insufficient, and a low gate leak current is realized.

The results of investigating the density of dislocation defects (dislocation density) contributing to leakage characteristics for AlGaN / GaN.HEMT will be described with reference to FIG. FIG. 6 is a characteristic diagram showing the relationship between dislocation defect density (/ cm ² ) and leakage current (relative value). In FIG. 6, a simulation was performed by defining a leak current 1 × 10 ⁵ times as large as a significant leak current in a portion (flat portion) where there is no dislocation defect and no leak current is generated.

When the dislocation density is less than 1 × 10 ⁵ / cm ² , the leak current corresponding to the current in the flat portion exceeds the leak current of 1 × 10 ⁵ times. In this case, the leakage characteristic is dominant in the flat portion, and the leakage current does not depend on the dislocation density when the dislocation density is less than 1 × 10 ⁵ / cm ² . On the other hand, when the dislocation density is 1 × 10 ⁵ / cm ² or more, the leakage current of 1 × 10 ⁵ times exceeds the leakage current of the flat portion. In this case, the leakage characteristic is dominated by the leakage current through the dislocation defect, and the leakage current depends on the dislocation density when the dislocation density is 1 × 10 ⁵ / cm ² or more. As described above, in the present embodiment, the dislocation density of the dislocation defects 13 generated due to the structures 11 at positions below the source electrode 4 and the drain electrode 5 is preferably 1 × 10 ⁵ / cm ² or more.

On the other hand, when the dislocation density of the dislocation defects 13 exceeds 5 × 10 ¹¹ / cm ² , there is a concern that depletion may occur in the crystal of the first region 13. Therefore, the dislocation density is 5 × 10 ¹¹ / cm ² or less. It is preferable.
As described above, the dislocation density of the dislocation defects 13 is preferably a predetermined value within a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² . Thereby, the contact resistance between the source electrode 4 and the drain electrode 5 and the compound semiconductor layer 2 is sufficiently reduced without being depleted in the crystal of the first region 13.

  As described above, according to the present embodiment, the conflicting characteristics of low resistance and high resistance, which are required between the compound semiconductor layer 2 and the source electrode 4, the drain electrode 5, and the gate electrode 6, are satisfied. . As a result, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

[Modification]
Here, various modifications of the AlGaN / GaN HEMT according to the first embodiment will be described. In addition, about the structural member etc. similar to 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

(Modification 1)
The first modification is different from the first embodiment in that the structures of structures located below the source electrode and the drain electrode are different.
7 to 8 are schematic cross-sectional views showing the main steps of the method for manufacturing an AlGaN / GaN HEMT according to the first modification of the first embodiment.

  First, as shown in FIG. 7A, structures 21 and 22 are formed on, for example, a Si substrate 1 as a growth substrate. As the growth substrate, an SiC substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the Si substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.

Specifically, for example, an insulating material on the Si substrate 1, specifically SiO _2, SiN, SiON or the like, wherein the SiO ₂ is deposited to a thickness of, for example, about 40nm by CVD. The deposited SiO ₂ is processed by lithography and etching, and a plurality of structures are formed on the Si substrate 1 only at a position aligned below the formation region of the later source electrode and drain electrode, for example, over a width of about 1 μm. The SiO ₂ is left so that the bodies 21a and 22a are gathered side by side. As described above, the structures 21 and 22 including the plurality of structures 21 a and 22 a are formed on the Si substrate 1.

  Subsequently, as shown in FIG. 7B, the compound semiconductor layer 2 is formed on the Si substrate 1 so as to embed the structures 21 and 22 as in FIG. 1B of the first embodiment. .

In the first modification, the compound semiconductor layer 2 is formed so as to embed the structures 21 and 22 on the Si substrate 1. In the compound semiconductor layer 2, the generated dislocation defects have a low density in the second region 24 where the structures 21 and 22 are absent above the Si substrate 1. The dislocation defects are not shown. On the other hand, due to the structures 21 and 22, the first region 23 located above the structures 21 and 22 of the compound semiconductor layer 2 has dislocation defects 23 a having a higher density than the dislocation defects in the second region 24. Generated. For the reason described above, the density of the dislocation defects 23a is set to a predetermined value within a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² , for example, about 1 × 10 ⁹ / cm ^2. The

  In the first modification, when the compound semiconductor layer 2 is grown (here, when AlN is grown as the initial layer 2a), the surface of each of the fine structures 21a and 22a constituting the structures 21 and 22 is substantially omitted. A high-density dislocation defect is generated from the central part. Since the structures 21a and 22a are gathered side by side over the first region 23 that is aligned below the formation region of the source electrode and the drain electrode on the Si substrate 1, the structures 21a and 22a cover the entire first region 23. As a result, dislocation defects of fine density and high density are formed substantially uniformly.

Subsequently, as in FIG. 1C of the first embodiment, the element isolation structure 3 is formed.
Subsequently, as illustrated in FIG. 7C, the source electrode 4 and the drain electrode 5 are formed as the first electrode, as in FIG. 2A of the first embodiment. The source electrode 4 and the drain electrode 5 are formed on the first region 23 where the high-density dislocation defects 23 a are formed on the surface of the compound semiconductor layer 2.

  Subsequently, as shown in FIG. 8, the gate electrode 6 is formed as the second electrode, similarly to FIG. 2B of the first embodiment. The gate electrode 6 is formed on the second region 24 on the surface of the compound semiconductor layer 2 where dislocation defects are low density.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 4, drain electrode 5, and gate electrode 6, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, an AlGaN / GaN.HEMT according to Modification 1 is formed.

  In the first modification, a current leak path is formed by a high-density dislocation defect 23 immediately below the source electrode 4 and the drain electrode 5 of the compound semiconductor layer 2 so that a low contact resistance is obtained and a large current operation is realized. To do. The dislocation defects 23a are formed almost uniformly and finely and densely over the entire region of the source electrode 4 and the drain electrode 5 by the structures 21 and 22, and a low contact resistance is reliably obtained.

  On the other hand, there are no high-density dislocation defects 23 immediately below the gate electrode 6 of the compound semiconductor layer 2 (the density of dislocation defects is lower than that of the dislocation defects 23a). Although n-type impurities are present on the outermost surface of the compound semiconductor layer 2, a large current leak path is not formed only by this. Accordingly, with respect to the gate electrode 6, a high resistance is obtained between the compound semiconductor layer 2 and a gate structure with a small gate leakage current is realized.

  As described above, according to the first modification, the conflicting characteristics of low resistance and high resistance required between the compound semiconductor layer 2 and the source electrode 4, the drain electrode 5, and the gate electrode 6 are satisfied. . As a result, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

(Modification 2)
Modification 2 is different from the first embodiment in that the arrangement positions of the structures located below the source electrode and below the drain electrode are different.
FIG. 9 to FIG. 10 are schematic cross-sectional views showing the main steps of the AlGaN / GaN.HEMT manufacturing method according to the second modification of the first embodiment.

  First, as shown in FIG. 9A, an initial layer 2a and a buffer layer 2b which are part of the compound semiconductor layer 2 are formed on, for example, a Si substrate 1 as a growth substrate.

Subsequently, as shown in FIG. 9B, the structures 11 and 12 are formed on the buffer layer 2b.
Specifically, for example, an insulating material on the buffer layer 2b, SiO _2, SiN specifically, SiON or the like, wherein the SiO ₂ is deposited to a thickness of, for example, about 40nm by CVD. The deposited SiO ₂ is processed by lithography and etching, and the SiO ₂ is left in a width of, for example, about 1 μm only at a position aligned below the formation region of the subsequent source electrode and drain electrode formation region on the buffer layer 2b. . Thus, the structures 11 and 12 made of SiO ₂ are formed on the buffer layer 2b.

  Subsequently, as shown in FIG. 9C, the electron transit layer 2c, the electron supply layer 2d, and the cap, which are the remaining portions of the compound semiconductor layer 2, are embedded on the buffer layer 2b so as to embed the structures 11 and 12. Layer 2e is formed. Thus, the compound semiconductor layer 2 including the structures 11 and 12 is formed.

In Modification 2, the compound semiconductor layer 2 is formed so as to embed the structures 11 and 12 on the buffer layer 2b. In the compound semiconductor layer 2, in the second region 14 where the structures 11 and 12 are absent above the buffer layer 2b, the generated dislocation defects have a low density. The dislocation defects are not shown. On the other hand, due to the structures 11, 12, dislocation defects 13 a having a higher density than the dislocation defects in the second region 14 are present in the first region 13 located above the structures 11, 12 of the compound semiconductor layer 2. Generated. For the reason described above, the density of the dislocation defects 13a is, for example, a predetermined value in a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² , for example, about 1 × 10 ⁹ / cm ^2. The

  If a dislocation line exists in the buffer layer, the dislocation line becomes a current leak path, so that electrons diffuse to the back of the device in such a manner that the dislocation line is transmitted. This means that electrons easily reach the buffer layer during device operation. Since there are many electron traps in the low quality buffer layer, there is a concern that the electron traps capture electrons and cause current collapse. In Modification 2, since the structures 11 and 12 are formed on the buffer layer 2b, the high-density dislocation defects 13a are not formed in the initial layer 2a and the buffer layer 2b of the compound semiconductor layer 2. Therefore, the initial layer 2a and the buffer layer 2b that have a great influence on the quality of the compound semiconductor layer 2 are not affected by the high-density dislocation defects 13a, and the high-quality compound semiconductor layer 2 can be obtained.

Further, the crystal quality of the compound semiconductor layer 2 is greatly influenced by the initial layer 2a grown directly on the Si substrate 1. In the modified example 2, there is no surface protective layer for controlling the dislocation density during the growth of the initial layer 2a. Therefore, the growth conditions such as ultra-high temperature conditions and severe conditions such as ultra-high NH ₃ partial pressure with high corrosivity Can be set freely. Thereby, the crystal quality of the compound semiconductor grown above the buffer layer 2b in the compound semiconductor layer 2 is improved.

  Subsequently, the same processes as in FIGS. 1C to 2B of the first embodiment are performed. Thus, as shown in FIG. 10, the source electrode 4 and the drain electrode 5 that are the first electrodes are formed on the first region 13 in which the high-density dislocation defects 13 a are formed on the surface of the compound semiconductor layer 2. . On the other hand, the gate electrode 6 as the second electrode is formed on the second region 14 where the density of dislocation defects is lower than that of the dislocation defects 13a.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 4, drain electrode 5, and gate electrode 6, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, an AlGaN / GaN.HEMT according to Modification 2 is formed.

  In the second modification, a current leak path is formed by a high-density dislocation defect 13a immediately below the source electrode 4 and the drain electrode 5 of the compound semiconductor layer 2, so that a low contact resistance is obtained and a large current operation is realized. To do.

  On the other hand, there are no high-density dislocation defects 13a immediately below the gate electrode 6 of the compound semiconductor layer 2 (the density of dislocation defects is lower than that of the dislocation defects 13a). Although n-type impurities are present on the outermost surface of the compound semiconductor layer 2, a large current leak path is not formed only by this. Accordingly, with respect to the gate electrode 6, a high resistance is obtained between the compound semiconductor layer 2 and a gate structure with a small gate leakage current is realized.

  As described above, according to the second modification, the conflicting characteristics of low resistance and high resistance required between the compound semiconductor layer 2 and the source electrode 4, the drain electrode 5, and the gate electrode 6 are satisfied. . As a result, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

(Modification 3)
Modification 3 is different from the first embodiment in that the arrangement positions of structures located below the source electrode and below the drain electrode are different.
FIG. 11 to FIG. 12 are schematic cross-sectional views showing main processes of an AlGaN / GaN.HEMT manufacturing method according to Modification 3 of the first embodiment.

  First, as shown in FIG. 11A, an initial layer 2a, a buffer layer 2b, which is a part of the compound semiconductor layer 2, and a lower layer portion 2c1 of the electron transit layer 2c are formed on, for example, a Si substrate 1 as a growth substrate. Form. The lower layer portion 2c1 is a portion below the 2DEG occurrence location in the electron transit layer 2c.

Subsequently, as shown in FIG. 11B, the structures 11 and 12 are formed on the lower layer portion 2c1.
Specifically, for example, insulation on the lower part 2c1, specifically SiO _2, SiN, SiON or the like, wherein the SiO ₂ is deposited to a thickness of, for example, about 40nm by CVD. The deposited SiO ₂ is processed by lithography and etching, and the SiO ₂ is left in a width of, for example, about 1 μm only at a position aligned below the formation region of the subsequent source electrode and drain electrode formation region on the buffer layer 2b. . Thus, the structures 11 and 12 made of SiO ₂ are formed on the lower layer portion 2c1.

  Subsequently, as shown in FIG. 11C, the upper layer portion 2c2 of the electron transit layer 2c, which is the remaining portion of the compound semiconductor layer 2 so as to embed the structures 11 and 12 on the lower layer portion 2c1, the electron supply A layer 2d and a cap layer 2e are formed. Thus, the compound semiconductor layer 2 including the structures 11 and 12 inside (including in the electron transit layer 2c) is formed.

In Modification 3, the compound semiconductor layer 2 is formed so as to embed the structures 11 and 12 on the lower layer portion 2c1 of the electron transit layer 2c. In the compound semiconductor layer 2, the generated dislocation defects have a low density in the second region 14 where the structures 11 and 12 are absent above the lower layer portion 2 c 1. The dislocation defects are not shown. On the other hand, due to the structures 11, 12, dislocation defects 13 a having a higher density than the dislocation defects in the second region 14 are present in the first region 13 located above the structures 11, 12 of the compound semiconductor layer 2. Generated. For the reason described above, the density of the dislocation defects 13a is, for example, a predetermined value in a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² , for example, about 1 × 10 ⁹ / cm ^2. The

  If a dislocation line exists in the buffer layer, the dislocation line becomes a current leak path, so that electrons diffuse to the back of the device in such a manner that the dislocation line is transmitted. This means that electrons easily reach the buffer layer during device operation. Since there are many electron traps in the low quality buffer layer, there is a concern that the electron traps capture electrons and cause current collapse. In Modification 3, since the structures 11 and 12 are formed on the lower layer portion 2c1 above the buffer layer 2b, the initial layer 2a and the buffer layer 2b of the compound semiconductor layer 2 have high-density dislocation defects 13a. Not formed. Therefore, the initial layer 2a and the buffer layer 2b that have a great influence on the quality of the compound semiconductor layer 2 are not affected by the high-density dislocation defects 13a, and the high-quality compound semiconductor layer 2 can be obtained.

Further, the crystal quality of the compound semiconductor layer 2 is greatly influenced by the initial layer 2a grown directly on the Si substrate 1. In Modification 3, since there is no surface protective layer for controlling the dislocation density during the growth of the initial layer 2a, growth conditions such as ultra-high temperature conditions and harsh conditions such as ultra-high NH ₃ partial pressure that is highly corrosive are used. Can be set freely. Thereby, the crystal quality of the compound semiconductor grown above the lower layer portion 2c1 in the compound semiconductor layer 2 is improved.

  Then, the process similar to FIG.1 (c)-FIG.2 (b) of 1st Embodiment is performed. As a result, as shown in FIG. 12, the source electrode 4 and the drain electrode 5 as the first electrode are formed on the first region 13 where the high-density dislocation defects 13a are formed on the surface of the compound semiconductor layer 2. . On the other hand, the gate electrode 6 as the second electrode is formed on the second region 14 where the density of dislocation defects is lower than that of the dislocation defects 13a.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 4, drain electrode 5, and gate electrode 6, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, an AlGaN / GaN.HEMT according to Modification 3 is formed.

  In the third modification, a current leak path is formed by a high-density dislocation defect 13a immediately below the source electrode 4 and the drain electrode 5 of the compound semiconductor layer 2, so that a low contact resistance is obtained and a large current operation is realized. To do.

  On the other hand, there are no high-density dislocation defects 13a immediately below the gate electrode 6 of the compound semiconductor layer 2 (the density of dislocation defects is lower than that of the dislocation defects 13a). Although n-type impurities are present on the outermost surface of the compound semiconductor layer 2, a large current leak path is not formed only by this. Accordingly, with respect to the gate electrode 6, a high resistance is obtained between the compound semiconductor layer 2 and a gate structure with a small gate leakage current is realized.

  As described above, according to the third modification, the conflicting characteristics of low resistance and high resistance required between the compound semiconductor layer 2, the source electrode 4, the drain electrode 5, and the gate electrode 6 are satisfied. . As a result, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

(Modification 4)
In the fourth modification, a so-called MIS type AlGaN / GaN.HEMT provided with a gate insulating film is disclosed.
FIG. 13 is a schematic cross-sectional view showing the main steps of an AlGaN / GaN HEMT manufacturing method according to Modification 4 of the first embodiment.

  First, the same processes as those in FIGS. 1A to 2A of the first embodiment are performed. At this time, as shown in FIG. 13A, the source electrode 4 and the drain electrode 5 that are the first electrodes are formed on the compound semiconductor layer 2.

Subsequently, as illustrated in FIG. 13B, the gate insulating film 7 is formed on the compound semiconductor layer 2.
Specifically, for example, Al ₂ O ₃ is deposited on the compound semiconductor layer 2 as an insulating material. Al ₂ O ₃ is deposited to a thickness of about 2 nm to 200 nm, here about 10 nm, for example, by atomic layer deposition (ALD method). Thereby, the gate insulating film 7 is formed.

Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

  Subsequently, as illustrated in FIG. 13C, the gate electrode 6 is formed on the gate insulating film 7 as the second electrode. The gate electrode 6 is formed in the region where the low density dislocation defects 24 are formed on the surface of the compound semiconductor layer 2 via the gate insulating film 7.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 4, drain electrode 5, and gate electrode 6, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, an AlGaN / GaN.HEMT according to Modification 4 is formed.

  In Modification 4, a current leak path is formed by a high-density dislocation defect 13a immediately below the source electrode 4 and the drain electrode 5 of the compound semiconductor layer 2, so that a low contact resistance is obtained and a large current operation is realized. To do.

  On the other hand, there are no high-density dislocation defects 13a below the gate electrode 6 of the compound semiconductor layer 2 (the density of dislocation defects is lower than that of the dislocation defects 13a). Although n-type impurities are present on the outermost surface of the compound semiconductor layer 2, a large current leak path is not formed only by this. In the modified example 4, the gate insulating film 7 is provided between the gate electrode 6 and the surface of the compound semiconductor layer 2, which contributes to further suppression of the gate leakage current. Accordingly, with respect to the gate electrode 6, a high resistance is obtained between the compound semiconductor layer 2 and a gate structure with a small gate leakage current is realized.

  As described above, according to the modification example 4, the conflicting characteristics of low resistance and high resistance required between the compound semiconductor layer 2 and the source electrode 4, the drain electrode 5, and the gate electrode 6 are satisfied. . As a result, an MIS type AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

Note that in the fourth modification, the first to third modifications can also be applied.
Specifically, by applying the first modification, the structures 11 and 12 can be formed so that a plurality of fine structures are gathered side by side.
By applying the second modification, the structures 11 and 12 can be formed on the buffer layer 2b.
By applying the modification 3, the structures 11 and 12 can be formed in the electron transit layer 2c.

(Modification 5)
The fifth modification is different from the first embodiment in that the partial configuration of the compound semiconductor layer 2 is different.
14 to 15 are schematic cross-sectional views showing the main steps of a method for manufacturing an AlGaN / GaN HEMT according to Modification 5 of the first embodiment.

  First, the same processes as those in FIGS. 1A to 1B of the first embodiment are performed. Here, instead of forming the n-GaN cap layer 2e, the i-GaN cap layer 31a is formed without doping an n-type impurity. As a result, as shown in FIG. 14A, the compound semiconductor layer 31 that embeds the structures 11 and 12 on the Si substrate 1 is formed. The compound semiconductor layer 31 includes an initial layer 2a, a buffer layer 2b, an electron transit layer 2c, an electron supply layer 2d, and an i-GaN cap layer 31a.

In the compound semiconductor layer 31, in the second region 14 where the structures 11 and 12 are absent above the Si substrate 1, the generated dislocation defects have a low density. The dislocation defects are not shown. On the other hand, due to the structures 11 and 12, dislocation defects 13 a having a higher density than the dislocation defects in the second region 14 are present in the first region 13 located above the structures 11 and 12 of the compound semiconductor layer 31. Generated. For the reason described above, the density of the dislocation defects 13a is, for example, a predetermined value in a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² , for example, about 1 × 10 ⁹ / cm ^2. The

Subsequently, as shown in FIG. 14B, grooves 32 and 33 are formed in the compound semiconductor layer 31.
Specifically, first, for example, a SiN film 34 is formed on the compound semiconductor layer 31. A resist is applied onto the SiN film 34, and the resist is processed by lithography to form a resist mask having openings that expose regions including the source electrode and drain electrode formation sites.
Using this resist mask, the portions exposed from the openings of the SiN film 34 and the compound semiconductor layer 31 are etched. By this etching, the SiN film 34 corresponding to each opening of the resist mask and the cap layer 31a, the electron supply layer 2d, and the electron transit layer 2c of the compound semiconductor layer 31 are removed, and grooves 32 and 33 are formed. . The resist mask is removed by wet processing using a chemical solution.

Subsequently, as shown in FIG. 14C, the most grown layers 35 and 36 filling the grooves 32 and 33 are formed.
More specifically, n-GaN is grown up so as to fill the grooves 32 and 33 by, for example, the MOVPE method. N-GaN does not grow on the portion of the compound semiconductor layer 31 where the SiN film 34 is formed. Thereby, the most grown layers 35 and 36 are selectively formed. When the most grown layers 35 and 36 are formed, the dislocation defects 13a are positioned on the bottom surfaces of the grooves 32 and 33, and the dislocation defects 13a are similarly formed in the most grown layers 35 and 36. It will be. For example, Si is used as the n-type impurity doped in GaN. In Si doping to GaN, the flow rate of SiH ₄ gas is gradually increased so that it becomes a predetermined value of, for example, 5 × 10 ¹⁶ / cm ³ or more near the upper surface, here, about 1 × 10 ¹⁸ / cm ^3. Adjust to. The most grown layers 35 and 36 may have a concentration profile in which the n-type impurity concentration is uniform in the film thickness direction. The SiN film 34 is removed by wet etching or the like.

Subsequently, as in FIG. 1C of the first embodiment, the element isolation structure 3 is formed.
Subsequently, as shown in FIG. 15A, the source electrode 4 and the drain electrode 5 are formed as the first electrode, as in FIG. 2A of the first embodiment. The source electrode 4 and the drain electrode 5 are formed on the first region 13 in which the high-density dislocation defects 13 a are formed on the surfaces of the most grown layers 35 and 36 of the compound semiconductor layer 31.

  Subsequently, as shown in FIG. 15B, the gate electrode 6 is formed as the second electrode, similarly to FIG. 2B of the first embodiment. The gate electrode 6 is formed on the second region 14 where the density of dislocation defects is lower than that of the dislocation defects 13a.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 4, drain electrode 5, and gate electrode 6, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. Then, an AlGaN / GaN.HEMT according to Modification 5 is formed.

  In Modification 5, a current leak path is formed by a high-density dislocation defect 13a immediately below the source electrode 4 and the drain electrode 5 of the compound semiconductor layer 31, so that a low contact resistance is obtained and a large current operation is realized. To do. Leakage current path due to both high-density dislocation defects 13a and n-type impurities in the outermost surface of the compound semiconductor layer 31 (the most grown layers 35 and 36, which are upper layers including the outermost surface of the first region 13). The formation of can be understood as follows. In dislocation defects, it is known that impurities and point defects gather around them. For this reason, the n-type impurity doped on the outermost surface of the compound semiconductor layer 31 tends to gather near the dislocation line, and the n-type impurity concentration locally increases. Thereby, it is considered that the pit position on the outermost surface works as a current leak path.

  On the other hand, there are no high-density dislocation defects 13a immediately below the gate electrode 6 of the compound semiconductor layer 31 (the density of dislocation defects is lower than that of the dislocation defects 13a). In Modification 5, since no n-type impurity exists immediately below the gate electrode 6 (the cap layer 31a that is the upper layer portion including the outermost surface of the second region 14), gate leakage is further suppressed. Therefore, with respect to the gate electrode 6, a high resistance is obtained between the compound semiconductor layer 31 and a gate structure with a small gate leakage current is realized.

  As described above, according to the fifth modification, the conflicting characteristics of low resistance and high resistance required between the compound semiconductor layer 31 and the source electrode 4, drain electrode 5, and gate electrode 6 are satisfied. . As a result, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

Note that in the fifth modification, the first to fourth modifications can be applied.
Specifically, by applying the first modification, the structures 11 and 12 can be formed so that a plurality of fine structures are gathered side by side.
By applying the second modification, the structures 11 and 12 can be formed on the buffer layer 2b.
By applying the modification 3, the structures 11 and 12 can be formed in the electron transit layer 2c.
By applying the modification 4, a thin insulating film having a thickness of, for example, about 2 nm can be formed between the gate electrode 6 and the compound semiconductor layer 2.

[Second Embodiment]
In the present embodiment, a nitride semiconductor diode is disclosed as the compound semiconductor device.
16 to 17 are schematic cross-sectional views illustrating the diode manufacturing method according to the second embodiment in the order of steps.

  First, as shown in FIG. 16A, a structure 51 is formed on, for example, a Si substrate 41 as a growth substrate. As the growth substrate, an SiC substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the Si substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.

Specifically, for example, an insulating material on the Si substrate 41, specifically SiO _2, SiN, SiON or the like, wherein the SiO ₂ is deposited to a thickness of, for example, about 40nm by CVD. The deposited SiO ₂ is processed by lithography and etching, and the SiO ₂ is left in a width of, for example, about 1 μm only at a position aligned below the formation region of the subsequent cathode electrode formation region on the Si substrate 41. As a result, the structure 51 made of SiO ₂ is formed on the Si substrate 41.

Subsequently, as illustrated in FIG. 16B, the compound semiconductor layer 42 is formed on the Si substrate 41 so as to bury the structure 51.
The compound semiconductor layer 42 includes an initial layer 42a, a buffer layer 42b, and a drift layer 42c.

Specifically, the following compound semiconductors are grown on the Si substrate 41 by, for example, the MOVPE method. The MBE method or the like may be used instead of the MOVPE method.
On the Si substrate 1, AlN, Al _x Ga _1-x N having a multilayer structure (0.2 <x <0.8) in which the Al composition is changed, and n-GaN are sequentially grown. AlN grows to a thickness of about 5 nm, the multilayer structure of Al _x Ga _1-x N grows to a total thickness of about 500 nm, and n-GaN grows to a thickness of about 1 μm. Thus, the initial layer 42a, the buffer layer 42b, and the drift layer 42c are formed.

As a growth condition for AlN, a mixed gas of TMA gas and NH ₃ gas is used as a source gas. As a growth condition of GaN, a mixed gas of TMG gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMA gas, TMG gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of the TMA gas as the Al source and the TMG gas as the Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of NH ₃ gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

During the growth of n-GaN in the drift layer 42c, for example, SiH ₄ gas containing, for example, Si as an n-type impurity is added to the source gas at a predetermined flow rate, and GaN is doped with Si. As the n-type impurity, Ge or O may be used instead of Si. The drift layer 42c has a concentration profile in which the n-type impurity concentration gradually increases from the lower surface toward the upper surface. In this case, Si doping to GaN is performed by gradually increasing the flow rate of the SiH ₄ gas and, for example, a predetermined value of 5 × 10 ¹⁶ / cm ³ or more in the vicinity of the upper surface, here, about 1 × 10 ¹⁸ / cm ^3. Adjust so that The drift layer 42c may have a concentration profile with a uniform n-type impurity concentration in the film thickness direction.

In the present embodiment, the compound semiconductor layer 42 is formed so as to bury the structure 51 on the Si substrate 41. In the compound semiconductor layer 42, the generated dislocation defects have a low density in the second region 53 at a position where the structure 51 is absent above the Si substrate 41. The dislocation defects are not shown. On the other hand, due to the structure 51, dislocation defects 52 a having a higher density than the dislocation density of the second region 53 are generated in the first region 52 located above the structure 51 of the compound semiconductor layer 42. For the reason described in the first embodiment, the density of dislocation defects 52a is, for example, a predetermined value within a range of about 1 × 10 ⁵ / cm ^{2 to} about 5 × 10 ¹¹ / cm ² , for example, 1 × 10 ^9. / Cm ² .

Subsequent to FIG. 16B, as shown in FIG. 16C, an element isolation structure 43 is formed.
Specifically, for example, Ar is implanted into the element isolation region of the compound semiconductor layer 42. Thereby, the element isolation structure 43 is formed in the compound semiconductor layer 42 and the surface layer portions of the Si substrate 1. An active region is defined on the compound semiconductor layer 42 by the element isolation structure 43.
Note that element isolation may be performed using, for example, the STI method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor layer 42.

Subsequently, as shown in FIG. 17A, an anode electrode 44 is formed as a first electrode.
Specifically, first, a resist mask for forming the anode electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor layer 42 to form an opening that exposes the anode electrode formation site. The formation site of the anode electrode, which is the first electrode, is a first region 52 in which a high-density dislocation defect 52 a located above the structure 51 is formed on the surface of the compound semiconductor layer 42. Thus, a resist mask having the opening is formed.

  Using this resist mask, the first electrode material is deposited on the resist mask including, for example, an opening exposing the formation site (first region 52) of the anode electrode on the surface of the compound semiconductor layer 2 by vapor deposition. As the first electrode material, a material having a work function lower than that of the second electrode material of the cathode electrode, which will be described later, such as Ti, Al, In, or the like is used. Here, for example, Ti (lower layer) / Al (upper layer) is used. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated in a nitrogen atmosphere, for example, at a temperature of about 400 ° C. to 1000 ° C., for example, about 600 ° C., and the remaining Ti / Al is brought into ohmic contact with the drift layer 42c. If an ohmic contact with the Ti / Al drift layer 42c is obtained, heat treatment may be unnecessary. Thus, the anode electrode 44 is formed on each first region 52 in which the high density dislocation defects 52a are formed on the surface of the compound semiconductor layer 42.

Subsequently, as shown in FIG. 17B, a cathode electrode 45 is formed as a second electrode.
Specifically, first, a resist mask for forming the cathode electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied to the surface of the compound semiconductor layer 42 to form an opening that exposes the cathode electrode formation site. The formation site of the cathode electrode, which is the second electrode, is the second region 53 where the structure 51 is absent below the surface of the compound semiconductor layer 42 and the dislocation defects are low density. Thus, a resist mask having the opening is formed.

  Using this resist mask, the second electrode material is deposited on the resist mask including the inside of the opening exposing the cathode electrode formation site (second region 53), for example, by vapor deposition. As the second electrode material, a material having a work function lower than that of the first electrode material of the cathode electrode, for example, a material appropriately selected from Ni, Pt, Pd, Au and the like is used. Here, for example, Ni (lower layer) / Au (upper layer) is used. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. As described above, the cathode electrode 45 is formed on the second region 53 on the surface of the compound semiconductor layer 42 where dislocation defects are low density.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the cathode electrode 44 and the anode electrode 45, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. A diode is formed.

  In the present embodiment, high density dislocation defects 52 a are formed immediately below the anode 44 of the compound semiconductor layer 42. Therefore, the resistance is low under the anode 44 of the compound semiconductor layer 42, and the forward direction from the anode 44 to the cathode 44 is a low-resistance current path. On the other hand, there are no high-density dislocation defects 52a immediately below the cathode electrode 45 of the compound semiconductor layer 42 (the density of dislocation defects is lower than that of the dislocation defects 52a). For this reason, the compound semiconductor layer 42 has a high resistance under the anode electrode 44, and the reverse direction from the cathode electrode 44 to the anode electrode 44 is a current path having a higher resistance than the forward direction.

  As described above, according to the present embodiment, the contradictory characteristics of low resistance and high resistance required between the compound semiconductor layer 42 and the anode electrode 44 and the cathode electrode 45 are satisfied. Thereby, a diode in which the forward direction and the reverse direction are reliably defined is realized.

Note that various modifications of the first embodiment can also be applied to this embodiment.
Specifically, by applying the first modification, the structure 51 can be formed such that a plurality of fine structures are gathered side by side.
By applying the second modification, the structure 51 can be formed on the buffer layer 42b.
The structure 51 can be formed in the drift layer 42c by applying the third modification.
By applying the modification example 4, a thin insulating film having a thickness of, for example, about 2 nm can be formed between the cathode electrode 45 and the compound semiconductor layer 42.
By applying the modification example 5, the portion of the compound semiconductor layer 42 immediately below the anode electrode 45 is i-GaN, and an n-GaN regrowth layer can be formed immediately below the cathode electrode 44.

(Third embodiment)
In the present embodiment, a power supply device to which one kind of AlGaN / GaN HEMT selected from the first embodiment and its various modifications is applied is disclosed.
FIG. 18 is a connection diagram illustrating a schematic configuration of the power supply device according to the third embodiment.

The power supply device according to the present embodiment includes a high-voltage primary circuit 61 and a low-voltage secondary circuit 62, and a transformer 63 disposed between the primary circuit 61 and the secondary circuit 62. The
The primary circuit 61 includes an AC power supply 64, a so-called bridge rectifier circuit 65, and a plurality (four in this case) of switching elements 66a, 66b, 66c, and 66d. The bridge rectifier circuit 65 includes a switching element 66e.
The secondary side circuit 62 includes a plurality (three in this case) of switching elements 67a, 67b, and 67c.

  In the present embodiment, the switching elements 66a, 66b, 66c, 66d, and 66e of the primary circuit 61 are one type of AlGaN / GaN HEMT selected from the first embodiment and its various modifications. On the other hand, the switching elements 67a, 67b, and 67c of the secondary circuit 62 are normal MIS • FETs using silicon.

  In the present embodiment, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is applied to a high voltage circuit. As a result, a highly reliable high-power power supply circuit is realized.

(Fourth embodiment)
In the present embodiment, a high-frequency amplifier to which one kind of AlGaN / GaN HEMT selected from the first embodiment and its various modifications is applied is disclosed.
FIG. 19 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the fourth embodiment.

The high frequency amplifier according to the present embodiment includes a digital predistortion circuit 71, mixers 72 a and 72 b, and a power amplifier 73.
The digital predistortion circuit 71 compensates for nonlinear distortion of the input signal. The mixer 72a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 73 amplifies the input signal mixed with the AC signal, and has one type of AlGaN / GaN HEMT selected from the first embodiment and various modifications thereof. In FIG. 19, for example, by switching the switch, the output side signal can be mixed with the AC signal by the mixer 72b and sent to the digital predistortion circuit 71.

  In the present embodiment, an AlGaN / GaN HEMT capable of obtaining a large current operation despite a small gate leakage current is applied to a high-frequency amplifier. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

[Other Embodiments]
In the first, third, and fourth embodiments, the AlGaN / GaN HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

(Other HEMT example 1)
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first, third, and fourth embodiments described above, the electron transit layer is formed of i-GaN, the electron supply layer is formed of n-InAlN, and the cap layer is formed of n-GaN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by spontaneous polarization of InAlN.

  According to this example, similarly to the AlGaN / GaN.HEMT described above, a highly reliable high withstand voltage InAlN / GaN.HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

(Other HEMT example 2)
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first to fifth embodiments described above, the electron transit layer is formed of i-GaN, the electron supply layer is formed of n-InAlGaN, and the cap layer is formed of n-GaN.

  According to this example, similarly to the AlGaN / GaN.HEMT described above, a highly reliable and high withstand voltage InAlGaN / GaN.HEMT capable of obtaining a large current operation despite a small gate leakage current is realized.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Appendix 1) a compound semiconductor layer;
A first electrode provided above the compound semiconductor layer;
A second electrode provided above the compound semiconductor layer and having a higher work function than the first electrode;
A structure provided at a position in the compound semiconductor layer below the first electrode and absent from the second electrode; and
In the compound semiconductor layer, a density of dislocation defects is higher in a first region between the structure and the first electrode than in a second region below the second electrode.

  (Supplementary note 2) The compound semiconductor device according to supplementary note 1, wherein the structure is formed by aggregating a plurality of structures.

(Supplementary Note 3) according to note 1 or 2, wherein the density of dislocation defects in the first region have a value in the range of 5 × 10 ¹¹ / cm ² or less at 1 × 10 ⁵ / cm ² or more Compound semiconductor device.

  (Supplementary note 4) The compound semiconductor device according to any one of supplementary notes 1 to 3, wherein the compound semiconductor layer contains an n-type impurity at least on an outermost surface under the first electrode.

  (Supplementary Note 5) In the compound semiconductor layer, the upper layer portion including the outermost surface of the second region does not contain an n-type impurity, and the upper layer portion including the outermost surface of the first region is an n-type. 5. The compound semiconductor device according to any one of appendices 1 to 4, further comprising an impurity.

(Appendix 6) The compound semiconductor layer is provided on a substrate,
6. The compound semiconductor device according to any one of appendices 1 to 5, wherein the structure is located on the substrate.

(Appendix 7) The compound semiconductor layer has a buffer layer and an electron transit layer above the buffer layer,
6. The compound semiconductor device according to any one of appendices 1 to 5, wherein the structure is located on the buffer layer.

(Appendix 8) The compound semiconductor layer has an electron transit layer,
6. The compound semiconductor device according to any one of appendices 1 to 5, wherein the structure is located in the electron transit layer.

  (Supplementary note 9) The compound semiconductor device according to any one of supplementary notes 1 to 8, wherein an insulating film is provided between the compound semiconductor layer and the second electrode.

(Additional remark 10) The process of forming a structure,
Embedding the structure, and forming a compound semiconductor layer in which a first region above the structure has a higher density of dislocation defects than a second region in which the structure is absent;
Forming a first electrode in the first region above the compound semiconductor layer;
Forming a second electrode having a work function higher than that of the first electrode in the second region above the compound semiconductor layer.

  (Additional remark 11) The said structure is a manufacturing method of the compound semiconductor device of Additional remark 10 characterized by the above-mentioned.

(Supplementary Note 12) according to note 10 or 11, wherein the density of dislocation defects in the first region have a value in the range of 5 × 10 ¹¹ / cm ² or less at 1 × 10 ⁵ / cm ² or more A method for manufacturing a compound semiconductor device.

  (Additional remark 13) The said compound semiconductor layer contains an n-type impurity in the outermost surface under a said 1st electrode, The manufacturing method of the compound semiconductor device of any one of Additional remark 10-12 characterized by the above-mentioned.

  (Supplementary Note 14) In the compound semiconductor layer, the upper layer portion including the outermost surface of the second region does not contain an n-type impurity, and the upper layer portion including the outermost surface of the first region is an n-type. 14. The method of manufacturing a compound semiconductor device according to any one of appendices 10 to 13, wherein the compound semiconductor device includes an impurity.

(Appendix 15) The compound semiconductor layer is provided on a substrate,
15. The method of manufacturing a compound semiconductor device according to any one of appendices 10 to 14, wherein the structure is located on the substrate.

(Supplementary Note 16) The compound semiconductor layer includes a buffer layer and an electron transit layer above the buffer layer,
15. The method of manufacturing a compound semiconductor device according to any one of appendices 10 to 14, wherein the structure is located on the buffer layer.

(Supplementary Note 17) The compound semiconductor layer has an electron transit layer,
15. The method of manufacturing a compound semiconductor device according to any one of appendices 10 to 14, wherein the structure is located in the electron transit layer.

  (Supplementary note 18) The method for manufacturing a compound semiconductor device according to any one of supplementary notes 10 to 17, wherein an insulating film is formed between the compound semiconductor layer and the second electrode.

(Supplementary note 19) A power supply circuit including a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A compound semiconductor layer;
A first electrode provided above the compound semiconductor layer;
A second electrode provided above the compound semiconductor layer and having a higher work function than the first electrode;
A structure provided at a position in the compound semiconductor layer below the first electrode and absent from the second electrode; and
In the compound semiconductor layer, a first region between the structure and the first electrode has a higher density of dislocation defects than a second region below the second electrode.

(Appendix 20) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A compound semiconductor layer;
A first electrode provided above the compound semiconductor layer;
A second electrode provided above the compound semiconductor layer and having a higher work function than the first electrode;
A structure provided at a position in the compound semiconductor layer below the first electrode and absent from the second electrode; and
The high frequency amplifier according to claim 1, wherein the compound semiconductor layer has a higher density of dislocation defects in a first region between the structure and the first electrode than in a second region below the second electrode.

1, 41 Si substrate 2, 31, 42 Compound semiconductor layer 2a, 42a Initial layer 2b, 42b Buffer layer 2c Electron traveling layer 2c1 Lower layer part 2c2 Upper layer part 2d Electron supply layer 2e, 31a Cap layer 3, 43 Element isolation structure 4 Source Electrode 4
5 Drain electrode 6 Gate electrode 7 Gate insulating films 11, 12, 21, 22, 51 Structures 13, 23, 52 First regions 13a, 14a, 23a, 52a Dislocation defects 14, 24, 53 Second regions 21a, 22a Structure Body 32, 33 Groove 34 SiN film 35, 36 Most grown layer 42c Drift layer 44 Anode electrode 45 Cathode electrode 61 Primary side circuit 62 Secondary side circuit 63 Transformer 64 AC power supply 65 Bridge rectifier circuits 66a, 66b, 66c, 66d, 66e , 67a, 67b, 67c Switching element 71 Digital predistortion circuit 72a, 72b Mixer 73 Power amplifier

Claims (10)

A compound semiconductor layer;
A first electrode provided above the compound semiconductor layer;
A second electrode provided above the compound semiconductor layer and having a higher work function than the first electrode;
A structure provided at a position in the compound semiconductor layer below the first electrode and absent from the second electrode; and
In the compound semiconductor layer, a density of dislocation defects is higher in a first region between the structure and the first electrode than in a second region below the second electrode.   The compound semiconductor device according to claim 1, wherein the structure is a collection of a plurality of structures. 3. The compound semiconductor device according to claim 1, wherein the density of dislocation defects in the first region is a value in a range of 1 × 10 ⁵ / cm ² to 5 × 10 ¹¹ / cm ^2. .   The compound semiconductor device according to claim 1, wherein the compound semiconductor layer contains an n-type impurity at least on an outermost surface under the first electrode.   In the compound semiconductor layer, an upper layer portion including the outermost surface of the second region does not contain an n-type impurity, and an upper layer portion including the outermost surface of the first region contains an n-type impurity. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a semiconductor device. The compound semiconductor layer is provided on a substrate,
The compound semiconductor device according to claim 1, wherein the structure is located on the substrate. The compound semiconductor layer has a buffer layer and an electron transit layer above the buffer layer,
The compound semiconductor device according to claim 1, wherein the structure is located on the buffer layer. The compound semiconductor layer has an electron transit layer,
The compound semiconductor device according to claim 1, wherein the structure is located in the electron transit layer.   The compound semiconductor device according to claim 1, wherein an insulating film is provided between the compound semiconductor layer and the second electrode. Forming a structure;
Embedding the structure, and forming a compound semiconductor layer in which a first region above the structure has a higher density of dislocation defects than a second region in which the structure is absent;
Forming a first electrode in the first region above the compound semiconductor layer;
Forming a second electrode having a work function higher than that of the first electrode in the second region above the compound semiconductor layer.