JP2019052869A - Semiconductor device and semiconductor device control method - Google Patents

Abstract

To suppress an increase in circuit area.SOLUTION: A semiconductor device includes: an oscillation unit 11 provided with a variable frequency oscillation circuit 11c for receiving a set value and outputting a signal of an oscillation frequency based on the set value; and a diagnosis unit 12 for supplying the set value to the oscillation unit 11, detecting an oscillation frequency change every time the set value is varied for each change unit, and determining the presence or absence of a characteristic defect of the variable frequency oscillation circuit 11c on the basis of a comparison result between an expected value of the change held in a holding circuit 12c in advance and the detected change.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a method for controlling the semiconductor device.

  Conventionally, when manufacturing a semiconductor device including a PLL (Phase Locked Loop) circuit that outputs a signal having a predetermined oscillation frequency, an external measurement device such as an LSI (Large Scale Integrated circuit) tester is used to set the oscillation frequency to an appropriate value. There was a way to diagnose whether there was. However, measurement by an external measuring device takes time and leads to an increase in test cost. Therefore, there is a method in which a measurement circuit is provided inside the semiconductor device and the oscillation frequency of a VCO (Voltage Control Oscillator) that is a variable frequency oscillation circuit included in the PLL circuit is measured.

  Recently, in order to reduce power consumption of electronic devices such as computers, the operation clock frequency of a processor is dynamically switched. The PLL circuit used in such an electronic device changes the frequency dividing ratio of the frequency dividing circuit in the feedback loop according to the set value, thereby multiplying the input frequency to the PLL circuit (frequency dividing ratio of the frequency dividing circuit). The oscillation frequency may be changed in a relatively wide range.

Japanese Patent Laid-Open No. 11-2666 JP 2000-212239 A JP 2006-41653 A

  The variable frequency oscillation circuit used in the PLL circuit as described above may exhibit a characteristic failure in which an oscillation frequency corresponding to a set value cannot be obtained in a certain oscillation frequency region due to a defect that occurs during manufacture. In order to detect such a characteristic defect, it is only necessary to test whether or not a value corresponding to the set value is obtained over a wide range of oscillation frequencies. However, when the above characteristic failure is detected using a measurement circuit provided in the semiconductor device, a memory area for holding an expected value of the oscillation frequency corresponding to each set value is provided in the semiconductor device. There is a problem that the circuit area increases.

  In one aspect, an object of the present invention is to provide a semiconductor device capable of suppressing an increase in circuit area and a control method thereof.

  In one embodiment, an oscillation unit including a variable frequency oscillation circuit that receives a setting value and outputs a signal having an oscillation frequency based on the setting value, and supplies the setting value to the oscillation unit, and the setting value The amount of change in the oscillation frequency is detected each time the value is changed for each change unit, and the variable is determined based on a comparison result between the expected value of the change held in advance in the holding circuit and the detected change. There is provided a semiconductor device having a diagnostic unit that determines the presence or absence of characteristic defects in the frequency oscillation circuit.

  In one embodiment, a method for controlling a semiconductor device is provided.

  In one aspect, an increase in circuit area of the semiconductor device can be suppressed.

It is a figure which shows an example of the semiconductor device of 1st Embodiment. It is a figure which shows an example of the semiconductor device of 2nd Embodiment. It is a timing chart which shows an example of a time change of various signals and a value in a diagnostic part of a semiconductor device of a 2nd embodiment. It is a flowchart which shows the flow of an example of the control method of a semiconductor device at the time of the diagnosis of a variable frequency oscillation circuit. It is a flowchart which shows the flow of an example of a diagnostic process. It is a figure which shows the example of the ideal characteristic of a variable frequency oscillation circuit. It is a figure which shows the example of the characteristic which has a defective location. It is a figure which shows an example of the characteristic of a variable frequency oscillation circuit. It is a figure which shows an example of the semiconductor device of 3rd Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of the semiconductor device according to the first embodiment.

The semiconductor device 10 includes an oscillating unit 11 and a diagnostic unit 12. The semiconductor device 10 is manufactured on an LSI chip, for example.
For example, as shown in FIG. 1, the oscillating unit 11 is a PLL circuit having a phase comparator 11a, a filter 11b, a variable frequency oscillating circuit 11c, and a frequency divider 11d.

  The phase comparator 11a outputs a signal indicating a phase difference between a reference signal (hereinafter referred to as a reference clock) CKr and a feedback signal output from the frequency divider 11d. The reference clock CKr may be supplied, for example, via an external terminal of the LSI chip, or may be supplied from a clock source provided on the LSI chip. The clock source is, for example, a crystal resonator.

The filter 11b outputs a control signal to be supplied to the variable frequency oscillation circuit 11c based on the signal output from the phase comparator 11a.
The variable frequency oscillation circuit 11c changes the oscillation frequency so as to reduce the phase difference based on the control signal output from the filter 11b. Furthermore, the variable frequency oscillation circuit 11c receives a set value from the diagnosis unit 12 or a control unit (not shown), and outputs an oscillation frequency signal (output signal OUT) based on the set value. For example, the output signal OUT may be supplied to another circuit in the LSI chip, or may be supplied to another circuit connected to the LSI chip via an external terminal of the LSI chip.

  The frequency divider 11d outputs a feedback signal obtained by dividing the output signal OUT of the variable frequency oscillation circuit 11c by a predetermined frequency division ratio. The frequency divider 11d may be a programmable frequency divider that can change the frequency division ratio corresponding to a plurality of frequencies used in the electronic device on which the semiconductor device 10 is mounted, or may have a different frequency division ratio. A plurality of frequency dividers may be provided. In that case, a frequency division ratio (or frequency divider) to be used is determined based on a set value supplied from a control unit (or diagnosis unit 12) (not shown).

  The oscillating unit 11 may be a digital PLL circuit in which at least a part of the circuit is a digital circuit, or an analog PLL circuit in which the entire circuit is an analog circuit. When the oscillation unit 11 is an analog PLL circuit and the set value is a digital signal, a D / A (Digital / Analogue) conversion circuit that converts the set value into an analog signal is used.

  The diagnosis unit 12 supplies a set value to the oscillation unit 11 and detects a change in the oscillation frequency every time the set value is changed (increased or decreased) for each change unit. Then, the diagnosis unit 12 determines whether or not there is a characteristic defect in the variable frequency oscillation circuit 11c based on the comparison result between the expected value of the change in the oscillation frequency held in advance and the detected change.

The diagnosis unit 12 includes a control circuit 12a, a frequency change detection circuit 12b, a holding circuit 12c, and a defect presence / absence determination circuit 12d.
The control circuit 12a operates in accordance with the reference clock CKr, and outputs a control signal for operating the frequency change detection circuit 12b, the holding circuit 12c, and the defect presence / absence determination circuit 12d. The control circuit 12a supplies the set value to the variable frequency oscillation circuit 11c.

  The frequency change detection circuit 12b receives the output signal OUT of the variable frequency oscillation circuit 11c, and detects the change in the oscillation frequency when the set value increases or decreases. An example of the frequency change detection circuit 12b will be described later.

  The holding circuit 12c holds an expected value corresponding to a change in the oscillation frequency. The expected value is represented by an upper limit value for the change in the oscillation frequency and a lower limit value for the change in the oscillation frequency. The smaller the difference between the upper limit value and the lower limit value of the change in the oscillation frequency, the more severe the determination of the presence / absence of defects, and the greater the difference, the weaker the determination of presence / absence of defects. The expected value is determined in advance using circuit simulation or the like based on, for example, required accuracy.

  The holding circuit 12c is, for example, a register using a flip-flop. The holding circuit 12c may be a memory such as a RAM (Random Access Memory) or a ROM (Read Only Memory).

  The defect presence / absence determination circuit 12d is based on the comparison result between the expected value of the change in the oscillation frequency held in the holding circuit 12c in advance and the change detected in the frequency change detection circuit 12b. The presence / absence of characteristic failure is determined, and the determination result ERR is output.

  The defect presence / absence determination circuit 12d outputs a determination result ERR indicating that there is no defect when the detected change is within the expected value range represented by the upper limit value and the lower limit value as described above. The defect presence / absence determination circuit 12d outputs a determination result ERR indicating that there is a defect when the detected change exceeds the upper limit value or falls below the lower limit value (when it is outside the range of the expected value).

  Hereinafter, a control method of the semiconductor device 10 according to the first embodiment at the time of diagnosis of the variable frequency oscillation circuit 11c will be described. At the time of diagnosis, since the operation of the PLL circuit is stopped, the output of the filter 11b becomes invalid under the control of the control circuit 22a, for example.

  When the control circuit 12a supplies the set value of the oscillation frequency to the variable frequency oscillation circuit 11c, the variable frequency oscillation circuit 11c outputs an output signal OUT having an oscillation frequency corresponding to the set value. After a predetermined period, the control circuit 12a changes the set value. As a result, the variable frequency oscillation circuit 11c outputs an output signal OUT having an oscillation frequency corresponding to the changed set value.

The frequency change detection circuit 12b detects and outputs the change in the oscillation frequency from the oscillation frequency before and after the setting value is changed.
Then, the failure presence / absence determination circuit 12d outputs a determination result ERR indicating that there is no failure if the detected change is within the expected value range, and the detected change is outside the expected value range. The determination result ERR indicating that there is a defect is output.

  The above processing is performed on all set values, for example. The defect presence / absence determination circuit 12d may fix the determination result ERR to a value indicating that there is a defect after detecting the defect even once.

  For example, when diagnosis is performed using only a specific set value for obtaining the oscillation frequency that is actually used, it may not be detected even if a characteristic failure occurs in other frequency bands. By making a diagnosis using, it is possible to prevent erroneous detection of characteristic defects. Examples of characteristic defects will be described below.

  FIG. 1 shows an example of a change in the oscillation frequency of the variable frequency oscillation circuit 11c when the set value is increased by 1 (that is, when the change unit is increased by 1). . The horizontal axis represents the set value, and the vertical axis represents the oscillation frequency (unit: GHz).

  It is desirable that the correlation between the oscillation frequency and the set value exhibits linearity in which the oscillation frequency increases in proportion to the increase in the set value. However, in the example of FIG. 1, the linearity is broken when the set value is a certain value. When there is such a defect, there is a possibility that the oscillation frequency may not increase as expected when it is desired to increase the oscillation frequency. In such a case, the followability to the reference clock CKr is deteriorated, so that a phase shift between the feedback signal and the reference clock CKr may occur. The diagnosis unit 12 detects such a defective portion based on the comparison result between the change in the oscillation frequency and the expected value.

  In the example of FIG. 1, the difference between the oscillation frequency fa at a certain set value and the oscillation frequency fb at the next set value is smaller than the difference between the oscillation frequencies at other adjacent set values, and is outside the expected value range. ing. For this reason, the defect presence / absence determination circuit 12d outputs a determination result ERR indicating that there is a characteristic defect of the variable frequency oscillation circuit 11c.

  As described above, in the semiconductor device 10 of the first embodiment, the characteristic failure of the variable frequency oscillation circuit 11c is determined based on the comparison result between the change in the oscillation frequency and the expected value every time the set value is changed. Determine presence or absence.

  When the expected value of the oscillation frequency corresponding to each set value is held, the memory area increases when the set value is large, so that the circuit area increases. However, in the semiconductor device 10 described above, the expected value for the change in the oscillation frequency is set. Since it is held, at least one expected value is held. Even when a variable frequency oscillation circuit having such a characteristic that the relationship between the oscillation frequency and the set value varies depending on the frequency band is used, the expected value to be held is small (see a third embodiment described later). For this reason, the memory area holding the expected value can be small, and the circuit area can be reduced. In addition, this makes it possible to increase the number of semiconductor devices 10 that can be manufactured per wafer (or the number of LSI chips including the semiconductor devices 10), and to suppress an increase in manufacturing cost per semiconductor device 10.

  When diagnosing the variable frequency oscillation circuit 11c by using an external measurement device such as an LSI tester, for example, repeated setting value input processing using a scan-in terminal and output signal acquisition processing from a scan-out terminal. As a result, the diagnosis time becomes longer. In contrast, in the semiconductor device 10, since the diagnosis unit 12 as described above is provided inside the semiconductor device 10, the input process and the acquisition process as described above can be omitted, and the diagnosis time can be prolonged. Can be suppressed. Moreover, since the diagnosis time can be prevented from being prolonged, an increase in test cost can be suppressed.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a semiconductor device according to the second embodiment.
The semiconductor device 20 includes a digital PLL circuit 21 and a diagnostic unit 22.

The digital PLL circuit 21 includes a phase comparator 21a, a filter 21b, a variable frequency oscillation circuit 21c, and a frequency divider 21d.
The phase comparator 21a outputs a digital signal indicating the phase difference between the reference clock CKr and the feedback signal output from the frequency divider 21d.

  The filter 21b is a digital filter, removes high-frequency components contained in the digital signal output from the phase comparator 21a, and provides, for example, a control value indicating that the phase is advanced or delayed to the variable frequency oscillation circuit 21c. Supply.

  The variable frequency oscillation circuit 21c includes a frequency control unit 21c1 and a variable frequency oscillation unit 21c2. The frequency control unit 21c1 changes the oscillation frequency of the output signal OUT output from the variable frequency oscillation unit 21c2 so as to reduce the phase difference based on the control value output from the filter 21b. At the time of diagnosis, for example, the output of the filter 21b becomes invalid under the control of the control circuit 22a. At the time of diagnosis, the frequency control unit 21c1 receives a setting value that is a digital signal from the diagnosis unit 22, and causes the variable frequency oscillation unit 21c2 to output an output signal OUT having an oscillation frequency based on the setting value. Such a variable frequency oscillation circuit 21c is also called a DCO (Digitally Controlled Oscillator).

  The frequency divider 21d outputs a feedback signal obtained by dividing the output signal OUT of the variable frequency oscillation circuit 21c by a predetermined frequency division ratio. The frequency divider 21d may be a programmable frequency divider capable of changing the frequency division ratio corresponding to a plurality of frequencies used in the electronic device on which the semiconductor device 20 is mounted, or may have a different frequency division ratio. A plurality of frequency dividers may be provided. In that case, a frequency division ratio (or frequency divider) to be used is determined based on a set value supplied from a control unit (or diagnosis unit 22) (not shown).

The diagnosis unit 22 includes a control circuit 22a, a counter 22b, a holding circuit 22c, a subtractor 22d, a holding circuit 22e, a comparison circuit unit 22f, and a holding circuit 22g.
The control circuit 22a includes a counter 22a1, a setting change instruction unit 22a2, a setting value generation unit 22a3, a count value determination unit 22a4, and a synchronization latch circuit unit 22a5.

The counter 22a1 counts the number of pulses of the reference clock CKr.
The setting change instruction unit 22a2 outputs a signal chg for instructing change of the set value every time the counter 22a1 counts a predetermined number of pulses.

  When receiving the signal chg instructing to change the set value, the set value generating unit 22a3 increases the set value by 1 and outputs the signal. When the signal chg for instructing the change of the set value is not supplied, the set value generation unit 22a3 continues to output the same set value at a timing synchronized with the reference clock CKr.

The count value determination unit 22a4 receives the count value of the counter 22a1 and outputs four pulse signals having different output timings.
The synchronization latch circuit unit 22a5 outputs the four pulse signals output from the count value determination unit 22a4 at a timing synchronized with the output signal OUT. Hereinafter, the four signals output from the synchronization latch circuit unit 22a5 are referred to as a measurement control signal str / stp, a reset signal rst, a copy control signal cpy, and a result capture control signal jdg.

The measurement control signal str / stp is a signal that instructs the counter 22b during a period for measuring the oscillation frequency of the variable frequency oscillation circuit 21c.
The reset signal rst is used to reset the counter 22b.

  The copy control signal cpy is a signal that instructs the holding circuit 22c when to take in the count value cnt of the counter 22b. The output timing of the copy control signal cpy is adjusted by the count value determination unit 22a4 so that the holding circuit 22c outputs the count value cnt based on the setting value immediately before the setting value output by the control circuit 22a. Yes.

The result capturing control signal jdg is a signal that instructs the holding circuit 22c when to capture the signal output from the comparison circuit unit 22f.
The control circuit 22a may be a processor such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor) having the above functions. In that case, the processor implements the above function by executing a program stored in the memory. However, since the functions as described above can be realized by a relatively simple logic circuit, flip-flop, or the like, the size of the semiconductor device 20 can be reduced by realizing it by hardware instead of software.

The counter 22b, the holding circuit 22c, and the subtractor 22d realize the function of the frequency change detection circuit 12b shown in FIG.
The counter 22b counts the number of oscillations (number of pulses) of the output signal OUT for a period specified by the measurement control signal str / stp, and outputs a count value cnt. The counter 22b sets the count value cnt to 0 when the reset is instructed by the reset signal rst.

The holding circuit 22c takes in and outputs the value reg of the count value cnt at the timing indicated by the copy control signal cpy.
The subtractor 22d outputs a subtraction result between the count value cnt based on the current set value and the value reg that is the count value cnt based on the previous set value output from the holding circuit 22c. This subtraction result corresponds to the change in the oscillation frequency when the previous set value is changed to the current set value.

  The holding circuit 22e holds an expected value corresponding to a change in the oscillation frequency. The expected value is represented by an upper limit value for the change in the oscillation frequency and a lower limit value for the change in the oscillation frequency. The holding circuit 22c is, for example, a register using a flip-flop.

The comparison circuit unit 22f and the holding circuit 22g realize the function of the defect presence / absence determination circuit 12d shown in FIG.
The comparison circuit unit 22f compares the subtraction result output from the subtractor 22d with the lower limit value and the upper limit value. When the subtraction result is smaller than the lower limit value or larger than the upper limit value, the comparison circuit unit 22f outputs a signal indicating that the variable frequency oscillation circuit 21c has a characteristic defect.

  In the following, it is assumed that when the logic level of the signal output from the comparison circuit unit 22f is H (High) level, the variable frequency oscillation circuit 21c has a characteristic defect. When the subtraction result is equal to or greater than the lower limit value and within the upper limit value (that is, within the range of the expected value), the comparison circuit unit 22f outputs a signal having a logic level of L (Low).

  Such a comparison circuit unit 22f can be realized by, for example, two comparison circuits and an OR circuit. One of the two comparison circuits outputs an H level comparison result when the subtraction result is smaller than the lower limit value, and the other outputs an H level comparison result when the subtraction result is larger than the upper limit value. To do. The logical sum circuit outputs a logical sum of the comparison results of the respective comparison circuits.

  The holding circuit 22g captures a signal output from the comparison circuit unit 22f at a timing indicated by the result capture control signal jdg, and outputs the signal as a determination result ERR. However, once the logic level of the determination result ERR becomes H level, the holding circuit 22g continues to output the H level determination result ERR regardless of the logic level of the signal output from the comparison circuit unit 22f.

  Such a holding circuit 22g can be realized by, for example, an OR circuit, a selector, and a flip-flop. The OR circuit outputs a logical sum of the signal output from the comparison circuit unit 22f and the determination result ERR. The selector selects and outputs the logical sum while the acquisition is instructed by the result acquisition control signal jdg, and selects and outputs the determination result ERR when the acquisition is not instructed. The flip-flop fetches and outputs the output of the selector as the determination result ERR at a timing synchronized with the output signal OUT.

  FIG. 3 is a timing chart illustrating an example of temporal changes of various signals and values in the diagnosis unit of the semiconductor device according to the second embodiment. FIG. 3 shows an example of a time change of the reference clock CKr, the output signal OUT, the reset signal rst, the measurement control signal str / stp, the result capture control signal jdg, the copy control signal cpy, the signal chg, the count value cnt, and the value reg. It is shown.

  Prior to timing t1, the reset signal rst is at the H level, and the counter 22b is in a reset state. Therefore, the count value is 0. The value reg is a count value cnt (represented as “n (before)”) based on the previous set value. Further, the measurement control signal str / stp, the result fetch control signal jdg, the copy control signal cpy, and the signal chg are all at the L level.

  When the reset signal rst changes to L level and the measurement control signal str / stp changes to H level (timing t1), the counter 22b starts counting the number of oscillations of the output signal OUT.

  When the measurement control signal str / stp changes from the H level to the L level (timing t2), the counter 22b finishes counting the number of oscillations of the output signal OUT. At timing t2, the result fetch control signal jdg is at the H level. For this reason, when the determination result ERR is at the L level, the signal output from the comparison circuit unit 22f is taken into the holding circuit 22g. The signal output from the comparison circuit unit 22f includes a subtraction result between a count value cnt (denoted as “n”) based on the current set value and a count value cnt based on the previous set value, The value is based on the comparison result between the lower limit value and the upper limit value.

  When the result fetch control signal jdg changes to L level and the copy control signal cpy changes to H level (timing t3), the count value cnt is fetched into the holding circuit 22c, and the value reg becomes “n”.

When the signal chg changes to the H level (timing t4), the set value increases by one.
Thereafter, the reset signal rst again becomes H level (timing t5), and the counter 22b is reset. Further, the copy control signal cpy and the signal chg return to the L level.

Next, a flow of a control method of the semiconductor device 20 at the time of diagnosis of the variable frequency oscillation circuit 21c will be described using a flowchart.
FIG. 4 is a flowchart showing a flow of an example of a control method of the semiconductor device when diagnosing the variable frequency oscillation circuit.

  First, the diagnosis unit 22 obtains an expected value of the frequency difference obtained from adjacent setting values (setting values different by 1 in the above example) from the outside of the semiconductor device 20 (step S1), and stores it in the holding circuit 22e. Set (step S2). The expected value is represented by an upper limit value for the change in the oscillation frequency and a lower limit value for the change in the oscillation frequency. The expected value is determined in advance by a circuit simulation or the like by an external computer or the like based on the required accuracy. The diagnosis unit 22 acquires the determined expected value via an input circuit (not shown). For example, the control circuit 22a sets the acquired expected value in the holding circuit 22e.

Thereafter, the diagnosis unit 22 performs a diagnosis process (step S3).
FIG. 5 is a flowchart showing an exemplary flow of the diagnostic process.
First, the control circuit 22a of the diagnosis unit 22 sets the oscillation frequency to the lowest oscillation frequency of the variable frequency oscillation circuit 21c, for example, by setting the setting value supplied to the variable frequency oscillation circuit 21c to 0 (step S10).

  The control circuit 22a receives the output signal OUT, causes the counter 22b to measure the number of oscillations in a predetermined period (period in which the measurement control signal str / stp shown in FIG. 3 is at the H level), and then holds the holding circuit. 22c (step S11).

Thereafter, the control circuit 22a increments the set value by 1 (step S12), and again causes the counter 22b to measure the number of oscillations for a predetermined period (step S13).
Then, the subtractor 22d calculates a difference between the number of oscillations measured last time (the number of oscillations held in the holding circuit 22c) and the number of oscillations measured this time (step S14).

  Further, the comparison circuit unit 22f determines whether or not the difference (subtraction result) calculated by the subtractor 22d is within the range of the expected value (step S15). When the difference is within the expected value range, if the characteristic failure has not already been detected (step S16: NO), the holding circuit 22g holds the determination result ERR that there is no characteristic failure (step S17). Thereafter, the process of step S19 is performed. When the difference is within the expected value range, if a characteristic defect has already been detected (step S16: YES), the process of step S19 is performed.

If the difference is outside the expected value range, the holding circuit 22g holds the determination result ERR that there is a characteristic defect (step S18). Thereafter, the process of step S19 is performed.
In the process of step S19, the control circuit 22a causes the holding circuit 22c to hold the oscillation number measured by the counter 22b.

  Thereafter, the control circuit 22a determines whether or not the set value is the upper limit (whether or not the oscillation frequency is the maximum oscillation frequency of the variable frequency oscillation circuit 21c) (step S20). When the set value is the upper limit, the control circuit 22a ends the diagnosis process, and when the set value has not reached the upper limit, the control circuit 22a repeats the process from step S12.

  The above processing is an example. For example, the control circuit 22a may set the oscillation frequency to the maximum oscillation frequency with the set value supplied to the variable frequency oscillation circuit 21c as the upper limit in the processing of step S10. . In this case, the control circuit 22a decreases the set value by 1 instead of the process of step S12. Further, the control circuit 22a determines whether or not the set value is the lower limit (the oscillation frequency is the lowest oscillation frequency) instead of the process of step S20.

FIG. 6 is a diagram illustrating an example of ideal characteristics of the variable frequency oscillation circuit. The horizontal axis represents the set value, and the vertical axis represents the oscillation frequency (unit: GHz).
The oscillation frequency increases with a constant slope every time the set value, which is a digital value, increases by one. The diagnosing unit 22 holds the oscillation frequency value corresponding to each set value as shown in FIG. 6 as an expected value, and can also determine the presence or absence of a characteristic defect by comparison with the measured oscillation frequency. However, in that case, the area of the holding circuit for holding the oscillation frequency values corresponding to many setting values as shown in FIG. 6 as expected values increases.

  In the semiconductor device 20 according to the second embodiment, the diagnosis unit 22 compares the difference between the oscillation frequencies when adjacent setting values (setting values different by 1 in the above example) are used and their expected values. Based on the result, the presence / absence of a characteristic defect of the variable frequency oscillation circuit 11c is determined. Therefore, as shown in FIG. 2, an expected value that can be expressed by two values of a lower limit value and an upper limit value may be held, and the circuit area can be reduced.

FIG. 7 is a diagram illustrating an example of a characteristic having a defective portion. The horizontal axis represents the set value, and the vertical axis represents the oscillation frequency (unit: GHz).
In the example of FIG. 7, in the region 25, even if the set value is increased from 211 to 212, the oscillation frequency is hardly changed, and the linearity of the oscillation frequency is broken. When such characteristic failure occurs, the output (subtraction result) of the subtractor 22d indicating the difference between the oscillation frequency when the set value is 211 and the oscillation frequency when the set value is 212 is the lower limit of the expected value. Smaller than the value. That is, the difference is out of the expected value range, and a characteristic defect can be detected.

As described above, according to the semiconductor device 20 of the second embodiment, the same effect as that of the semiconductor device 10 of the first embodiment can be obtained.
(Third embodiment)
In the above description, the set value and the oscillation frequency are in a proportional relationship. However, the characteristics of the variable frequency oscillation circuit 21c may vary depending on the frequency band of the oscillation frequency. In that case, the oscillation frequency has a plurality of frequency bands having different degrees of change of the oscillation frequency with respect to the change of the set value.

FIG. 8 is a diagram illustrating an example of characteristics of the variable frequency oscillation circuit. The horizontal axis represents the set value, and the vertical axis represents the oscillation frequency (unit: GHz).
In the example of the characteristic of the variable frequency oscillation circuit 21c as shown in FIG. 8, when the set value is 100 or more, the oscillation frequency and the set value are in a substantially proportional relationship. However, when the set value is less than 100, the smaller the set value, the greater the change in the oscillation frequency.

  In the case of such characteristics, when the expected value is determined based only on the change in the oscillation frequency when the set value is 100 or more, when the set value is smaller than 100, the characteristic is not defective. The possibility of being detected as a characteristic defect is increased. Therefore, the semiconductor device of the third embodiment shown below suppresses the occurrence of misdiagnosis using a plurality of expected values.

  FIG. 9 is a diagram illustrating an example of a semiconductor device according to the third embodiment. 9, the same elements as those of the semiconductor device 20 according to the second embodiment shown in FIG.

  In the semiconductor device 30 according to the third embodiment, the diagnosis unit 31 includes a holding circuit 31a that holds a boundary setting value, a comparison circuit 31b, a holding circuit 31c that holds a plurality of expected values, and a selection circuit 31d.

  The boundary setting value is a setting value serving as a boundary for switching the expected value to be used. When the variable frequency oscillation circuit 21c has characteristics as shown in FIG. 8, the boundary setting value is set to 100, for example.

  The comparison circuit 31b compares the set value output from the set value generation unit 22a3 with the boundary set value and outputs the comparison result. In the following description, it is assumed that the comparison circuit 31b outputs an L level comparison result when the set value is smaller than the boundary set value, and outputs an H level comparison result when the set value is greater than or equal to the boundary set value.

  The holding circuit 31c holds, for example, an expected value for low frequency and an expected value for high frequency. When the variable frequency oscillation circuit 21c has the characteristics as shown in FIG. 8, the expected value for low frequency is, for example, the expected value used when the set value is smaller than 100, and the expected value for high frequency. Is an expected value used when the set value is 100 or more, for example.

  The expected value for low frequency and the expected value for high frequency are represented by an upper limit value and a lower limit value, respectively. When the variable frequency oscillation circuit 21c has the characteristics as shown in FIG. 8, the difference between the upper limit value and the lower limit value in the expected value for low frequency is the difference between the upper limit value and the lower limit value in the expected value for high frequency. Is set larger than.

  When the comparison result output from the comparison circuit 31b is L level, the selection circuit 31d selects and outputs the upper limit value and the lower limit value of the low-frequency expected value. When the comparison result output from the comparison circuit 31b is H level, the selection circuit 31d selects and outputs the upper limit value and the lower limit value of the high-frequency expected value.

Other elements of the diagnosis unit 31 are the same as those of the diagnosis unit 22 shown in FIG.
According to the semiconductor device 30 as described above, even when the characteristics of the variable frequency oscillation circuit 21c are different depending on the frequency band, it is possible to appropriately diagnose and suppress the occurrence of misdiagnosis. Further, the expected value to be held is larger than that of the semiconductor device 20 of the second embodiment, but can be reduced as compared with the case where the expected value of the oscillation frequency is held for each set value, and an increase in circuit area can be suppressed.

That is, also in the semiconductor device 30 of the third embodiment, the same effect as that of the semiconductor device 10 of the first embodiment can be obtained.
In the above example, the expected values to be held are two types for low frequency and high frequency, but may be three or more types according to the characteristics of the variable frequency oscillation circuit 21c.

  As described above, one aspect of the semiconductor device and the control method thereof according to the present invention has been described based on the embodiments, but these are only examples and are not limited to the above description.

10 Semiconductor device 11 Oscillator (PLL circuit)
11a phase comparator 11b filter 11c variable frequency oscillation circuit 12 diagnostic unit 12a control circuit 12b frequency change detection circuit 12c holding circuit 12d defect presence / absence determination circuit CKr reference clock ERR determination result fa, fb oscillation frequency OUT output signal

Claims (6)

An oscillation unit including a variable frequency oscillation circuit that receives a set value and outputs a signal having an oscillation frequency based on the set value;
The set value is supplied to the oscillating unit, and the change of the oscillation frequency is detected every time the set value is changed for each change unit, and the expected value of the change held in the holding circuit in advance is detected. A diagnostic unit for determining the presence or absence of a characteristic defect of the variable frequency oscillation circuit based on a comparison result with the changed amount;
A semiconductor device. The expected value has an upper limit value and a lower limit value,
The diagnostic unit outputs a determination result indicating that the characteristic defect is present when the change in the oscillation frequency exceeds the upper limit value or is lower than the lower limit value.
The semiconductor device according to claim 1. The diagnostic unit increases or decreases the set value for each change unit, so that the oscillation frequency is changed from the lowest oscillation frequency to the highest oscillation frequency of the variable frequency oscillation circuit, or from the highest oscillation frequency. Change to the lowest oscillation frequency,
The semiconductor device according to claim 1. When the diagnostic unit changes the set value from the first set value to the second set value,
Counting the first oscillation number in the first period of the first output signal of the oscillating unit obtained based on the first set value, and holding the counting result;
Counting the second number of oscillations in the first period of the second output signal of the oscillating unit obtained based on the second set value;
By detecting a difference between the held first oscillation number and the second oscillation number, the change in the oscillation frequency is detected.
The semiconductor device according to claim 1. The oscillation frequency has a first frequency band and a second frequency band having different degrees of change with respect to a change in the set value,
The holding circuit holds a first expected value and a second expected value for the change in the oscillation frequency,
The diagnostic unit determines the presence or absence of the characteristic defect using the first expected value when a third set value for setting the oscillation frequency in the first frequency band is supplied to the oscillation unit. When the fourth setting value for setting the oscillation frequency in the second frequency band is supplied to the oscillation unit, the presence or absence of the characteristic defect is determined using the second expected value.
The semiconductor device according to claim 1. The variable frequency oscillation circuit included in the oscillation unit included in the semiconductor device receives a set value and outputs a signal having an oscillation frequency based on the set value.
The diagnosis unit included in the semiconductor device supplies the set value to the oscillation unit, detects the change in the oscillation frequency each time the set value is changed for each change unit, and is held in a holding circuit in advance. Based on a comparison result between the expected value of the change and the detected change, the presence or absence of a characteristic defect of the variable frequency oscillation circuit is determined.
A method for controlling a semiconductor device.

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