JP2019050434A - Semiconductor device - Google Patents

Abstract

To reduce on-resistance.SOLUTION: A semiconductor device comprises a first electrode, a second electrode, a first semiconductor region, a first connection region, a second connection region, a third electrode, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a fifth semiconductor region. The second connection region is arranged side by side with the first connection region, and electrically connected with the second electrode. The third electrode is located between the first connection region and the second connection region. A length in a first direction of the third electrode is shorter than a length in the first direction of the first connection region and a length in the first direction of the second connection region. In the second semiconductor region, a lower end along a first insulating film in the first direction is located at the first electrode side from a lower end along a third insulating film in the first direction. In the third semiconductor region, a lower end along a second insulating film in the first direction is located at the first electrode side from the lower end along the third insulating film in the first direction.SELECTED DRAWING: Figure 1

Description

  Embodiments of the present invention relate to a semiconductor device.

  There is an IGBT (Insulated Gate Bipolar Transistor) as a semiconductor device for power. When the IGBT is used for applications such as switching, it is desirable that the on-resistance be low and the switching speed be high.

  When the distance between the trench gates of the IGBTs becomes narrow, the resistance component of the n-type base region provided between the trench gates becomes large. As a result, an IE (Injection Enhanced) effect is generated, and the on-resistance of the IGBT is reduced.

  However, the smaller the trench gate spacing, the higher the aspect ratio of the trench gate and the more difficult it is to manufacture. On the other hand, when the trench gate is formed shallow, the IE effect is reduced and the on-resistance is increased.

JP, 2008-021918, A

  The problem to be solved by the present invention is to provide a semiconductor device capable of reducing on-resistance.

  A semiconductor device according to an embodiment includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a first connection region, a second connection region, a third electrode, and a second conductivity type. A second semiconductor region, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type, a first insulating film, and a second insulating film , And a third insulating film. The first semiconductor region is provided between the first electrode and the second electrode. The first connection region is provided between the first semiconductor region and the second electrode, and is electrically connected to the second electrode. The second connection region is provided between the first semiconductor region and the second electrode, and the first connection region intersects a first direction from the first electrode to the second electrode. It is aligned with the connection region and electrically connected to the second electrode. The third electrode is provided between the first connection region and the second connection region, and a length in the first direction corresponds to a length of the first connection region in the first direction and the first direction. Shorter than the length of the second connection area in The second semiconductor region is provided between the first connection region and the third electrode. The third semiconductor region is provided between the second connection region and the third electrode. The fourth semiconductor region is provided between the second semiconductor region and the second electrode. The fifth semiconductor region is provided between the third semiconductor region and the second electrode. The first insulating film is provided between the first connection region and the second semiconductor region. The second insulating film is provided between the second connection region and the third semiconductor region. The third insulating film is provided between the third electrode and the second semiconductor region and between the third electrode and the third semiconductor region. The lower end of the second semiconductor region along the first insulating film in the first direction is closer to the first electrode than the lower end of the second semiconductor region along the third insulating film in the first direction. Located in The lower end of the third semiconductor region along the second insulating film in the first direction is closer to the first electrode than the lower end of the third semiconductor region along the third insulating film in the first direction. Located in

FIG. 1A and FIG. 1B are schematic views showing the semiconductor device according to the first embodiment. FIG. 2A to FIG. 2C are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. 3 (a) to 3 (c) are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing the operation of the semiconductor device according to the first embodiment. FIG. 5A and FIG. 5B are schematic cross-sectional views showing the operation of the semiconductor device according to the first embodiment. 6A to 6C are schematic views showing a semiconductor device according to the second embodiment. FIGS. 7A and 7B are schematic views showing a semiconductor device according to the third embodiment. FIG. 8A and FIG. 8B are schematic views showing a semiconductor device according to the fourth embodiment. FIG. 9A and FIG. 9B are schematic views showing a semiconductor device according to the fifth embodiment. FIGS. 10A and 10B are schematic views showing a semiconductor device according to the sixth embodiment. 11 (a) and 11 (b) are schematic cross-sectional views showing the operation of the semiconductor device according to the sixth embodiment. 12A to 12C are schematic views showing a semiconductor device according to the seventh embodiment. FIG. 13A and FIG. 13B are schematic views showing the semiconductor device according to the eighth embodiment. FIG. 14A and FIG. 14B are schematic views showing the semiconductor device according to the ninth embodiment. FIG. 15A and FIG. 15B are schematic views showing a semiconductor device according to the tenth embodiment. FIG. 16A and FIG. 16B are schematic views showing the semiconductor device according to the eleventh embodiment. 17A and 17B are schematic plan views showing a semiconductor device according to a twelfth embodiment. FIG. 18A and FIG. 18B are schematic plan views showing a semiconductor device according to a thirteenth embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals are given to the same members, and the description of the members once described will be omitted as appropriate. The drawings are drawn schematically or conceptually, and the dimensions of each part are not necessarily the same as the actual ones. Even in the case of representing the same part, the dimensions and proportions may differ from one another depending on the drawings.

In the embodiment, the n ^{+ -type} and the n-type indicate that the n-type (first conductivity type) impurity concentration is relatively low. The p ^{+ -type} and p-type indicate that the p-type (second conductivity type) impurity concentration is relatively low. Also, three-dimensional coordinates (X axis, Y axis, Z axis) may be introduced in the figure. Here, the X axis intersects the Y axis and the Z axis, and the Y axis intersects the Z axis. The first direction is the Z-axis direction, the second direction is the Y-axis direction, and the third direction is the X-axis direction.

First Embodiment
FIG. 1A and FIG. 1B are schematic views showing the semiconductor device according to the first embodiment. FIG. 1A shows a cross-sectional view taken along line B1-B1 ′ of FIG. 1B. FIG. 1 (b) shows a cross-sectional view along line A1-A1 'of FIG. 1 (a).

The semiconductor device 101 according to the first embodiment includes a first electrode (collector electrode 11), a second electrode (emitter electrode 12), a first semiconductor region of a first conductivity type (n-type base region 10), and First connection region 51, second connection region 52, third electrode (gate electrode 13), second semiconductor region of second conductivity type (p-type base region 20), third semiconductor region of second conductivity type (P-type base region 30), fourth semiconductor region of first conductivity type (n ⁺ -type emitter region 40), fifth semiconductor region of first conductivity type (n ⁺ -type emitter region 50), second conductivity A sixth semiconductor region (p ^{+ -type} collector region 60), a first insulating film (insulating film 61), a second insulating film (insulating film 62), and a third insulating film (gate insulating film 63); Equipped with The semiconductor device 101 is, for example, an IGBT.

  The Z-axis direction corresponds to the direction from the first electrode 11 to the second electrode 12. The Y-axis direction corresponds to the direction from the first connection area 51 to the second connection area 52.

The n-type base region 10 is provided between the first electrode 11 and the second electrode 12 in the Z-axis direction. The n-type base region 10 extends in the X-axis direction. The p ^{+ -type} collector region 60 is provided between the first electrode 11 and the n-type base region 10 in the Z-axis direction. The p ^{+ -type} collector region 60 is electrically connected to the first electrode 11. The p ^{+ -type} collector region 60 extends in the X-axis direction. The p ^{+ -type} collector region 60 is in contact with the n-type base region 10 and the first electrode 11.

  The first connection region 51 is provided between the n-type base region 10 and the second electrode 12 in the Z-axis direction. The first connection region 51 is electrically connected to the second electrode 12. The first connection region 51 is in contact with the second electrode 12. The first connection region 51 has a predetermined length in the Z-axis direction. The first connection region 51 extends in the X-axis direction. The length of the first connection region 51 in the Z-axis direction is, for example, 4 μm to 10 μm.

  The second connection region 52 is provided between the n-type base region 10 and the second electrode 12 in the Z-axis direction. The second connection area 52 is aligned with the first connection area 51 in the Y-axis direction. The second connection region 52 is electrically connected to the second electrode 12. The second connection region 52 is in contact with the second electrode 12. The second connection region 52 has a predetermined length in the Z-axis direction. The second connection region 52 extends in the X-axis direction. The length of the second connection region 52 in the Z-axis direction is, for example, 4 μm to 10 μm. The distance between the center of the first connection region 51 and the center of the second connection region 52 in the Y-axis direction is, for example, 2 μm to 12 μm.

  The gate electrode 13 is located between the first connection region 51 and the second connection region 52 in the Y-axis direction. The gate electrode 13 is provided between the n-type base region 10 and the second electrode 12 in the Z-axis direction. The length of the gate electrode 13 in the Z-axis direction is shorter than the length of the first connection region 51 in the Z-axis direction and the length of the second connection region 52 in the Z-axis direction. The gate electrode 13 has a predetermined length in the Z-axis direction. The gate electrode 13 extends in the X-axis direction. The length of the gate electrode 13 in the Z-axis direction is, for example, 1 μm to 4 μm. The distance between the center of the gate electrode 13 and the center of the first connection region 51 in the Y-axis direction is, for example, 1 μm to 6 μm. The distance between the center of the gate electrode 13 and the center of the second connection region 52 in the Y-axis direction is, for example, 1 μm to 6 μm.

  The p-type base region 20 is provided between the n-type base region 10 and the second electrode 12 in the Z-axis direction. The p-type base region 20 is provided between the first connection region 51 and the gate electrode 13 in the Y-axis direction. The p-type base region 20 is electrically connected to the second electrode 12. The p-type base region 20 is electrically connected to the n-type base region 10. The p-type base region 20 is in contact with the n-type base region 10 and the second electrode 12.

  The p-type base region 20 has a predetermined length in the Z-axis direction. The p-type base region 20 extends in the X-axis direction. The p-type base region 20 includes a region 20a and a region 20b. In the region 20 a, the length in the Z-axis direction decreases from the first connection region 51 toward the gate electrode 13. In the semiconductor device 101, a pn junction at which the p-type base region 20 and the n-type base region 10 are in contact is referred to as a junction pn1. In the region 20b, the distance between the junction pn1 in the Z-axis direction and the second electrode 12 is longer than the length of the gate electrode 13 in the Z-axis direction. The length of the region 20b in the Z-axis direction is thicker than the length of the region 20a in the Z-axis direction.

  The p-type base region 30 is provided between the n-type base region 10 and the second electrode 12 in the Z-axis direction. The p-type base region 30 is provided between the second connection region 52 and the gate electrode 13 in the Y-axis direction. The p-type base region 30 is electrically connected to the second electrode 12. The p-type base region 30 is electrically connected to the n-type base region 10. The p-type base region 30 is in contact with the second electrode 12 and the n-type base region 10.

  The p-type base region 30 has a predetermined length in the Z-axis direction. The p-type base region 30 extends in the X-axis direction. The p-type base region 30 includes a region 30a and a region 30b. In the region 30 a, the length in the Z-axis direction decreases from the second connection region 52 toward the gate electrode 13. In the semiconductor device 101, a pn junction at which the p-type base region 30 and the n-type base region 10 are in contact is referred to as a junction pn2. In the region 30 b, the distance between the junction pn2 in the Z-axis direction and the second electrode 12 is longer than the length of the gate electrode 13 in the Z-axis direction. The length of the region 30b in the Z-axis direction is thicker than the length of the region 30a in the Z-axis direction.

The n ⁺ -type emitter region 40 is provided between the p-type base region 20 and the second electrode 12 in the Z-axis direction. The n ⁺ -type emitter region 40 is electrically connected to the second electrode 12 and the p-type base region 20. The n ⁺ -type emitter region 40 is in contact with the second electrode 12 and the p-type base region 20. The n ⁺ -type emitter region 40 has a predetermined length in the Z-axis direction. The n ⁺ -type emitter region 40 extends in the X-axis direction.

The n ⁺ -type emitter region 50 is provided between the p-type base region 30 and the second electrode 12 in the Z-axis direction. The n ⁺ -type emitter region 50 is electrically connected to the second electrode 12 and the p-type base region 30. The n ⁺ -type emitter region 50 is in contact with the second electrode 12 and the p-type base region 30. The n ⁺ -type emitter region 50 has a predetermined length in the Z-axis direction. The n ⁺ -type emitter region 50 extends in the X-axis direction.

  The insulating film 61 is provided between the first connection region 51 and the n-type base region 10. The insulating film 61 is provided between the first connection region 51 and the p-type base region 20. The insulating film 61 is in contact with the first connection region 51, the n-type base region 10 and the p-type base region 20. The insulating film 61 extends in the X-axis direction. The thickness of the insulating film 61 is, for example, 50 to 200 nm.

  The insulating film 62 is provided between the second connection region 52 and the n-type base region 10. The insulating film 62 is provided between the second connection region 52 and the p-type base region 30. The insulating film 62 is in contact with the second connection region 52, the n-type base region 10 and the insulating film 62. The insulating film 62 extends in the X-axis direction. The thickness of the insulating film 62 is, for example, 50 to 200 nm.

The gate insulating film 63 is provided between the gate electrode 13 and the n-type base region 10. The gate insulating film 63 is provided between the gate electrode 13 and the p-type base region 20. The gate insulating film 63 is provided between the gate electrode 13 and the p-type base region 30. Gate insulating film 63 is provided between gate electrode 13 and n ⁺ -type emitter region 40. Gate insulating film 63 is provided between gate electrode 13 and n ⁺ -type emitter region 50.

The gate insulating film 63 is in contact with the gate electrode 13, the n-type base region 10, the p-type base region 20, the p-type base region 30, the n ⁺ -type emitter region 40 and the n ⁺ -type emitter region 50. The gate insulating film 63 extends in the X-axis direction. The thickness of the gate insulating film 63 is, for example, 50 to 200 nm.

The first length L 1 is the sum of the length of the n ⁺ -type emitter region 40 along the gate insulating film 63 and the length of the p-type base region 20 in the Z-axis direction. The second length L2 is the length of the p-type base region 20 along the insulating film 61 in the Z-axis direction. That is, the first length L1 is the length of the region 20a in the Z-axis direction. The second length L2 is the length of the region 20b in the Z-axis direction. The first length L1 is shorter than the second length L2.

The third length L 3 is the sum of the length of the n ⁺ -type emitter region 50 along the gate insulating film 63 and the length of the p-type base region 30 in the Z-axis direction. The fourth length L4 is the length of the p-type base region 30 along the insulating film 62 in the Z-axis direction. That is, the third length L3 is the length of the region 30a in the Z-axis direction. The fourth length L4 is the length of the region 30b in the Z-axis direction. The third length L3 is shorter than the fourth length L4.

  2A to 3C are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment.

  As shown in FIG. 2A, a mask 90 is formed on the n-type base region 10. A p-type impurity is deeply implanted into the n-type base region 10 exposed from the mask 90. Thereby, the p-type semiconductor region 20Ly and the p-type semiconductor region 30Ly are selectively formed on the surface of the n-type base region 10.

  As shown in FIG. 2B, a first connection region 51 and an insulating film 61 penetrating the p-type semiconductor region 20Ly from the surface of the n-type base region 10 are formed. A second connection region 52 and an insulating film 62 penetrating the p-type semiconductor region 30Ly from the surface of the n-type base region 10 are formed. In the steps of forming the first connection region 51, the insulating film 61, the second connection region 52, and the insulating film 62, photolithography, dry etching, sputtering, CVD, and the like are used.

  As shown in FIG. 2C, a mask 91 is formed on the first connection region 51, the insulating film 61, and the p-type semiconductor region 20Ly. A mask 91 is formed on the second connection region 52, the insulating film 62, and the p-type semiconductor region 30Ly.

  A p-type impurity is shallowly implanted into the n-type base region 10 exposed from the mask 91. Thereby, the p-type semiconductor region 25Ly is formed on the surface of the n-type base region 10. Instead of using the mask 91, the p-type impurity may be shallowly implanted overlapping the p-type semiconductor region 20Ly and the p-type semiconductor region 30Ly.

  As shown in FIG. 3A, the p-type semiconductor region 20Ly, the p-type semiconductor region 30Ly, and the p-type semiconductor region 25Ly are heated. Thereby, a p-type semiconductor region 25 in which the p-type semiconductor region 20Ly, the p-type semiconductor region 30Ly and the p-type semiconductor region 25Ly are integrated is formed between the first connection region 51 and the second connection region 52. . In the p-type semiconductor region 25, the length in the Z-axis direction of the central portion is selectively thinned.

  As shown in FIG. 3B, the gate insulating film 63 and the gate electrode 13 which pass through the p-type semiconductor region 25 and reach the n-type base region 10 are formed. The p-type semiconductor region 25 is divided by the gate insulating film 63 and the gate electrode 13. Thus, the p-type base region 20 is formed between the first connection region 51 and the gate electrode 13, and the p-type base region 30 is formed between the second connection region 52 and the gate electrode 13.

  As shown in FIG. 3C, a mask 92 is formed on the first connection region 51, the insulating film 61, and the p-type semiconductor region 20Ly. A mask 92 is formed on the second connection region 52, the insulating film 62, and the p-type semiconductor region 30Ly. The mask 92 is formed such that a portion of the p-type base region 20 and a portion of the p-type base region 30 are exposed.

An n-type impurity is implanted into the p-type base region 20 exposed from the mask 92. Thereby, n ⁺ -type emitter region 40 is formed on the surface of p-type base region 20, and n ⁺ -type emitter region 50 is formed on the surface of p-type base region 30. Thereafter, as shown in FIG. 1A, a p-type impurity is implanted on the collector side to form ap ⁺ collector region 60.

The operation of the semiconductor device 101 will be described.
FIG. 4, FIG. 5 (a) and FIG. 5 (b) are typical sectional drawings which show operation | movement of the semiconductor device concerning 1st Embodiment.

  FIG. 4 shows the state after the semiconductor device 101 is turned on. In the present embodiment, the state “after turn-on” may be referred to as the on state.

  In the ON state, a potential higher than that of the second electrode 12 is applied to the first electrode 11. A potential equal to or higher than the threshold potential (Vth) is applied to the gate electrode 13. Thus, a channel region is formed in the p-type base regions 20 and 30 along the gate insulating film 63.

The electron current e1 flows from the n ⁺ -type emitter region 40 to the n-type base region 10 via the channel. The electron current e2 flows from the n ⁺ -type emitter region 50 to the n-type base region 10 via the channel.

n ⁺ -type emitter region electron current injected from the 40 e1 reaches the ^{n +} -type emitter region below 40 ^{p +} form collector region 60. n ⁺ was injected from -type emitter region 50 the electron current e2 reaches the ^{n +} -type emitter region 50 under the ^{p +} -type collector region 60.

On the other hand, holes are injected from the p ^{+ -type} collector region 60. In FIG. 4, hole injection is represented as hole currents h1 and h2.

  The hole current h 1 flows to the second electrode 12 via the n-type base region 10 and the p-type base region 20. The hole current h 2 flows to the second electrode 12 via the n-type base region 10 and the p-type base region 30.

  In the semiconductor device 101, the length L 1 of the p-type base region 20 is shorter than the length L 2 of the p-type base region 20. Further, the length L 3 of the p-type base region 30 is shorter than the length L 4 of the p-type base region 20. That is, in the semiconductor device 101, the length of the channel region in the Z-axis direction is short.

This shortening of the channel promotes electron injection from the n ⁺ -type emitter regions 40, 50. Thus, in the semiconductor device 101, the on resistance is reduced.

  In addition, parasitic capacitance Cge between the gate electrode 13 and the second electrode 12 and parasitic capacitance Cgc between the gate electrode 13 and the first electrode 11 are reduced in the on state by the shortening of the channel. Thereby, the switching operation of the semiconductor device 101 becomes fast.

Further, in the semiconductor device 101, the distance between the first connection region 51 and the second connection region 52 in the Y-axis direction can be changed. When the distance between the first connection region 51 and the second connection region 52 is narrowed, holes are easily accumulated in the n-type base region 10 between the first connection region 51 and the second connection region 52 (IE effect) ). Thereby, in the semiconductor device 101, the on resistance is reduced.
For example, even if the distance between the first connection region 51 and the second connection region 52 is shortened and the miniaturization of the IGBT progresses and the number of gate electrodes 13 per unit area increases, in the semiconductor device 101, From the beginning, the parasitic capacitance Cge and the parasitic capacitance Cgc of the gate electrode 13 are low. As a result, in the semiconductor device 101, the switching speed does not easily decrease even if the miniaturization progresses.

  On the other hand, FIG. 5A shows a state after the semiconductor device 101 is turned off. In the present embodiment, the state “after turn-off” may be referred to as the off state. FIG. 5B schematically shows the depletion layer 10 dp in the n-type base region 10 after the turn-off.

For example, even if a potential higher than that of the second electrode 12 is applied to the first electrode 11, when a potential smaller than the threshold potential (Vth) is applied to the gate electrode 13, the channel region disappears and the n ^{+ type} Electron injection from the emitter regions 40, 50 is cut off. On the other hand, holes remaining in the n-type base region 10 are discharged to the second electrode 12 via the p-type base regions 30 and 40.

  In semiconductor device 101, a depletion layer extends from junction pn1 to p-type base region 20 and n-type base region 10 after turn-off. After turn-off, the depletion layer extends from the junction pn 2 to the p-type base region 30 and the n-type base region 10. The depletion layer is also an n-type base from the interface between insulating film 61 and n-type base region 10, the interface between insulating film 62 and n-type base region 10, and the interface between gate insulating film 63 and n-type base region 10. It extends to the area 10. These depletion layers are connected in the n-type base region 10. The connected depletion layer 10 dp extends below the insulating film 61, the insulating film 62 and the gate insulating film 63. Thereby, the blocking voltage (that is, the withstand voltage) is increased.

  Further, in the semiconductor device 101, the electric field is more easily concentrated at the lower end 62 d of the insulating film 62 or the lower end 61 d of the insulating film 61 than the lower end 63 d of the gate insulating film 63. As a result, avalanche tends to occur near the lower end 62 d of the insulating film 62 or near the lower end 61 d of the insulating film 61.

  Here, the p-type base region 20 includes a region 20 b. The region 20 b is in contact with the insulating film 61 and is closest to the first electrode 11 in the p-type base region 20. The region 20 b is a p-type region, which is a region having low resistance to holes. Thereby, the avalanche current (for example, the hole current h3) generated in the vicinity of the lower end 61d of the insulating film 61 is efficiently discharged to the second electrode 12 via the region 20b.

  On the other hand, p-type base region 30 includes a region 30 b. The region 30 b is in contact with the insulating film 62 and is closest to the first electrode 11 in the p-type base region 30. The region 30 b is a p-type region, which is a region having low resistance to holes. Thereby, the avalanche current (for example, the hole current h4) generated near the lower end 62d of the insulating film 62 is efficiently discharged to the second electrode 12 via the region 30b. Thus, in the semiconductor device 101, not only a sufficient blocking voltage can be realized in the off state, but also the breakdown tolerance in the switching process of the turn-off can be improved.

The regions 20 b and 30 b are separated from the n ⁺ -type emitter region 40 in the Y-axis direction.

As a result, the hole current h 3 flowing into the regions 20 b and 30 b is easily discharged to the second electrode 12 before reaching the n ⁺ -type emitter region 40.

If the hole current h3 reaches the n ⁺ -type emitter regions 40 and 50, a parasitic npn transistor may operate as an element. The parasitic npn transistor is, for example, n ^{+ -type} region 40 / p-type region 20 / n-type region 10 or n ^{+ -type} region 50 / p-type region 30 / n-type region 10. When the parasitic npn transistor operates, so-called latch-up occurs. When latch-up occurs, the gate can not be driven and the IGBT may be broken.

In the semiconductor device 101, the region 20b and the region 30b are separated from the n ⁺ -type emitter region 40 in the Y-axis direction. As a result, the hole current that has reached the regions 20 b and 30 b does not easily reach the n ⁺ -type emitter regions 40 and 50, and latch-up is less likely to occur.

In addition, when the length of the channel region is shortened, the resistance of the p-type base region in the vicinity of the channel region may be increased, and holes may be easily accumulated in the p-type base region in the vicinity of the channel region. In this case, the energy barrier between the n ⁺ -type emitter region and the p-type base region is lowered, and a parasitic npn transistor may operate.

  On the other hand, in the semiconductor device 101, the hole currents h3 and h4 are efficiently discharged to the second electrode 12 through the regions 20b and 30b even if the length of the channel region is shortened. As a result, holes do not easily accumulate in the p-type base regions 20 and 30 near the channel region, and the parasitic npn transistor does not easily operate. This makes it difficult for latch-up to occur.

The lower end 61 d of the insulating film 61 and the lower end 62 d of the insulating film 62 are positioned closer to the first electrode 11 than the lower end 63 d of the gate insulating film 63. As a result, avalanche is more likely to occur in the n-type base region 10 below the p-type base regions 20, 30 and the n ⁺ -type emitter regions 40, 50.

As a result, the temperature rise due to avalanche is likely to occur in the regions 20b and 30b and the n-type base region 10, and the temperature rise of the p-type base regions 20a and 30a and the n ⁺ -type emitter regions 40 and 50 is suppressed. As a result, latch up is less likely to occur.

  In semiconductor device 101, after turn-off, it extends from junction pn1 to p-type base region 20 and n-type base region 10. Also, after turn-off, the depletion layer extends from junction pn 2 to p-type base region 30 and n-type base region 10. The depletion layer is also an n-type base region from the interface between insulating film 61 and n-type base region 10, the interface between insulating film 62 and n-type base region 10, and the interface between gate insulating film 63 and n-type base region 10. Extends to ten.

  These depletion layers are connected in the n-type base region 10. The connected depletion layer 10 dp extends below the insulating film 61, the insulating film 62 and the gate insulating film 63.

  Assuming that depletion layer 10 dp is regarded as an insulating layer, the length of the insulating layer located between gate electrode 13 and n-type base region 10 corresponds to the length of gate insulating film 63 in the Z-axis direction, the depletion in the Z-axis direction. It becomes the length which added the length of layer 10dp.

  Thus, the length of the insulating layer between the gate electrode 13 and the n-type base region 10 is increased, and the parasitic capacitance Cgc between the gate electrode 13 and the first electrode 11 is reduced. Thereby, in the semiconductor device 101, the switching operation becomes faster.

  On the other hand, after turn-off, n-type base region 10 between first connection region 51 and second connection region 52 is shielded by depletion layer 10 dp. Thereby, the leak current between the first electrode 11 and the second electrode 12 after the turn-off can be reliably suppressed.

Second Embodiment
6A to 6C are schematic views showing a semiconductor device according to the second embodiment. FIG. 6A shows a cross-sectional view taken along the line B1-B1 ′ of FIG. FIG. 6 (b) shows a cross-sectional view along line A1-A1 'of FIG. 6 (a). FIG. 6C shows the concentration profiles of p-type impurities at points P to R and P ′ to R ′ in FIG. 6A.

  In the semiconductor device 102 according to the second embodiment, the p-type base region 20 includes a region 20 h in which the p-type impurity concentration is relatively high. The p-type base region 30 includes a region 30 h in which the p-type impurity concentration is relatively high. In each of the regions 20 h and 30 h, the impurity concentration is higher from the first electrode 11 to the second electrode 12. Each of the regions 20 h and 30 h is a low resistance region for holes.

The area 20 h overlaps the area 20 b in the Z-axis direction. The region 30 h overlaps the region 30 b in the Z-axis direction. In the Y-axis direction, the region 20 h is provided between the n ⁺ -type emitter region 40 and the first connection region 51. In the Y-axis direction, the region 30 h is provided between the n ⁺ -type emitter region 50 and the second connection region 52. Either the region 20 h or the region 30 h may be excluded.

  Due to the presence of the region 20 h, after turning off, the holes flowing into the p-type base region 20 are efficiently discharged to the second electrode 12 through the region 20 h. Due to the presence of the region 30 h, the holes flowing into the p-type base region 30 are efficiently discharged to the second electrode 12 through the region 30 h. Thereby, in the semiconductor device 102, latch-up after turn-off is further suppressed. In the semiconductor device 102 in which latch-up is further suppressed, a large current turn-off operation is possible.

Third Embodiment
FIGS. 7A and 7B are schematic views showing a semiconductor device according to the third embodiment. FIG. 7A shows a cross-sectional view taken along line B1-B1 ′ of FIG. 7B. FIG. 7 (b) shows a cross-sectional view along line A1-A1 ′ of FIG. 7 (a).

In the semiconductor device 103 according to the third embodiment, the impurity concentration of the p-type base region 20 provided between the n ⁺ -type emitter region 40 and the n-type base region 10 in the Z-axis direction is relatively low. There is. For example, the p-type base region 20 includes a portion 20H and a portion 20L. The portion 20H is aligned with the portion 20L in the Y-axis direction. In the case of this embodiment, the portion 20H is a p + -type semiconductor region, and the portion 20L is a p-type semiconductor region. The portion 20L is provided between the n + -type emitter region 40 and the n-type base region 10 in the Z-axis direction.

Further, the impurity concentration of the p-type base region 30 provided between the n + -type emitter region 50 and the n-type base region 10 in the Z-axis direction is relatively low. For example, the p-type base region 30 includes a portion 30H and a portion 30L. The portion 30H is aligned with the portion 30L in the Y-axis direction. The portion 30H is a p ^{+ -type} semiconductor region, and the portion 30L is a p-type semiconductor region. The portion 30L is provided between the n ⁺ -type emitter region 50 and the n-type base region 10 in the Z-axis direction.

  Due to the presence of the portion 20H, the holes flowing into the p-type base region 20 are efficiently discharged to the second electrode 12 through the portion 20H after the turn-off. Due to the presence of the portion 30H, the holes flowing into the p-type base region 30 are efficiently discharged to the second electrode 12 through the portion 30H. This further suppresses latch-up after turn-off. In the semiconductor device 103 in which latch-up is further suppressed, a large current turn-off operation is possible.

Fourth Embodiment
FIG. 8A and FIG. 8B are schematic views showing a semiconductor device according to the fourth embodiment. FIG. 8A shows a cross-sectional view taken along line B1-B1 ′ of FIG. 8B. FIG. 8B is a cross-sectional view taken along line A1-A1 ′ of FIG. 8A.

  The semiconductor device 104 according to the fourth embodiment further includes a third connection region 53 and a fourth connection region 54. At least one of the illustrated area 20h and the area 30h may be excluded.

The third connection region 53 is provided between the p-type base region 20 and the second electrode 12 in the Z-axis direction. The third connection region 53 is electrically connected to the second electrode 12 and the p-type base region 20. The third connection region 53 has a predetermined length in the Z-axis direction. The third connection region 53 extends in the X-axis direction. The n ⁺ -type emitter region 40 is provided between the third connection region 53 and the gate electrode 13 in the Y-axis direction.

The fourth connection region 54 is provided between the p-type base region 30 and the second electrode 12 in the Z-axis direction. The fourth connection region 54 is electrically connected to the second electrode 12 and the p-type base region 30. The fourth connection region 54 has a predetermined length in the Z-axis direction. The four connection regions 54 extend in the X-axis direction. The n ⁺ -type emitter region 50 is provided between the fourth connection region 54 and the gate electrode 13 in the Y-axis direction.

In the semiconductor device 104, the width of the n ⁺ -type emitter region 40 in the Y-axis direction is set by the distance between the third connection region 53 and the gate insulating film 63 in the Y-axis direction. By setting the distance between the third connection region 53 and the gate insulating film 63 narrow in the Y-axis direction, the width of the n ⁺ -type emitter region 40 in the Y-axis direction can be miniaturized. Further, by setting the distance between the fourth connection region 54 and the gate insulating film 63 narrow in the Y-axis direction, the width of the n ⁺ -type emitter region 50 in the Y-axis direction can be miniaturized.

  Further, in the semiconductor device 104, the holes flowing into the p-type base region 20 after the turn-off can be discharged to the second electrode 12 through the third connection region 53. In addition, the holes flowing into the p-type base region 30 can also be discharged to the second electrode 12 through the fourth connection region 54. This further suppresses latch-up after turn-off. In the semiconductor device 104 in which latch-up is further suppressed, a large current turn-off operation is possible.

Fifth Embodiment
FIG. 9A and FIG. 9B are schematic views showing a semiconductor device according to the fifth embodiment. FIG. 9A shows a cross-sectional view taken along line B1-B1 ′ of FIG. 9B. In FIG.9 (b), the A1-A1 'sectional view taken on the line of Fig.8 (a) is shown.

  The semiconductor device 105 according to the fifth embodiment further includes a fifth connection region 55, a sixth connection region 56, and a fourth insulating film (insulating film 64).

  The fifth connection region 55 electrically connects the first connection region 51 and the second electrode 12. The fifth connection region 55 has a predetermined length in the Z-axis direction. The fifth connection region 55 extends in the X-axis direction.

  The sixth connection region 56 electrically connects the second connection region 52 and the second electrode 12. The sixth connection region 56 has a predetermined length in the Z-axis direction. The sixth connection region 56 extends in the X-axis direction.

The insulating film 64 is between the second electrode 12 and the p-type base region 20, between the second electrode 12 and the p-type base region 30, between the second electrode 12 and the n ⁺ -type emitter region 40, and It is provided between the electrode 12 and the n ⁺ -type emitter region 50.

  In the semiconductor device 105, in the step of forming the third connection region 53 and the fourth connection region 54, the fifth connection region 55 and the sixth connection region 56 are formed. Thereby, when forming the 3rd connection field 53 and the 4th connection field 54, the manufacturing process for connecting the 1st connection field 51 and the 2nd connection field 52 directly to the 2nd electrode 12 can be omitted.

Sixth Embodiment
FIGS. 10A and 10B are schematic views showing a semiconductor device according to the sixth embodiment. FIG. 10A shows a cross-sectional view taken along line B1-B1 ′ of FIG. FIG. 10 (b) shows a cross-sectional view along line A <b> 1-A <b> 1 of FIG. 10 (a).

The semiconductor device 106 according to the sixth embodiment includes the first electrode 11, the second electrode 12, the n-type base region 10, the first connection region 51, the second connection region 52, the gate electrode 13, and p. Base region 20, p-type base region 30, n ⁺ -type emitter region 40, n ⁺ -type emitter region 50, insulating film 61, insulating film 62, gate insulating film 63, p ^{+ -type} collector region And 60.

  The n-type base region 10 is provided between the first electrode 11 and the second electrode 12. The n-type base region 10 includes a first portion 10L and a second portion 10H. The second portion 10H is provided between the first portion 10L and the second electrode 12. The impurity concentration of the second portion 10H is higher than the impurity concentration of the first portion 10L.

  The first connection region 51 is provided between the first portion 10 </ b> L of the n-type base region 10 and the second electrode 12. The first connection region 51 is electrically connected to the second electrode 12. The second connection region 52 is provided between the first portion 10 </ b> L of the n-type base region 10 and the second electrode 12. The second connection region 52 is aligned with the first connection region in the X-axis direction. The second connection region 52 is electrically connected to the second electrode 12.

  The gate electrode 13 is provided between the second portion 10H of the n-type base region 10 and the second electrode 12.

The operation of the semiconductor device 106 will be described.
11 (a) and 11 (b) are schematic cross-sectional views showing the operation of the semiconductor device according to the sixth embodiment.

  FIG. 11A shows the state after the semiconductor device 106 is turned on.

  When a potential higher than the threshold potential (Vth) is applied to gate electrode 13, a channel region is formed along gate insulating film 63.

The electron current e1 flows from the n ⁺ -type emitter region 40 to the n-type base region 10 via the channel. The electron current e2 flows from the n ⁺ -type emitter region 50 to the n-type base region 10 via the channel. The electron current e1 reaches the p ^{+ -type} collector region 60. The electron current e 2 reaches the p ^{+ -type} collector region 60. On the other hand, holes h 1 and h 2 are injected from the p ^{+ -type} collector region 60.

  Here, a second portion 10H having a high n-type impurity concentration is provided below the channel region. As a result, the electron currents e1 and e2 are easily spread in the second portion 10H, and at the same time, the holes injected from the p + -type collector region 60 are less likely to be discharged from the p-type base region 20 and the p-type base region 30 An electron injection promoting effect (IE effect) is generated that the number of carriers is increased. Thus, in the semiconductor device 106, the on resistance is further reduced.

  In the semiconductor device 106, the length of the gate insulating film 63 in the Z-axis direction is shorter than the length of the insulating film 61 in the Z-axis direction and the length of the insulating film 62 in the Z-axis direction.

  Thus, in the on state, the parasitic capacitance Cge between the gate electrode 13 and the second electrode 12 and the parasitic capacitance Cgc between the gate electrode 13 and the first electrode 11 are reduced. Thereby, in the semiconductor device 106, the switching operation becomes fast.

  Further, in the semiconductor device 106, the distance between the first connection region 51 and the second connection region 52 in the Y-axis direction can be changed. When the distance between the first connection region 51 and the second connection region 52 is narrowed, holes are more easily accumulated in the n-type base region 10 between the first connection region 51 and the second connection region 52 (IE Increased effectiveness). Thereby, in the semiconductor device 106, the on-resistance is further reduced.

  On the other hand, FIG. 11B shows a state after the semiconductor device 106 is turned off.

After turn-off, the channel region disappears and the electron injection from the n ⁺ -type emitter regions 40, 50 is blocked. On the other hand, holes remaining in the n-type base region 10 are discharged to the second electrode 12 via the p-type base regions 30 and 40.

  In the semiconductor device 106, the lower end 61 d of the insulating film 61 and the lower end 62 d of the insulating film 62 are located closer to the first electrode 11 than the lower end 63 d of the gate insulating film 63.

  As a result, as described in the first embodiment, not only a sufficient blocking voltage can be realized in the off state, but also an effect such as a significant improvement in the breakdown tolerance during the turn-off switching process can be obtained.

  In semiconductor device 106, after turn-off, it extends from junction pn1 to p-type base region 20 and n-type base region 10. Also, after turn-off, the depletion layer extends from junction pn 2 to p-type base region 30 and n-type base region 10. The depletion layer is also an n-type base region from the interface between insulating film 61 and n-type base region 10, the interface between insulating film 62 and n-type base region 10, and the interface between gate insulating film 63 and n-type base region 10. Extends to ten.

  These depletion layers are connected in the n-type base region 10. The connected depletion layer 10 dp extends below the insulating film 61, the insulating film 62 and the gate insulating film 63.

  Assuming that depletion layer 10 dp is regarded as an insulating layer, the length of the insulating layer located between gate electrode 13 and n-type base region 10 corresponds to the length of gate insulating film 63 in the Z-axis direction, the depletion in the Z-axis direction. It becomes the length which added the length of layer 10dp.

  Thus, the length of the insulating layer between the gate electrode 13 and the n-type base region 10 is increased, and the parasitic capacitance Cgc between the gate electrode 13 and the first electrode 11 is reduced. Thereby, in the semiconductor device 106, the switching operation becomes faster.

  On the other hand, after turn-off, n-type base region 10 between first connection region 51 and second connection region 52 is shielded by depletion layer 10 dp. Thereby, the leak current between the first electrode 11 and the second electrode 12 after the turn-off can be reliably suppressed.

  In the present embodiment, the p-type base region 20 and the p-type base region 30 have a uniform structure in the Y-axis direction, but as in the first embodiment, Z on the side of the insulating film 61 and the insulating film 62 The axially wide structure further enhances the effect of the present invention.

Seventh Embodiment
12A to 12C are schematic views showing a semiconductor device according to the seventh embodiment. FIG. 12 (a) shows a cross-sectional view along the line B1-B1 ′ of FIG. 12 (b). FIG. 12 (b) shows a cross-sectional view along line A <b> 1-A <b> 1 of FIG. 12 (a). FIG. 12C shows the concentration profile of the p-type impurity at points P to R and P ′ to R ′ in FIG.

  In the semiconductor device 107 according to the seventh embodiment, the p-type base region 20 includes a region 20 h in which the p-type impurity concentration becomes relatively high. The p-type base region 30 includes a region 30 h in which the p-type impurity concentration is relatively high. Either the region 20 h or the region 30 h may be excluded.

  Due to the presence of the region 20 h, after turning off, the holes flowing into the p-type base region 20 are efficiently discharged to the second electrode 12 through the region 20 h. Due to the presence of the region 30 h, the holes flowing into the p-type base region 30 are efficiently discharged to the second electrode 12 through the region 30 h. Thereby, in the semiconductor device 107, latch-up after turn-off is further suppressed. In the semiconductor device 107 in which latch-up is further suppressed, a large current turn-off operation is possible.

Eighth Embodiment
FIG. 13A and FIG. 13B are schematic views showing the semiconductor device according to the eighth embodiment. FIG. 13A shows a cross-sectional view taken along line B1-B1 ′ of FIG. FIG. 13 (b) shows a cross-sectional view along line A1-A1 ′ of FIG. 13 (a).

  In the semiconductor device 108 according to the eighth embodiment, the p-type base region 20 includes a portion 20H and a portion 20L. The p-type base region 30 includes a portion 30H and a portion 30L.

  Due to the presence of the portion 20H, the holes flowing into the p-type base region 20 are efficiently discharged to the second electrode 12 through the portion 20H after the turn-off. Due to the presence of the portion 30H, the holes flowing into the p-type base region 30 are efficiently discharged to the second electrode 12 through the portion 30H. This further suppresses latch-up after turn-off. In the semiconductor device 108 in which latch-up is further suppressed, a large current turn-off operation is possible.

The ninth embodiment
FIG. 14A and FIG. 14B are schematic views showing the semiconductor device according to the ninth embodiment. FIG. 14A is a cross-sectional view taken along line B1-B1 ′ of FIG. FIG. 14 (b) shows a cross-sectional view along line A <b> 1-A <b> 1 of FIG. 14 (a).

  The semiconductor device 109 according to the ninth embodiment further includes a third connection region 53 and a fourth connection region 54. At least one of the region 20 h and the region 30 h may be excluded.

In the semiconductor device 109, the width of the n ⁺ -type emitter region 40 in the Y-axis direction is set by the distance between the third connection region 53 and the gate insulating film 63 in the Y-axis direction. By setting the distance between the third connection region 53 and the gate insulating film 63 narrow in the Y-axis direction, the width of the n ⁺ -type emitter region 40 in the Y-axis direction can be miniaturized. Further, by setting the distance between the fourth connection region 54 and the gate insulating film 63 narrow in the Y-axis direction, the width of the n ⁺ -type emitter region 50 in the Y-axis direction can be miniaturized.

  In addition, in the semiconductor device 109, the holes which flow into the p-type base region 20 after the turn-off can be discharged to the second electrode 12 through the third connection region 53. In addition, the holes flowing into the p-type base region 30 can also be discharged to the second electrode 12 through the fourth connection region 54. This further suppresses latch-up after turn-off. In the semiconductor device 109 in which latch-up is further suppressed, a large current turn-off operation is possible.

Tenth Embodiment
FIG. 15A and FIG. 15B are schematic views showing a semiconductor device according to the tenth embodiment. FIG. 15 (a) shows a cross-sectional view along the line B1-B1 ′ of FIG. 15 (b). FIG. 15 (b) shows a cross-sectional view along line A1-A1 ′ of FIG. 15 (a).

  The semiconductor device 110 according to the tenth embodiment further includes a fifth connection region 55, a sixth connection region 56, and an insulating film 64.

  In the semiconductor device 110, in the step of forming the third connection region 53 and the fourth connection region 54, the fifth connection region 55 and the sixth connection region 56 are formed. Thereby, when forming the 3rd connection field 53 and the 4th connection field 54, the manufacturing process for connecting the 1st connection field 51 and the 2nd connection field directly to the 2nd electrode 12 can be omitted.

Eleventh Embodiment
FIG. 16A and FIG. 16B are schematic views showing the semiconductor device according to the eleventh embodiment. FIG. 16C is a graph showing the impurity concentration profile of a partial region of the semiconductor device according to the fifth embodiment. The horizontal axis in FIG. 16C is the position in the Z-axis direction, and the vertical axis is the impurity concentration (the unit is an arbitrary value (au)), which indicates the relative impurity concentration.

In the semiconductor devices 111A and 111B shown in FIG. 16A, the n ⁻ -type base region 10 has a region in which the impurity concentration becomes higher as it approaches the collector electrode 11. This area is called an n-type buffer area 10b. The n-type buffer area 10 b has a predetermined length in the Z-axis direction. The n-type buffer region 10 b extends in the X-axis direction and the Y-axis direction. The impurity concentration of the n-type buffer region 10 b is higher than the impurity concentration of the n-type base region 10 excluding the n-type buffer region 10 b.

  By providing the n-type buffer region 10b in the n-type base region 10, the length in the Z-axis direction of the n-type base region 10 is reduced, and the resistance thereof is further reduced. Thereby, in the semiconductor devices 111A and 111B, the on voltage in the on state is further reduced.

(Twelfth embodiment)
FIG. 17A and FIG. 17B are schematic views showing a semiconductor device according to the twelfth embodiment.

  A semiconductor device 112A shown in FIG. 17A includes a semiconductor device 101 and a diode region 101D. In the diode region 101D, the first electrode 11 is a cathode electrode, and the second electrode 12 is an anode electrode.

  In the diode region 101D, an n-type semiconductor region 11D is provided between the first electrode 11 and the second electrode 12. The impurity concentration of the n-type semiconductor region 11D is the same as the impurity concentration of the n-type base region 10. In the diode region 101D, a p-type semiconductor region 31 is provided between the n-type semiconductor region 11D and the second electrode 12. The p-type semiconductor region 31 is provided between the second connection region 52 and the seventh connection region 57 in the Y-axis direction. An insulating film 67 is provided between the seventh connection region 57 and the p-type semiconductor region 31 and between the seventh connection region 57 and the n-type semiconductor region 11D.

  A semiconductor device 112B shown in FIG. 17B includes a semiconductor device 106 and a diode region 101D.

  Such semiconductor devices 112A and 112B are also included in the embodiment.

(13th Embodiment)
FIG. 18A and FIG. 18B are schematic plan views showing a semiconductor device according to a thirteenth embodiment.

  18A and 18B show the state in the XY plane below the second electrode 12 of the semiconductor device 101. FIG. FIG. 18A shows a first example of the thirteenth embodiment. FIG. 18B shows a second example of the thirteenth embodiment.

In the first example shown in FIG. 18A, the end 20 e of the p-type base region 20 is provided between the first connection region 51 and the gate electrode 13. An end 30 e of the p-type base region 30 is provided between the gate electrode 13 and the second connection region 52. The end 40 e of the n ⁺ -type emitter region 40 is located in the p-type base region 20. An end 50 e of the n ⁺ -type emitter region 50 is located in the p-type base region 30. In the first example, the end 51 e of the first connection region 51 is in contact with the n-type base region 10 via the insulating film 61, and the end 13 e of the gate electrode 13 is n-type base via the gate insulating film 63. The end 52 e of the second connection region 52 is in contact with the n-type base region 10 via the insulating film 62 in contact with the region 10. In the first example, the p-type base region 20 and the p-type base region 30 are divided by the gate electrode 13.

  In the second example shown in FIG. 18B, the end 20 e of the p-type base region 20 and the end 30 e of the p-type base region 30 are the first connection region 51, the gate electrode 13, and the second connection region 52. Located outside the end of the In the second example, the p-type base region 20 and the p-type base region 30 are connected outside the end portions of the first connection region 51, the gate electrode 13, and the second connection region 52.

  In the first to twelfth embodiments, the cross section of a portion of the semiconductor device or the plane thereof is illustrated. Even if the p-type base region 20 and the p-type base region 30 are connected outside the end of the first connection region 51, the gate electrode 13 and the second connection region 52, the individual p illustrated in the partial cross section A shaped base region is defined as p-type base region 20 or p-type base region 30.

Termination structures of the p-type base regions 20 and 30, n ⁺ -type emitter regions 40 and 50, the first connection region 51, the gate electrode 13 and the second connection region 52 in the thirteenth embodiment are the second to twelfth embodiments. It also applies to the form.

  In each semiconductor device in the embodiment, the same effect can be obtained even if p-type and n-type are reversed.

The p ^{+ -type} collector region 60 may be removed from each semiconductor device in the embodiment. In this case, each semiconductor device is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this case, in the present embodiment, “emitter” is replaced with “source”, and “collector” is replaced with “drain”.

  The main component of each semiconductor region in the embodiment is, for example, silicon (Si). The main component of each semiconductor region may be silicon carbide (SiC), gallium nitride (GaN) or the like. As the impurity element of the first conductivity type, for example, phosphorus (P), arsenic (As) or the like is applied. As the impurity element of the second conductivity type, for example, boron (B) or the like is applied. In addition, although an n-channel IGBT is illustrated in this specification, it may be a p-channel IGBT.

Also, “impurity concentration (atoms / cm ³ )” refers to the effective concentration of the impurity element contributing to the conductivity of the semiconductor material. For example, in the case where the semiconductor material contains an impurity element serving as a donor and an impurity element serving as an acceptor, the concentration of the activated impurity element excluding the offset between the donor and the acceptor is an effective impurity. It is the concentration. Further, the concentration of electrons or holes ionized from an effective impurity element is taken as a carrier concentration. The high and low of the impurity concentration according to the embodiment is compared by the maximum value or the average value of the impurity concentration profile in the Z direction. The impurity concentration can be analyzed by SIMS analysis. The electrically activated carrier concentration can be analyzed by SR analysis. The pn junction interface can be analyzed by, for example, SCM analysis.

The first electrode 11, the second electrode 12, the gate electrode 13, the first connection region 51, the second connection region 52, the third connection region 53, the fourth connection region 54, the fifth connection region 55, and the sixth connection region 56 The material is, for example, a metal including at least one selected from the group of aluminum (Al), titanium (Ti), nickel (Ni), tungsten (W), gold (Au), polysilicon and the like. The first insulating film 61, the second insulating film 62, or the gate insulating film 63 contains, for example, silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

  In the above embodiment, “on” when expressed as “A is provided on B” means that A is in contact with B and A is provided on B. In addition to the case, A may not be in contact with B, and may be used in the sense that A is provided above B. Also, “A is provided on B” is also applied when A and B are inverted and A is positioned below B, or when A and B are arranged side by side. There is a case. This is because the structure of the semiconductor device does not change before and after the rotation even if the semiconductor device according to the embodiment is rotated.

  The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. That is, those to which a person skilled in the art appropriately adds design changes to these specific examples are also included in the scope of the embodiments as long as the features of the embodiments are included. The elements included in the above-described specific examples and the arrangement, materials, conditions, shapes, sizes, and the like of the elements are not limited to those illustrated, and can be changed as appropriate.

  Moreover, each element with which each embodiment mentioned above is equipped can be combined as much as technically possible, and what combined these is also included in the range of the embodiment as long as the feature of the embodiment is included. In addition, within the scope of the concept of the embodiment, those skilled in the art can conceive of various modifications and modifications, and it is understood that the modifications and modifications also fall within the scope of the embodiment. .

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

10 n-type base region, 10 dp depletion layer, 10 L, 10 H portion, 11 collector electrode, 11 D n-type semiconductor region, 12 emitter electrode, 13 gate electrode, 13 e end, 20 p-type base region, 20 a region, 20 b region, 20 d Lower end, 20e end, 20H portion, 20L portion, 20h region, 20L p type semiconductor region, 25p type semiconductor region, 25Ly p type semiconductor region, 30p type base region, 30a region, 30b region, 30d lower end, 30e end Part, 30h area, 30Ly p type semiconductor area, 40, 50n ^{+ type} emitter area, 40e, 50e end, 51 first connection area, 51e end, 52 second connection area, 52e end, 53 third connection region, 54 fourth connection region 55 fifth connecting region, 56 sixth connecting region, 60 ^{p +} form collection 61, 62, 64 insulating film, 61d, 62d lower end, 63 gate insulating film, 63d lower end, 90, 91, 92 mask, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111A, 111B, 112A, 112B semiconductor device, 101D diode region, L1 first length, L2 second length, L3 third length, L4 fourth length, pn1, pn2 pn junction, e1 , E2 electron current, h1, h2, h3, h4 hole current

Claims (13)

A first electrode,
A second electrode,
A first semiconductor region of a first conductivity type provided between the first electrode and the second electrode;
A first connection region provided between the first semiconductor region and the second electrode and electrically connected to the second electrode;
The first connection region is provided between the first semiconductor region and the second electrode, and is aligned with the first connection region in a second direction intersecting the first direction from the first electrode to the second electrode, A second connection region electrically connected to the two electrodes;
It is provided between the first connection area and the second connection area, and the length in the first direction is the length of the first connection area in the first direction and the second connection area in the first direction. A third electrode shorter than the length of
A second semiconductor region of the second conductivity type provided between the first connection region and the third electrode;
A third semiconductor region of the second conductivity type provided between the second connection region and the third electrode;
A fourth semiconductor region of the first conductivity type provided between the second semiconductor region and the second electrode;
A fifth semiconductor region of the first conductivity type provided between the third semiconductor region and the second electrode;
A first insulating film provided between the first connection region and the second semiconductor region;
A second insulating film provided between the second connection region and the third semiconductor region;
A third insulating film provided between the third electrode and the second semiconductor region and between the third electrode and the third semiconductor region;
Equipped with
The lower end of the second semiconductor region along the first insulating film in the first direction is closer to the first electrode than the lower end of the second semiconductor region along the third insulating film in the first direction. Located in
The lower end of the third semiconductor region along the second insulating film in the first direction is closer to the first electrode than the lower end of the third semiconductor region along the third insulating film in the first direction. Semiconductor devices located in   In the first direction, the lengths of the fourth semiconductor region and the second semiconductor region along the third insulating film are the lengths of the second semiconductor region along the first insulating film in the first direction. The semiconductor device according to claim 1, wherein the semiconductor device is shorter.   In the first direction, lengths of the fifth semiconductor region and the third semiconductor region along the third insulating film are equal to lengths of the third semiconductor region along the second insulating film in the first direction. The semiconductor device according to claim 1, wherein the semiconductor device is shorter.   In the second semiconductor region, the distance between the junction between the second semiconductor region and the first semiconductor region and the second electrode is longer than the length of the third electrode in the first direction. The semiconductor device according to claim 1, comprising an area.   In the third semiconductor region, a distance between a junction between the third semiconductor region and the first semiconductor region and the second electrode is longer than a length of the third electrode in the first direction. The semiconductor device according to any one of claims 1 to 4, including an area. A first electrode,
A second electrode,
Provided between the first electrode and the second electrode and including a first portion and a second portion, wherein the second portion is provided between the first portion and the second electrode; A first semiconductor region of a first conductivity type, wherein the impurity concentration of the two parts is higher than the impurity concentration of the first part;
A first connection region provided between the first portion of the first semiconductor region and the second electrode and electrically connected to the second electrode;
The first connection region is provided between the first portion of the first semiconductor region and the second electrode, and in a second direction intersecting the first direction from the first electrode to the second electrode A second connection region electrically connected to the second electrode;
It is provided between the second portion of the first semiconductor region and the second electrode, and the length in the first direction is the length of the first connection region in the first direction and the first direction A third electrode shorter than the length of the second connection region at
A second semiconductor region of the second conductivity type, provided between the first connection region and the third electrode;
A third semiconductor region of the second conductivity type provided between the second connection region and the third electrode;
A fourth semiconductor region of the first conductivity type provided between the second semiconductor region and the second electrode;
A fifth semiconductor region of the first conductivity type provided between the third semiconductor region and the second electrode;
A first insulating film provided between the first connection region and the second semiconductor region;
A second insulating film provided between the second connection region and the third semiconductor region;
A third insulating film provided between the third electrode and the second semiconductor region, and between the third electrode and the third semiconductor region;
Equipped with
The lower end of the second semiconductor region along the first insulating film in the first direction is closer to the first electrode than the lower end of the second semiconductor region along the third insulating film in the first direction. Located in
The lower end of the third semiconductor region along the second insulating film in the first direction is closer to the first electrode than the lower end of the third semiconductor region along the third insulating film in the first direction. Semiconductor devices located in   The method according to any one of claims 1 to 6, wherein at least one of the second semiconductor region and the third semiconductor region includes a region where the impurity concentration increases from the first electrode to the second electrode. Semiconductor device.   The impurity concentration of the second semiconductor region provided between the fourth semiconductor region and the first semiconductor region in the first direction is relatively low in the second semiconductor region, or the first direction The impurity concentration of the third semiconductor region provided between the fifth semiconductor region and the first semiconductor region is relatively low in the third semiconductor region. Semiconductor device according to claim 1. A third connection region provided between the second semiconductor region and the second electrode and electrically connected to the second electrode and the second semiconductor region;
A fourth connection region provided between the third semiconductor region and the second electrode and electrically connected to the second electrode and the third semiconductor region;
And further
The fourth semiconductor region is provided between the third connection region and the third electrode,
The semiconductor device according to any one of claims 1 to 8, wherein the fifth semiconductor region is provided between the fourth connection region and the third electrode. A fifth connection region electrically connecting the first connection region and the second electrode;
A sixth connection region for electrically connecting the second connection region and the second electrode;
The semiconductor device according to any one of 1 to 9, further comprising:   Between the second electrode and the second semiconductor region, between the second electrode and the third semiconductor region, between the second electrode and the fourth semiconductor region, and between the second electrode and the fifth The semiconductor device according to any one of claims 1 to 10, further comprising a fourth insulating film between the semiconductor region and the semiconductor region.   The semiconductor device according to any one of claims 1 to 11, wherein the first semiconductor region has a region in which the impurity concentration increases as approaching the first electrode.   The semiconductor device according to any one of claims 1 to 12, further comprising a sixth semiconductor region of a second conductivity type between the first electrode and the first semiconductor region.

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