JP2019046228A - Programmable controller and ladder circuit program verification system - Google Patents

Abstract

To make a ladder circuit logged and displayed efficiently without increasing a memory capacity and a ladder circuit verification time.SOLUTION: A programmable controller comprises: a control unit 30 for detecting register information necessary for displaying a past ladder circuit; a memory 36 for storing the detected register information based on a change point of the register information; and an interface unit 31 transmits the register information of the past ladder circuit stored in the memory 36 from the programmable controller 10 to a peripheral device 11 via communication and displays the register information on the peripheral device 11 based on the change point.SELECTED DRAWING: Figure 1a

Description

  The present invention relates to a programmable controller and a ladder circuit program verification system.

  The programmable controller uses a ladder circuit program created by the user to create a ladder using a register that handles external input / output data (hereinafter referred to as an external input / output register) and a register that is used for ladder calculation (hereinafter referred to as an internal calculation register). Perform arithmetic processing.

  The user verifies whether the ladder circuit program is executed as intended when the apparatus using the programmable controller is started up or when a malfunction occurs. When a peripheral device is connected to the programmable controller and ladder circuit monitoring or register monitoring is executed from the peripheral device, register information is acquired from the programmable controller by communication and displayed on the display of the peripheral device.

  The user performs verification based on information (ladder diagram or register information) displayed in real time on the display. In this way, register information is monitored from the programmable controller using a communication function in real time and displayed on the display of the peripheral device.

  At this time, in the case of external input / output registers and internal calculation registers whose data displayed on the peripheral device display changes at high speed, it may be difficult or overlooked on the peripheral device display, and verification of the ladder circuit program It takes time.

  For this reason, when verification in real time is difficult, ladder circuit verification is performed using a logging function that periodically saves and stores designated register information. For example, Patent Document 1 discloses a technique for performing ladder circuit verification using this logging function.

Japanese Patent Laid-Open No. 10-11118

  However, in the verification method of Patent Document 1, the time chart or numerical data is displayed on the display of the peripheral device, and the ladder circuit itself is not displayed. For this reason, the user needs to make the ladder circuit correspond to the logging data on the desk, and it takes time to verify the ladder circuit.

  At this time, it is conceivable to log the entire ladder circuit to the memory and display it on the display. However, the memory capacity increases and the ladder circuit verification time also increases.

  An object of the present invention is to efficiently log and display a ladder circuit without increasing the memory capacity and the time for verifying the ladder circuit.

A programmable controller according to one embodiment of the present invention is a programmable controller that is connected to a peripheral device that displays information so as to be communicable and performs a ladder operation on a ladder circuit program using register information of the ladder circuit. A control unit for detecting the register information necessary for displaying a circuit;
A memory for storing the register information detected by the control unit with reference to a change point of the register information, and the register information of the past ladder circuit stored in the memory are communicated from the programmable controller to the peripheral device. And an interface unit that displays the sent register information on the peripheral device based on the change point.

A ladder circuit program verification system according to an aspect of the present invention includes a programmable controller that performs a ladder operation on a ladder circuit program using register information of the ladder circuit, and is connected to the programmable controller so as to be communicable. A peripheral device for displaying the register information, and the programmable controller detects the register information necessary for displaying the ladder circuit in the past, and the register information detected by the control unit. A memory for storing the change point of the register information as a reference,
The peripheral device acquires the register information of the past ladder circuit stored in the memory from the programmable controller by communication, and displays the acquired register information on the basis of the change point.

  A ladder circuit program verification system according to an aspect of the present invention includes a programmable controller that performs a ladder operation on a ladder circuit program using register information of the ladder circuit, and is connected to the programmable controller so as to be communicable. A peripheral device for displaying register information, wherein the programmable controller detects the register information necessary for displaying the ladder circuit in the past, and the peripheral device detects the register detected by the programmable controller. Information is acquired from the programmable controller by communication, the acquired register information is stored with reference to a change point of the register information, and the saved register information of the past ladder circuit is set with reference to the change point. To display And butterflies.

  According to one embodiment of the present invention, a ladder circuit can be efficiently logged and displayed without increasing the memory capacity and the ladder circuit verification time.

It is a figure which shows the ladder circuit program verification system of Example 1. FIG. It is a block diagram of a programmable controller. It is a figure which shows the example of a ladder circuit display on the display of a peripheral device. It is a figure which shows the example of a ladder circuit display on the display of the peripheral device in execution of the past ladder circuit monitor. It is an image figure when frame-by-frame playback is performed. 6 is a flowchart illustrating a procedure for verifying a past calculation result of the first embodiment on a ladder circuit diagram. 12 is a flowchart illustrating a procedure for verifying a past calculation result of the fourth embodiment on a ladder circuit diagram. FIG. 10 is a diagram illustrating an example of a time chart of Example 4. It is an image figure which skip-reproduced the change point of register information.

  In the case of external input / output registers and internal arithmetic registers in which data displayed on the peripheral device display changes at high speed, it may be difficult or overlooked on the peripheral device display. For this reason, it takes time to verify the ladder circuit program. In the embodiment, the ladder circuit is displayed on the display of the peripheral device retroactively rather than in real time.

  Specifically, in the embodiment, an external input / output register and an internal calculation register necessary for displaying past data are detected, the register information is periodically collected and stored, and the stored register information is stored. Display on the ladder circuit monitor of the peripheral device. In this way, register information (external input / output registers and internal arithmetic registers) for ladder circuits that you want to verify retroactively can be detected with simple operations, and the register information is collected periodically based on user specifications. save.

In the embodiment, it is possible to display a past ladder calculation result executed by the programmable controller on a ladder circuit monitor on the peripheral device. Therefore, it is possible to easily determine which circuit is established in the illustrated state, and it is easy to verify the ladder circuit program.
Embodiments will be described below with reference to the drawings.

A ladder circuit program verification system according to the first embodiment will be described with reference to FIG.
The ladder circuit program verification system includes a programmable controller 10 that performs ladder calculation processing and a peripheral device 11 that performs editing and monitor display of the ladder circuit program. The programmable controller 10 and the peripheral device 11 are connected by a communication cable 12. As the communication cable 12, for example, serial communication, Ethernet (registered trademark) is used.

The configuration of the programmable controller 10 will be described with reference to FIG.
The programmable controller 10 includes an MPU (control unit) 30 that performs calculation of a ladder program and communication processing with the peripheral device 11 connected via the peripheral device interface unit 31. Furthermore, it has a non-volatile system program memory 32 storing contents and procedures controlled by the MPU 30, and a rewritable ladder circuit storage memory 33 for storing ladder circuits created by the user.

  Further, the programmable controller 10 includes an internal operation register memory 34, an external input / output register memory 35, a work memory 36, and a comparison work memory 41 that store the operation results of the ladder circuit program executed by the MPU 30. Furthermore, an input module 37 for capturing an input signal from an external device 42 (sensor, switch, etc.), an output module 38 for outputting a calculation result to an output signal to an external device 43 (lamp, actuator, etc.), interface An external bus interface 39 is provided. In addition, external devices 40 such as a general-purpose USB memory and an SD card memory can be additionally connected.

  The ladder circuit program is created by the peripheral device 11 and stored in the ladder circuit storage memory 33 via the communication cable 12 and the peripheral device interface 31.

A display example of the ladder circuit displayed on the display of the peripheral device 11 will be described with reference to FIG.
This display example is a ladder circuit diagram in which the external input / output registers X0 (13), X1 (14), Y100 (15) and the internal arithmetic register R0 (16) are combined.
On the display of the peripheral device 11, an activation button 17 for executing a past ladder circuit monitor is provided.

A display example of the ladder circuit on the display of the peripheral device 11 that is executing the past ladder circuit monitor will be described with reference to FIG. 2a.
On the display of the peripheral device 11, a stop button 25, a past data playback button 18, an elapsed time 19 from the reference axis, a playback pause button 20, a frame advance / play button 21, a frame rewind button 22, and a time from the reference axis. And a skip button 24 for skipping to the change point of the register information.

  Then, the programmable controller 10 and the peripheral device 11 shift to a communicable state (online mode), and the ladder circuit diagram monitor is executed. In this state, the ladder calculation result is displayed in a ladder circuit diagram in real time.

  For example, as shown in FIG. 2a, when X0 (13), X1 (14), and R0 (16) are turned on, a ladder circuit is established and Y100 (15) is turned on and can be viewed on the display of the peripheral device 11. In this case, when X0 (13) changes at high speed, the state of Y100 (15) also changes at high speed according to the ladder calculation result. For this reason, it may be overlooked by visual confirmation. Therefore, in order to verify past calculation results on the ladder circuit diagram, it is necessary to collect and store register information.

A procedure for verifying past calculation results on a ladder circuit diagram will be described with reference to the flowchart of FIG.
First, the activation button 17 is pressed to turn it on (S300). Thereby, the external input / output register and the internal calculation register displayed on the display of the side device 11 are automatically detected (S301). In this case, X0 (13), X1 (14), Y100 (15), R0 (16), X0, X1, and R0 are automatically detected. If register numbers overlap, they are sorted and deleted (S302), and a collection target register table (in this case, X0, X1, Y100, R0) is automatically created (S303).

  Next, data logging is executed based on the collection target register table (S304). The external input / output registers and internal calculation registers recognized as the collection target registers can be recognized at a glance by changing the display color on the display.

  The peripheral device 11 periodically collects information on the collection target register from the programmable controller 10 by communication means (S305) and stores it in a memory (not shown) of the peripheral device 11 (S306). As the memory of the peripheral device 11, for example, an HDD, a USB memory or the like is used.

  Until the stop button 25 is pressed, data in the collection target register is periodically collected (S307). This data collection period is automatically optimized by the communication capability of the programmable controller 10 and the peripheral device 11 and the number of collection target registers. In the first embodiment, this period is assumed to be 1 ms.

  During data logging, the data in the collection target register can be acquired and stored in a cycle of 1 ms while displaying the calculation result in real time on the display of the peripheral device 11.

  When displaying the ladder circuit monitor with past information, the past data reproduction button 18 is pressed. Thus, using the collection target register information stored in the memory of the peripheral device 11 from the real time display, the display is started with the time when the data logging is started by pressing the start button 17 on the ladder circuit diagram monitor as the reference axis. .

  When the elapsed time 19 from the reference axis is displayed and the playback pause button 20 is pressed, the elapsed time 19 from the reference axis is stopped and the ladder calculation result in that state is displayed on the ladder circuit monitor.

When the frame advance / playback button 21 is pressed, the ladder circuit monitor display of the elapsed time 19 from the reference axis in units of a data collection cycle (1 ms in the first embodiment) can be performed.
When the frame rewind button 22 is pressed, the elapsed time 19 from the reference axis can be traced back in units of data collection periods to display a ladder circuit monitor.
The time axis of the ladder circuit monitor display can also be changed by displaying the elapsed time 19 from the reference axis as a slider 23 and operating this slider.

FIG. 2B is an image diagram of frame-by-frame playback from an elapsed time of 10 ms to 17 ms from the reference axis. As shown in FIG. 2b, it can be easily understood that the external output register Y100 is OFF during the period of 12 ms to 13 ms because the external input register X1 is OFF.
Finally, when the stop button 25 is turned on (S308), the data logging is finished (S309).

Next, a ladder circuit program verification system according to the second embodiment will be described.
In the first embodiment, the data in the collection target register is acquired by the programmable controller 10 and the peripheral device 11 through communication, and stored in a memory (not shown) of the peripheral device 11. However, if the communication capability between the programmable controller 10 and the peripheral device 11 is low and the number of collection target registers is enormous, there is a concern that the data collection cycle will be increased. In consideration of this point, in the second embodiment, the data of the collection target register is stored in the memory of the programmable controller 10.

  Specifically, when the activation button 17 shown in FIG. 2 is pressed, the external input / output register and the internal calculation register displayed on the display of the peripheral device 11 are detected. After detecting the collection target register, the information of the collection target register is transferred to the programmable controller 10, the programmable controller 10 executes data logging based on the information, and the work memory 36 of the programmable controller 10 or an externally connectable external device The register information is stored in 40 or the like.

  When the past data reproduction button 18 is pressed to display the ladder circuit monitor with the past information, the peripheral device 11 collectively reads the data of the collection target register stored in the memory of the programmable controller 10 and the peripheral device 11 Copy to memory. Then, the ladder circuit monitor of past information is displayed using the data copied on the memory of the peripheral device 11.

Next, a ladder circuit program verification system according to the third embodiment will be described.
The second embodiment has an advantage that the programmable controller 10 itself can perform data logging of the collection target register, and the data collection cycle can be performed in units of scans unique to the programmable controller 10 instead of the time axis.

  Thus, in the third embodiment, by instructing the peripheral device 11 to perform the data collection cycle in scan units, the programmable controller 10 collects data in the collection target register in scan units and stores it in the memory of the programmable controller 10. . The peripheral device 11 displays the past ladder circuit monitor in units of the number of steps elapsed from the reference axis.

Next, a ladder circuit program verification system according to the fourth embodiment will be described.
In the first to third embodiments, since the information of the collection target registers is collected and stored at regular intervals, a storage memory corresponding to the number of collection target registers × time axis is required. In the fourth embodiment, the work memory 36 serving as a storage amount memory is not enlarged.

A procedure for verifying past calculation results on a ladder circuit diagram will be described with reference to the flowchart of FIG.
First, the activation button 17 is pressed to turn it on (S400). Thereby, the external input / output register and the internal calculation register displayed on the display of the peripheral device 11 are automatically detected (S401). In this case, X0 (13), X1 (14), Y100 (15), R0 (16), X0, X1, and R0 are automatically detected.

  When register numbers overlap, sorting and deletion are executed (S402), and a collection target register table (in this case, X0, X1, Y100, R0) is automatically created (S403).

Next, data logging is executed based on the collection target register table (S404). The steps so far are the same as those in the first and second embodiments.
At the start of data logging, the MPU 30 collects information on all registers (S405) and stores it in the external device 40 that can be externally connected to the work memory 36 or the programmable controller 10 (S406).

  Then, it is determined whether or not it is the next data collection cycle (S407). When the next data collection cycle comes, data logging is executed based on the collection target register table and stored in the comparison work memory 41 (S408). Then, the register information stored in the comparison work memory 41 is compared with the register information stored in the previous work memory 36 to detect the register information change point 50 (see FIG. 5) (S409).

  Next, it is determined whether there is a change point in the register information (S409). When there is no change point of the register information, the comparison result is the same as the register information, so the data in the comparison work memory 41 is discarded without being stored in the work memory 36.

If there is a change point in the register information, the comparison result is not the same as the register information, so it is determined as logging valid data, and the register information and time stamp are added to the work memory 36 and stored (S411). Data in the collection target register is periodically collected until the stop button 25 is pressed.
Finally, when the stop button 25 is pressed and turned on (S412), the data logging is finished (S413).

  In the case of the first and second embodiments, as shown in FIG. 2b, the register information is stored eight times at intervals of 1 ms between the elapsed times of 10 ms and 17 ms. In this case, the same data is stored in register information of 10 ms and 11 ms, 12 ms and 13 ms, and 14 ms to 17 ms.

  In the case of the fourth embodiment, as shown in FIGS. 5 and 6, since logging is executed at the change point 50 of the register information, the register information is stored only twice, that is, the elapsed time 12 ms and the elapsed time 14 ms. For this reason, it is possible to reduce the enlargement of the storage amount memory.

  Further, when displaying the ladder circuit monitor with past information, as shown in FIG. 5, the time for verifying the ladder circuit program can be shortened by using the function of reproducing the change point 50 of the register information as a point.

Referring to FIG. 6, the past data reproduction button 18 is pressed, and the start button 17 is pressed on the ladder circuit diagram monitor using the data of the collection target register stored in the work memory 36. Thereby, the display is started with the time when the data logging is started as the reference axis.
At this time, when skip playback 24 is pressed instead of normal playback, the skip is performed from the elapsed time 10 ms to the register information change point elapsed time 12 ms, and is paused.
Thereafter, when the skip playback 24 is pressed again, the next register information change point elapsed time is skipped to 14 ms and paused.

By using the skip reproduction 24, it is possible to verify by skipping the time when the resist information remains unchanged.
Thus, in Example 4, the enlargement of the storage amount memory can be reduced. Furthermore, by using the function of reproducing the register information change point 50 as a point, the ladder circuit program verification time can be shortened.

10 Programmable controller,
11 Peripheral device 12 Communication cable 30 MPU
31 Peripheral device interface section 32 System program memory 33 Ladder circuit storage memory 34 Internal operation register memory 35 External input / output register memory 36 Work memory 37 Input module 38 Output module 39 External bus interface 40 External device 41 Comparison work memory 42 External device 43 External equipment

Claims (8)

A programmable controller that is communicably connected to a peripheral device that displays information and performs a ladder operation on a ladder circuit program using register information of the ladder circuit,
A control unit for detecting the register information necessary for displaying the ladder circuit in the past;
A memory for storing the register information detected by the control unit with reference to a change point of the register information, and the register information of the past ladder circuit stored in the memory to the peripheral device by communication from the programmable controller. An interface unit that displays the sent register information on the peripheral device based on the change point;
A programmable controller comprising: The ladder circuit is
An external input / output register that handles external input / output data;
An internal operation register used for the ladder operation;
The programmable controller according to claim 1, comprising: A programmable controller for performing a ladder operation on a ladder circuit program using register information of the ladder circuit;
A peripheral device that is communicably connected to the programmable controller and displays the register information of the ladder circuit;
The programmable controller is
A control unit for detecting the register information necessary for displaying the ladder circuit in the past;
A memory for storing the register information detected by the control unit on the basis of a change point of the register information;
The peripheral device is:
A ladder circuit program verification system, wherein the register information of the past ladder circuit stored in the memory is acquired from the programmable controller by communication, and the acquired register information is displayed based on the change point. The ladder circuit is
An external input / output register that handles external input / output data;
An internal operation register used for the ladder operation;
The ladder circuit program verification system according to claim 3, further comprising: The peripheral device is:
4. The ladder circuit program verification system according to claim 3, wherein the ladder circuit program is verified by displaying the register information of the past ladder circuit with reference to the change point. A programmable controller for performing a ladder operation on a ladder circuit program using register information of the ladder circuit;
A peripheral device that is communicably connected to the programmable controller and displays the register information of the ladder circuit;
The programmable controller is
The register information necessary for displaying the ladder circuit in the past is detected,
The peripheral device is:
The register information detected by the programmable controller is acquired from the programmable controller by communication, and the acquired register information is stored with reference to a change point of the register information,
A ladder circuit program verification system, wherein the stored register information of the past ladder circuit is displayed with reference to the change point. The ladder circuit is
An external input / output register that handles external input / output data;
An internal operation register used for the ladder operation;
The ladder circuit program verification system according to claim 6, further comprising: The peripheral device is:
The ladder circuit program verification system according to claim 6, wherein the program of the ladder circuit is verified by displaying the register information of the past ladder circuit with reference to the change point.

Images