JP2019045759A - Display - Google Patents

Abstract

To make it possible to improve display quality.SOLUTION: A display comprises: a first substrate that includes scan lines extending in a first direction, signal lines extending in a second direction intersecting the first direction, and first projections superimposed on the signal lines and extending along the signal lines; and a second substrate that faces the first substrate and includes second projections extending along the scan lines at positions superimposed on the scan lines. The display has first intersections at which the scan lines and the signal lines respectively intersect each other, and the first projections and the second projections are in contact with each other respectively at the first intersections.SELECTED DRAWING: Figure 1

Description

  Embodiments of the present invention relate to a display device.

  A display device provided with a sheet-like display panel has been considered. The display panel is provided with flexible first and second substrates facing each other, and a liquid crystal layer and a spacer located between the first and second substrates. The display panel is configured by bonding a first substrate and a second substrate with a spacer interposed therebetween. Such a display panel is likely to be misaligned between the first substrate and the second substrate, as compared to a display panel configured by bonding two rigid substrates. If misalignment occurs between the first substrate and the second substrate, the spacer may rub against the alignment film provided on the first substrate or the second substrate to damage the alignment film. Where the alignment film is damaged due to the rubbing with the spacer, the alignment of the liquid crystal molecules is disturbed, light leakage occurs, and the contrast ratio may be lowered due to the light leakage.

JP 2000-214469 A JP, 2016-14776, A JP, 2016-177080, A JP, 2016-224298, A

  An object of the present embodiment is to provide a display device capable of improving display quality.

  According to one embodiment, the scanning line extending in the first direction, the signal line extending in the second direction intersecting the first direction, and the signal line overlap and extending along the signal line A first substrate having a first protrusion, and a second substrate having a second protrusion facing the first substrate and extending along the scanning line at a position overlapping the scanning line; A display device comprising: a first intersection portion where the scanning line and the signal line intersect; wherein the first projection and the second projection are in contact at the first intersection. Be done.

FIG. 1 is a view showing a configuration example of a display panel which constitutes the display device of the first embodiment. FIG. 2 is a plan view showing a configuration example of the first substrate. FIG. 3 is a plan view showing a configuration example of the first spacer and the second spacer according to the first embodiment. FIG. 4 is a plan view showing a configuration example of the second substrate. FIG. 5 is a cross-sectional view showing a configuration example of the display device cut along the line A-A shown in FIG. FIG. 6 is a cross-sectional view showing a configuration example of the display device cut along the line B-B shown in FIG. FIG. 7 is a perspective view showing a configuration example of a display device. FIG. 8 is a cross-sectional view showing a configuration example of the display device cut along the line C-C shown in FIG. FIG. 9 is a plan view showing a configuration example of a first spacer and a second spacer according to the first modification. FIG. 10 is a plan view showing a configuration example of the first spacer and the second spacer according to the second modification. FIG. 11 is a plan view showing a configuration example of a first spacer and a second spacer according to the third modification. FIG. 12 is a plan view showing a configuration example of the first spacer and the second spacer according to the fourth modification.

  Hereinafter, embodiments will be described with reference to the drawings. The disclosure is merely an example, and it is naturally included within the scope of the present invention as to what can be easily conceived of by those skilled in the art as to appropriate changes while maintaining the gist of the invention. In addition, the drawings may be schematically represented as to the width, thickness, shape, etc. of each portion as compared with the actual embodiment in order to clarify the description, but this is merely an example, and the present invention It does not limit the interpretation. In the specification and the drawings, components having the same or similar functions as those described above with reference to the drawings already described may be denoted by the same reference symbols, and overlapping detailed descriptions may be omitted as appropriate. .

  In the embodiment, a display device is disclosed as an example of the electronic device. This display device can be used, for example, in various devices such as a smartphone, a tablet terminal, a mobile phone terminal, a notebook type personal computer, a game machine, a virtual reality (VR) viewer, and the like. Hereinafter, the display device DSP will be described as a liquid crystal display device.

FIG. 1 is a view showing a configuration example of a display panel PNL which constitutes the display device DSP of the first embodiment. Hereinafter, the display panel PNL will be described as a sheet-like flexible display panel.
Here, FIG. 1 shows a plan view of the display panel PNL in an XY plane defined by the first direction X and the second direction Y which intersect with each other. In the illustrated example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 °. Further, viewing an XY plane defined by the first direction X and the second direction Y from the third direction Z is referred to as a plan view.

  When viewed in plan, the display panel PNL is formed, for example, in a substantially rectangular shape. Note that the display panel PNL may be formed in a round shape with rounded corners. The display panel PNL includes a first substrate SUB1, a second substrate SUB2 facing the first substrate SUB1, and a liquid crystal layer LC held between the first substrate SUB1 and the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 are bonded together by the sealing material SL in a state where a predetermined cell gap is formed therebetween. The liquid crystal layer LC is held at the inside surrounded by the sealing material SL in the cell gap between the first substrate SUB1 and the second substrate SUB2. The display panel PNL has a display area DA for displaying an image inside surrounded by the sealing material SL. The display area DA has, for example, a substantially rectangular shape. The display area DA may have another polygonal shape or a round shape. In addition, the display panel PNL has a non-display area NDA outside the display area DA. The second substrate SUB2 has a light transmission area TA which is an area overlapping the display area DA in plan view and a non-transmission area NTA which is an area overlapping the non-display area NDA in plan view. Here, in the light transmission area TA, a member having a light shielding property such as a wire may be disposed.

  The display panel PNL includes a plurality of sub-pixels PX in the display area DA. Here, the sub-pixel indicates the smallest unit that can be individually controlled according to the pixel signal, and is present in, for example, a region including a switching element arranged at a position where a scanning line and a signal line described later Do. Also, the main pixel is composed of a plurality of sub-pixels. For example, one main pixel is configured by sub-pixels corresponding to red, sub-pixels corresponding to green, and sub-pixels corresponding to blue. In another example, one main pixel is configured by sub-pixels corresponding to red, sub-pixels corresponding to green, sub-pixels corresponding to blue, and sub-pixels corresponding to white. The main pixel corresponds to the minimum unit of the image displayed in the display area DA. The plurality of sub pixels PX are arranged in a matrix in the display area DA.

  The display panel PNL includes a scanning line G extending in the first direction X, a signal line S extending in the second direction Y, and a scanning line G and a signal line S in each sub-pixel PX in the display area DA. And a pixel electrode PE electrically connected to the switching element SW in each sub-pixel PX, a common electrode CE, and the like.

  The display panel PNL may be configured as a transmissive panel that displays an image by selectively transmitting light from the backlight unit disposed on the back side thereof, or external light incident on the display panel PNL is It may be configured as a reflective panel that displays an image by selectively reflecting it, or may be configured as a semi-transmissive panel combining a transmissive type and a reflective type.

A signal supply source necessary for driving the display panel PNL such as the drive IC chip 2 and the flexible printed circuit (FPC) substrate 3 is located in the non-display area NDA. In the illustrated example, the drive IC chip 2 and the FPC board 3 are mounted on the mounting portion MT of the first substrate SUB1 extending outward beyond one substrate side edge SUB2e of the second substrate SUB2. The mounting portion MT is formed along one substrate side edge SUB1e of the first substrate SUB1. In the illustrated example, the substrate side edges SUB1e and SUB2e are formed substantially parallel to each other along the first direction X. Further, in the illustrated example, the mounting portion MT is located between the substrate side edges SUB1e and SUB2e. Although not shown, the first substrate SUB1 includes connection terminals (hereinafter referred to as pads) for connecting a signal supply source to the mounting unit MT. The pads include those electrically connected to the scanning lines G and the signal lines S described above. In the illustrated example, the other three substrate side edges of the second substrate SUB2 face the other three substrate side edges of the first substrate SUB1.
The sealing material SL is disposed in the non-display area NDA and surrounds the display area DA. In the illustrated example, the sealing material SL is formed in a rectangular shape.

FIG. 2 is a plan view showing a configuration example of the first substrate SUB1. FIG. 2 shows the main part of the first substrate SUB1. The illustrated example corresponds to an example in which an FFS (Fringe Field Switching) mode, which is one of display modes using lateral electrolysis, is applied.
The first substrate SUB1 has scanning lines G (G1, G2, G3...), Signal lines S (S1, S2, S3, S4...), Switching elements SW (SW1, SW2, SW3, SW4...), Sources / drains ( An S / D) layer RE (RE1...), A common electrode CE, and pixel electrodes PE (PE1...) Are provided. In FIG. 2, only the configuration necessary for the description is illustrated, and the illustration of the common electrode CE and the like is omitted.

  The plurality of scanning lines G are arranged in the second direction Y at intervals. The scanning lines G extend linearly along the first direction X. The scanning line G may be partially bent. The plurality of signal lines S are arranged in the first direction X at intervals. The signal line S extends substantially in the second direction Y, and a part of the signal line S is bent. In the illustrated example, the signal line S extends in a direction different from the first direction X and the second direction Y between two adjacent scanning lines G. The signal line S may be formed in a straight line along the second direction Y. The scanning line G and the signal line S intersect at an intersection XP (XP1, XP2, XP3, XP4, XP5, XP6, XP7, XP8, XP9, XP10, XP11, XP12,...) In plan view. ing. For example, the scanning line G1 and the signal line S1 intersect at the intersection XP1. Similarly, the scanning line G1 and the signal lines S2 to S4 intersect at intersections XP2 to XP4, respectively. The scanning line G2 and the signal lines S1 to S4 intersect at intersections XP5 to XP8, respectively. The scanning line G3 and the signal lines S9 to S12 intersect at intersections XP9 to XP12, respectively. The scanning lines G and the signal lines S are made of metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo, tungsten (W), copper (Cu), chromium (Cr), etc. The scanning line G and the signal line S may have a single-layer structure or a multi-layer structure as shown in FIG. Corresponds to a region partitioned by two scanning lines G and two adjacent signal lines S. As an example, the sub-pixel PX1 is partitioned by scanning lines G1 and G2 and signal lines S1 and S2. It corresponds to the area.

  The pixel electrode PE is disposed in each sub-pixel PX. The pixel electrode PE is electrically connected to the S / D layer RE through the contact hole CH1 (CH11...). As an example, the pixel electrode PE1 is disposed in the sub-pixel PX1. The pixel electrode PE1 is electrically connected to the S / D layer RE1 through the contact hole CH11. The pixel electrode PE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The shape of the pixel electrode PE is not limited to the illustrated example, and can be appropriately changed in accordance with the shape of the sub-pixel PX.

  The S / D layer RE is disposed in each sub-pixel PX. The S / D layer RE is electrically connected to the switching element SW via the contact hole CH2 (CH21...). The S / D layer RE is, for example, formed of the same material in the same layer as the signal line S. As an example, the S / D layer RE1 is disposed in the sub-pixel PX1. The S / D layer RE1 is electrically connected to the switching element SW1 via the contact hole CH21.

The switching element SW is electrically connected to the scanning line G and the signal line S. The switching element SW is electrically connected to the signal line S via the contact hole CH3 (CH31...). As an example, the switching element SW1 is electrically connected to the scanning line G1 and the signal line S1. The switching element SW1 is electrically connected to the signal line S1 via the contact hole CH31.
Further, the switching element SW includes a semiconductor layer SC. In the illustrated example, the switching element SW1 has the semiconductor layer SC1, the switching element SW2 has the semiconductor layer SC2, the switching element SW3 has the semiconductor layer SC3, and the switching element SW4 has the semiconductor layer SC4. Have. The semiconductor layers SC (SC1 to SC4...) Will be described later.

FIG. 3 is a plan view showing a configuration example of the first spacer UC and the second spacer DC according to the first embodiment. Here, the main part of the first substrate SUB1 shown in FIG. 2 is indicated by a dotted line.
The plurality of first spacers (projections) UC (UC1, UC2...) Are arranged in the first direction X at intervals. The first spacer (projected portion) UC extends substantially in the second direction Y, and a portion thereof is bent. The first spacer UC may be formed without a break in the second direction Y so as to cross the display area DA. In addition, the first spacer UC may extend linearly in the second direction Y. The first spacers UC1 and UC2 are formed to have a width W1 in the first direction X.

  In the illustrated example, the first spacer UC1 is superimposed on the signal line S1, and extends in the second direction Y along the signal line S1. The first spacer UC2 is superimposed on the signal line S4 and extends in the second direction Y along the signal line S4. The first spacer UC1 and the first spacer UC2 are spaced apart in the first direction X by an interval of one main pixel. In other words, the first spacer UC is not formed at the position overlapping with the signal lines S2 and S3.

  The plurality of second spacers DC (DC1, DC2, DC3...) Are arranged in the second direction Y at intervals. For example, the second spacer DC is disposed for each scanning line G. The second spacers DC extend linearly along the first direction X. The second spacer DC may be formed without a break in the first direction X so as to cross the display area DA. In addition, the second spacer DC may be partially bent. In the illustrated example, the second spacer DC has at least one gap GP1. The gap GP1 is smaller than the width W1 in the first direction X of the first spacer UC. The second spacer DC intersects with the first spacer UC. The second spacers DC1, DC2, and DC3 are formed to have a width W2 in the second direction Y. As an example, the width W2 is the same as the width W1. The width W2 may be different from the width W1.

  In the illustrated example, the second spacers DC1, DC2, DC3 and the first spacers UC1, UC2 respectively cross in a cross shape. The second spacers DC1, DC2, DC3 and the first spacers UC1, UC2 may intersect in a T-shape or a Y-shape. The second spacer DC1 overlaps the scanning line G1 and extends in the first direction X along the scanning line G1. The second spacers DC1 and DC2 and the first spacers UC1 and UC2 surround the main pixel. The second spacers DC2 and DC3 and the first spacers UC2 and UC3 surround the main pixel. The second spacer DC1 includes a partial spacer (projection) DC11 and a partial spacer (projection) DC12. The partial spacer DC11 intersects the first spacer UC1 at a position corresponding to the intersection XP1. The partial spacer DC12 intersects the first spacer UC2 at a position corresponding to the intersection XP4. The partial spacer DC11 and the partial spacer DC12 are linearly arranged along the first direction X, and are separated in the first direction X with a gap (interval) GP1. As an example, the partial spacer DC11 and the partial spacer DC12 are spaced apart with a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The second spacer DC2 overlaps the scanning line G2 and extends in the first direction X along the scanning line G2. The second spacer DC2 includes a partial spacer DC21 and a partial spacer DC22. The partial spacer DC21 intersects the first spacer UC1 at a position corresponding to the intersection XP5. The partial spacer DC22 intersects the first spacer UC2 at a position corresponding to the intersection XP8. That is, the first spacers UC1 and UC2 and the partial spacers DC11, DC12, DC21 and DC22 are disposed so as to surround the main pixel. The partial spacer DC21 and the partial spacer DC22 are linearly arranged along the first direction X, and are separated in the first direction X with a gap (interval) GP1. As an example, the partial spacer DC21 and the partial spacer DC22 are spaced apart with a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The second spacer DC3 overlaps the scanning line G3 and extends in the first direction X along the scanning line G3. The second spacer DC3 includes a partial spacer DC31 and a partial spacer DC32. The partial spacer DC31 intersects the first spacer UC1 at a position corresponding to the intersection XP9. The partial spacer DC32 intersects the first spacer UC2 at a position corresponding to the intersection XP12. That is, the first spacers UC1 and UC2 and the partial spacers DC21, DC22, DC31, and DC32 are arranged to surround the main pixel. The partial spacer DC31 and the partial spacer DC32 are linearly arranged along the first direction X, and are separated in the first direction X with a gap (interval) GP1. As an example, the partial spacer DC31 and the partial spacer DC32 are spaced apart with a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2.

FIG. 4 is a plan view showing a configuration example of the second substrate SUB2. Here, the main part of the first substrate SUB1 shown in FIG. 2 is shown by a dotted line, and the second spacer DC and the first spacer UC shown in FIG. 3 are shown by an alternate long and short dash line.
The second substrate SUB2 includes a light shielding layer BM, a color filter CF, and the like.
The light shielding layer BM has a light shielding property. In the illustrated example, the light shielding layer BM is formed in a lattice shape. The light shielding layer BM may have a configuration other than a lattice shape such as a ladder shape or a stripe shape. For example, the light shielding layer BM includes vertical portions BMY (BMY1, BMY2, BMY3, BMY4...) And horizontal portions BMX (BMX1, BMX2, BMX3...).
The longitudinal portions BMY are arranged in the first direction X at intervals and extend in the second direction Y. When viewed in plan, the vertical portion BMY overlaps the signal line S. In the illustrated example, the vertical portion BMY1 overlaps the signal line S1 and the first spacer UC1. The vertical portion BMY2 is superimposed on the signal line S2. The vertical portion BMY3 overlaps the signal line S3. The vertical portion BMY4 overlaps the signal line S4 and the first spacer UC2. The vertical portions BMY1, BMY2, BMY3 and BMY4 are arranged in the first direction X at intervals of one sub-pixel. The longitudinal portion BMY is formed in a band shape having a substantially constant width in the first direction X.
The lateral portions BMX are arranged in the second direction Y at intervals and extend in the first direction X. The horizontal portion BMX overlaps the scanning line G, the switching element SW, and the wiring portion such as the S / D layer RE when viewed in plan. In the illustrated example, the horizontal portion BMX1 overlaps the scanning line G1 and the second spacer DC1. The lateral portion BMX2 overlaps the scanning line G2 and the second spacer DC2. The lateral portion BMX3 overlaps the scanning line G3 and the second spacer DC3. The lateral portion BMX is formed in a band shape having a substantially constant width in the second direction Y.

  The longitudinal portion BMY and the lateral portion BMX intersect in plan view. In the illustrated example, the longitudinal portion BMY and the lateral portion BMX intersect in a cross shape in plan view. An opening OP (OP1, OP2, OP3, OP4, OP5, OP6,...) Is formed by the vertical portion BMY and the horizontal portion BMX. The openings OP are arranged in a matrix on the X-Y plane. The opening OP is an area that contributes to display. In the illustrated example, the openings OP1 to OP6 are formed to have substantially the same size. That is, the longitudinal portions BMY and the lateral portions BMX, which define the opening OP, are formed to have a constant width in the direction intersecting with the direction in which each extends. In other words, the intersection of the vertical portion BMY and the horizontal portion BMX and the other portion do not have the portion where the width of the light shielding layer BM is expanded. Therefore, it is not necessary to arrange the light shielding layer BM in consideration of the arrangement of the spacers UC and DC, and the aperture ratio can be improved.

The color filter CF is provided at the opening OP. The color filter CF includes a color filter CF1 of a first color, a color filter CF2 of a second color, and a color filter CF3 of a third color. The first color, the second color, and the third color are different from one another. In one example, the color filter CF1 is a red color filter, the color filter CF2 is a green color filter, and the color filter CF3 is a blue color filter.
In the illustrated example, the color filters CF1, CF2, and CF3 are repeatedly arranged in the first direction X in this order. The color filters CF1, CF2, and CF3 are arranged in the second direction Y, respectively. As an example, the openings OP1 and OP4 include the color filter CF1. The openings OP2 and OP5 have a color filter CF2. The openings OP3 and OP6 have a color filter CF3. The combination of colors of the color filters CF1 to CF3 is not limited to the example described above. Also, the color filter CF may have a white color filter. In this case, in the first direction X, an opening having a white color filter may be added to three openings each having a red color filter, a green color filter, and a blue color filter. A non-colored resin material may be disposed in the opening corresponding to the opening (white pixel) having the white color filter.

  FIG. 5 is a cross-sectional view showing a configuration example of the display device DSP cut along the line A-A shown in FIG. Hereinafter, the direction toward the tip of the arrow indicating the third direction Z is defined as upper, and the reverse direction to the tip of the arrow is defined as lower. In the case of “the second member on the first member” and “the second member below the first member”, the second member may be in contact with the first member, or may be located away from the first member It may be done.

The display device DSP includes a backlight unit BL, a display panel PNL, a cover member CG, and the like.
The display panel PNL is disposed in the order of the first substrate SUB1, the liquid crystal layer LC, and the second substrate SUB2 along the third direction Z. The first substrate SUB1 includes a first insulating substrate 10, a first insulating film 11, a second insulating film 12, a third insulating film 13, a fourth insulating film 14, a fifth insulating film 15, a signal line S, a scanning line G, The common electrode CE, the first spacers UC (UC1 and UC2), and the first alignment film AL1 are provided. For example, the first insulating film 11, the second insulating film 12, the third insulating film 13, and the fifth insulating film 15 are inorganic insulating films such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the fourth insulating film 14 is an organic insulating film such as an acrylic resin. The first insulating film 11, the second insulating film 12, the third insulating film 13, and the fifth insulating film 15 may have a single layer structure or a multilayer structure.

The first insulating substrate 10 is a substrate having light transparency. As an example, the first insulating substrate 10 is a flexible substrate having flexibility. For example, the first insulating substrate 10 is a resin substrate such as polyimide. The first insulating film 11 is located on the first insulating substrate 10.
The semiconductor layer SC is located on the first insulating film 11 and covered with the second insulating film 12. In the illustrated example, the semiconductor layers SC1, SC2, SC3, and SC4 are arranged in the first direction X on the first insulating film 11 at an interval. The second insulating film 12 is located on the first insulating film 11. The scanning line G is located on the second insulating film 12. In the illustrated example, the scanning line G <b> 1 extends in the first direction X along the second insulating film 12 on the second insulating film 12. The third insulating film 13 is located on the scanning line G.
The signal line S is located on the third insulating film 13 and covered by the fourth insulating film 14. In the illustrated example, the signal lines S1, S2, S3, and S4 are arranged in the first direction X on the third insulating film 13 at an interval. The signal line S1 is located immediately above the semiconductor layer SC1. The signal line S2 is located immediately above the semiconductor layer SC2. The signal line S3 is located immediately above the semiconductor layer SC3. The signal line S4 is located immediately above the semiconductor layer SC4.

The common electrode CE is located on the fourth insulating film 14. The common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The fifth insulating film 15 is located on the common electrode CE.
The first spacer UC is located on the fifth insulating film 15. The first spacer UC has a tapered shape protruding toward the second substrate SUB2. In the illustrated example, the first spacers UC1 and UC2 are arranged on the fifth insulating film 15 at an interval of one main pixel. The first spacer UC1 is located immediately above the signal line S1. The first spacer UC2 is located immediately above the signal line S4. The first spacer UC1 has a tapered shape that tapers toward the tip surface UT1 facing the second substrate SUB2. The first spacer UC2 has a tapered shape that tapers toward a tip surface UT2 facing the second substrate SUB2. The first alignment film AL1 is located on part of the fifth insulating film 15 and the first spacer UC. In the illustrated example, the first alignment film AL1 is located on the tapered portion of the fifth insulating film 15 and the first spacer UC.

The second substrate SUB2 includes a second insulating substrate 20, a light shielding layer BM, a color filter CF, an overcoat layer OC, a second spacer DC (DC1), and the like. In the illustrated example, the second substrate SUB2 is located on the first substrate SUB1 and faces the first substrate SUB1.
The second insulating substrate 20 is a substrate having light transparency. As an example, the second insulating substrate 20 is a flexible substrate having flexibility. For example, the second insulating substrate 20 is a resin substrate such as polyimide.
The light shielding layer BM is located below the second insulating substrate 20. The color filter CF is located below the light shielding layer BM. In the illustrated example, the color filters CF1, CF2, and CF3 are sequentially arranged in the first direction X between the first spacer UC1 and the first spacer UC2. The overcoat layer OC is located below the color filter CF. The color filter CF may be located on the light shielding layer BM.

The second spacer DC is located below the overcoat layer OC. The second spacer DC extends in the first direction X along the overcoat layer OC. A portion of the second spacer DC faces the first spacer UC. For example, the second spacer DC is in contact with the first spacer UC at a position corresponding to the intersection XP. The second spacer DC may be in contact with the first spacer UC except at the intersection XP. The thickness in the third direction Z of the second spacer DC is constant in the first direction X. The thickness in the third direction Z of the second spacer DC may be the same as the thickness in the third direction Z of the first spacer UC. In the illustrated example, in the second spacer DC1, the partial spacer DC11 and the partial spacer DC12 are separated in the first direction X with the gap GP1 under the overcoat layer OC. Thus, the fluidity of the liquid crystal molecules of the liquid crystal layer LC is enhanced by separating the partial spacer DC11 and the partial spacer DC12 with the gap GP1 therebetween. The partial spacer DC11 faces the first spacer UC1. The end surface DT1 of the partial spacer DC11 facing the first substrate SUB1 is in contact with the end surface UT1 of the first spacer UC1 at a position corresponding to the intersection XP1. The partial spacer DC12 faces the first spacer UC2. The end surface DT2 of the partial spacer DC12 facing the first substrate SUB1 is in contact with the end surface UT2 of the first spacer UC2 at a position corresponding to the intersection XP4. The second alignment film AL2 is located below the overcoat layer OC.
A predetermined cell gap is formed between the first alignment film AL1 and the second alignment film AL2. The cell gap is, for example, 2 to 5 μm. The first substrate SUB1 and the second substrate SUB2 are bonded together by the above-described seal material in a state in which a predetermined cell gap is formed.

  The liquid crystal layer LC is held in a cell gap formed between the first substrate SUB1 and the second substrate SUB2. In the illustrated example, the liquid crystal layer LC is held between the first alignment film AL1 and the second alignment film AL2. The liquid crystal layer LC contains liquid crystal molecules. Such a liquid crystal layer LC is made of a positive type (positive dielectric anisotropy is positive) liquid crystal material or a negative type (negative dielectric anisotropy is negative) liquid crystal material.

  In the display panel PNL configured as described above, the first optical element OD1 including the first polarizing plate PL1 is disposed below the first substrate SUB1. Further, on the second substrate SUB2, a second optical element OD2 including the second polarizing plate PL2 is disposed. In the illustrated example, the first optical element OD1 is disposed below the first insulating substrate 10, and the second optical element OD2 is disposed on the second insulating substrate 20. In one example, the first polarizing plate PL1 and the second polarizing plate PL2 are arranged such that their absorption axes are orthogonal to each other in the X-Y plane. The first optical element OD1 and the second optical element OD2 may be provided with a retardation plate such as a quarter wavelength plate or a half wavelength plate, a scattering layer, an antireflection layer, etc., as necessary. .

  The cover member CG is located on the second substrate SUB2. The cover member CG is made of, for example, glass, but may be made of resin. The cover member CG is bonded to the second substrate SUB2 with an adhesive AD. In the illustrated example, the cover member CG is adhered with an adhesive AD on the second optical element OD2. In addition to the adhesive AD, several layers may be disposed between the cover member CG and the second optical element OD2.

FIG. 6 is a cross-sectional view showing a configuration example of the display device DSP cut along the line B-B shown in FIG.
The first substrate SUB1 includes a light shielding layer LS. The light shielding layer LS is located between the first insulating substrate 10 and the first insulating film 11. The light shielding layer LS is made of molybdenum tungsten alloy in one example. The signal line S is electrically connected to the switching element SW (semiconductor layer SC) through a contact hole CH3 penetrating the second insulating film 12 and the third insulating film 13. In the illustrated example, the signal line S1 is electrically connected to the switching element SW1 (semiconductor layer SC1) through the contact hole CH31 penetrating the second insulating film 12 and the third insulating film 13. The gate electrode WG1, which is a part of the scanning line G1, is located between the second insulating film 12 and the third insulating film 13, and is opposed to the light shielding layer LS via the semiconductor layer SC1. The first spacer UC extends along the fifth insulating film 15. The thickness in the third direction Z of the first spacer UC is constant along the extending direction. In the illustrated example, the first spacer UC <b> 1 extends along the fifth insulating film 15. The thickness in the third direction Z of the first spacer UC1 is constant along the extending direction.

  In the second substrate SUB2, the second spacer DC has a tapered shape projecting toward the first substrate. In the illustrated example, the second spacer DC1 is located immediately above the scanning line G1. The second spacer DC1 has a tapered shape that tapers toward the tip surface DT1. The second alignment film AL2 is also located below a portion of the second spacer DC. In the illustrated example, the second alignment film AL2 is also located below the tapered portion of the second spacer DC1.

FIG. 7 is a perspective view showing a configuration example of the display device DSP.
In the illustrated example, the cover member CG is substantially flat between a curved portion CP (CP1 and CP2) curved in the third direction Z at both ends in the first direction X and the two curved portions CP. And a flat portion FP. The curved portion CP (CP1, CP2) is formed by the bus bar GL extending in the second direction Y. The cover member CG may have a configuration in which the region between the two curved portions CP is curved in the first direction X. In addition, the cover member CG may have a flat configuration without the curved portion CP in the first direction X. The cover member CG may be configured to include two curved portions curved at both ends in the second direction Y. In this case, the curved portions curved at both ends in the second direction Y are formed by the generatrix GL extending in the first direction X. In the cover member CG, the display panel PNL is attached to the lower side in the third direction Z.

FIG. 8 is a cross-sectional view showing a configuration example of the display device DSP cut along the line C-C shown in FIG.
The display panel PNL is bonded to the lower surface CB of the cover member CG. In the illustrated example, the upper surface PU of the display panel PNL is bonded to the lower surface CB of the cover member CG. The upper surface PU of the display panel PBL corresponds to the upper surface of the second substrate SUB2. The display panel PNL has a first area AR1 facing the flat portion FP and a second area AR2 facing the curved portion CP (CP1, CP2). For example, the first region AR1 is flat along the flat portion FP. The second region AR2 is curved along the curved portion CP. Further, in the illustrated example, the curved portion CP (CP1, CP2) of the cover member CG is curved toward the first substrate with respect to the flat portion FP.

For example, in the case where the display panel PNL is attached to the cover member CG at the time of manufacturing the display device DSP, or in the case of normal use, a stress is generated in the first substrate SUB1 extending outward in the first direction X, and the second substrate SUB2 In the first direction X, a stress may be generated that shrinks inward. The magnitude of the stress applied to the display panel PNL is larger in the stress generated in the second area AR2 than in the first area AR1. For example, in order to facilitate bending of the display panel PNL, the gap GP1 formed in the second spacer DC is located at least in the second region AR2. For example, the gap GP1 between the partial spacer DC11 and the partial spacer DC12 shown in FIG. 3 is located in the second region AR2. That is, the partial spacer DC11 and the partial spacer DC12 are separated in the second region AR2 with a gap GP1. Similarly, the partial spacers DC21 and DC31 and the partial spacers DC22 and DC32 shown in FIG. 3 are separated in the second region AR2 by leaving a gap GP1. The gap GP1 formed in the second spacer DC may be located at the boundary between the first area AR1 and the second area AR2. Further, when the display device 2 is curved in the first direction X as in the example illustrated in FIG. 7, the spacers extending in the first direction X are formed longer than the spacers extending in the second direction Y. It may be done. For example, in the example shown in FIG. 7, the second spacer DC shown in FIG. 3 may be formed longer than the first spacer UC shown in FIG.
In the case where the display panel PNL includes the curved portion that is curved in the second direction Y, the first spacer UC may be formed in the curved region, that is, the region including the curved portion in order to make the display panel PNL easy to bend. Gap (space) is located.

  According to the present embodiment, the display device DSP includes the display panel PNL configured by bonding the first substrate SUB1 and the second substrate SUB2 with the sealing material SL. The first substrate SUB1 includes a first spacer UC projecting toward the second substrate SUB2 side. The second substrate SUB2 is provided with a second spacer DC that faces the first spacer UC and protrudes toward the first substrate SUB1. The first spacer UC extends in the second direction Y, and the second spacer DC extends in the first direction X. In addition, the first spacer UC and the second spacer DC intersect. The second spacer DC has a gap GP1 smaller than the width W1 of the first spacer UC in the first direction X. Therefore, the display device DSP prevents the second spacer DC from dropping off from the first spacer UC and damaging the first alignment film AL1 due to positional deviation between the first substrate SUB1 and the second substrate SUB2, etc. it can. In addition, the display device DSP can support the entire of the first substrate SUB1 and the second substrate SUB2 with the first spacer UC and the second spacer DC. That is, the display device DSP can suppress the light leakage due to the alignment failure due to the damage of the alignment film, and can prevent the decrease of the contrast ratio. Therefore, a display device capable of improving the display quality can be provided.

  Next, display devices according to modifications and other embodiments will be described. In the modification and other embodiments described below, the same reference numerals are given to the same parts as the first embodiment described above, and the detailed description thereof is omitted or simplified, and parts different from the first embodiment. The details will be described focusing on the

FIG. 9 is a plan view showing a configuration example of the first spacer UC and the second spacer DC according to the first modification. Here, the main part of the first substrate SUB1 shown in FIG. 2 is indicated by a dotted line.
The display device DSP according to the first modification is different from the display device DSP shown in FIG. 3 in that the second spacer DC does not have the gap GP1.

  In the illustrated example, the first spacer UC101 is superimposed on the signal line S101 and extends in the second direction Y along the signal line S101. The first spacer UC102 is superimposed on the signal line S104, and extends in the second direction Y along the signal line S104. The first spacer UC101 and the first spacer UC102 are spaced apart by a distance of one main pixel in the first direction X. The first spacers UC101 and UC102 are formed to have a width W1 in the first direction X.

The second spacer DC does not have the gap GP1. In the illustrated example, the second spacers DC1, DC2, DC3 and the first spacers UC101, UC102 respectively cross in a cross shape. The second spacers DC1, DC2, DC3 and the first spacers UC101, UC102 may intersect in a T-shape or a Y-shape. The second spacer DC1 overlaps the scanning line G1 and extends in the first direction X along the scanning line G1. The second spacer DC1 intersects the first spacer UC101 at the intersection XP21 and intersects the first spacer UC102 at the intersection XP24. The second spacers DC1 are arranged in a straight line along the first direction X. The second spacer DC2 overlaps the scanning line G2 and extends in the first direction X along the scanning line G2. The second spacer DC2 intersects the first spacer UC101 at the intersection XP25 and intersects the first spacer UC102 at the intersection XP28. The second spacers DC2 are arranged in a straight line along the first direction X. That is, the first spacers UC101 and UC102 and the second spacers DC1 and DC2 are arranged to surround the main pixel. The second spacer DC3 overlaps the scanning line G1 and extends in the first direction X along the scanning line G1. The second spacer DC3 intersects the first spacer UC101 at the intersection XP29 and intersects the first spacer UC102 at the intersection XP32. That is, the first spacers UC101 and UC102 and the second spacers DC2 and DC3 are disposed so as to surround the main pixel. The second spacers DC3 are arranged in a straight line along the first direction X.
For example, the second spacer DC shown in FIG. 9 is located in the first area AR1 shown in FIGS. 7 and 8. At this time, the second spacer DC shown in FIG. 3 is located in the second area AR2 shown in FIGS. 7 and 8.
According to the first modification, the display device DSP can increase the rigidity of the first region of the display panel PNL facing the flat portion FP of the cover member CG.

FIG. 10 is a plan view showing a configuration example of the first spacer UC and the second spacer DC according to the second modification. Here, the main part of the first substrate SUB1 shown in FIG. 2 is indicated by a dotted line.
The display device DSP according to the second modification is different from the display device DSP shown in FIG. 3 in that the second spacer DC has a plurality of gaps GP1 in the first direction X.

The second spacer DC has a plurality of gaps GP1 in the first direction X. In the illustrated example, the second spacer DC1 includes a partial spacer DC11, a partial spacer DC12, and a partial spacer DC13. The partial spacer DC11 intersects the first spacer UC1 at the intersection XP1. The partial spacer DC12 intersects the first spacer UC2 at the intersection XP4. The partial spacer DC13 is located between the partial spacer DC11 and the partial spacer DC12. The partial spacer DC11, the partial spacer DC12, and the partial spacer DC13 are linearly arranged along the first direction X, and are separated in the first direction X with a gap GP1. As an example, the partial spacer DC11 and the partial spacer DC13 are spaced apart with a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The partial spacer DC13 and the partial spacer DC12 are separated by a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The second spacer DC2 includes a partial spacer DC21, a partial spacer DC22, and a partial spacer DC23. The partial spacer DC21 intersects the first spacer UC1 at the intersection XP5. The partial spacer DC22 intersects the first spacer UC2 at the intersection XP8. That is, the first spacers UC1 and UC2 and the second spacers DC11 to DC13 and DC21 to DC23 are disposed so as to surround the main pixel. The partial spacer DC23 is located between the partial spacer DC21 and the partial spacer DC22. The partial spacer DC21, the partial spacer DC22, and the partial spacer DC23 are linearly arranged along the first direction X, and are separated in the first direction X with a gap GP1. As an example, the partial spacer DC21 and the partial spacer DC23 are spaced apart with a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The partial spacer DC23 and the partial spacer DC22 are separated by a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The second spacer DC3 includes a partial spacer DC31, a partial spacer DC32, and a partial spacer DC33. The partial spacer DC31 intersects the first spacer UC1 at the intersection XP9. The partial spacer DC32 intersects the first spacer UC2 at the intersection XP12. The first spacers UC1 and UC2 and the second spacers DC21 to DC23 and DC31 to DC33 are disposed so as to surround the main pixel. The partial spacer DC33 is located between the partial spacer DC31 and the partial spacer DC32. The partial spacer DC31, the partial spacer DC32, and the partial spacer DC33 are linearly arranged along the first direction X, and are separated in the first direction X with a gap GP1. As an example, the partial spacer DC31 and the partial spacer DC33 are spaced apart with a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2. The partial spacer DC33 and the partial spacer DC32 are separated by a gap GP1 in the first direction X between the first spacer UC1 and the first spacer UC2.
For example, the second spacer DC illustrated in FIG. 10 is located in the second region AR2 illustrated in FIGS. 7 and 8. The second spacer DC shown in FIG. 10 may be located in the first area AR2 shown in FIGS. 7 and 8.
According to the second modification, the same effect as the above embodiment can be obtained. In addition, the display device DSP can enhance the flowability of liquid crystal molecules in the liquid crystal layer LC.

FIG. 11 is a plan view showing a configuration example of the first spacer UC and the second spacer DC according to the third modification. Here, the main part of the first substrate SUB1 shown in FIG. 2 is indicated by a dotted line.
The display device DSP according to the third modification is different from the display device DSP shown in FIG. 3 in that the first spacer UC has a gap GP2.

  The first spacer UC has at least one gap GP2. The gap GP2 is smaller than the width W2 of the second spacer DC in the second direction Y. The gap GP2 may be the same as the gap GP1. In the illustrated example, the first spacer UC1 includes a partial spacer UC11, a partial spacer UC12, and a partial spacer UC13. The partial spacer UC11 intersects the second spacer DC1 at the intersection XP1. The partial spacer UC12 intersects the second spacer DC2 at the intersection XP5. The partial spacer UC13 intersects the second spacer DC3 at the intersection XP9. The partial spacer UC11, the partial spacer UC12, and the partial spacer UC13 are disposed along the second direction Y, and are separated in the second direction X by leaving a gap (interval) GP2. As an example, the partial spacer UC11 and the partial spacer UC12 are separated by a gap GP2 in the second direction X between the second spacer DC1 and the second spacer DC2. The partial spacer UC12 and the partial spacer UC13 are separated by a gap GP2 in the second direction X between the second spacer DC2 and the second spacer DC3. The first spacer UC1 may have a plurality of gaps GP2 between the second spacer DC1 and the second spacer DC2. Similarly, the first spacer UC1 may have a plurality of gaps GP2 between the second spacer DC2 and the second spacer DC3.

  The first spacer UC2 includes a partial spacer UC21, a partial spacer UC22, and a partial spacer UC23. The partial spacer UC21 intersects the second spacer DC1 at the intersection XP4. The partial spacer UC22 intersects the second spacer DC2 at the intersection XP8. The partial spacer UC23 intersects the second spacer DC3 at the intersection XP12. The partial spacer UC21, the partial spacer UC22, and the partial spacer UC23 are disposed along the second direction Y, and are separated in the second direction X with a gap GP2. As an example, the partial spacer UC21 and the partial spacer UC22 are separated by a gap GP2 in the second direction X between the second spacer DC1 and the second spacer DC2. The partial spacer UC22 and the partial spacer UC23 are separated by a gap GP2 in the second direction X between the second spacer DC2 and the second spacer DC3. The first spacer UC2 may have a plurality of gaps GP2 between the second spacer DC1 and the second spacer DC2. Similarly, the first spacer UC2 may have a plurality of gaps GP2 between the second spacer DC2 and the second spacer DC3. In addition, in the case where the cover member CG includes two curved portions that are curved at both ends in the second direction Y, the display panel PNL may include the first spacer UC in the region including the curved portion to facilitate bending. Gap (interval) GP2 is located.

The second spacer DC does not have the gap GP1. In the illustrated example, the second spacer DC1 is disposed linearly along the first direction X, and has no gap in the first direction X. The second spacers DC2 are arranged in a straight line along the first direction X. The second spacers DC3 are arranged in a straight line along the first direction X.
According to the third modification, the display device DSP can be easily bent in the second direction Y when it is bent in the second direction Y. In addition, the display device DSP can enhance the flowability of liquid crystal molecules in the liquid crystal layer LC.

FIG. 12 is a plan view showing a configuration example of the first spacer UC and the second spacer DC according to the fourth modification. Here, the main part of the first substrate SUB1 shown in FIG. 2 is indicated by a dotted line.
The display device DSP according to the fourth modification is different from the display device DSP shown in FIG. 3 in that the second spacer has a gap GP1 and the first spacer UC has a gap GP2.
The second spacer DC has at least one gap GP1. The first spacer UC has at least one gap GP2.

According to the fourth modification, the same effect as the above embodiment can be obtained. In addition, the display device DSP can be easily bent in the second direction Y when it is bent in the second direction Y. In addition, the display device DSP can enhance the flowability of liquid crystal molecules in the liquid crystal layer LC.
While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DSP: Display device PNL: Display panel SUB1: First substrate SUB2: Second substrate BL: Lighting device DA: Display area NDA: Non-display area G: Scanning line S: Signal line SW: Switching element PE: Pixel electrode CE: Common Electrode BM: Light shielding layer CF: Color filter UC: First spacer DC: Second spacer.

Claims (11)

A scanning line extending in a first direction, a signal line extending in a second direction intersecting the first direction, and a first protrusion overlapping the signal line and extending along the signal line; A first substrate having
And a second substrate facing the first substrate and having a second protrusion extending along the scanning line at a position overlapping the scanning line.
A first intersection where the scanning line and the signal line intersect;
The display device, wherein the first protrusion and the second protrusion are in contact at the first intersection. The first protrusion has a first width in the first direction,
The second protrusion has a first portion and a second portion separated from each other at a first distance,
The display device according to claim 1, wherein the first interval is smaller than the first width. The second protrusion has a second width in the second direction,
The first protrusion has a third portion and a fourth portion separated from each other at a second distance,
The display device according to claim 2, wherein the second interval is smaller than the second width.   The display device according to claim 3, wherein the first width and the second width are the same width. The second protrusion has a second width in the second direction,
The first protrusion has a third portion and a fourth portion separated from each other at a second distance,
The display device according to claim 1, wherein the second interval is smaller than the second width. The signal lines include first to fourth signal lines arranged in parallel in the first direction,
The display device according to any one of claims 1 to 5, wherein the first protrusion is disposed so as to overlap the first signal line and the fourth signal line.   The display device according to any one of claims 1 to 6, wherein the second protrusion is disposed for each of the scanning lines. And a cover member adhered to the second substrate,
The cover member has a flat portion and a curved portion which is curved toward the first substrate with respect to the flat portion.
The first portion is located on the flat portion,
The display device according to claim 2, wherein the second portion is located at the curved portion.   The display device according to claim 8, wherein the first distance is located at the curved portion. And a cover member adhered to the second substrate,
The cover member has a flat portion and a curved portion which is curved toward the first substrate with respect to the flat portion.
The third portion is located on the flat portion,
The display device according to claim 3, wherein the fourth portion is located at the curved portion.   The display device according to claim 10, wherein the second distance is located at the curved portion.

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