JP2019041034A - Semiconductor device for electric power and manufacturing method therefor - Google Patents

Abstract

To suppress deterioration in a junction for joining an external connection terminal to a circuit pattern under a high-temperature environment.SOLUTION: A semiconductor device 100 for electric power includes an insulation substrate 9 and an external connection terminal 4. on a principal plane 9a side of the insulation substrate 9, a circuit pattern 7 is formed. The external connection terminal 4 is brazed to the circuit pattern 7 through a brazing material 5.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power semiconductor device including an external connection terminal and a manufacturing method thereof.

  In a conventional power semiconductor device, when joining an external connection terminal to a circuit pattern provided on an insulating substrate, solder joining has been used as in Patent Document 1.

  Patent Document 1 discloses a configuration (hereinafter also referred to as “related configuration A”) that increases the reliability of a solder portion (joint portion) that connects a terminal (external connection terminal) and a circuit on an insulating substrate (ceramic substrate). Is disclosed. Specifically, in Related Configuration A, the thickness of the portion of the terminal bonded to the circuit pattern on the insulating substrate is made thinner than the thickness of the other portion. Moreover, the part joined to the circuit pattern on an insulating board among terminals is divided | segmented by the slit. Thereby, the stress concerning a solder part (joining part) is reduced. As a result, a highly reliable joint can be obtained.

  Moreover, in order to join an external connection terminal to a terminal block formed in a circuit pattern on an insulating substrate, ultrasonic bonding may be used as in Patent Document 2.

  Patent Document 2 discloses a configuration (hereinafter also referred to as “related configuration B”) in which electrode terminals (external connection terminals) are bonded to a terminal block formed on an insulating substrate by ultrasonic bonding. Patent Document 2 shows a result of comparison between solder bonding using Pb-based solder and ultrasonic bonding in a temperature cycle test. Patent Document 2 states that ultrasonic bonding can provide a more reliable bonded portion than solder bonding.

JP 2006-253516 A Japanese Patent No. 3524360

  The power semiconductor device needs to operate normally even in a high temperature environment of about 200 to 300 degrees. When solder joints are used to join the external connection terminals to the circuit pattern provided on the insulating substrate, there is a problem that the joints made of solder are likely to deteriorate under the high temperature environment. .

  In addition, when ultrasonic bonding is used to bond the external connection terminal to the circuit pattern, ultrasonic vibration is applied to the external connection terminal in a state where force is applied to the external connection terminal. In this case, depending on the magnitude of the force, there is a problem that a member or the like existing below the external connection terminal may be damaged. Therefore, the use of ultrasonic bonding is not desirable.

  Therefore, it is required to suppress the occurrence of deterioration of the joint portion for joining the external connection terminal to the circuit pattern in a high temperature environment. The related configurations A and B cannot satisfy such a requirement.

  The present invention has been made to solve such a problem, and for electric power capable of suppressing the occurrence of deterioration of a joint portion for joining an external connection terminal to a circuit pattern in a high temperature environment. An object is to provide a semiconductor device or the like.

  In order to achieve the above object, a power semiconductor device according to an aspect of the present invention includes an insulating substrate and an external connection terminal, and a circuit pattern is provided on a main surface side of the insulating substrate. The external connection terminals are brazed to the circuit pattern via a hard brazing material.

  According to the present invention, the external connection terminal is brazed to the circuit pattern via a hard brazing material. The hard brazing material is a brazing material having a melting point of 450 degrees or more. That is, the melting point of the brazing filler metal is higher than the melting point of the solder. Therefore, the hard brazing material, which is a joint for joining the external connection terminals to the circuit pattern, is less likely to be degraded than solder in a high temperature environment. Therefore, it is possible to suppress the deterioration of the joint portion in a high temperature environment.

1 is a cross-sectional view of a power semiconductor device according to a first embodiment of the present invention. It is a flowchart of the semiconductor manufacturing method Pr which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the semiconductor manufacturing method Pr which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the semiconductor manufacturing method Pr which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the transfer of the heat by irradiation of the laser beam in the structure which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the external connection terminal in the structure which concerns on the modification 1 of this invention. In the structure which concerns on the modification 2 of this invention, it is sectional drawing of the edge part vicinity of an external connection terminal which exists above a circuit pattern. It is a flowchart of semiconductor manufacturing method Pra concerning the modification 2 of this invention. It is a figure for demonstrating the semiconductor manufacturing method Pra which concerns on the modification 2 of this invention. It is a figure for demonstrating the semiconductor manufacturing method Pra which concerns on the modification 2 of this invention. It is a figure for demonstrating the semiconductor manufacturing method Pra which concerns on the modification 2 of this invention. In the structure which concerns on the modification 3 of this invention, it is sectional drawing of the edge part vicinity of an external connection terminal which exists above a circuit pattern. It is a figure for demonstrating the structure which concerns on the modification 4 of this invention. It is a flowchart of semiconductor manufacturing method Prb which concerns on the modification 4 of this invention. It is a figure for demonstrating the external connection terminal in the structure which concerns on the modification 5 of this invention. It is a flowchart of semiconductor manufacturing method Prc which concerns on the modification 5 of this invention. It is a figure which shows the structure of the through-hole provided in an external connection terminal. It is sectional drawing of the power semiconductor device which has a structure concerning the modification 6 of this invention. It is a perspective view of the external connection terminal which has a structure concerning the modification 7 of this invention. It is a perspective view of the external connection terminal used as a comparison object. It is a figure for demonstrating the semiconductor manufacturing method Prd which concerns on the modification 8 of this invention. It is a figure for demonstrating the semiconductor manufacturing method Prd which concerns on the modification 8 of this invention. It is a flowchart of semiconductor manufacturing method Prd which concerns on the modification 8 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same components are denoted by the same reference numerals. The names and functions of the components having the same reference numerals are the same. Therefore, a detailed description of some of the components having the same reference numerals may be omitted.

  Note that the dimensions, materials, shapes, and relative arrangements of the components exemplified in the embodiments may be appropriately changed depending on the configuration of the apparatus to which the present invention is applied, various conditions, and the like.

<Embodiment 1>
FIG. 1 is a sectional view of a power semiconductor device 100 according to the first embodiment of the present invention. The power semiconductor device 100 is, for example, a power module for home appliances, industrial use, and train use. In FIG. 1, components other than the main components in the power semiconductor device 100 are not shown for easy understanding of the configuration. For example, FIG. 1 does not show a sealing material such as a gel.

  In FIG. 1, the X direction, the Y direction, and the Z direction are orthogonal to each other. The X direction, Y direction, and Z direction shown in the following figures are also orthogonal to each other. Hereinafter, a direction including the X direction and the direction opposite to the X direction (−X direction) is also referred to as “X axis direction”. In the following, the direction including the Y direction and the direction opposite to the Y direction (−Y direction) is also referred to as “Y-axis direction”. Hereinafter, a direction including the Z direction and a direction opposite to the Z direction (−Z direction) is also referred to as a “Z-axis direction”.

  Hereinafter, a plane including the X-axis direction and the Y-axis direction is also referred to as an “XY plane”. Hereinafter, a plane including the X-axis direction and the Z-axis direction is also referred to as an “XZ plane”. Hereinafter, a plane including the Y-axis direction and the Z-axis direction is also referred to as a “YZ plane”.

  Referring to FIG. 1, a power semiconductor device 100 includes a power semiconductor element S <b> 1, two external connection terminals 4, a connection wiring 3, a base plate 11, an insulating substrate 9, and a case 12. . The insulating substrate 9 is bonded to the base plate 11 via the bonding material 10. The bonding material 10 is solder. The insulating substrate 9 has a main surface 9a. The main surface 9a is a surface on which the power semiconductor element S1 is mounted.

  The insulating substrate 9 includes a ceramic substrate 8 and circuit patterns 7a, 7b, 7c. The ceramic substrate 8 has a front surface 8a and a back surface 8b. Circuit patterns 7 a and 7 b are provided on the surface 8 a of the ceramic substrate 8. The circuit patterns 7a and 7b are bonded to the surface 8a of the ceramic substrate 8 through an active metal brazing material.

  The surface 8 a of the ceramic substrate 8 corresponds to the main surface 9 a side of the insulating substrate 9. That is, circuit patterns 7 a and 7 b are provided on the main surface 9 a side of the insulating substrate 9. A circuit pattern 7 c is provided on the back surface 8 b of the ceramic substrate 8. The circuit pattern 7c is bonded to the back surface 8b of the ceramic substrate 8 through an active metal brazing material.

  Each of the circuit patterns 7a, 7b, 7c is made of copper. Specifically, each of the circuit patterns 7a, 7b, and 7c is made of, for example, C1020 (oxygen-free copper). The melting point of C1020 is 1083 degrees.

  A power semiconductor element S <b> 1 is provided on the circuit pattern 7 a via the bonding material 2. That is, the power semiconductor element S1 is mounted on the circuit pattern 7a. The bonding material 2 is a sintered bonding material containing Ag nanoparticles, Cu nanoparticles, and the like. The power semiconductor element S1 is made of, for example, SiC (silicon carbide). The power semiconductor element S1 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an SBD (Schottky barrier diode), or the like.

  A surface electrode (not shown) on the power semiconductor element S <b> 1 is electrically connected to the circuit pattern 7 b through the connection wiring 3. The connection wiring 3 is a wire made of aluminum, copper or the like. The connection wiring 3 is bonded to the surface electrode on the power semiconductor element S1 and the circuit pattern 7b by ultrasonic bonding. Hereinafter, each of the circuit patterns 7a and 7b is also referred to as “circuit pattern 7”.

  A cylindrical case 12 is joined to the base plate 11 via an adhesive 13. The adhesive 13 is made of a silicone material. The case 12 is filled with a sealing material (not shown).

  The external connection terminal 4 is a terminal for electrically connecting the power semiconductor device 100 and a device outside the power semiconductor device 100. Each external connection terminal 4 is connected to the case 12 and the circuit pattern 7. Each external connection terminal 4 is made of copper. Specifically, each external connection terminal 4 is made of C1020 (oxygen-free copper), for example.

  Each external connection terminal 4 has end portions 4a and 4b. The end 4 a is one end of the external connection terminal 4. The end 4 b is the other end of the external connection terminal 4. The end 4b is provided with a through hole h4. The through hole h4 functions as a screw fastening portion for joining the end portion 4b to the case 12 with a screw. The end 4b is joined to the case 12 by a screw (not shown) and a through hole h4.

  The end 4 a is joined to the circuit pattern 7 via the hard brazing material 5. The hard brazing material 5 is a brazing material having a melting point of 450 degrees or more. In the present embodiment, the melting point of the brazing filler metal 5 is, for example, a temperature in the range of about 700 degrees to 800 degrees. Hereinafter, the melting point of the brazing filler metal 5 is also referred to as a “hard brazing melting point”. The brazing filler metal 5 is phosphor copper brazing. The melting point (hard solder melting point) of the phosphor copper brazing is lower than the melting point of the above active metal brazing material. The brazing filler metal 5 may be a material other than phosphor copper brazing having the same characteristics as phosphor copper brazing. The brazing filler metal 5 may be, for example, brass brazing, phosphor bronze brazing, copper brazing, silver brazing, gold brazing, aluminum brazing, nickel brazing, or the like.

  The end 4a has surfaces 4a1 and 4a2. The surface 4 a 2 is a joint surface joined to the circuit pattern 7 via the hard brazing material 5.

  Each external connection terminal 4 is brazed to the circuit pattern 7 via a hard brazing material 5. Specifically, the end 4 a of one of the two external connection terminals 4 is brazed to the circuit pattern 7 a via a hard brazing material 5. Of the two external connection terminals 4, the end 4 a of the other external connection terminal 4 is brazed to the circuit pattern 7 b via a hard brazing material 5.

  Next, the semiconductor manufacturing method Pr in the present embodiment will be described. The semiconductor manufacturing method Pr is a method for manufacturing the power semiconductor device 100. FIG. 2 is a flowchart of the semiconductor manufacturing method Pr according to the first embodiment of the present invention. Note that FIG. 2 shows only the characteristic steps included in the semiconductor manufacturing method Pr.

  In the semiconductor manufacturing method Pr, first, the power semiconductor element S <b> 1 is mounted on the insulating substrate 9. Specifically, as illustrated in FIG. 3A, the power semiconductor element S <b> 1 is bonded to the circuit pattern 7 a via the bonding material 2. Heat generated by driving the power semiconductor element S1 is easily transferred to the bonding material 2 existing below the power semiconductor element S1. Sn-based solder is liable to deteriorate due to heat, such as vertical cracks and horizontal cracks. Therefore, the bonding material 2 is a sintered bonding material having excellent heat resistance, including Ag nanoparticles, Cu nanoparticles, and the like.

  For example, the sintering temperature of the sintered bonding material containing Ag nanoparticles is about 250 degrees. Further, the melting point of the Ag joint after sintering is about 960 degrees (the melting point of Ag). That is, the sintered bonding material containing Ag nanoparticles is a high heat-resistant die bond material.

  Next, as illustrated in FIG. 3B, the insulating substrate 9 on which the power semiconductor element S <b> 1 is mounted is bonded to the base plate 11 via the bonding material 10. That is, the insulating substrate 9 is soldered to the base plate 11. Next, the connection wiring 3 is bonded to the surface electrode (not shown) on the power semiconductor element S1 and the circuit pattern 7b by ultrasonic bonding.

  Next, as shown in FIG. 4, the cylindrical case 12 to which the end 4 b of the external connection terminal 4 is joined is joined to the base plate 11 via the adhesive 13. The case 12 is made by insert molding. Hereinafter, a state in which the brazing filler metal 5 is sandwiched between the external connection terminal 4 (the surface 4a2 of the end 4a) and the circuit pattern 7 is also referred to as a “squeezed state”.

  Next, a brazing process is performed (step S110). The brazing step is a step of brazing the external connection terminals 4 to the circuit pattern 7 through the hard brazing material 5 in the sandwiched state.

  Specifically, in the brazing process, a pinching process is first performed. In the pinching process, the hard brazing material 5 is pinched by the external connection terminals 4 (end portions 4a) and the circuit pattern 7, as shown in FIG. Next, in the brazing process, an irradiation process Ia is performed. Although the irradiation process Ia will be described in detail later, the irradiation process Ia is a process of irradiating a part of the external connection terminal 4 with laser light so that the hard brazing material 5 is melted by the heat generated in the external connection terminal 4.

  In the irradiation process Ia, laser light is irradiated by the laser 18 and the galvano scanner system 14. The laser 18 is, for example, a fiber laser using an optical fiber.

  The galvano scanner system 14 is a system capable of performing high-speed laser beam irradiation and high-precision laser beam irradiation. The galvano scanner system 14 has a function of adjusting the irradiation position and irradiation shape of the laser beam. For example, the galvano scanner system 14 has a function of adjusting the irradiation position of the laser light without moving the XY axes of the laser light on the stage.

  Specifically, in the irradiation process Ia, laser light oscillated from the laser 18 is transmitted to the galvano scanner system 14. The galvano scanner system 14 irradiates the surface 4a1 of the end 4a of the external connection terminal 4 with the laser light so that the brazing filler metal 5 is melted.

  By irradiating the surface 4a1 of the end 4a of the external connection terminal 4 with laser light, heat (hereinafter also referred to as “heat Ht”) is generated in the end 4a. With the heat Ht, the brazing filler metal 5 in contact with the surface 4a2 of the end 4a is heated to the melting point of the brazing filler metal or higher. Thereby, the brazing filler metal 5 is melted, and then the molten brazing filler metal 5 is solidified. As a result, the end 4 a of the external connection terminal 4 is brazed to the circuit pattern 7 via the hard brazing material 5.

  In the irradiation process Ia, the galvano scanner system 14 irradiates laser light in the order of the upper end 4a of the circuit pattern 7a and the upper end 4a of the circuit pattern 7b. Thereby, the end 4a of one external connection terminal 4 is brazed to the circuit pattern 7a, and the end 4a of the other external connection terminal 4 is brazed to the circuit pattern 7b.

  Note that the laser beam may be emitted in the order of the upper end 4a of the circuit pattern 7b and the upper end 4a of the circuit pattern 7a.

  As described above, according to the present embodiment, the external connection terminal 4 is brazed to the circuit pattern 7 via the hard brazing material 5. The brazing filler metal 5 is a brazing filler metal having a melting point of 450 degrees or more. That is, the melting point of the brazing filler metal 5 is higher than the melting point of the solder. Therefore, the hard brazing material 5 which is a joint for joining the external connection terminal 4 to the circuit pattern 7 is less likely to be deteriorated than solder in a high temperature environment. Therefore, it is possible to suppress the deterioration of the joint (hard soldering material 5) in a high temperature environment. In addition, a joint having high heat resistance can be obtained.

  Further, in the present embodiment, unlike solid-phase ultrasonic bonding such as ultrasonic bonding, brazing is performed by melting and solidifying the hard brazing material. As a result, a stable joint can be formed. As a result, a highly reliable power semiconductor device with little damage to the insulating substrate 9 can be obtained.

  In the present embodiment, the external connection terminal 4 is heated with laser light, and the brazing filler metal 5 is melted with the heat of the heated external connection terminal 4. As a result, the external connection terminals 4 are brazed to the circuit pattern 7 via the hard brazing material 5. That is, the portion to be brazed can be locally heated without heating the entire power semiconductor device 100. Therefore, the external connection terminals 4 can be brazed to the circuit pattern 7 without affecting the solder, the case, etc. existing below the insulating substrate 9. In addition, since it is not necessary to heat the entire power semiconductor device 100, a large atmosphere furnace is unnecessary. Moreover, brazing can be performed in a short time.

  Moreover, in this Embodiment, the circuit pattern 7 and the external connection terminal 4 are comprised with copper (C1020) with high heat conductivity. Therefore, the heat dissipation during driving of the power semiconductor device 100 can be improved. Further, the circuit pattern 7 and the external connection terminal 4 made of copper have a low electrical resistivity. Therefore, even when a large current flows, the heat generation of the copper can be kept low.

  Further, in the present embodiment, a hard brazing material 5 which is a phosphor copper braze is used to braze the external connection terminals 4 to a circuit pattern 7 made of copper. Therefore, since phosphorus contained in the phosphor copper braze plays a role of flux, there is an effect that the flux is unnecessary in the above brazing.

  Further, the melting point of the phosphor copper brazing (hard brazing material 5) is lower than the melting point of the above active metal brazing material. Therefore, brazing can be performed without remelting the active metal brazing material. Moreover, the time required for brazing can be shortened by reducing the melting point of the phosphor copper brazing as much as possible.

  In the present embodiment, the laser 18 used in the irradiation process Ia is a fiber laser. The fiber laser, for example, has better laser light quality and can reduce the spot diameter of the laser light as compared with the YAG laser. Therefore, for example, when the external connection terminal 4 is made of copper having a high reflectance, a part of the laser light is reflected, but the amount of laser light absorbed by the copper is larger than that of the YAG laser. Therefore, there is an effect that the heating efficiency of the external connection terminal 4 is good.

  The laser 18 is not limited to a fiber laser, and may be another type of laser. The laser 18 may be a YAG laser, for example. In order to obtain the same heating efficiency as the fiber laser with the YAG laser, it is necessary to drive the YAG laser with high output.

  In this embodiment, a galvano scanner system 14 that can irradiate laser light at high speed is used. Therefore, brazing can be performed in a short time.

  Note that a power semiconductor device using a wide gap semiconductor element such as a SiC (silicon carbide) element needs to operate normally in a higher temperature environment than a power semiconductor device using Si. Therefore, when a power cycle test, a temperature cycle test, or the like is performed in a configuration using Sn-based solder for bonding between the external connection terminal and the circuit pattern of the insulating substrate, the bonding portion formed of the solder deteriorates. Likely to happen. Therefore, there is a possibility that the reliability of the joint portion is lower than in the past.

  When ultrasonic bonding is used for bonding the external connection terminal and the circuit pattern of the insulating substrate, bonding is performed by applying ultrasonic waves while applying a large pressure to the insulating substrate. Therefore, there is a concern that the ceramic substrate of the insulating substrate is damaged. Further, according to the investigation by the inventors, it is known from the SAT observation result after the temperature cycle test that the junction area decreases as the number of cycles progresses. Therefore, there is a concern in terms of long-term reliability.

  Therefore, the power semiconductor device 100 of the present embodiment has the above configuration. Further, the semiconductor manufacturing method Pr of the present embodiment is performed as described above. Therefore, each of the above problems can be solved by the power semiconductor device 100 and the semiconductor manufacturing method Pr of the present embodiment.

<Modification 1>
Hereinafter, the configuration of the first embodiment is also referred to as “configuration Ct1”. In the following, the configuration of this modification is also referred to as “configuration Ctm1”. In the configuration Ctm1 of the present modification, the end 4a of the external connection terminal 4 has a characteristic shape. The configuration Ctm1 is applied to the configuration Ct1 (Embodiment 1). The power semiconductor device 100 to which the configuration Ctm1 is applied includes an external connection terminal 4C instead of the external connection terminal 4.

  Here, in the configuration Ct1 of the first embodiment, the brazing filler metal 5 as a joint portion after the brazing step (irradiation process Ia) is performed will be described. FIG. 5 is a diagram for explaining heat transfer due to laser light irradiation in the configuration Ct1 according to the first embodiment of the present invention. FIG. 5A is a perspective view of the vicinity of the end 4a of the external connection terminal 4 in the configuration Ct1 according to the first embodiment. FIG. 5B is a cross-sectional view in the vicinity of the end 4a of the external connection terminal 4 existing above the circuit pattern 7a in the configuration Ct1 according to the first embodiment.

  As described above, in the irradiation process Ia, the galvano scanner system 14 irradiates the surface 4a1 of the end 4a of the external connection terminal 4 with laser light. Thereby, after the irradiation process Ia is performed, the cross-sectional shape of the brazing filler metal 5 becomes as shown in FIG.

  The reason why the cross-sectional shape of the brazing filler metal 5 is as shown in FIG. 5B is as follows. The reason Rs is, for example, that only the external connection terminal 4 is heated and heat is not transmitted to the circuit pattern 7 of the insulating substrate 9. The reason Rs is, for example, that only the external connection terminal 4 is heated, and even if heat is transmitted to the circuit pattern 7 of the insulating substrate 9, the heat dissipation of the insulating substrate 9 is high. This is because the location where the melting point of the hard solder is exceeded is local.

  Therefore, the configuration Ctm1 of this modification will be described. FIG. 6 is a diagram for explaining the external connection terminal 4C in the configuration Ctm1 according to the first modification of the present invention. FIG. 6A is a perspective view of the vicinity of the end 4a of the external connection terminal 4C. FIG. 6B is a cross-sectional view of the vicinity of the end 4a of the external connection terminal 4C existing above the circuit pattern 7a.

  With reference to FIG. 6A and FIG. 6B, the external connection terminal 4 </ b> C is different from the external connection terminal 4 in that the external connection terminal 4 </ b> C has a tip portion 4 ax as a protruding portion. Since the other shape and configuration of external connection terminal 4C are the same as those of external connection terminal 4, detailed description will not be repeated.

  The tip portion 4ax is included in the end portion 4a of the external connection terminal 4C. The width of the tip portion 4ax is smaller than the width of the portion other than the tip portion 4ax in the external connection terminal 4C.

  In the brazing process (irradiation process Ia) to which the configuration Ctm1 is applied, the galvano scanner system 14 is in a state where the brazing filler metal 5 is sandwiched between the distal end portion 4ax of the external connection terminal 4 and the circuit pattern 7. Laser light is applied to the surface 4a1 of the tip 4ax so that the material 5 melts. Thereby, the front end 4ax of the external connection terminal 4C is brazed to the circuit pattern 7 via the hard brazing material 5.

  Therefore, in the power semiconductor device 100 to which the configuration Ctm1 is applied, the tip end 4ax of the external connection terminal 4C is brazed to the circuit pattern 7 (7a, 7b) via the hard brazing material 5.

  As described above, according to the present modification, the tip portion 4ax of the external connection terminal 4C is irradiated with laser light, so that the tip portion 4ax is connected to the circuit pattern 7 ( 7a, 7b). Thereby, the cross-sectional shape of the brazing filler metal 5 becomes as shown in FIG. Hereinafter, the part other than the tip part 4ax in the external connection terminal 4C is also referred to as a “non-tip part”.

  In addition, the heat capacity of the tip portion 4ax is small. Therefore, when the tip portion 4ax is irradiated with laser light, the amount of heat at the tip portion 4ax is larger than the amount of heat transmitted to the non-tip portion of the external connection terminal 4C. Therefore, there is an effect that the time for brazing the external connection terminal 4C to the circuit pattern 7 is shorter than the time for brazing the external connection terminal 4 of the configuration Ct1 to the circuit pattern 7. That is, the external connection terminal 4 </ b> C can be brazed to the circuit pattern 7 more efficiently and in a shorter time than the external connection terminal 4.

  Further, the configuration Ctm1 does not require a large pressing force unlike the ultrasonic bonding.

  In addition, there is a concern that the ceramic substrate 8 of the insulating substrate 9 may be damaged by the heating due to the laser light irradiation. Accordingly, the inventors observed the cross-sectional state of the ceramic substrate 8 after brazing, and confirmed that the ceramic substrate 8 did not have cracks, cracks, or the like.

<Modification 2>
In the following, the configuration of this modification is also referred to as “configuration Ctm2”. The configuration Ctm2 has a feature in the method for manufacturing the power semiconductor device 100. The configuration Ctm2 is applied to the configuration Ct1 (Embodiment 1). Hereinafter, the method for manufacturing the power semiconductor device 100 in the configuration Ctm2 is also referred to as “semiconductor manufacturing method Pra”. The processing of the semiconductor manufacturing method Pra will be described later.

  By performing the semiconductor manufacturing method Pra, the end portion 4 a of the external connection terminal 4 is brazed to the circuit pattern 7 via the hard brazing material 5. FIG. 7 is a cross-sectional view of the vicinity of the end portion 4a of the external connection terminal 4 existing above the circuit pattern 7a in the configuration Ctm2 according to the second modification of the present invention. In the configuration Ctm2, fillets Ft1 and Ft2 are formed on the brazing filler metal 5 sandwiched between the end 4a and the circuit pattern 7. The fillet Ft1 is present in a portion of the hard brazing material 5 on the end 4a side. The fillet Ft2 is present in the portion of the hard brazing material 5 on the circuit pattern 7 side.

  Hereinafter, the shape of the brazing filler metal 5 having the fillets Ft1 and Ft2 is also referred to as “shape Cf”. In the following, the brazing filler metal 5 having the shape Cf is also referred to as “hard brazing filler metal 5A”.

  FIG. 8 is a flowchart of the semiconductor manufacturing method Pra according to the second modification of the present invention. In FIG. 8, the processing with the same step number as the step number in FIG. 2 is performed in the same way as the processing described in the first embodiment, and therefore detailed description will not be repeated. Hereinafter, a description will be given focusing on differences from the first embodiment. FIG. 8 shows only the characteristic steps included in the semiconductor manufacturing method Pra.

  Below, the part for joining the edge part 4a of the external connection terminal 4 among the circuit patterns 7 is also called "joining object part." The joining target portion exists in both of the circuit patterns 7a and 7b.

  Next, the semiconductor manufacturing method Pra will be described. In the semiconductor manufacturing method Pra, first, a preparation process is performed (step S101). In the preparation step, preliminary brazing is performed on the circuit pattern 7. Specifically, as shown in FIG. 9A, a hard brazing material 5 is provided on the circuit pattern 7. Specifically, the brazing filler metal 5 is provided in each joining target portion of the circuit patterns 7a and 7b.

  The brazing material 5 is brazed in a nitrogen atmosphere so that the copper constituting the circuit pattern 7 (7a, 7b) and the circuit pattern 7c is not oxidized. Specifically, a phosphor copper braze is arranged at each joining target portion of the circuit patterns 7a and 7b.

  Next, in the nitrogen atmosphere, the phosphor copper solder is heated so that the temperature of the phosphor copper solder rises to the melting point of the phosphor copper solder. Next, the phosphor copper braze is cooled. Thereby, the brazing filler metal 5 is provided in each joining object part of circuit pattern 7a, 7b. That is, the hard brazing material 5 is brazed to the joining target portion in advance.

  In the following, the hard brazing material 5 brazed to the joining target portion in advance is also referred to as “preparation brazing material”. Next, as in the first embodiment, the power semiconductor element S1 is bonded to the circuit pattern 7a through the bonding material 2 as shown in FIG. 9B. Next, as in FIG. 10, as in the first embodiment, the insulating substrate 9 on which the power semiconductor element S <b> 1 is mounted is bonded to the base plate 11 via the bonding material 10.

  Next, as in the first embodiment, the connection wiring 3 is bonded to the surface electrode (not shown) on the power semiconductor element S1 and the circuit pattern 7b by ultrasonic bonding. Next, as shown in FIG. 11, as in the first embodiment, the cylindrical case 12 to which the end 4 b of the external connection terminal 4 is joined is joined to the base plate 11 via the adhesive 13. Is done.

  Hereinafter, the state in which the hard brazing material 5 as the preparation brazing material is sandwiched between the external connection terminal 4 (the surface 4a2 of the end 4a) and the circuit pattern 7 is also referred to as a “squeezed state”.

  Next, a brazing process is performed (step S110). As described above, the brazing step is a step of brazing the external connection terminals 4 to the circuit pattern 7 via the hard brazing material 5 as the preparation brazing material in the sandwiched state.

  Specifically, in the brazing process, first, a pinching process is performed as in the first embodiment. In the pinching process, the hard brazing material 5 as the preparation brazing material is thus pinched by the external connection terminals 4 (end portions 4a) and the circuit pattern 7, as shown in FIG. As a result, the shape of the hard brazing material 5 (prepared brazing material) is, for example, a semi-elliptical sphere.

  Next, in the brazing process, an irradiation process Ia is performed. In the irradiation process Ia, as in the first embodiment, the galvano scanner system 14 applies the laser beam to the surface 4a1 of the end 4a of the external connection terminal 4 so that the hard brazing material 5 (prepared brazing material) is melted. Irradiate.

  As a result, heat Ht is generated at the end 4a. With the heat Ht, the brazing filler metal 5 (prepared brazing filler metal) in contact with the surface 4a2 of the end 4a is heated to the melting point of the brazing filler metal or higher. Thereby, the brazing filler metal 5 (preparation brazing filler metal) is melted, and the upper portion of the brazing filler metal 5 flows toward the surface 4a1 of the end portion 4a to form the fillet Ft1.

  The brazing filler metal 5A having the shape Cf as shown in FIG. 7 is formed by the semiconductor manufacturing method Pra as described above. The brazing filler metal 5A has fillets Ft1 and Ft2. In the following, the shape of the brazing filler metal 5 in FIG. 5B is also referred to as “shape Cn”. In the brazing filler metal 5 having the shape Cn, the bottom of the fillet exists only at the end 4a side of the brazing filler metal 5.

  The shape Cf of the brazing filler metal 5A is a shape that does not have a notch shape as compared with the brazing filler metal 5 having the shape Cn shown in FIG. Therefore, stress is less likely to concentrate on the brazing filler metal 5A than on the brazing filler metal 5 having the shape Cn. That is, the brazing material 5A is a more reliable joint than the brazing material 5 having the shape Cn.

  In addition, after the preparation step (S110) is performed and until the brazing step (S110) is performed, for the joining of the power semiconductor element S1, the joining of the insulating substrate 9, the joining of the case 12, etc. , Heat is applied. However, the temperature of the heat is much lower than the melting point (brazing temperature) of phosphor copper brazing. For this reason, the heat does not affect the brazing of the external connection terminals 4 to the circuit pattern 7.

  In the irradiation process Ia, as in the first embodiment, the galvano scanner system 14 irradiates the laser light in the order of the upper end 4a of the circuit pattern 7a and the upper end 4a of the circuit pattern 7b. As a result, the end 4a of one external connection terminal 4 is brazed to the circuit pattern 7a via the hard brazing material 5A, and the end 4a of the other external connection terminal 4 is passed through the hard brazing material 5A. The circuit pattern 7b is brazed.

  Note that the laser beam may be emitted in the order of the upper end 4a of the circuit pattern 7b and the upper end 4a of the circuit pattern 7a.

  As described above, according to this modification, the brazing filler metal 5A having the shape Cf as shown in FIG. 7 can be formed. Therefore, in addition to the effects of the first embodiment, a highly reliable joint (hard soldering material 5A) can be obtained.

  In the preparation step (S101), the circuit pattern 7 is provided with the hard brazing material 5 as the preparation brazing material, but is not limited thereto. In the preparation step (S101), instead of the circuit pattern 7, the external connection terminal 4 may be provided with a hard brazing material 5 as a preparatory brazing material (hereinafter also referred to as “configuration Ctm2a”). Below, the part for joining to the circuit pattern 7 among the edge parts 4a of the external connection terminal 4 is also called "joining object part."

  In the configuration Ctm2a, the brazing filler metal 5 is provided in the joint target portion of the external connection terminal 4 in the preparation step (S101). Thereafter, similarly to the processing of the configuration Ctm2, processes such as bonding of the power semiconductor element S1, bonding of the insulating substrate 9, and bonding of the case 12 are performed, and a brazing process (S110) is performed.

<Modification 3>
Hereinafter, the configuration of this modification is also referred to as “configuration Ctm3”. The configuration Ctm3 is a configuration in which the configuration Ctm1 of the first modification is applied to the configuration Ctm2 of the second modification.

  The configuration Ctm1 is a configuration using the external connection terminal 4C of FIG. That is, in the configuration Ctm3, the external connection terminal 4C is brazed to the circuit pattern 7 in the semiconductor manufacturing method Pra. The description of the processing in the configuration Ctm1 and the description of the processing of the semiconductor manufacturing method Pra have been described above, and will be omitted.

  Here, it is assumed that the size of the tip portion 4ax in a plan view is, for example, 2 mm × 2 mm. In this case, the size of the preparatory brazing material formed in the preparatory step (S101) in plan view is desirably 2 mm × 2 mm to 2.5 mm × 2.5 mm.

  In the configuration Ctm3, the semiconductor manufacturing method Pra is performed, so that the tip end portion 4ax of the external connection terminal 4 is brazed to the circuit pattern 7 via the hard brazing material 5A as shown in FIG. That is, the front end portion 4ax of the external connection terminal 4 is a portion for brazing to the circuit pattern 7 (7a, 7b).

  As described above, according to this modification, in addition to the effects of the first embodiment, the effects of Modification 1 and Modification 2 can be obtained. That is, the tip end 4ax of the external connection terminal 4 can be brazed to the circuit pattern 7 in a short time. Moreover, a highly reliable joint (hard soldering material 5A) can be obtained.

<Modification 4>
In the following, the configuration of this modification is also referred to as “configuration Ctm4”. The configuration Ctm4 is a configuration having characteristics in the shape of the brazing filler metal 5 and the laser beam irradiation method. In the configuration Ctm4, the shape of the brazing filler metal 5 is a plate shape. Hereinafter, the method for manufacturing the power semiconductor device 100 in the configuration Ctm4 is also referred to as “semiconductor manufacturing method Prb”. The processing of the semiconductor manufacturing method Prb will be described later.

  The configuration Ctm4 is applied to the configuration Ct1 (Embodiment 1) or the configuration Ctm1 (Modification 1). As an example, a configuration Ctm1 to which the configuration Ctm4 is applied (hereinafter also referred to as “configuration Ctm14”) will be described.

  In the configuration Ctm14, the semiconductor manufacturing method Prb is performed, so that the tip end 4ax of the end 4a of the external connection terminal 4C is brazed to the circuit pattern 7 via the plate-like hard soldering material 5.

  FIG. 13 is a diagram for explaining a configuration Ctm14 according to the fourth modification of the present invention. FIG. 13A is a cross-sectional view of the vicinity of the end 4a of the external connection terminal 4C that exists above the circuit pattern 7a in the configuration Ctm14 of the fourth modification. FIG. 13B is a plan view of the vicinity of the end 4a of the external connection terminal 4C.

  FIG. 14 is a flowchart of a semiconductor manufacturing method Prb according to Modification 4 of the present invention. FIG. 14 shows only the characteristic steps included in the semiconductor manufacturing method Prb. The semiconductor manufacturing method Prb differs from the semiconductor manufacturing method Pr of FIG. 2 in that step S110A is performed instead of step S110. Since other processes of the semiconductor manufacturing method Prb are the same as those of the semiconductor manufacturing method Pr, detailed description will not be repeated.

  Next, the semiconductor manufacturing method Prb will be described. In the semiconductor manufacturing method Prb, steps such as bonding of the power semiconductor element S1, bonding of the insulating substrate 9, and bonding of the case 12 are performed as in the first embodiment. Next, brazing process A (S110A) is performed.

  In the brazing process A, a pinching process is first performed. In the pinching process in the configuration Ctm14, as shown in FIG. 13A, the plate-like brazing filler metal 5 is disposed in the joining target portion of the circuit pattern 7. Then, the plate-like hard soldering material 5 is sandwiched between the external connection terminal 4C (the tip portion 4ax of the end portion 4a) and the circuit pattern 7.

  Next, in the brazing process A, an irradiation process Ia is first performed. FIG. 13B is a plan view of the configuration shown in FIG. In the irradiation process Ia, the galvano scanner system 14 causes the laser beam so that the brazing filler metal 5 is melted in a state where the brazing filler metal 5 is sandwiched between the tip portion 4ax of the external connection terminal 4C and the circuit pattern 7. Is irradiated onto the surface 4a1 of the tip portion 4ax. Note that the laser light is applied to the surface 4a1 of the tip end 4ax along, for example, the direction of the arrow Dr1a in FIG.

  Next, in the brazing process A, an irradiation process Ib is performed. In the irradiation process Ib, the galvano scanner system 14 irradiates a region around the brazing filler metal 5 in the circuit pattern 7 with laser light so that the brazing filler metal 5 is melted by heat generated in the circuit pattern 7. . For example, until the brazing filler metal 5 is melted, the laser beam moves around the brazing filler metal 5 existing below the tip portion 4ax one or more times along the arrow Dr1b in FIG. The circuit pattern 7 is irradiated.

  As described above, according to this modification, both the external connection terminal 4C and the circuit pattern 7 are heated by the laser light. That is, in this modification, both the external connection terminal 4C and the circuit pattern 7 are heated to the melting point of the hard solder. Thereby, the shape of the brazing filler metal 5 becomes the shape Cf of the brazing filler metal 5A having the fillets Ft1 and Ft2, as shown in FIG. Therefore, a highly reliable joint (hard soldering material 5A) can be obtained.

  Moreover, according to this modification, there exists an advantage that it is not necessary to perform a preparation process like the modification 2.

  According to the brazing process A using the external connection terminals 4C, a region around the hard brazing material 5 (joint portion) in the circuit pattern 7 can be heated by laser light. That is, in the brazing process A using the external connection terminals 4C, a region closer to the hard brazing material 5 (joint portion) can be heated than when the external connection terminals 4 are used. Therefore, the external connection terminals 4C can be brazed to the circuit pattern 7 in a short time with high efficiency.

  Moreover, according to the brazing process A using the external connection terminal 4C, since the galvano scanner system 14 is used, the external connection terminal 4C and the circuit pattern 7 can be heated at high speed, and the brazing can be performed in a shorter time. Attaching can be done.

  In the brazing process A of this modification, the laser light is applied to the external connection terminals 4C and the circuit pattern 7 in the order of the external connection terminals 4C and the circuit pattern 7. However, the present invention is not limited to this. The laser light may be applied to the external connection terminal 4C and the circuit pattern 7 in the order of the circuit pattern 7 and the external connection terminal 4C. That is, in the brazing process A, the irradiation process Ia may be performed after the irradiation process Ib.

  The heat dissipation of the insulating substrate 9 (circuit pattern 7) is higher than the heat dissipation of the external connection terminal 4C. Therefore, in the brazing process A, the energy density of the laser beam irradiated on the circuit pattern 7 is set higher than the energy density of the laser beam irradiated on the external connection terminal 4C.

  Further, in the circuit pattern 7, the position where the laser beam is irradiated is desirably a position separated from each side of the tip portion 4ax in FIG. 13B by a distance of 0.5 mm to 1.0 mm. Moreover, it is desirable that the size of the brazing filler metal 5 in the plan view is equal to the size of the tip portion 4ax in the plan view immediately after the above-described sandwiching process is performed.

<Modification 5>
In the following, the configuration of this modification is also referred to as “configuration Ctm5”. The configuration Ctm5 has a feature in the shape of the external connection terminal and the laser beam irradiation method. The configuration Ctm5 is applied to the configuration Ct1 (Embodiment 1). The power semiconductor device 100 to which the configuration Ctm5 is applied includes an external connection terminal 4D instead of the external connection terminal 4. Hereinafter, the method for manufacturing the power semiconductor device 100 in the configuration Ctm5 is also referred to as “semiconductor manufacturing method Prc”. The processing of the semiconductor manufacturing method Prc will be described later.

  FIG. 15 is a diagram for explaining the external connection terminal 4D in the configuration Ctm5 according to the fifth modification of the present invention. FIG. 15A is a perspective view of the vicinity of the end 4a of the external connection terminal 4D. FIG. 15B is a plan view of the vicinity of the end 4a of the external connection terminal 4D.

  15A and 15B, the external connection terminal 4D is different from the external connection terminal 4 of FIG. 5 in that a through hole H1 is provided in the end 4a. Since the other shape and configuration of external connection terminal 4D are the same as those of external connection terminal 4, detailed description thereof will not be repeated.

  Before the semiconductor manufacturing method Prc is performed, the end 4a of the external connection terminal 4D is a portion to be brazed to the circuit pattern 7. After the semiconductor manufacturing method Prc is performed, the end 4a of the external connection terminal 4D is brazed to the circuit pattern 7.

  The shape of the through hole H1 is, for example, a U-shape. As shown in FIG. 15B, the end 4a has a region Rg1. The region Rg1 of the end 4a is a region existing inside the through hole H1 in a plan view (XY plane).

  A region Rg <b> 1 of the end portion 4 a is a region that is brazed to the circuit pattern 7 via the hard brazing material 5. That is, the hard brazing material 5 is present below the region Rg1 of the end 4a. Therefore, the brazing filler metal 5 exists inside the through hole H1 in a plan view (XY plane). That is, the through-hole H1 is provided in the end portion 4a so that the through-hole H1 surrounds a part of the brazing filler metal 5 (region Rg1) as a joint in a plan view (XY plane).

  FIG. 16 is a flowchart of the semiconductor manufacturing method Prc according to the fifth modification of the present invention. FIG. 16 shows only the characteristic steps included in the semiconductor manufacturing method Prc. The semiconductor manufacturing method Prc is different from the semiconductor manufacturing method Pr of FIG. 2 in that step S110B is performed instead of step S110. Since other processes of the semiconductor manufacturing method Prc are the same as those of the semiconductor manufacturing method Pr, detailed description will not be repeated.

  Next, the semiconductor manufacturing method Prc will be described. In the semiconductor manufacturing method Prc, as in the first embodiment, steps such as bonding of the power semiconductor element S1, bonding of the insulating substrate 9, and bonding of the case 12 are performed. Next, brazing process B (S110B) is performed.

  In the brazing process B, a pinching process is first performed. In the pinching process in the configuration Ctm5, the brazing filler metal 5 is disposed in the joining target portion of the circuit pattern 7 that exists below the region Rg1 of the end portion 4a in FIG. Then, the brazing filler metal 5 is sandwiched between the external connection terminal 4D (region Rg1 of the end 4a) and the circuit pattern 7. At this time, the brazing filler metal 5 exists inside the through hole H1 in a plan view (XY plane).

  Next, in the brazing process B, first, an irradiation process Ia is performed. In the irradiation process Ia, the galvano scanner system 14 causes the brazing filler metal 5 to melt in a state where the brazing filler metal 5 is sandwiched by the region Rg1 of the end 4a of the external connection terminal 4D and the circuit pattern 7. The laser beam is irradiated to the upper surface (surface 4a1) of the region Rg1 of the end 4a. Note that the laser beam is applied to the upper surface (surface 4a1) of the region Rg1 of the end 4a, for example, along the direction of the arrow Dr2a in FIG. That is, the laser beam is irradiated to the region Rg1 in a spiral shape so as to be directed outward from the center of the region Rg1 of the end 4a.

  Next, in the brazing process B, an irradiation process Ic is performed. In the irradiation process Ic, the galvano scanner system 14 oscillates the laser light toward the through hole H1 so that the circuit pattern 7 is irradiated with the laser light. Therefore, the laser light passes through the through hole H1 and is irradiated to the circuit pattern 7.

  Specifically, in the irradiation process Ic, the galvano scanner system 14 is disposed in a region around the brazing filler metal 5 in the circuit pattern 7 so that the brazing filler metal 5 is melted by heat generated in the circuit pattern 7. Laser light passing through the through hole H1 is irradiated. For example, the laser beam moves one or more times around the brazing filler metal 5 existing below the region Rg1 of the end 4a along the arrow Dr2b in FIG. 15B until the brazing filler metal 5 is melted. Thus, the circuit pattern 7 is irradiated.

  As described above, according to the present modification, the galvano scanner system 14 irradiates the region around the hard brazing material 5 in the circuit pattern 7 with the laser light passing through the through hole H1. Thereby, the area | region around the brazing filler metal 5 among the circuit patterns 7 can be heated efficiently. Further, both the external connection terminal 4D and the circuit pattern 7 are heated by the laser light. That is, in this modification, both the external connection terminal 4D and the circuit pattern 7 are heated to the melting point of the hard solder.

  Thereby, the shape of the brazing filler metal 5 becomes the shape Cf of the brazing filler metal 5A having the fillets Ft1 and Ft2, as shown in FIG. Therefore, a highly reliable joint (hard soldering material 5) can be obtained.

  The shape of the through hole H1 provided in the end 4a of the external connection terminal 4D may be different from the shape of the through hole H1 shown in FIG. For example, the shape of the through hole H1 may be an arc as shown in FIG. In this case, the brazing filler metal 5 is disposed below the region Rg1a surrounded by the through hole H1 in the end portion 4a.

  For example, the shape of the through hole H1 may be V-shaped as shown in FIG. In this case, the brazing filler metal 5 is disposed below the region Rg1ab surrounded by the through hole H1 in the end portion 4a. Even if the shape of the through hole H1 is an arc shape, a V shape, or the like, the above-described effect in the present modification can be obtained.

  As described above, in the present modification, the through hole H1 is provided in a region around the hard brazing material 5 in the end 4a in plan view (XY plane). Thereby, in the state where the temperature of the external connection terminal 4D is high, the state where the external connection terminal 4D is cooled, or the like by a power cycle test, a temperature cycle test, or the like, of the end 4a, around the through hole H1. The portion receives a vertical force applied to the external connection terminal 4D. Therefore, the load added to the lower part of the through-hole H1 among the brazing filler metals 5 (joint part) reduces. Therefore, the reliability of the brazing filler metal 5 (joint part) can be improved.

  In the brazing process B of the present modification, the laser light is applied to the external connection terminal 4D and the circuit pattern 7 in the order of the external connection terminal 4D and the circuit pattern 7. However, the present invention is not limited to this. The laser light may be applied to the external connection terminal 4D and the circuit pattern 7 in the order of the circuit pattern 7 and the external connection terminal 4D. That is, in the brazing process B, the irradiation process Ia may be performed after the irradiation process Ic.

  Similarly to the brazing process A of the modified example 4, in the brazing process B, the energy density of the laser light applied to the circuit pattern 7 is higher than the energy density of the laser light applied to the external connection terminal 4D. Set to

<Modification 6>
Hereinafter, the configuration of the present modification is also referred to as “configuration Ctm6”. The configuration Ctm6 is characterized by a part of the external connection terminals. The configuration Ctm6 is applied to all or part of the configuration Ct1 (Embodiment 1), the configuration Ctm1 (Modification 1), and the configuration Ctm4 (Modification 4).

  As an example, configurations Ctm1 and Ctm4 (hereinafter also referred to as “configuration Ctm146”) to which the configuration Ctm6 is applied will be described. The power semiconductor device 100 to which the configuration Ctm 146 is applied includes an external connection terminal 4E instead of the external connection terminal 4.

  FIG. 18 is a cross-sectional view of the power semiconductor device 100 having the configuration Ctm 146 according to the sixth modification of the present invention. The external connection terminal 4E is different from the external connection terminal 4C in that it has a thin portion. Since the other configuration of external connection terminal 4E is similar to that of external connection terminal 4C, detailed description will not be repeated.

  The external connection terminal 4E has a bent part Bd1 as a thin part. The thickness of the bent portion Bd1 is smaller than the thickness of the portion other than the bent portion Bd1 in the external connection terminal 4E.

  In the configuration Ctm 146, the semiconductor manufacturing method Pr is performed as in the first embodiment. That is, the irradiation process Ia is performed. In the irradiation process Ia in the configuration Ctm 146, the galvano scanner system 14 irradiates the laser light in the order of the end 4a (tip 4ax) above the circuit pattern 7a and the end 4a (tip 4ax) above the circuit pattern 7b. Is done.

  Note that the laser light may be emitted in the order of the end 4a (tip 4ax) above the circuit pattern 7b and the end 4a (tip 4ax) above the circuit pattern 7a. Hereinafter, a region of the external connection terminal 4E that is in contact with the brazing filler metal is also referred to as a “joining region”.

  As described above, according to this modification, when laser light is applied to the end 4a (tip 4ax) of the external connection terminal 4E, the heat generated at the end 4a is transferred to the through-hole h4 (screw fastening). Part). However, the thickness of at least one bent portion Bd1 of the external connection terminal 4E is smaller than the thickness of the portion other than the bent portion Bd1 in the external connection terminal 4E. Therefore, the transient thermal resistance at the external connection terminal 4E is increased. Therefore, in the external connection terminal 4E, the amount of heat transferred in the direction of the through hole h4 (screw fastening portion) can be reduced. As a result, it is possible to obtain an effect that the temperature of the joining region (tip portion 4ax) of the external connection terminal 4E is easily increased.

  The external connection terminal 4E has a bent portion Bd1 as a thin portion. Therefore, when the power semiconductor device 100 is driven, even if the external connection terminal 4E expands and contracts along the vertical direction, the bent portion Bd1 (thin wall portion) relaxes the stress. Therefore, the effect that the thermal stress added to the joining area | region of the external connection terminal 4E can be relieved is acquired.

<Modification 7>
In the following, the configuration of this modification is also referred to as “configuration Ctm7”. The configuration Ctm7 is characterized by a part of the external connection terminals. The configuration Ctm6 is applied to all or part of the configuration Ct1 (Embodiment 1), the configuration Ctm1 (Modification 1), and the configuration Ctm4 (Modification 4).

  As an example, a configuration Ctm1 to which the configuration Ctm7 is applied (hereinafter also referred to as “configuration Ctm17”) will be described. The power semiconductor device 100 to which the configuration Ctm17 is applied includes an external connection terminal 4F instead of the external connection terminal 4.

  FIG. 19 is a perspective view of the external connection terminal 4F having the configuration Ctm17 according to the modified example 7 of the present invention. For comparison with the external connection terminal 4C, FIG. 20 shows a perspective view of the external connection terminal 4C. The external connection terminal 4F is different from the external connection terminal 4C in that it has details. Since the other configuration of external connection terminal 4F is the same as that of external connection terminal 4C, detailed description will not be repeated.

  The external connection terminal 4F has a bent portion Bd2 as details. The width of the bent portion Bd2 is smaller than the width of the portion other than the bent portion Bd2 in the external connection terminal 4F.

  In the configuration Ctm17, the semiconductor manufacturing method Pr is performed as in the first embodiment. That is, the irradiation process Ia is performed. In the irradiation process Ia in the configuration Ctm17, the galvano scanner system 14 irradiates the laser light in the order of the upper end 4a (tip 4ax) of the circuit pattern 7a and the upper end 4a (tip 4ax) of the circuit pattern 7b. Is done. Hereinafter, a region of the external connection terminal 4F that is in contact with the hard brazing material is also referred to as a “joining region”.

  As described above, according to the present modification, as in Modification 6, when the end 4a (tip 4ax) of the external connection terminal 4F is irradiated with laser light, the heat generated at the end 4a is It transmits also to the direction of the through-hole h4 (screw fastening part).

  However, the width of at least one bent portion Bd2 included in the external connection terminal 4F is smaller than the width of the portion other than the bent portion Bd2 in the external connection terminal 4F. Therefore, the transient thermal resistance at the external connection terminal 4F is increased. Therefore, in the external connection terminal F, the amount of heat transferred in the direction of the through hole h4 (screw fastening portion) can be reduced. As a result, it is possible to obtain an effect that the temperature of the joining region (tip portion 4ax) of the external connection terminal 4F is easily increased.

  The external connection terminal 4F has a bent portion Bd2 in detail. Therefore, when the power semiconductor device 100 is driven, even if the external connection terminal 4F expands and contracts along the vertical direction, the bent portion Bd2 (details) relieves stress. Therefore, the effect that the thermal stress added to the joining area | region of the external connection terminal 4F can be relieved is acquired.

  Next, the external connection terminal 4E of the modification 6 and the external connection terminal 4F of the modification 7 will be described. The cooling path for heat generated by laser light irradiation includes a heat dissipation path (hereinafter also referred to as “pattern path”) in the circuit patterns 7a and 7b and a heat dissipation path (hereinafter referred to as “pattern path”) in the external connection terminal 4E (4F). Terminal route ”).

  In the power semiconductor device 100 of the present invention, the heat dissipation of the pattern path is usually five times or more that of the terminal path. The cross-sectional area of the terminal path is n (an integer in the range of 1 to 9) square millimeters. In the terminal path, heat is transferred one-dimensionally. On the other hand, in the pattern path, heat moves three-dimensionally (spreads). Such a three-dimensional heat transfer is called a 45 degree spread law. In the 45-degree spread law, heat moves (spreads) in both the lateral direction and the thickness direction. Therefore, the difference between the heat dissipation of the pattern path and the heat dissipation of the terminal path is large.

  In order to perform brazing, it is necessary to heat the temperature of the circuit pattern 7 (7a, 7b) to the hard solder melting point or higher. However, if heating is not performed in consideration of the high heat dissipation of the circuit pattern 7, the temperature of the external connection terminal 4E (4F) will be higher than the melting point of the hard solder, but the temperature of the circuit pattern 7 will be higher than the melting point of the hard solder. It may not be possible. If the temperature of the circuit pattern 7 does not exceed the melting point of the hard solder, there arises a problem that the wetting and spreading of the hard soldering material in contact with the circuit pattern 7 becomes insufficient.

  Therefore, in the irradiation process Ia of the modified example 6 or the modified example 7, the laser beam is applied to the circuit pattern 7 and the external connection terminal 4E (4F) so that the energy amount E1 is given to the circuit pattern 7 and the external connection terminal 4E (4F). Is irradiated. The energy amount E1 is an energy amount represented by the reciprocal of the ratio of the thermal resistance of the terminal path to the thermal resistance of the pattern path. As a result, the circuit pattern 7 can be supplied with heat at or above the melting point of the hard solder. Therefore, the non-wetting of the hard brazing material 5 can be prevented. As a result, a highly reliable joint (hard soldering material 5) can be obtained.

<Modification 8>
In the following, the configuration of this modification is also referred to as “configuration Ctm8”. The configuration Ctm8 has a feature in the laser light irradiation method. The configuration Ctm8 is applied to all or part of the configuration Ct1 (Embodiment 1), the configuration Ctm1m, the configuration Ctm4, the configuration Ctm6, and the configuration Ctm7.

  As an example, configurations Ctm1 and Ctm4 (hereinafter also referred to as “configuration Ctm148”) to which the configuration Ctm8 is applied will be described. Hereinafter, the method for manufacturing the power semiconductor device 100 in the configuration Ctm8 is also referred to as “semiconductor manufacturing method Prd”.

  21 and 22 are diagrams for explaining a semiconductor manufacturing method Prd according to the modification 8 of the present invention. 21 and 22 show a power semiconductor device 100 having the configuration Ctm148.

  FIG. 23 is a flowchart of a semiconductor manufacturing method Prd according to Modification 8 of the present invention. FIG. 23 shows only the characteristic steps included in the semiconductor manufacturing method Prd. The semiconductor manufacturing method Prd is different from the semiconductor manufacturing method Pr of FIG. 2 in that step S110C is performed instead of step S110. Since other processes of the semiconductor manufacturing method Prd are the same as those of the semiconductor manufacturing method Pr, detailed description will not be repeated.

  Next, the semiconductor manufacturing method Prd will be described. In the semiconductor manufacturing method Prd, processes such as bonding of the power semiconductor element S1, bonding of the insulating substrate 9, and bonding of the case 12 are performed as in the first embodiment. Next, a brazing process C (S110C) is performed.

  In the brazing process C, a pinching process is first performed. In the pinching process, the brazing filler metal 5 is pinched by the tip end 4ax of the external connection terminal 4C and the circuit pattern 7.

  Next, in the brazing process B, the irradiation process Ia and the irradiation process Id are performed simultaneously. In the brazing process B, the irradiation process Ia and the irradiation process Id are performed twice. In the brazing process B, as an example, three lasers 18 and three galvano scanner systems 14 are used. Two lasers 18 of the three lasers 18 and two galvano scanner systems 14 of the three galvano scanner systems 14 are used simultaneously.

  Hereinafter, the three lasers 18 are also referred to as lasers 18n, 18a, and 18b, respectively. In the following, the three galvano scanner systems 14 are also referred to as galvano scanner systems 14n, 14a, and 14b, respectively. The lasers 18n, 18a, and 18b are connected to galvano scanner systems 14n, 14a, and 14b, respectively.

  First, in the first irradiation processes Ia and Id, as an example, two laser beams are irradiated simultaneously as shown in FIG. In the present specification, the expression “two laser beams are irradiated simultaneously” also includes the meaning “two laser beams are irradiated at substantially the same timing”.

  Specifically, in the first irradiation process Ia, the galvano scanner system 14n is connected to the external connection terminal 4C existing above the circuit pattern 7a so that the brazing filler metal 5 is melted by the heat generated in the external connection terminal 4C. A laser beam is irradiated to a part (tip portion 4ax).

  Further, in the first irradiation process Id, the galvano scanner system 14a is disposed in a region around the brazing filler metal 5 in the circuit pattern 7a so that the brazing filler metal 5 is melted by heat generated in the circuit pattern 7a. Irradiate with laser light.

  Next, in the second irradiation processes Ia and Id, as an example, two laser beams are simultaneously irradiated as shown in FIG. Specifically, in the second irradiation process Ia, the galvano scanner system 14n is connected to the external connection terminal 4C existing above the circuit pattern 7b so that the brazing filler metal 5 is melted by the heat generated in the external connection terminal 4C. A laser beam is irradiated to a part (tip portion 4ax).

  Further, in the second irradiation process Id, the galvano scanner system 14b is arranged in a region around the brazing filler metal 5 in the circuit pattern 7b so that the brazing filler metal 5 is melted by heat generated in the circuit pattern 7b. Irradiate with laser light.

  As described above, according to this modification, the external connection terminal 4C and the circuit pattern 7 (7a, 7b) are simultaneously irradiated with laser light. Thereby, thermal interference occurs and the temperature of the brazing filler metal 5 rises rapidly. Therefore, the effect that brazing can be performed efficiently in a shorter time than the above-described semiconductor manufacturing methods other than the present modification can be obtained.

  Note that the present invention can be freely combined with each embodiment and each modification within the scope of the invention, and each embodiment and each modification can be appropriately modified and omitted.

  For example, the number of external connection terminals 4 included in the power semiconductor device 100 is not limited to 2, and may be 1 or 3 or more.

  Further, in the above-described embodiment and each modification, the laser beam is used to melt the brazing filler metal 5, but the present invention is not limited to this. For example, an electron beam may be used.

  4, 4C, 4D, 4E, 4F External connection terminal, 5, 5A brazing material, 7, 7a, 7b, 7c circuit pattern, 9 insulating substrate, 100 power semiconductor device, S1 power semiconductor element.

Claims (16)

An insulating substrate;
An external connection terminal,
A circuit pattern is provided on the main surface side of the insulating substrate,
The external connection terminal is brazed to the circuit pattern via a hard brazing material. The power semiconductor device according to claim 1, wherein a power semiconductor element is mounted on the circuit pattern. The tip of the external connection terminal is brazed to the circuit pattern via the hard brazing material,
The power semiconductor device according to claim 1, wherein a width of the tip portion is smaller than a width of a portion other than the tip portion of the external connection terminal. The external connection terminal has an end portion brazed to the circuit pattern,
The end portion is provided with a through hole,
The power semiconductor device according to claim 1, wherein the through hole is provided at the end so that the through hole surrounds a part of the brazing filler metal in a plan view. The external connection terminal has a bent portion,
The power semiconductor device according to claim 1, wherein a thickness of the bent portion is smaller than a thickness of a portion other than the bent portion in the external connection terminal. The external connection terminal has a bent portion,
The power semiconductor device according to claim 1, wherein a width of the bent portion is smaller than a width of a portion of the external connection terminal other than the bent portion. The power semiconductor device according to any one of claims 1 to 6, wherein the brazing filler metal is phosphor copper brazing. The power semiconductor device according to any one of claims 1 to 7, wherein each of the circuit pattern and the external connection terminal is made of copper. A method of manufacturing a power semiconductor device comprising an insulating substrate and external connection terminals,
A circuit pattern is provided on the main surface side of the insulating substrate,
The manufacturing method includes:
Including a brazing step of brazing the external connection terminal to the circuit pattern via the hard brazing material in a state where the hard brazing material is sandwiched between the external connection terminal and the circuit pattern;
The brazing process includes
A method for manufacturing a power semiconductor device, comprising: a first irradiation process in which a part of the external connection terminal is irradiated with laser light so that the brazing filler metal is melted by heat generated in the external connection terminal. The manufacturing method further includes:
A preparatory step of providing the hard soldering material on the circuit pattern or the external connection terminal;
The method for manufacturing a power semiconductor device according to claim 9, wherein the brazing step is performed after the preparation step. The external connection terminal has a tip for brazing to the circuit pattern,
The method of manufacturing a power semiconductor device according to claim 10, wherein a width of the tip portion is smaller than a width of a portion other than the tip portion of the external connection terminal. The shape of the brazing filler metal is a plate shape,
The brazing step further includes
The second irradiation process of irradiating the laser beam to a region around the brazing material of the circuit pattern so that the brazing material is melted by heat generated in the circuit pattern. A method of manufacturing a power semiconductor device. The external connection terminal has an end part to be brazed to the circuit pattern,
The end portion is provided with a through hole,
The through hole is provided in the end so that the through hole surrounds a part of the brazing filler metal in plan view,
The brazing step further includes
In the circuit pattern, a region around the brazing filler metal is irradiated with the laser beam passing through the through hole so that the brazing filler metal is melted by heat generated in the circuit pattern. A method for manufacturing a power semiconductor device according to claim 9. The method for manufacturing a power semiconductor device according to claim 9, wherein the laser light is irradiated by a galvano scanner system. The brazing step further includes
A fourth irradiation process for irradiating a region around the brazing filler metal in the circuit pattern with another laser beam so that the brazing filler metal is melted by heat generated in the circuit pattern;
The method for manufacturing a power semiconductor device according to claim 9, wherein the first irradiation process and the fourth irradiation process are performed simultaneously. The laser light is irradiated by a galvano scanner system,
The method of manufacturing a power semiconductor device according to claim 15, wherein the another laser beam is irradiated by another galvano scanner system.

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