JP2019033607A - Image forming apparatus - Google Patents

Abstract

To reduce energy loss of a power supply when an operation mode of a load apparatus is a power saving mode, and to further prevent breakage of an electrolytic capacitor resulting from noise to be generated in AC input voltage.SOLUTION: A noise detector 71 detects noise to be generated in input voltage Va0. Controllers 72, 63a stop switching processing of a switching element 63b in the case where an operation mode of a load apparatus is a power saving mode with power consumption smaller than that of a normal mode, and a detection result of the noise by the noise detector 71 does not satisfy a predetermined abnormality condition. The controllers 72, 63a further cause the switching element 63b to execute the switching processing in the case where the operation mode of the load apparatus changes into the normal mode when the switching processing of the switching element 63b is stopped, or in the case where the detection result of the noise by the noise detector 71 satisfies the abnormality condition.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an image forming apparatus that executes control according to noise of an input voltage.

  In general, an image forming apparatus such as a printer, a copier, or a multifunction peripheral includes a DC power supply device and a load device to which power is supplied from the DC power supply device.

  The load device includes a device related to an image forming process for forming an image on a sheet. For example, the load device includes a motor, a heater, various sensors, a control processor, and the like.

  The DC power supply device converts an AC input voltage into a DC output voltage. The DC power supply device includes a primary rectifier circuit including an electrolytic capacitor, a switching element, a transformer, and a secondary rectifier circuit.

  In the image forming apparatus, it is known that a predetermined apparatus operates the switching element intermittently when the operation mode of the load device is a power saving mode in which the power consumption is smaller than the normal mode ( For example, see Patent Document 1). This contributes to a reduction in power consumption of the DC power supply device.

JP2013-1888083A

  By the way, when the operation mode of the load device is the power saving mode, it is conceivable that the predetermined device stops the processing of the switching element. Thereby, the energy loss of the power supply in the said power saving mode can be reduced more.

  In the DC power supply device, when the processing of the switching element is stopped, the electrolytic capacitor of the primary rectifier circuit does not discharge while retaining a charge.

  Therefore, in the situation where the processing of the switching element is stopped, when noise frequently appears on the AC input voltage, the electric charge caused by the noise further accumulates in the electrolytic capacitor. If it does so, there exists a possibility that the said electrolytic capacitor may be damaged by overvoltage.

  The object of the present invention is to reduce the energy loss of the power supply when the operation mode of the load device is the power saving mode, and further to prevent the electrolytic capacitor from being damaged due to the noise generated in the AC input voltage. It is to provide a forming apparatus.

  An image forming apparatus according to an aspect of the present invention includes a DC power supply device, a load device, a noise detection device, and a control device. The DC power supply device includes a primary rectifier circuit, a switching element, a transformer, and a secondary rectifier circuit. The primary rectifier circuit includes an electrolytic capacitor, rectifies an AC input voltage supplied from the outside, and outputs a primary DC voltage. The switching element generates a primary AC voltage by switching the primary DC voltage. The transformer converts the primary AC voltage into a secondary AC voltage. The secondary rectifier circuit rectifies the secondary AC voltage and outputs a secondary DC voltage. The load device includes a device related to an image forming process for forming an image on a sheet, and the secondary DC voltage is applied thereto. The noise detection device detects noise generated in the input voltage. The control device is when the operation mode of the load device is a power saving mode in which the power consumption is smaller than the normal mode, and the detection result of the noise by the noise detection device does not satisfy a predetermined abnormal condition. The switching process of the switching element is stopped. Further, the control device is configured such that when the switching process of the switching element is stopped, the operation mode of the load device is changed to the normal mode, or the detection result of the noise by the noise detection device is the abnormality. When the condition is satisfied, the switching element is caused to execute the switching process.

  According to the present invention, the energy loss of the power source when the operation mode of the load device is the power saving mode can be reduced, and further, the electrolytic capacitor can be prevented from being damaged due to noise generated in the AC input voltage. A forming apparatus can be provided.

FIG. 1 is a configuration diagram of an image forming apparatus according to an embodiment. FIG. 2 is a configuration diagram of a first power supply circuit included in the image forming apparatus according to the embodiment. FIG. 3 is a configuration diagram of a second power supply circuit and a second power supply control circuit included in the image forming apparatus according to the embodiment. FIG. 4 is a trend graph showing changes in AC input voltage including noise.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the following embodiment is an example which actualized this invention, Comprising: It does not have the character which limits the technical scope of this invention.

[Configuration of Image Forming Apparatus 10]
The image forming apparatus 10 according to the embodiment is an apparatus including an image forming unit 4 that executes an image forming process by an electrophotographic method. The image forming process is a process for forming an image on the sheet 9. The sheet 9 is a sheet-like image forming medium such as paper or a resin film.

  As shown in FIG. 1, the image forming apparatus 10 includes a sheet conveying mechanism 3, an image forming unit 4, a DC power supply circuit 50, a control board 8, and the like disposed in a main body 100. The control board 8 includes a CPU (Central Processing Unit) 81 and a storage device 82. The CPU 81 is realized by an integrated circuit. Further, the image forming apparatus 10 includes an operation device 8a and a display device 8b.

  The operation device 8a and the display device 8b are user interface devices. The operation device 8a is a device that receives a user operation, and includes, for example, an operation button or a touch panel device. The display device 8b is a device that displays information, and includes, for example, a liquid crystal panel unit.

  The CPU 81 executes various types of data processing by executing a program stored in advance in the storage device 82, and further controls the electrical equipment included in the image forming apparatus 10.

  The CPU 81 records state data representing various states of the image forming apparatus 10 in the storage device 82 before stopping and before shifting to the sleep mode. Further, the CPU 81 acquires the state data from the storage device 82 when activated, and sets initial values of various control parameters based on the state data.

  Note that other processors such as a DSP (Digital Signal Processor) may be employed instead of the CPU 81.

  The storage device 82 is a computer-readable non-volatile memory. For example, it is contemplated that the storage device 82 includes one or both of flash memory or a hard disk drive.

  In the sheet conveyance mechanism 3, the sheet delivery mechanism 30 sends out the sheet 9 accommodated in the sheet accommodating portion 101 to the sheet conveyance path 300, and a plurality of pairs of conveyance rollers 31 causes the sheet 9 to pass along the sheet conveyance path 300. Transport.

  The image forming unit 4 is a print processing apparatus including an optical scanning unit 40, a photoreceptor 41, a charging device 42, a developing device 43, a toner replenishing unit 44, a transfer device 45, a cleaning device 46, a fixing device 47, a motor 400, and the like. .

  The drum-shaped photoconductor 41 rotates, and the charging device 42 charges the surface of the photoconductor 41. The optical scanning unit 40 writes an electrostatic latent image on the surface of the photoconductor 41 by scanning the surface of the photoconductor 41 with the beam light.

  The developing device 43 develops the electrostatic latent image into a toner image by supplying toner 90 to the surface of the photoreceptor 41. The transfer device 45 transfers the toner image on the surface of the photoconductor 41 to the sheet 9 moving on the sheet conveyance path 300.

  The fixing device 47 fixes the toner image on the sheet 9 by heating the toner image transferred to the sheet 9. The fixing device 47 includes a fixing heater 470 that heats the toner image, and a fixing temperature sensor 471 such as a thermistor that detects the temperature of the fixing device 47. The fixing temperature sensor 471 is used for feedback control of the fixing heater 470.

  The cleaning device 46 removes the toner 90 remaining on the surface of the photoreceptor 41. The toner supply unit 44 supplies toner 90 to the developing device 43.

  The motor 400 drives the rotating body and the photoconductor 41 included in the sheet transport mechanism 3, the developing device 43, the transfer device 45, the fixing device 47, and the like.

  The DC power supply circuit 50 is a circuit that converts an AC input voltage Va0 supplied from the external power supply 1000 into a DC output voltage Vd2 by a switching method. The external power supply 1000 is a commercial power supply, for example. The DC power supply circuit 50 is an example of a DC power supply device.

  As shown in FIGS. 2 and 3, DC power supply circuit 50 includes transformers 55 and 65, a circuit on the primary side of transformers 55 and 65, and a circuit on the secondary side of transformers 55 and 65. The output voltage Vd2 corresponds to the secondary DC voltage output from the secondary circuit of the transformers 55 and 65.

  The image forming apparatus 10 further includes a ventilation fan 102, a dehumidifying heater 103, and the like. The ventilation fan 102 is a fan that incorporates a motor and ventilates the inside of the main body 100. The dehumidifying heater 103 heats and dries the sheet 9 accommodated in the sheet accommodating portion 101. The dehumidifying heater 103 is a heater that consumes less power than the fixing heater 470.

  Load devices to which the output voltage Vd2 of the DC power supply circuit 50 is applied directly or through a step-down circuit (not shown) are electrical devices included in the image forming unit 4, a ventilation fan 102, a dehumidifying heater 103, a control board 8, and an operating device 8a And a display device 8b. These load devices are examples of devices related to the image forming process.

  The CPU 81 controls the image forming unit 4, the display device 8b, the ventilation fan 102, the dehumidifying heater 103, and the like.

  Further, the CPU 81 executes mode control for shifting the operation mode of the load device from one of the standard mode and the power saving mode that consumes less power than the standard mode. The image forming unit 4 can execute the image forming process in the standard mode. On the other hand, the image forming unit 4 cannot execute the image forming process in the power saving mode.

  The CPU 81 itself shifts from the normal mode to the sleep mode when shifting the operation mode of the load device including the image forming unit 4 and the control board 8 from the standard mode to the power saving mode. In the sleep mode, the CPU 81 operates with a slower clock than the normal mode, and can execute only a limited part of the processing.

  In the present embodiment, the CPU 81 also functions as a mode signal output circuit. The mode signal output circuit is a circuit that outputs a mode signal Ms0 indicating whether the operation mode of the load device is the standard mode or the power saving mode.

  The mode signal Ms0 is transmitted from the mode signal output circuit to the DC power supply circuit 50. As will be described later, when the mode signal Ms0 indicates the power saving mode, the DC power supply circuit 50 shifts to a state where the power consumption is smaller than when the mode signal Ms0 indicates the standard mode.

  Note that the mode signal output circuit may be realized by a circuit other than the CPU 81.

  For example, when the print job data is received and no operation on the operation unit 8a continues for a predetermined time after the print job ends, the CPU 81 shifts the load device from the standard mode to the power saving mode. Transition.

  Further, when a predetermined return event occurs while the load device is operating in the power saving mode, the CPU 81 shifts from the sleep mode to the normal mode, and the CPU 81 Other devices in the device are shifted from the power saving mode to the standard mode. The return event is, for example, that the print job data has been received or that some operation has been performed on the operation device 8a.

  In the present embodiment, the DC power supply circuit 50 includes a first power supply circuit 5 and a second power supply circuit 6. The first power supply circuit 5 and the second power supply circuit 6 each convert an AC input voltage Va0 into a DC output voltage Vd2. The first power supply circuit 5 and the second power supply circuit 6 are examples of the first power supply device and the second power supply device, respectively.

  The first power supply circuit 5 and the second power supply circuit 6 apply the output voltage Vd2 to the load device, respectively. For example, it is conceivable that the output terminal of the first power supply circuit 5 and the output terminal of the second power supply circuit 6 are electrically connected in parallel. In this case, the first power supply circuit 5 and the second power supply circuit 6 apply the output voltage Vd2 in parallel to the same load device. It is also conceivable that the first power supply circuit 5 and the second power supply circuit 6 apply the output voltage Vd2 to a part of the load device and the other part, respectively.

  As shown in FIG. 2, the first power supply circuit 5 includes a primary rectifier circuit 52, a switching element 53b, a transformer 55, a secondary rectifier circuit 56, and the like. As shown in FIG. 3, the second power supply circuit 6 also includes a primary rectifier circuit 62, a switching element 63 b, a transformer 65, and a secondary rectifier circuit 66.

  The primary rectifier circuit 52 of the first power supply circuit 5 includes a primary electrolytic capacitor 52b, and the primary rectifier circuit 62 of the second power supply circuit 6 includes a primary electrolytic capacitor 62b. Details of the first power supply circuit 5 and the second power supply circuit 6 will be described later.

  In the image forming apparatus 10, it is known that a predetermined apparatus intermittently operates, for example, the switching element 53 b shown in FIG. 2 when the operation mode of the load device is the power saving mode. This contributes to a reduction in power consumption of the DC power supply circuit 50.

  By the way, when the operation mode of the load device is the power saving mode, it is conceivable that the predetermined device stops the processing of the switching elements 53b and 63b. Thereby, the energy loss of the power supply in the said power saving mode can be reduced more.

  In the DC power supply circuit 50, if the processing of the switching elements 53b and 63b is stopped, the primary electrolytic capacitors 52b and 62b do not emit while retaining the electric charge.

  Therefore, in the situation where the processing of the switching elements 53b and 63b is stopped, when noise frequently appears on the AC input voltage Va0, charges caused by the noise further accumulate in the primary electrolytic capacitors 52b and 62b. If it does so, there exists a possibility that the primary electrolytic capacitors 52b and 62b may be damaged by overvoltage.

  As shown in FIG. 4, the noise is usually a voltage superimposed on the input voltage Va0 and has a frequency component higher than the frequency of the input voltage Va0.

  The image forming apparatus 10 has a configuration for reducing the energy loss of the DC power supply circuit 50 when the operation mode of the load device is the power saving mode. Further, the image forming apparatus 10 has a configuration that can prevent the primary electrolytic capacitors 52b and 62b from being damaged due to the noise generated in the AC input voltage Va0.

[Configuration of First Power Supply Circuit 5]
The first power supply circuit 5 includes a protection circuit 51, a primary rectifier circuit 52, an output control circuit 53, a transformer 55, a secondary rectifier circuit 56, and the like.

  The protection circuit 51 includes a fuse 51a that prevents an overcurrent from flowing, a varistor 51b that prevents an overvoltage from being applied, and a noise filter 51c.

  Primary rectifier circuit 52 includes a bridge rectifier circuit 52a for full-wave rectification of input voltage Va0 and a primary electrolytic capacitor 52b for smoothing the voltage after full-wave rectification. The primary rectifier circuit 52 rectifies the input voltage Va0 and outputs a primary DC voltage Vd1.

  The output control circuit 53 generates the primary pulsed primary AC voltage Vp1 by switching the primary DC voltage Vd1. The transformer 55 is a high-frequency transformer that converts the primary DC voltage Vd1 into the secondary AC voltage Vp2.

  The output control circuit 53 includes a pulse width modulation element 53a and a switching element 53b. The output control circuit 53 will be described later.

  Secondary rectifier circuit 56 includes a diode 56a that full-wave rectifies secondary AC voltage Vp2 and a secondary electrolytic capacitor 56b that smoothes the voltage after full-wave rectification. The secondary rectifier circuit 56 generates a DC output voltage Vd2 by rectifying the secondary AC voltage Vp2.

  The first power supply circuit 5 also includes a load feedback circuit 54. In FIG. 2, the load feedback circuit 54 is simply indicated by a virtual line. The load feedback circuit 54 is a circuit that detects the relative magnitude of the power consumption of the load device with respect to the output power of the DC power supply circuit 50.

  The load feedback circuit 54 includes a shunt regulator and a photocoupler light emitting element provided on the secondary side of the first power supply circuit 5, a load detection capacitor, a constant current circuit provided on the primary side of the first power supply circuit 5, And a light receiving element of a photocoupler.

  The light receiving element and the load detection capacitor are electrically connected in parallel on the primary side of the first power supply circuit 5. The constant current circuit is electrically connected in series to the light receiving element and the load detection capacitor.

  When the output voltage Vd2 exceeds the target voltage due to a reduction in power consumption of the load device, the shunt regulator and the photocoupler are turned on, and the voltage of the load detection capacitor decreases.

  On the other hand, when the output voltage Vd2 falls below the target voltage due to an increase in power consumption of the load device, the shunt regulator and the photocoupler are turned off, and the voltage of the load detection capacitor flows from the constant current circuit. It rises by electric charge.

  Therefore, the voltage level of the load detection capacitor represents the relative power consumption of the load device with respect to the output power of the DC power supply circuit 50. In the following description, the voltage level of the load detection capacitor is referred to as a load level.

  The shunt regulator is an example of a regulator element that stabilizes the output voltage Vd2. The photocoupler plays a role of returning the operating state of the shunt regulator from the secondary side to the primary side.

  Next, the output control circuit 53 will be described. The pulse width modulation element 53a generates a continuous or intermittent PWM (pulse width modulation) signal as the output control signal Sg1. The PWM signal is a continuous pulse signal having a constant frequency with a duty ratio adjusted according to the load level. The output control signal Sg1 is supplied to the switching element 53b.

  When the mode signal Ms0 indicates the normal mode, the pulse width modulation element 53a outputs the continuous PWM signal as the output control signal Sg1. In this case, the switching element 53b operates continuously.

  On the other hand, when the mode signal Ms0 indicates the power saving mode, the pulse width modulation element 53a outputs the alternately generated PWM signal and pause signal as the output control signal Sg1. The pause signal is a negative signal and is a control signal for stopping the switching element 53b. In this case, the switching element 53b operates intermittently.

  The switching element 53b is a field effect transistor that receives the output control signal Sg1 as a gate signal. The switching element 53b generates the primary AC voltage Vp1 by switching the primary DC voltage Vd1.

  When the output control signal Sg1 is the continuous PWM signal, the switching element 53b continuously generates the primary AC voltage Vp1 by switching the primary DC voltage Vd1 in synchronization with the PWM signal.

  The switching element 53b adjusts the power supplied to the transformer 55 according to the PWM control by the pulse width modulation element 53a. Thereby, the output voltage Vd2 of the DC power supply circuit 50 is maintained at the predetermined target voltage.

  On the other hand, when the output control signal Sg1 is the intermittent PWM signal, the switching element 53b is sequentially switched between an operation state for switching the primary DC voltage Vd1 and a stop state. That is, the switching element 53b operates intermittently.

  As described above, the pulse width modulation element 53a causes the switching element 53b in the first power supply circuit 5 to continuously execute the switching process when the operation mode of the load device is the normal mode.

  Further, the pulse width modulation element 53a causes the switching element 53b in the first power supply circuit 5 to intermittently execute the switching process when the operation mode of the load device is the power saving mode. The pulse width modulation element 53a is an example of a first control unit.

  Therefore, when the operation mode of the load device is the power saving mode, although some energy loss occurs in the transformer 55, the power consumption of the first power supply circuit 5 is greatly reduced.

  Further, the switching element 53b operates intermittently under the situation where the operation mode of the load device is the power saving mode. In this case, charge accumulation and discharge in the primary electrolytic capacitor 52b are also performed in the power saving mode.

  Therefore, in both the normal mode and the power saving mode, overvoltage of the primary electrolytic capacitor 52b is unlikely to occur. That is, the primary electrolytic capacitor 52b is not easily damaged due to the noise generated in the input voltage Va0.

[Configuration of Second Power Supply Circuit 6]
The image forming apparatus 10 further includes a second power supply control circuit 7, and the second power supply circuit 6 is electrically connected to the second power supply control circuit 7.

  Similar to the first power supply circuit 5, the second power supply circuit 6 includes a protection circuit 61, a primary rectifier circuit 62, a load feedback circuit 64, a transformer 65 and a secondary rectifier circuit 66. These perform the same functions as the protection circuit 51, the primary rectifier circuit 52, the load feedback circuit 54, the transformer 55, and the secondary rectifier circuit 56 of the first power supply circuit 5, respectively.

  Further, like the protection circuit 51, the protection circuit 61 includes a fuse 61a, a varistor 61b, and a noise filter 61c. These perform the same functions as the fuse 51a, varistor 51b, and noise filter 51c of the first power supply circuit 5, respectively.

  Further, like the primary rectifier circuit 52, the primary rectifier circuit 62 includes a bridge rectifier circuit 62a and a primary electrolytic capacitor 62b. These perform the same functions as the bridge rectifier circuit 52a and the primary electrolytic capacitor 52b of the first power supply circuit 5, respectively.

  Further, the secondary rectifier circuit 66 includes a diode 66 a and a secondary electrolytic capacitor 66 b, similarly to the secondary rectifier circuit 56. These perform the same functions as the diode 56a and the secondary electrolytic capacitor 56b of the first power supply circuit 5, respectively.

  The load feedback circuit 64 also has the same configuration as the load feedback circuit 54 of the first power supply circuit 5 and performs the same function as the load feedback circuit 54.

  Further, like the output control circuit 53, the output control circuit 63 includes a pulse width modulation element 63a and a switching element 63b. The switching element 63 b performs the same function as the switching element 63 b of the first power supply circuit 5. The switching element 63b operates using the output control signal Sg2 as a gate signal.

  Similar to the pulse width modulation element 53a of the first power supply circuit 5, the pulse width modulation element 63a of the second power supply circuit 6 generates the output control signal Sg2, and outputs the output control signal Sg2 to the switching element 63b.

  However, the pulse width modulation element 63a outputs the continuous PWM signal or the pause signal as the output control signal Sg2 in accordance with the command signal Cs0 supplied from the second power supply control circuit 7. The output control signal Sg2 will be described later.

  Note that the second power supply circuit 6 may not include the load feedback circuit 64. In this case, the pulse width modulation element 63a outputs the PWM signal having a predetermined duty ratio. Further, the load feedback circuit 54 and the pulse width modulation element 63a of the first power supply circuit 5 serve to maintain the output voltage Vd2 of the entire DC power supply circuit 50 constant.

  The second power supply control circuit 7 is a circuit that generates a command signal Cs0. Second power supply control circuit 7 includes a noise detection circuit 71 and a command output circuit 72.

  The noise detection circuit 71 is a circuit that detects the noise generated in the input voltage Va0. The noise detection circuit 71 is an example of a noise detection device. For example, the noise detection circuit 71 detects the amount or number of occurrences of the noise at the input voltage Va0.

  For example, it is conceivable that the noise detection circuit 71 includes a high-pass filter circuit and an integration circuit. The high-pass filter circuit removes a component of the rated frequency of the input voltage Va0 from the input voltage Va0. The integration circuit integrates the output signal of the high-pass filter circuit.

  When the noise detection circuit 71 outputs the output signal of the integration circuit as the noise detection signal Ns0, the noise detection signal Ns0 indicates the amount of noise generated.

  On the other hand, it is conceivable that the noise detection circuit 71 includes the high-pass filter circuit and the counter circuit. The counter circuit counts the number of times that the level of the output signal of the high-pass filter circuit exceeds a predetermined level.

  When the noise detection circuit 71 outputs the output signal of the counter circuit as the noise detection signal Ns0, the noise detection signal Ns0 indicates the number of occurrences of the noise.

  The command output circuit 72 generates a command signal Cs0 based on the mode signal Ms0 and the noise detection signal Ns0.

  Specifically, the command output circuit 72 generates a command signal Cs0 representing a stop command when the mode signal Ms0 indicates the power saving mode and the noise detection signal Ns0 does not satisfy a predetermined abnormal condition. To do.

  For example, the abnormal condition may include a first condition that the detected amount of the noise per predetermined time indicated by the noise detection signal Ns0 exceeds a predetermined first threshold value. In this case, it is conceivable that the noise detection circuit 71 includes the high-pass filter circuit and the integration circuit.

  Further, it is conceivable that the abnormal condition includes a second condition that the number of detection times of the noise per predetermined time indicated by the noise detection signal Ns0 exceeds a predetermined second threshold value. In this case, it is conceivable that the noise detection circuit 71 includes the high-pass filter circuit and the counter circuit.

  Further, when the noise detection circuit 71 includes the high-pass filter circuit, the integration circuit, and the counter circuit, the first detection signal indicating the detected amount of noise and the second detection signal indicating the number of detections of noise are converted into noise. It can be considered to output the detection signal Ns0. In this case, it is conceivable that the abnormal condition is a condition representing a logical sum or logical product of the first condition and the second condition.

  The pulse width modulation element 63a outputs the pause signal as the output control signal Sg2 when receiving the command signal Cs0 representing the stop command. Thereby, the switching process of the switching element 63b stops.

  The command output circuit 72 outputs a command signal Cs0 representing the stop command, and the mode signal Ms0 changes to a state indicating the normal mode, or the noise detection signal Ns0 satisfies the abnormal condition. When it is satisfied, a command signal Cs0 representing an operation command is generated.

  The command output circuit 72 generates a command signal Cs0 representing the operation command in the initial state.

  The pulse width modulation element 63a outputs the continuous PWM signal as the output control signal Sg2 when receiving the command signal Cs0 representing the operation command. Thereby, the switching process of the switching element 63b is executed.

  As described above, in the command output circuit 72 and the pulse width modulation element 63a, the operation mode of the load device is the power saving mode, and the detection result of the noise by the noise detection circuit 71 satisfies the abnormal condition. When not satisfy | filling, the said switching process of the switching element 63b in the 2nd power supply circuit 6 is stopped.

  Further, the command output circuit 72 and the pulse width modulation element 63a are provided when the operation mode of the load device is changed to the normal mode or when the switching process of the switching element 63b is stopped, or the noise detection circuit 71. When the detection result of the noise by satisfies the abnormal condition, the switching element 63b is caused to execute the switching process.

  The command output circuit 72 and the pulse width modulation element 63a are an example of a second control unit. The pulse width modulation element 53a, the command output circuit 72, and the pulse width modulation element 63a are an example of a control device that controls the DC power supply circuit 50.

  As described above, the second power supply circuit 6 which is one of the two power supply circuits in the DC power supply circuit 50 stops when the operation mode of the load device is the power saving mode. Thereby, the energy loss of the DC power supply circuit 50 in the power saving mode is reduced.

  Furthermore, when the noise satisfying the abnormal condition is detected when the switching element 63b of the second power supply circuit 6 is stopped, the command output circuit 72 and the pulse width modulation element 63a operate the switching element 63b. . As a result, charge is accumulated and released in the primary electrolytic capacitor 62b.

  Therefore, in both the normal mode and the power saving mode, an overvoltage of the primary electrolytic capacitor 62b hardly occurs. That is, the primary electrolytic capacitor 62b is hardly damaged due to the noise generated in the input voltage Va0.

  When the noise detection signal Ns0 changes to a state satisfying a predetermined abnormality release condition after satisfying the abnormal condition, the command output circuit 72 determines the content of the command signal Cs0 based on the mode signal Ms0. To do. That is, the command output circuit 72 outputs the command signal Cs0 representing the stop command when the mode signal Ms0 represents the power saving mode, and outputs the command signal Cs0 representing the operation command otherwise.

  For example, it is conceivable that the abnormality cancellation condition is a condition that the state in which the noise detection signal Ns0 does not satisfy the abnormality condition continues for a predetermined period.

  The noise detection signal Ns0 is also transmitted to the CPU 81. The CPU 81 executes a predetermined alarm process when the noise detection signal Ns0 satisfies the abnormal condition.

  For example, the alarm process is a process of outputting a predetermined alarm message to the display device 8b. The CPU 81 that executes the alarm process is an example of an alarm device.

  For example, the alarm message may be a message indicating that the energy loss of the DC power supply circuit 50 may increase due to noise of the AC input voltage Va0.

[Application example]
In the image forming apparatus 10, the command output circuit 72 may output a command signal Cs0 selected from three types of signals. The three types of signals are signals representing the stop command, continuous operation command, and intermittent operation command.

  The command signal Cs0 representing the stop command is a signal for instructing to stop the switching element 63b as described above. The command signal Cs0 representing the continuous operation command is a signal that instructs the switching element 63b to operate continuously. The command signal Cs0 representing the intermittent operation command is a signal for instructing the intermittent operation of the switching element 63b.

  In this application example, the pulse width modulation element 63a outputs the continuous PWM signal as the output control signal Sg2 when receiving the command signal Cs0 representing the continuous operation command. Thereby, the switching element 63b operates continuously.

  Further, the pulse width modulation element 63a outputs the intermittent PWM signal as the output control signal Sg2 when receiving the command signal Cs0 representing the intermittent operation command. Thereby, the switching element 63b operates intermittently.

  The pulse width modulation element 63a outputs the pause signal as the output control signal Sg2 when receiving the command signal Cs0 representing the stop command. Thereby, the switching element 63b stops.

  The command output circuit 72 outputs a command signal representing the stop command when the operation mode of the load device is the power saving mode and the noise detection signal Ns0 does not satisfy the abnormal condition. This point is as described above.

  In this application example, the command output circuit 72 is a command signal representing the continuous operation command when the operation mode of the load device is changed to the normal mode when the switching process of the switching element 63b is stopped. Cs0 is output.

  On the other hand, the command output circuit 72 outputs the command signal Cs0 representing the intermittent operation command when the noise detection signal Ns0 satisfies the abnormal condition when the switching process of the switching element 63b is stopped.

  According to this application example, the energy loss of the second power supply circuit 6 when the noise detection signal Ns0 satisfies the abnormal condition can be minimized.

3: Sheet conveyance mechanism 4: Image forming unit 5: First power supply circuit (first power supply unit)
6: Second power supply circuit (second power supply unit)
7: Second power supply control circuit 8: Control board 8a: Controller 8b: Display device 9: Sheet 10: Image forming device 30: Sheet feeding mechanism 31: Conveying roller pair 40: Optical scanning unit 41: Photoconductor 42: Charging device 43: Developing device 44: Toner replenishing unit 45: Transfer device 46: Cleaning device 47: Fixing device 50: DC power supply circuit (DC power supply device)
51: protection circuit 51a: fuse 51b: varistor 51c: noise filter 52: primary rectifier circuit 52a: bridge rectifier circuit 52b: primary electrolytic capacitor 53: output control circuit 53a: pulse width modulation element (first control unit)
53b: Switching element 54: Load feedback circuit 55: Transformer 56: Secondary rectifier circuit 56a: Diode 56b: Secondary electrolytic capacitor 61: Protection circuit 61a: Fuse 61b: Varistor 61c: Noise filter 62: Primary rectifier circuit 62a: Bridge rectifier Circuit 62b: Primary electrolytic capacitor 63: Output control circuit 63a: Pulse width modulation element (second control unit)
63b: switching element 64: load feedback circuit 65: transformer 66: secondary rectifier circuit 66a: diode 66b: secondary electrolytic capacitor 71: noise detection circuit (noise detection device)
72: Command output circuit (second control unit)
81: CPU
82: Storage device 90: Toner 100: Main body 101: Sheet container 102: Ventilation fan 103: Dehumidifying heater 300: Sheet conveyance path 400: Motor 470: Fixing heater 471: Fixing temperature sensor 1000: External power supply Cs0: Command signal Ms0: Mode signal Ns0: Noise detection signal Sg1: Output control signal Sg2: Output control signal Va0: Input voltage Vd1: Primary DC voltage Vd2: Output voltage Vp1: Primary AC voltage Vp2: Secondary AC voltage

Claims (5)

A primary rectifier circuit including an electrolytic capacitor, rectifying an AC input voltage supplied from the outside, and outputting a primary DC voltage;
A switching element that generates a primary AC voltage by switching the primary DC voltage;
A transformer for converting the primary AC voltage into a secondary AC voltage;
A secondary rectifier circuit that rectifies the secondary AC voltage and outputs a secondary DC voltage;
A load device to which the secondary DC voltage is applied, including a device related to an image forming process for forming an image on a sheet;
A noise detection device for detecting noise generated in the input voltage;
When the operation mode of the load device is a power saving mode in which the power consumption is smaller than that in the normal mode, and the detection result of the noise by the noise detection device does not satisfy a predetermined abnormal condition, When the switching process is stopped and the switching process of the switching element is stopped, when the operation mode of the load device is changed to the normal mode, or the detection result of the noise by the noise detection device is the abnormality An image forming apparatus comprising: a control device that causes the switching element to execute the switching process when a condition is satisfied.   The control device causes the switching element to continuously execute the switching process when an operation mode of the load device changes to the normal mode when the switching process of the switching element is stopped, The switching element is caused to intermittently execute the switching process when the noise detection result by the noise detection device satisfies the abnormal condition when the switching process of the switching element is stopped. The image forming apparatus described.   The image forming apparatus according to claim 1, wherein the abnormal condition includes a condition that an amount of detection or the number of detections of the noise by the noise detection apparatus exceeds a predetermined threshold value. The DC power supply device includes a first power supply device and a second power supply device, which include the primary rectifier circuit, the switching element, the transformer, and the secondary rectifier circuit, respectively, and apply the secondary DC voltage to the load device. ,
The control device includes:
When the operation mode of the load device is the normal mode, the switching element in the first power supply device is caused to continuously execute the switching process, and the operation mode of the load device is the power saving mode. A first controller that causes the switching element in the first power supply device to intermittently execute the switching process;
When the operation mode of the load device is the power saving mode and the detection result of the noise by the noise detection device does not satisfy the abnormal condition, the switching process of the switching element in the second power supply device is stopped. When the switching mode of the switching element is stopped and the operation mode of the load device is changed to the normal mode, or the detection result of the noise by the noise detection device satisfies the abnormal condition The image forming apparatus according to claim 1, further comprising: a second control unit that causes the switching element to execute the switching process.   The image forming apparatus according to claim 1, further comprising an alarm device that executes a predetermined alarm process when the noise is detected by the noise detection device.

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