JP2019033382A - Signal transmitter and signal transmission system - Google Patents

Abstract

To provide a signal transmitter and a signal transmission system capable of inhibiting power consumption more than before.SOLUTION: A signal transmitter includes a sense amplifier performing sensing operation outputting a first sensing signal having a signal value, corresponding to the difference of potential between first and second signal lines, and a second sensing signal having a signal value different from that of the first sensing signal, when the signal value of a clock signal is a first value, and stopping the sensing operation when the signal value of the clock signal is a second value, and a logic circuit for changing the potential of the first signal line according to logical operation results of signal value each of the data signal, the clock signal and the first sensing signal, and changing the potential of the second signal line according to logical operation results of signal value each of the data signal, the clock signal and the second sensing signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a signal transmission device and a signal transmission system.

  The following technologies are known as technologies related to signal transmission devices. For example, Patent Document 1 incorporates a CMOS clamp circuit, transmits a signal using a clamp amplitude voltage having a very small amplitude, receives a signal from the transmitter circuit, performs waveform reproduction, and has a hysteresis characteristic as an input threshold value. A transmission circuit that has a receiving circuit and performs signal transmission between the transmitting circuit and the receiving circuit is described. A large-scale integrated circuit device for a transmission circuit includes a signal transmission circuit including a plurality of unit transmission circuits. Each unit transmission circuit is provided with a level detection circuit including a level shift circuit and a sense amplifier. The transmission circuit is connected to the large-scale integrated circuit device of the reception circuit via a transmission line. A large-scale integrated circuit device of a receiving circuit is composed of a plurality of unit receiving circuits including a level shift circuit and a sense amplifier.

JP 7-297688 A

  The sense amplifier provided in the transmission circuit and the reception circuit described in Patent Document 1 always consumes power because a static operation is required.

  An object of this invention is to provide the signal transmission apparatus and signal transmission system which can suppress power consumption more than before.

  In the signal transmission device according to the present invention, when the signal value of the input clock signal is the first value, the potential of the first signal line and the potential of the second signal line different from the first signal line are A sensing operation for outputting a first sensing signal having a signal value corresponding to the difference between the first sensing signal and a second sensing signal having a signal value different from the signal value of the first sensing signal, and the signal value of the clock signal Is a second value different from the first value, a sense amplifier that stops the sensing operation, and a logical operation of each signal value of the input data signal, the clock signal, and the first sensing signal The potential of the first signal line is changed according to a result, and the potential of the second signal line is changed according to a logical operation result of each signal value of the data signal, the clock signal, and the second sensing signal. The Including a logic circuit for reduction, the.

  In another signal transmission device according to the present invention, when the signal value of the input clock signal is the first value, the potential of the first signal line and the second signal line different from the first signal line A sensing operation for outputting a first sensing signal having a signal value corresponding to a difference from the potential and a second sensing signal having a signal value different from the signal value of the first sensing signal is performed, and the clock signal When the signal value is a second value different from the first value, the sense amplifier that stops the sensing operation, the signal value of the first sensing signal, and the signal value of the second sensing signal And an output circuit for generating an output signal having a signal value.

  Another signal transmission system according to the present invention includes a first signal transmission device, a first signal transmission device, a first signal line, and a second signal line different from the first signal line. And a second signal transmission device connected to be communicable. When the signal value of the input clock signal is the first value, the first signal transmission device has a signal value corresponding to a difference between the potential of the first signal line and the potential of the second signal line. And a first sensing operation for outputting a second sensing signal having a signal value different from the signal value of the first sensing signal, and the signal value of the clock signal is the first sensing signal. When the second value is different from the first value, each of the first sense amplifier that stops the first sensing operation, the first data signal, the clock signal, and the first sensing signal that are input. The potential of the first signal line is changed according to the logical operation result of the signal value, and according to the logical operation result of the signal values of the first data signal, the clock signal, and the second sensing signal. Said second signal Including the a first logic circuit for changing the potential. When the signal value of the clock signal is the first value, the second signal transmission device has a signal value corresponding to a difference between the potential of the first signal line and the potential of the second signal line. A second sensing operation for outputting a third sensing signal and a fourth sensing signal having a signal value different from a signal value of the third sensing signal, and the signal value of the clock signal is the second sensing signal. A second sense amplifier that stops the second sensing operation when the value is a value, and generates an output signal having a signal value corresponding to the signal value of the third sensing signal and the signal value of the fourth sensing signal A first output circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the signal transmission apparatus and signal transmission system which can suppress power consumption more than before are provided.

1 is a block diagram illustrating a configuration of a signal transmission system according to a first embodiment of the present invention. It is a figure which shows the detailed structure of the sense amplifier which concerns on embodiment of this invention. It is a time chart which shows an example of the signal transmission performed between the master part which concerns on embodiment of this invention, and a slave part It is a figure which shows the result of having performed operation verification about the signal transmission system which concerns on the 1st Embodiment of this invention using a SPICE simulator. It is a block diagram which shows the structure of the signal transmission system which concerns on the 2nd Embodiment of this invention. It is a figure which shows the detailed structure of the logic circuit which concerns on embodiment of this invention. It is a time chart which shows an example of the signal transmission performed between the master part which concerns on embodiment of this invention, and a slave part. It is a figure which shows the result of having performed operation verification using the SPICE simulator about the signal transmission system which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the signal transmission system which concerns on the 3rd Embodiment of this invention. It is a figure which shows the detailed structure of the logic circuit which concerns on embodiment of this invention. It is a time chart which shows an example of operation | movement of C element which concerns on embodiment of this invention. It is a time chart which shows an example of the signal transmission performed between the master part which concerns on embodiment of this invention, and a slave part. It is a block diagram which shows the structure of the signal transmission system which concerns on the 4th Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a signal transmission system 1 according to the first embodiment of the present invention. The signal transmission system 1 includes a master unit 10, a slave unit 20, and a transmission line 30 provided between the master unit 10 and the slave unit 20. In the present embodiment, the master unit 10 functions as a transmission device that transmits a signal to the transmission line 30, and the slave unit 20 functions as a reception device that receives a signal transmitted from the master unit 10. Each of the master unit 10 and the slave unit 20 is an example of a signal transmission device according to the present invention.

  The transmission line 30 includes a first signal line L1, a second signal line L2, and a clock signal line L3, and signals transmitted from the master unit 10 are the first signal line L1 and the second signal line. The data is transmitted to the slave unit 20 via L2. The clock signal (system clock) sent from the master unit 10 is transmitted to the slave unit 20 via the clock signal line L3. The master unit 10 and the slave unit 20 operate in synchronization with the clock signal.

  The master unit 10 includes a data input terminal din to which data to be transmitted to the slave unit 20 is input and a clock input terminal ckin to which a clock signal is input. The master unit 10 includes a sense amplifier 100m, a logic circuit, and a D flip-flop (hereinafter referred to as D-FF) 13.

  The data input terminal D of the D-FF 13 is connected to the data input terminal din, and the clock input terminal C of the D-FF 13 is connected to the clock input terminal ckin. The D-FF 13 captures and holds the signal value of the data signal input to the data input terminal D at the rising edge of the clock signal input to the clock input terminal C, and the stored signal value from the data output terminal Q. Output.

  The logic circuit includes three-input NAND circuits 11 and 12. The NAND circuit 11 has a first input terminal connected to the data output terminal Q of the D-FF 13, a second input terminal connected to the clock input terminal ckin, and a third input terminal connected to the output terminal out of the sense amplifier 100m. It is connected to the. Note that a value obtained by logically inverting the signal value output from the output terminal out of the sense amplifier 100m is input to the third input terminal of the NAND circuit 11. The output terminal of the NAND circuit 11 is connected to the first signal line L1 and the first input terminal of the sense amplifier 100m.

  The NAND circuit 12 has a first input terminal connected to the data output terminal Q of the D-FF 13, a second input terminal connected to the clock input terminal ckin, and a third input terminal connected to the output terminal outb of the sense amplifier 100m. It is connected to the. Note that a value obtained by logically inverting the signal value output from the data output terminal Q of the D-FF 13 is input to the first input terminal of the NAND circuit 12. A value obtained by logically inverting the signal value output from the output terminal outb of the sense amplifier 100m is input to the third input terminal of the NAND circuit 12. The output terminal of the NAND circuit 12 is connected to the second signal line L2 and the second input terminal of the sense amplifier 100m.

  The sense amplifier 100m has three input terminals and two output terminals out and outb. The first input terminal of the sense amplifier 100m is connected to the first signal line L1, and is also connected to the output terminal of the NAND circuit 11, and the second input terminal is connected to the second signal line L2. At the same time, it is connected to the output terminal of the NAND circuit 12, and the third input terminal is connected to the clock input terminal ckin via the buffer 14.

  On the other hand, the slave unit 20 has a data output terminal dout that outputs a data signal transmitted from the master unit 10 and received by the slave unit 20. The slave unit 20 includes a sense amplifier 100s, an RS flip-flop (hereinafter referred to as RS-FF) 21, and a D-FF 24. The RS flip-flop (hereinafter referred to as RS-FF) 21 and the D-FF 24 are examples of the output circuit in the present invention.

  The sense amplifier 100 s has the same configuration as the sense amplifier 100 m provided in the master unit 10. That is, the sense amplifier 100s has three input terminals and two output terminals out and outb. The sense amplifier 100s has a first input terminal connected to the first signal line L1, a second input terminal connected to the second signal line L2, and a third input terminal connected to the clock signal line L3. It is connected.

  The RS-FF 21 includes NOR circuits 22 and 23. The first input terminal of the NOR circuit 22 is connected to the output terminal out of the sense amplifier 100 s, and the second input terminal is connected to the output terminal of the NOR circuit 23. The output terminal of the NOR circuit 22 is connected to the first input terminal of the NOR circuit 23. The second input terminal of the NOR circuit 23 is connected to the output terminal outb of the sense amplifier 100s, the output terminal of the NOR circuit 23 is connected to the output terminal ffo of the RS-FF 21, and is connected to the data input terminal D of the D-FF 24. Has been. When the signal value of the sensing signal output from the output terminal out of the sense amplifier 100s transitions to “1”, the RS-FF 21 transitions the signal value of the output signal output from the output terminal ffo to “1”. When the signal value of the sensing signal output from the output terminal outb of the amplifier 100s transitions to “1”, the signal value of the output signal output from the output terminal ffo transitions to “0”.

  The data input terminal D of the D-FF 24 is connected to the output terminal ffo of the RS-FF, and the clock input terminal C of the D-FF 24 is connected to the clock signal line L3 via the buffer 25, and the data output of the D-FF 24 The end Q is connected to the data output terminal dout. The D-FF 24 captures and holds the signal value of the data signal input to the data input terminal D at the falling edge of the clock signal input to the clock input terminal C, and the stored signal value to the data output terminal Q. Output from.

  FIG. 2 is a diagram illustrating a detailed configuration of the sense amplifier 100 m provided in the master unit 10 and the sense amplifier 100 s provided in the slave unit 20. The sense amplifiers 100m and 100s have the same configuration and include a differential circuit 150 and a latch circuit 160.

  The differential circuit 150 includes N-channel MOSFETs (hereinafter referred to as N-MOS) 101, 102, 103 and P-channel MOSFETs (hereinafter referred to as P-MOS) 104, 105. Yes. The N-MOS 101 has a gate connected to the node MO (node SI) which is a node of the first signal line L1, a drain connected to the drain of the P-MOS 104, and a source connected to the drain of the N-MOS 103. . The N-MOS 102 has a gate connected to the node MOb (node SIb) which is a node of the second signal line L2, a drain connected to the drain of the P-MOS 105, and a source connected to the drain of the N-MOS 103. . The N-MOS 103 has a gate connected to the node SCK which is a node of the clock signal line, and a source connected to the ground line. In each of the P-MOSs 104 and 105, the source is connected to the power supply line, and the gate is connected to a node SCK that is an output node of the buffer 14.

  The latch circuit 160 includes N-MOSs 111 to 116 and P-MOSs 117 to 120.

  The N-MOS 111 has a gate connected to the drain of the N-MOS 102 and the gate of the P-MOS 117, a drain connected to the drain of the P-MOS 119 and the output terminal out of the sense amplifier, and a source connected to the ground line. The N-MOS 112 has a gate connected to the gate of the P-MOS 119 and the output end outb of the sense amplifier, a drain connected to the drain of the P-MOS 119 and the output end out of the sense amplifier, and a source connected to the ground line. . The N-MOS 115 has a gate connected to the gate of the P-MOS 117, a drain connected to the drain of the P-MOS 117, and a source connected to the source of the N-MOS 116. The P-MOS 117 has a source connected to the power supply line and a drain connected to the source of the P-MOS 119.

  The N-MOS 114 has a gate connected to the drain of the N-MOS 101 and the gate of the P-MOS 118, a drain connected to the drain of the P-MOS 120 and the output terminal outb of the sense amplifier, and a source connected to the ground line. The N-MOS 113 has a gate connected to the gate of the P-MOS 120 and the output end out of the sense amplifier, a drain connected to the drain of the P-MOS 120 and the output end outb of the sense amplifier, and a source connected to the ground line. . The N-MOS 116 has a gate connected to the gate of the P-MOS 118, a drain connected to the drain of the P-MOS 118, and a source connected to the source of the N-MOS 115. The P-MOS 118 has a source connected to the power supply line and a drain connected to the source of the P-MOS 120.

  Hereinafter, operations of the sense amplifiers 100m and 100s will be described. When the signal value of the clock signal input to the gate of the N-MOS 103 is “0”, the sense amplifiers 100 m and 100 s stop the sensing operation, and the node vx that is the drain node of the N-MOS 102 and the drain of the N-MOS 101. The node vxb, which is a node, is precharged at the power supply voltage level. On the other hand, in the sense amplifiers 100m and 100s, when the signal value of the clock signal input to the gate of the N-MOS 103 is “1”, the node MO (node SI) and the second signal line L2 of the first signal line L1. A sensing operation is performed to sense the state of the node MOb (node SIb).

  When the potential of the node MO of the first signal line L1 is lower than the potential of the node MOb of the second signal line L2, the resistance value of the N-MOS 101 becomes higher than the resistance value of the N-MOS 102. The discharge rate of vx is faster than the discharge rate of node vxb. Therefore, the signal value of the output terminal out connected to the latch circuit 160 at the subsequent stage becomes “1” before the output terminal outb.

  On the other hand, when the potential of the node MOb of the second signal line L2 is lower than the potential of the node MO of the first signal line L1, the resistance value of the N-MOS 102 becomes higher than the resistance value of the N-MOS 101. The discharge speed of the node vxb is faster than the discharge speed of the node vx. Accordingly, the signal value of the output terminal outb connected to the latch circuit 160 at the subsequent stage becomes “1” before the output terminal out.

  Next, the operation of the signal transmission system 1 will be described. FIG. 3 is a time chart illustrating an example of signal transmission performed between the master unit 10 and the slave unit 20. In the signal transmission system 1, the master unit 10 transmits the data signal input to the signal input terminal din to the slave unit 20 via the first signal line L1 and the second signal line L2. When the signal value of the data signal transmitted from the master unit 10 is “1”, signal transmission is performed using the first signal line L1 (node MO), and the signal value of the data signal transmitted from the master unit 10 Is “0”, signal transmission is performed using the second signal line L2 (node MOb).

  As an initial state, the signal value of the node d at the output terminal Q of the D-FF 13 is set to “0”, and the node MO of the first signal line L1 and the node MOb of the second signal line L2 are at the power supply voltage level. It is assumed that it is precharged.

  As shown in [1], when the signal value of the clock signal transits to “1”, the signal value of the node d at the output terminal Q of the D-FF 13 transits to “1”. At this time, since the signal values of the output terminals out and outb of the sense amplifier 100m are both “0”, all three input values of the NAND circuit 11 are “1”, and the output value of the NAND circuit 11 is “0”. " As a result, as shown in [2], the node MO of the first signal line L1 is discharged, and the voltage level decreases. On the other hand, when the signal value of the node d transitions to “1”, one input value of the NAND circuit 12 becomes “0”, so that the output value of the NAND circuit 12 becomes “1”. As a result, the node MOb of the second signal line L2 is precharged at the power supply voltage level.

  When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10 and the sense amplifier 100s of the slave unit 20 start a sensing operation. As shown in [2], when the potential of the node MO of the first signal line L1 becomes lower than the potential of the node MOb of the second signal line L2, the sense amplifiers 100m and 100s are respectively set to [3]. As shown, a sensing signal having a signal value “1” is output from the output terminal out.

  Accordingly, in the master unit 10, the output value of the NAND circuit 11 transitions from “0” to “1”, so that the node MO of the first signal line L1 is, as shown in [4], Precharged at power supply voltage level. On the other hand, in the slave unit 20, the signal value output from the output terminal ffo of the RS-FF 21 is “1”.

  As shown in [5], when the signal value of the clock signal transits to “0”, the signal value “1” output from the output terminal ffo of the RS-FF 21 is output from the data output terminal dout in the slave unit 20. Is done. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”.

  As shown in [6], when the signal value of the clock signal transits to “1”, the signal value of the node d at the output terminal Q of the D-FF 13 transits to “0”. At this time, since the signal values of the output terminals out and outb of the sense amplifier 100m are both “0”, all three input values of the NAND circuit 12 are “1”, and the output value of the NAND circuit 12 is “0”. " As a result, as shown in [7], the node MOb of the second signal line L2 is discharged, and the voltage level decreases. On the other hand, when the signal value of the node d transitions to “0”, one input value of the NAND circuit 11 becomes “0”, so that the output value of the NAND circuit 11 becomes “1”. As a result, the node MO of the first signal line L1 is precharged at the power supply voltage level.

  When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10 and the sense amplifier 100s of the slave unit 20 start a sensing operation. As shown in [7], when the potential of the node MOb of the second signal line L2 becomes lower than the potential of the node MO of the first signal line L1, the sense amplifiers 100m and 100s are respectively set to [8]. As shown, a sensing signal having a signal value “1” is output from the output end outb.

  Accordingly, in the master unit 10, the output value of the NAND circuit 12 transitions from “0” to “1”, so that the node MOb of the second signal line L2 is, as shown in [9], Precharged at power supply voltage level. On the other hand, in the slave unit 20, the signal value output from the output terminal ffo of the RS-FF 21 is “0”.

  As shown in [10], when the signal value of the clock signal transits to “0”, the signal value “0” output from the output terminal ffo of the RS-FF 21 is output from the data output terminal dout in the slave unit 20. Is done. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”.

  As described above, the sense amplifiers 100m and 100s provided in the master unit 10 and the slave unit 20 respectively have the potential of the first signal line L1 and the second signal level when the signal value of the clock signal is “1”. The sensing operation of outputting the first sensing signal and the second sensing signal having signal values corresponding to the difference from the potential of the signal line L2 from the output end out and the output end outb, respectively, and the signal value of the clock signal When “0” is “0”, the sensing operation is stopped. That is, the sense amplifiers 100m and 100s operate intermittently according to the signal value of the clock signal. Therefore, power consumption can be suppressed as compared with a conventional sense amplifier that always consumes power.

  Further, the sense amplifiers 100m and 100s can detect even a slight potential difference between the first signal line L1 (node MO) and the second signal line L2 (node MOb). The amplitude va (see FIG. 3) of signals transmitted to the first signal line L1 (node MO) and the second signal line L2 (node MOb) can be reduced. That is, since the amount of discharge charges of the first signal line L1 and the second signal line L2 when performing signal transmission can be suppressed, power saving can be achieved also in this respect.

  The operation of the signal transmission system 1 according to the first embodiment of the present invention was verified using a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator. FIG. 4 shows the result. The simulation conditions were a power supply voltage of 1.5 V, an ambient temperature of 27 ° C., and an operating frequency of 1 MHz. Further, it is assumed that a load capacity of 10 pF is connected to the transmission line 30. The input waveforms of the data signal and the clock signal were the same as those shown in the time chart of FIG. As a result, it was confirmed that the signal transmission system 1 operates in the same manner as the time chart of FIG. Further, the amplitude va of the signal transmitted to the first signal line L1 (node MO) and the second signal line L2 (node MOb) can be reduced to 35 mV.

[Second Embodiment]
FIG. 5 is a block diagram showing a configuration of a signal transmission system 1A according to the second exemplary embodiment of the present invention.

  In the signal transmission system 1 according to the first embodiment described above, the first signal line L1 (node MO) or the second signal line L2 (node MOb) is discharged by the sense amplifiers 100m and 100b. When a potential difference between the signal lines is detected, it is immediately precharged at the power supply voltage level. Therefore, for example, in the signal value of the signal transmitted from the master unit 10 to the slave unit 20, when the same value continues like “00...” Or “11. The signal line is repeatedly discharged and precharged with respect to the value signal, and power is consumed each time.

  On the other hand, in the signal transmission system 1A according to the second embodiment of the present invention, when the same value continues in the signal value of the signal transmitted from the master unit 10 to the slave unit 20, a plurality of consecutive identical values. For the value signal, the signal line is discharged and precharged only once, and the power consumption is further reduced.

  In the signal transmission system 1A, the configuration of the master unit 10A is different from the master unit 10 in the signal transmission system 1 according to the first embodiment. On the other hand, in the signal transmission system 1A, the configuration of the slave unit 20 is the same as that of the slave unit 20 configuring the signal transmission system 1 according to the first embodiment.

  The master unit 10A has a data input terminal din to which data to be transmitted to the slave unit 20 is input and a clock input terminal ckin to which a clock signal is input. The master unit 10 includes a sense amplifier 100m, a logic circuit 200, and D-FFs 13a and 13b.

  The data input terminal D of the D-FF 13a is connected to the data input terminal din, the data output terminal Q of the D-FF 13a is connected to the data input terminal Q of the D-FF 13b and the logic circuit 200, and the clock input of the D-FF 13a. The end C is connected to the clock input terminal ckin. The data output terminal Q of the D-FF 13b is connected to the logic circuit 200, and the clock input terminal C of the D-FF 13b is connected to the clock input terminal ckin. The D-FFs 13a and 13b capture and hold the signal value of the data signal input to the data input terminal D at the falling edge of the clock signal input to the clock input terminal C, and output the stored signal value as data. Output from terminal Q.

  The logic circuit 200 is connected to the first signal line L1, the second signal line L2, the output terminals out and outb of the sense amplifier 100m, and the clock input terminal ckin.

  FIG. 6 is a diagram illustrating a detailed configuration of the logic circuit 200. The logic circuit 200 includes NOT circuits 201 to 204, AND circuits 211 to 214, and NOR circuits 215 and 216. The logic circuit 200 includes N-MOSs 221 to 223 and P-MOSs 231 and 232.

  The input terminal of the NOT circuit 201 is connected to the node d [1] of the data output terminal Q of the D-FF 13a. The output terminal of the NOT circuit 201 is the input terminal of the NOT circuit 202, one input terminal of the NOR circuit 215, One input terminal of the AND circuit 213 is connected to the gate of the P-MOS 232. The output terminal of the NOT circuit 202 is connected to the gate of the P-MOS 231, one input terminal of the AND circuit 211, and one input terminal of the NOR circuit 216. The input terminal of the NOT circuit 203 is connected to the node d [0] of the data output terminal Q of the D-FF 13b. The output terminal of the NOT circuit 203 is connected to the input terminal of the NOT circuit 204 and the other input terminal of the AND circuit 213. Each is connected. The output terminal of the NOT circuit 204 is connected to the other input terminal of the AND circuit 211.

  The output terminal of the AND circuit 211 is connected to the other input terminal of the NOR circuit 215. The output terminal of the NOR circuit 215 is connected to one input terminal of the AND circuit 212. The other input terminal of the AND circuit 212 is connected to the output terminal out of the sense amplifier 100m. Note that a value obtained by logically inverting the signal value output from the output terminal out of the sense amplifier 100m is input to the other input terminal of the AND circuit 212. The output terminal of the AND circuit 212 is connected to the gate of the N-MOS 221.

  The output terminal of the AND circuit 213 is connected to the other input terminal of the NOR circuit 216. The output terminal of the NOR circuit 216 is connected to one input terminal of the AND circuit 214. The other input terminal of the AND circuit 214 is connected to the output terminal outb of the sense amplifier 100m. Note that a value obtained by logically inverting the signal value output from the output terminal outb of the sense amplifier 100m is input to the other input terminal of the AND circuit 214. The output terminal of the AND circuit 214 is connected to the gate of the N-MOS 222.

  The N-MOS 221 has a drain connected to the node MO of the first signal line L 1 and the drain of the P-MOS 231, and a source connected to the drain of the N-MOS 223. The N-MOS 222 has a drain connected to the node MOb of the second signal line L2 and the drain of the P-MOS 232, and a source connected to the drain of the N-MOS 223. The gate of the N-MOS 223 is connected to the clock input terminal ckin, and the source is connected to the ground line. Each of the P-MOSs 231 and 232 has a source connected to the power supply line.

  The operation of the signal transmission system 1A will be described below. FIG. 7 is a time chart illustrating an example of signal transmission performed between the master unit 10 </ b> A and the slave unit 20. In the signal transmission system 1A, the master unit 10A transmits the data signal input to the signal input terminal din to the slave unit 20 via the first signal line L1 and the second signal line L2. When the signal value of the data signal transmitted from the master unit 10A is “1”, signal transmission is performed using the first signal line L1 (node MO), and the signal value of the data signal transmitted from the master unit 10A. Is “0”, signal transmission is performed using the second signal line L2 (node MOb).

  As an initial state, the signal value of the node d [0] at the output terminal Q of the D-FF 13b is “0”, the signal value of the node d [1] at the output terminal Q of the D-FF 13a is “1”, The node MO of the first signal line L1 and the node MOb of the second signal line L2 are precharged at the power supply voltage level. Further, a data signal having a signal value “0” is input to the data input terminal din of the master unit 10A in the first period, and a data signal having a signal value “1” is continuously input in the second period and the third period. , And the data signal is transmitted from the master unit 10A to the slave unit 20.

  As shown in [1], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] at the output terminal Q of the D-FF 13b transits to “1”, and the output of the D-FF 13a. The signal value of the node d [1] at the end Q transitions to “0”. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”. Accordingly, the N-MOS 222 and the P-MOS 231 of the logic circuit 200 are turned on, and the N-MOS 221 and the P-MOS 232 are turned off. As a result, the node MO of the first signal line L1 is precharged at the power supply voltage level.

  As shown in [2], when the signal value of the clock signal transitions to “1”, the N-MOS 223 of the logic circuit 200 is turned on. As a result, the node MOb of the second signal line L2 is discharged, and the voltage level decreases. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10A and the sense amplifier 100s of the slave unit 20 start a sensing operation. When the potential of the node MOb of the second signal line L2 becomes lower than the potential of the node MO of the first signal line L1, the sense amplifiers 100m and 100s are respectively connected from the output terminal outb as shown in [3]. A sensing signal having a signal value “1” is output. When the signal value of the output terminal outb of the sense amplifier 100m transitions to “1”, the N-MOS 222 of the logic circuit 200 is turned off. Since the logic circuit N-MOS 232 maintains the OFF state, the potential of the node MOb of the second signal line L2 maintains a low level as shown in [4]. In the slave unit 20, the signal value output from the output terminal ffo of the RS-FF 21 becomes “0” when the signal value of the output terminal outb of the sense amplifier 100 s transitions to “1”.

  As shown in [5], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] at the output terminal Q of the D-FF 13b transits to “0” and the output of the D-FF 13a. The signal value of the node d [1] at the end Q transitions to “1”. In the slave unit 20, the signal value “0” output from the output terminal ffo of the RS-FF 21 is output from the data output terminal dout. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”. As a result, the N-MOS 221 and the P-MOS 232 of the logic circuit 200 are turned on, and the N-MOS 222 and the P-MOS 231 are turned off. As a result, the node MOb of the second signal line L2 is precharged at the power supply voltage level.

  As shown in [6], when the signal value of the clock signal transits to “1”, the N-MOS 223 of the logic circuit 200 is turned on. As a result, the node MO of the first signal line L1 is discharged, and the voltage level decreases. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10A and the sense amplifier 100s of the slave unit 20 start a sensing operation. When the potential of the node MO of the first signal line L1 is lower than the potential of the node MOb of the second signal line L2, the sense amplifiers 100m and 100s are respectively connected from the output terminal out as shown in [7]. A sensing signal having a signal value “1” is output. When the signal value of the output terminal out of the sense amplifier 100m transitions to “1”, the N-MOS 221 of the logic circuit is turned off. Since the logic circuit P-MOS 231 maintains the OFF state, as shown in [8], the potential of the node MO of the first signal line L1 is maintained at a low level. In the slave unit 20, the signal value output from the output terminal ffo of the RS-FF 21 becomes “1” when the signal value of the output terminal out of the sense amplifier 100 s transitions to “1”.

  As shown in [9], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] of the output terminal Q of the D-FF 13b transits to “1”, and the output of the D-FF 13a The signal value of the node d [1] at the end Q is maintained at “1”. In the slave unit 20, the signal value “1” output from the output terminal ffo of the RS-FF 21 is output from the data output terminal dout. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”. As a result, the P-MOS 232 of the logic circuit 200 is turned on, and the N-MOSs 221 and 222 and the P-MOS 231 are turned off. Therefore, as shown in [10], the potential of the node MO of the first signal line L1 is maintained at a low level.

  As shown in [11], when the signal value of the clock signal transits to “1”, the N-MOS 223 of the logic circuit 200 is turned on. Since the N-MOSs 221 and 222 of the logic circuit are in the OFF state, the node MO of the first signal line L1 and the node MOb of the second signal line L2 are not discharged. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10A and the sense amplifier 100s of the slave unit 20 start a sensing operation. Since the potential of the node MO of the first signal line L1 is kept lower than the potential of the node MOb of the second signal line L2, the sense amplifiers 100m and 100s are respectively shown in [12]. In addition, a sensing signal having a signal value “1” is output from the output terminal out. When the signal value of the output terminal out of the sense amplifier 100m transitions to “1”, the N-MOS 221 of the logic circuit is turned off. Since the logic circuit P-MOS 231 maintains the OFF state, as shown in [13], the potential of the node MO of the first signal line L1 is maintained at a low level. In the slave unit 20, the signal value output from the output terminal ffo of the RS-FF 21 is maintained at “1” when the signal value of the output terminal out of the sense amplifier 100 s transitions to “1”.

  As shown in [14], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] of the output terminal Q of the D-FF 13b maintains “1”, and the output of the D-FF 13a. The signal value of the node d [1] at the end Q transitions to “0”. In the slave unit 20, the signal value “1” output from the output terminal ffo of the RS-FF 21 is output from the data output terminal dout. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”.

  As described above, according to the signal transmission system 1A according to the present embodiment, the sense amplifiers 100m and 100s intermittently correspond to the signal value of the clock signal, similarly to the signal transmission system 1 according to the first embodiment. Since it operates, the power consumption can be suppressed as compared with a conventional sense amplifier that always consumes power.

  Further, the sense amplifiers 100m and 100s can detect even a slight potential difference between the first signal line L1 (node MO) and the second signal line L2 (node MOb). The amplitude va (see FIG. 7) of signals transmitted to the first signal line L1 (node MO) and the second signal line L2 (node MOb) can be reduced. That is, since the amount of discharge charges of the first signal line L1 and the second signal line L2 when performing signal transmission can be suppressed, power saving can be achieved also in this respect.

  Further, according to the signal transmission system 1A according to the present embodiment, the signal value of the signal transmitted from the master unit 10A to the slave unit 20A is the same as “00...” Or “11. When the values are continuous, the signal line is discharged and precharged only once for a plurality of continuous signals of the same value, so that the effect of suppressing power consumption can be further promoted.

  The operation of the signal transmission system 1A according to the second embodiment of the present invention was verified using a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator. FIG. 8 shows the result. The simulation conditions were a power supply voltage of 1.5 V, an ambient temperature of 27 ° C., and an operating frequency of 1 MHz. Further, it is assumed that a load capacity of 10 pF is connected to the transmission line 30. The input waveforms of the data signal and the clock signal were the same as those shown in the time chart of FIG. As a result, it was confirmed that the signal transmission system 1A operates similarly to the time chart of FIG. Further, the amplitude va of the signal transmitted to the first signal line L1 (node MO) and the second signal line L2 (node MOb) can be reduced to 60 mV. The amplitude va can be further reduced by reducing the size of the N-MOS 223 of the logic circuit 200.

[Third Embodiment]
FIG. 9 is a block diagram showing a configuration of a signal transmission system 1B according to the third embodiment of the present invention.

  In the signal transmission system 1 according to the first embodiment and the signal transmission system 1A according to the second embodiment, the master units 10 and 10A have only a signal transmission function, and the slave unit 20 receives a signal. It had only a function. In contrast, in the signal transmission system 1B according to the present embodiment, the master unit 10B and the slave unit 20B both have a signal transmission function and a reception function.

  The master unit 10B includes a sense amplifier 100m, a logic circuit 200m, an RS-FF 21m, D-FFs 13am and 13bm for signal transmission, and a D-FF 24m for signal reception. The RS-FF 21m and the D-FF 24m are examples of the output circuit in the present invention. The master unit 10B further includes a switching circuit 300m that switches between operating as a transmitting device and operating as a receiving device, and a timing adjusting circuit 400 that controls the input timing of the clock signal. The switching circuit 300m includes NAND circuits 301 and 302 and a NOT circuit 303. One input terminal of the NAND circuit 301 is connected to a control terminal sel_m to which a control signal for selecting whether to operate the master unit 10B as a transmission device or a reception device is input. The output terminal of the NOT circuit 303 is a control output node s [0] _m, and the output terminal of the NAND circuit 302 is a control output node s [1] _m. The timing adjustment circuit 400 includes a C element 401 and an AND circuit 402, and one input terminal of the AND circuit 402 is connected to a clock input terminal ckin.

  The slave unit 20B has the same configuration as the master unit 10B except that it does not include a timing adjustment circuit. That is, the slave unit 20B includes a sense amplifier 100s, a logic circuit 200s, an RS-FF 21s, signal transmission D-FFs 13as and 13bs, and a signal reception D-FF 24s. The slave unit 20B further includes a switching circuit 300s that switches between operating as a transmitting device and operating as a receiving device. The switching circuit 300 s includes NAND circuits 301 and 302 and a NOT circuit 303. One input terminal of the NAND circuit 301 is connected to a control terminal sel_s to which a control signal for selecting whether the slave unit 20B operates as a transmission device or a reception device is input. The output terminal of the NOT circuit 303 is a control output node s [0] _s, and the output terminal of the NAND circuit 303 is a control output node s [1] _s.

  FIG. 10 is a diagram illustrating the configuration of the logic circuits 200m and 200s. The logic circuits 200m and 200s, with respect to the logic circuit 200 shown in FIG. 6, have one input terminal connected to the control output node s [0], OR circuits 241, 245 and AND circuits 243, 247, and one input. AND circuits 242, 244, 246 and 248 whose ends are connected to the control output node s [1] are added. Note that a value obtained by logically inverting the signal value output to the control output node s [0] is input to one input terminal of the OR circuits 241 and 245.

  FIG. 11 is a time chart showing an example of the operation of the C element 401 provided in the master unit 10B. As shown in FIG. 11, in the C element 401, when the signal values input to both of the two input terminals IN1 and IN2 are “0”, the signal value output from the output terminal OUT is “0”. When the signal value input to both of the two input terminals IN1 and IN2 becomes “1”, the signal value output from the output terminal OUT changes to “1”.

  One input terminal of the C element 401 is connected to the control output node s [1] _m, and the other input terminal of the C element 401 is connected to the clock input terminal ckin. The output terminal of the C element 401 is connected to one input terminal of the AND circuit 402. Note that a value obtained by logically inverting the signal value output to the control output node s [1] _m is input to one input terminal of the C element 401. A signal value obtained by logically inverting the signal value output from the output terminal of the C element 401 is input to one input terminal of the AND circuit 402. When the timing adjustment circuit 400 including the C element 401 and the AND circuit 402 performs function switching between the master unit 10B and the slave unit 20B operating as a transmission device or a reception device, After switching, control is performed so that the signal value of the clock signal first input to each block constituting the master unit 10B and the slave unit 20B is always “1”.

  Hereinafter, the operation of the signal transmission system 1B will be described. The master unit 10B and the slave unit 20B function as a transmission device or a reception device according to the signal values of the control signals input to the control terminals sel_m and sel_s, respectively. Table 1 below is a truth table regarding function switching of whether the master unit 10B and the slave unit 20B operate as a transmission device or a reception device.

  When the signal values of the control signals input to the control terminals sel_m and sel_s are both “0”, they are output to the control output nodes s [0] _m, s [0] _s, s [1] _m, and s [1] _s. The signal value to be set is “0”. In this case, both the master unit 10B and the slave unit 20B are in a standby state. In this case, since the P-MOSs 231 and 232 are turned on in the logic circuits 200m and 200s, the signal values of the node MIO of the first signal line L1 and the node MIOb of the second signal line L2 are the power supply voltage, respectively. Precharged at level. The signal value of the clock signal output from the output terminal of the timing adjustment circuit 400 is “0”. Further, the signal transmission D-FFs 13bm and 13bs and the signal reception D-FFs 24m and 24s are in a reset state, respectively, and nodes d [0] _m and d [0] _s at the output terminals Q of these D-FFs. The signal values at the data output terminals dout_m and dout_s are “0”. Further, the signal transmission D-FFs 13am and 13as are set, and the signal values of the nodes d [1] _m and d [1] _s at the output terminals Q of these D-FFs are “1”.

  When the signal value of the control signal input to the control terminal sel_m is “0” and the signal value of the control signal input to the control terminal sel_s is “1”, the signal is output to the control output node s [0] _m. The signal value is “0”, and the signal values output to the control output nodes s [0] _s, s [1] _m, and s [1] _s are “1”. In this case, the master unit 10B functions as a receiving device, and the slave unit 20B functions as a transmitting device.

  On the other hand, when the signal value of the control signal input to the control terminal sel_m is “1” and the signal value of the control signal input to the control terminal sel_s is “0”, the signal is output to the control output node s [0] _s. The signal value to be output is “0”, and the signal values output to the control output nodes s [0] _m, s [1] _m, and s [1] _s are “1”. In this case, the master unit 10B functions as a transmission device, and the slave unit 20B functions as a reception device.

  When one of the master unit 10B and the slave unit 20B functions as a transmission device and the other functions as a reception device, the D-FFs 13bm and 13bs for signal transmission and the D-FFs 24m and 24s for signal reception are released from the reset state. The signal transmission D-FFs 13am and 13as are released from the set state and become the normal state. Further, the clock signal input to the clock input terminal ckin is output from the output terminal of the timing adjustment circuit 400 as it is.

  Of the master unit 10B and the slave unit 20B, the logic circuit (logic circuit 200m or 200s) provided on the side that functions as the transmission device is enabled, and the N-MOSs 221 and 222 and the P-MOSs 231 and 232 are turned on / off. The state is determined according to the signal values of the nodes d [1] and d [0] at the output terminal Q of each D-FF for signal transmission. That is, the potentials of the first signal line L1 and the second signal line L2 are controlled by a logic circuit provided on the master unit 10B and the slave unit 20B that functions as a transmission device.

  On the other hand, of the master unit 10B and the slave unit 20B, the N-MOSs 221 and 222 and the P-MOSs 231 and 232 of the logic circuit (logic circuit 200m or 200s) provided on the side functioning as the receiving device are all turned off. The function of the logic circuit is invalidated.

  FIG. 12 is a time chart illustrating an example of signal transmission performed between the master unit 10B and the slave unit 20B.

  As shown in [1], the signal value of the control signal input to the control terminal sel_m of the master unit 10B is “1”, and the signal value of the control signal input to the control terminal sel_s of the slave unit 20B is “0”. Then, the logic circuit 200m of the master unit 10B is activated, the master unit 10B functions as a transmission device, the logic circuit 200s of the slave unit 20B is deactivated, and the slave unit 20B functions as a reception device.

  As shown in [2], when the signal value of the clock signal transitions to “1”, the signal value of the node d [0] _m is “0” and the signal value of the node d [1] _m is “1”. Therefore, as shown in [3], the node MIO of the first signal line L1 is discharged, and the voltage level decreases. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10B and the sense amplifier 100s of the slave unit 20B start the sensing operation. Since the potential of the node MIO of the first signal line L1 is lower than the potential of the node MIOb of the second signal line L2, the sense amplifiers 100m and 100s are respectively connected to the output terminal out as shown in [4]. A sensing signal having a signal value “1” is output. The potential of the node MIO of the first signal line L1 is maintained at a low level. In the slave unit 20B, the signal value output from the output terminal ffo of the RS-FF 21s becomes “1” when the signal value of the output terminal out of the sense amplifier 100s transitions to “1”.

  As shown in [5], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] _m transits to “1”, and the signal value of the node d [1] _m transits to “0”. Transition to As shown in [6], in the slave unit 20B, the signal value “1” output from the output terminal ffo of the RS-FF 21s is output from the data output terminal dout_s. At this time, the signal value output from the data output terminal dout_s is an initial value. Therefore, the signal value output from the data output terminal dout_s at the timing when the signal value of the clock signal transitions to “0” next becomes the signal value transmitted first. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”. As a result, the node MIO of the first signal line L1 is precharged at the power supply voltage level.

  As shown in [7], when the signal value of the clock signal transitions to “1”, the signal value of the node d [0] _m is “1”, and the signal value of the node d [1] _m is “0”. Therefore, as shown in [8], the node MIOb of the second signal line L2 is discharged, and the voltage level decreases. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10B and the sense amplifier 100s of the slave unit 20B start the sensing operation. Since the potential of the node MIOb of the second signal line L2 is lower than the potential of the node MIO of the first signal line L1, the sense amplifiers 100m and 100s are respectively connected from the output terminal outb as shown in [9]. A sensing signal having a signal value “1” is output. The potential of the node MIOb of the second signal line L2 is maintained at a low level. In the slave unit 20B, the signal value output from the output terminal ffo of the RS-FF 21s becomes “0” when the signal value of the output terminal outb of the sense amplifier 100s transitions to “1”.

  As shown in [10], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] _m transits to “0”, and the signal value of the node d [1] _m transits to “1”. Transition to Further, as shown in [11], in the slave unit 20B, the signal value “0” output from the output terminal ffo of the RS-FF 21s is output from the data output terminal dout_s. At this time, the signal value output from the data output terminal dout_s is the signal value transmitted first. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”. As a result, the node MIOb of the second signal line L2 is precharged at the power supply voltage level.

  As shown in [12], the signal value of the control signal input to the control terminal sel_m of the master unit 10B transitions to “0”, and the signal value of the control signal input to the control terminal sel_s of the slave unit 20B is “ If 0 ″ is maintained, the master unit 10B and the slave unit 20B enter a standby state. Accordingly, the circuit blocks of the master unit 10B and the slave unit 20B are in the initial state. That is, the signal values of the node MIO of the first signal line L1 and the node MIOb of the second signal line L2 are respectively precharged at the power supply voltage level. The signal value of the clock signal output from the output terminal of the timing adjustment circuit 400 is “0”. Further, the signal transmission D-FFs 13bm and 13bs and the signal reception D-FFs 24m and 24s are in a reset state, respectively, and nodes d [0] _m and d [0] _s at the output terminals Q of these D-FFs. The signal values at the data output terminals dout_m and dout_s are “0”. Further, the signal transmission D-FFs 13am and 13as are set, and the signal values of the nodes d [1] _m and d [1] _s at the output terminals Q of these D-FFs are “1”.

  As shown in [13], the signal value of the control signal input to the control terminal sel_m of the master unit 10B is maintained at “0”, and the signal value of the control signal input to the control terminal sel_s of the slave unit 20B is “ When the transition is made to 1 ″, the logic circuit 200m of the master unit 10B is invalidated, the master unit 10B functions as a reception device, the logic circuit 200s of the slave unit 20B is activated, and the slave unit 20B functions as a transmission device.

  As shown in [14], when the signal value of the clock signal transitions to “1”, the signal value of the node d [0] _s is “0”, and the signal value of the node d [1] _s is “1”. Therefore, as shown in [15], the node MIO of the first signal line L1 is discharged, and the voltage level decreases. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10B and the sense amplifier 100s of the slave unit 20B start the sensing operation. Since the potential of the node MIO of the first signal line L1 is lower than the potential of the node MIOb of the second signal line L2, the sense amplifiers 100m and 100s are respectively connected to the output terminal out as shown in [16]. A sensing signal having a signal value “1” is output. The potential of the node MIO of the first signal line L1 is maintained at a low level. In the master unit 10B, the signal value output from the output terminal ffo of the RS-FF 21m becomes “1” when the signal value of the output terminal out of the sense amplifier 100m transitions to “1”.

  As shown in [17], when the signal value of the clock signal transits to “0”, the signal value of the node d [0] _s transits to “1”, and the signal value of the node d [1] _s transits to “0”. Transition to Also, as shown in [18], in the master unit 10B, the signal value “1” output from the output terminal ffo of the RS-FF 21m is output from the data output terminal dout_m. At this time, the signal value output from the data output terminal dout_m is an initial value. Therefore, the signal value output from the data output terminal dout_m at the timing when the signal value of the clock signal transitions to “0” next becomes the signal value transmitted first. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”. As a result, the node MIO of the first signal line L1 is precharged at the power supply voltage level.

  As shown in [19], when the signal value of the clock signal transits to “1”, the signal value of the node d [0] _m is “1”, and the signal value of the node d [1] _ is “0”. Therefore, as shown in [20], the node MIOb of the second signal line L2 is discharged, and the voltage level decreases. When the signal value of the clock signal transitions to “1”, both the sense amplifier 100m of the master unit 10B and the sense amplifier 100s of the slave unit 20B start the sensing operation. Since the potential of the node MIOb of the second signal line L2 is lower than the potential of the node MIO of the first signal line L1, the sense amplifiers 100m and 100s are respectively connected from the output terminal outb as shown in [21]. A sensing signal having a signal value “1” is output. The potential of the node MIOb of the second signal line L2 is maintained at a low level. In the master unit 10B, the signal value output from the output terminal ffo of the RS-FF 21m becomes “0” when the signal value of the output terminal outb of the sense amplifier 100m transitions to “1”.

  As shown in [22], when the signal value of the clock signal transitions to “0”, the signal value of the node d [0] _s transitions to “0”, and the signal value of the node d [1] _m changes to “0”. ”. Also, as shown in [23], in the master unit 10B, the signal value “0” output from the output terminal ffo of the RS-FF 2m is output from the data output terminal dout_m. At this time, the signal value output from the data output terminal dout_m is the signal value transmitted first. When the signal value of the clock signal transitions to “0”, the sense amplifiers 100m and 100s stop the sensing operation, and the signal values of the output terminals out and outb both become “0”, but the second signal line The node MIOb of L2 maintains the low level.

  As described above, according to the signal transmission system 1B according to the present embodiment, as in the signal transmission system 1 according to the first embodiment, the sense amplifiers 100m and 100s are intermittently set according to the signal value of the clock signal. Since it operates, the power consumption can be suppressed as compared with a conventional sense amplifier that always consumes power.

  Further, the sense amplifiers 100m and 100s can detect even a slight potential difference between the first signal line L1 (node MIO) and the second signal line L2 (node MIOb). The amplitude va (see FIG. 12) of the signal transmitted to the first signal line L1 (node MIO) and the second signal line L2 (node MIOb) can be reduced. That is, since the amount of discharge charges of the first signal line L1 and the second signal line L2 when performing signal transmission can be suppressed, power saving can be achieved also in this respect.

  Further, according to the signal transmission system 1B according to the present embodiment, the signal value of the signal transmitted between the master unit 10B and the slave unit 20B is “00...” Or “11. In addition, when the same value continues, since the signal line is discharged and precharged only once for a plurality of continuous signals having the same value, the effect of suppressing power consumption can be further promoted.

  Further, according to the signal transmission system 1B according to the present embodiment, the master unit 10B and the slave unit 20B have both a signal transmission function and a reception function. Here, consider a case where the signal transmission system has a configuration that requires two signal lines for transmission and reception (total of four signal lines). In this case, when signal transmission is performed between one master unit and a plurality of slave units, it is necessary to assign a large number of pins to an LSI functioning as a master unit. This is disadvantageous for an LSI with a limited number of pins. According to the signal transmission system 1B according to the present embodiment, bidirectional communication is performed between the master unit 10 and the slave unit 20 using only two signal lines, the first signal line L1 and the second signal line L2. It becomes possible. Therefore, the number of signal lines can be reduced as compared with the case where two signal lines are required for transmission and reception (total of four signal lines).

[Fourth Embodiment]
FIG. 13 is a block diagram showing a configuration of a signal transmission system 1C according to the fourth embodiment of the present invention. The signal transmission system 1C is different from the signal transmission system 1B according to the third embodiment described above in that the master unit 10C and the slave unit 20C include frequency multiplication circuits 500m and 500s, respectively.

  The frequency multiplication circuit 500m is connected to the output terminal of the timing adjustment circuit 400 and the control output terminal s [1] _m. The frequency multiplication circuit 500s is connected to the output terminal of the timing adjustment circuit 400 and the control output terminal s [1] _s. When the control signal having the signal value “0” is input to both the control terminals sel_m and sel_s, that is, when the master unit 10C and the slave unit 20C are in the standby state, the frequency multiplication circuits 500m and 500s are in the standby state. Become. On the other hand, when the control signal having the signal value “1” is input to at least one of the control terminals sel_m and sel_s, that is, one of the master unit 10C and the slave unit 20C is the transmitter. When the other functions as a receiving device, a converted clock signal is generated by multiplying the frequency of the clock signal output from the timing adjustment circuit 400 by an integer, and this is converted into each circuit constituting the master unit 10C or the slave unit 20C. Supply to block. Since the converted clock signal is synchronized with the original clock signal, the converted clock signal output from the frequency multiplier circuit 500m of the master unit 10C and the converted clock signal output from the frequency multiplier circuit 500s of the slave unit 20C are Are in sync with each other. The frequency multiplication circuits 500m and 500s may be configured to include, for example, a PLL (Pulse Locked Loop) or a DLL (Delay Locked Loop).

  In the signal transmission system 1C according to the third embodiment described above, since the clock signal is transmitted from the master unit 10B to the slave unit 20B, the power consumption on the transmission line 30 increases as the frequency of the clock signal is increased. To increase. According to the signal transmission system 1C according to the present embodiment, since the master unit 10C and the slave unit 20C have the frequency multiplication circuits 500m and 500s, respectively, the master unit 10C while suppressing the frequency of the clock signal transmitted to the transmission line 30. The clock frequency in the inside and the slave unit 20 can be increased. Therefore, it is possible to increase the speed of signal transmission while suppressing power consumption.

1, 1A, 1B, 1C Signal transmission system 10, 10A, 10B, 10C Master unit 20, 20B, 20C Slave unit 30 Transmission line 100m, 100s Sense amplifier 200, 200m, 200s Logic circuit 300m, 300s Switching circuit 400 Timing adjustment circuit L1 first signal line L2 second signal line

Claims (13)

When the signal value of the input clock signal is the first value, it has a signal value corresponding to the difference between the potential of the first signal line and the potential of the second signal line different from the first signal line. A sensing operation is performed to output a first sensing signal and a second sensing signal having a signal value different from the signal value of the first sensing signal, and the signal value of the clock signal is different from the first value. A sense amplifier that stops the sensing operation when the second value;
The potential of the first signal line is changed in accordance with the logical operation result of the signal values of the input data signal, the clock signal, and the first sensing signal, and the data signal, the clock signal, and the first sensing signal are changed. A logic circuit that changes a potential of the second signal line in accordance with a logical operation result of each signal value of the two sensing signals;
Including a signal transmission device. The logic circuit is configured to set the potential of the first signal line or the second signal line to a plurality of data signals having the same value, which are continuously input. The signal transmission device according to claim 1, wherein the signal transmission device is changed only once according to a data signal input first. The signal transmission device according to claim 1, further comprising an output circuit that generates an output signal having a signal value corresponding to the signal value of the first sensing signal and the signal value of the second sensing signal. The signal transmission device according to claim 3, further comprising: a frequency multiplication circuit that generates a converted clock signal obtained by multiplying the frequency of the clock signal by an integer, and supplies the converted clock signal to the sense amplifier, the logic circuit, and the output circuit. . When the signal value of the input clock signal is the first value, it has a signal value corresponding to the difference between the potential of the first signal line and the potential of the second signal line different from the first signal line. A sensing operation is performed to output a first sensing signal and a second sensing signal having a signal value different from the signal value of the first sensing signal, and the signal value of the clock signal is different from the first value. A sense amplifier that stops the sensing operation when the second value;
An output circuit for generating an output signal having a signal value corresponding to the signal value of the first sensing signal and the signal value of the second sensing signal;
Including a signal transmission device. A first signal transmission device, and a second signal transmission that is communicably connected via a second signal line different from the first signal transmission device, the first signal line, and the first signal line. A signal transmission system comprising:
The first signal transmission device includes:
A first sensing signal having a signal value corresponding to a difference between a potential of the first signal line and a potential of the second signal line when the signal value of the input clock signal is a first value; A first sensing operation for outputting a second sensing signal having a signal value different from the signal value of the first sensing signal is performed, and a second value in which the signal value of the clock signal is different from the first value. A first sense amplifier that stops the first sensing operation;
The potential of the first signal line is changed in accordance with the logical operation result of each signal value of the input first data signal, the clock signal, and the first sensing signal, and the first data signal, A first logic circuit that changes a potential of the second signal line in accordance with a logical operation result of each of the signal values of the clock signal and the second sensing signal;
Including
The second signal transmission device includes:
A third sensing signal having a signal value corresponding to a difference between the potential of the first signal line and the potential of the second signal line when the signal value of the clock signal is the first value; A second sensing operation for outputting a fourth sensing signal having a signal value different from the signal value of the third sensing signal, and when the signal value of the clock signal is the second value, the second sensing operation is performed. A second sense amplifier that stops operation;
A first output circuit for generating an output signal having a signal value corresponding to the signal value of the third sensing signal and the signal value of the fourth sensing signal;
Including signal transmission system. The first logic circuit is configured to set the potential of the first signal line or the second signal line to the plurality of data signals having the same value with respect to the plurality of data signals having the same value that are continuously input. The signal transmission system according to claim 6, wherein the signal transmission system is changed only once according to a data signal input first. The first signal transmission device includes:
The signal according to claim 6, further comprising a second output circuit that generates an output signal having a signal value corresponding to the signal value of the first sensing signal and the signal value of the second sensing signal. Transmission system. The first signal transmission device generates a first converted clock signal obtained by multiplying the frequency of the clock signal by an integer, and the first converted clock signal is used as the first sense amplifier, the first logic circuit, and The signal transmission system according to claim 8, further comprising a first frequency multiplication circuit that supplies the second output circuit. The second signal transmission device includes:
The potential of the first signal line is changed according to the logical operation result of each signal value of the input second data signal, the clock signal, and the third sensing signal, and the second data signal, 10. The circuit according to claim 6, further comprising: a second logic circuit that changes a potential of the second signal line in accordance with a logical operation result of each of the signal values of the clock signal and the fourth sensing signal. The signal transmission system according to claim 1. The second logic circuit is configured to set the potential of the first signal line or the second signal line to the plurality of data signals having the same value with respect to the plurality of data signals having the same value that are continuously input. The signal transmission system according to claim 10, wherein the signal transmission system is changed only once according to a data signal input first. The second signal transmission device generates a second converted clock signal obtained by multiplying the frequency of the clock signal by an integer, and uses the second converted clock signal as the second sense amplifier, the second logic circuit, and the like. The signal transmission system according to claim 10, further comprising a second frequency multiplication circuit that supplies the first output circuit. The signal transmission is performed between the first signal transmission device and the second signal transmission device in a state where one function of the first logic circuit and the second logic circuit is invalidated. Item 13. The signal transmission system according to any one of Items 12 to 12.