JP2019028540A - Information processing apparatus, compiling method, and compiling program - Google Patents

Abstract

To provide an information processing apparatus, a compiling method, and a compiling program which make it possible to easily acquire information on loop exchange performed by a compiler.SOLUTION: When a source code is compiled, based on the order of memory access performed in a specific loop in which loop exchange is not instructed among loops included in the source code, first information on the specific loop when the loop exchange is performed or second information on the specific loop when the loop exchange is not performed is generated, and the generated first information or the second information is output.SELECTED DRAWING: Figure 11

Description

  The present invention relates to an information processing apparatus, a compiling method, and a compiling program.

  For example, a compiler used for HPC (High Performance Computing) or the like performs optimization processing for improving processing performance such as processing speed when compiling source code.

  Specifically, the compiler as described above performs, for example, loop division that divides each loop included in the source code into a plurality of loops, and loop exchange that replaces subscripts used in each loop included in the source code. Do. Thereby, for example, the compiler can efficiently perform memory access during execution of processing corresponding to the source code. Therefore, the compiler can improve the processing performance of the HPC when executing the object code generated from the source code (see, for example, Patent Documents 1 to 3).

Japanese Patent Laying-Open No. 2015-194881 JP 2007-226589 A JP 2005-122506 A

  The loop division and loop exchange as described above may be automatically performed, for example, not only when the source code developer (hereinafter also referred to simply as the developer) designates, but also at the discretion of the compiler. . Specifically, for example, the compiler automatically performs loop division even for a loop designated by the developer to perform loop exchange. In this case, the compiler performs loop exchange for each of the plurality of loops generated by the loop division.

  Here, when loop exchange is performed for each of a plurality of loops generated by loop division, these loop exchanges include loop exchanges that are preferably not performed from the viewpoint of improving the processing performance of HPC. May be. Therefore, the developer needs to verify, for example, whether each loop exchange performed by the compiler is necessary to improve the processing performance of the HPC.

  However, when performing the verification as described above, for example, the developer needs to operate the object code generated by the compiler in the actual machine, and cannot easily obtain necessary information. Therefore, the developer may not be able to easily verify whether or not each loop exchange performed by the compiler is necessary to improve the processing performance of the HPC.

  Therefore, an object of one aspect is to provide an information processing apparatus, a compiling method, and a compiling program that can easily acquire information related to loop exchange performed by a compiler.

  According to one aspect of the embodiment, when compiling the source code, among the loops included in the source code, based on the order of memory access performed in a specific loop instructed to replace the loop, An information generator that generates first information about the specific loop when a loop is exchanged or second information about the specific loop when a loop is not exchanged, and An information output unit that outputs the first information or the second information.

  According to one aspect, it is possible to easily obtain information regarding loop exchange performed by a compiler.

FIG. 1 is a diagram illustrating an overall configuration of the information processing system 10. FIG. 2 is a flowchart for explaining a compile process performed by the information processing apparatus 1. FIG. 3 is a flowchart for explaining code execution processing performed by the information processing apparatus 1. FIG. 4 is a diagram for explaining a specific example of the source code 131. FIG. 5 is a diagram for explaining a specific example of the source code 131. FIG. 6 is a diagram for explaining a specific example when stride access is performed. FIG. 7 is a diagram illustrating a specific example when continuous access is performed. FIG. 8 is a diagram for explaining the hardware configuration of the information processing apparatus 1. FIG. 9 is a block diagram of functions of the information processing apparatus 1. FIG. 10 is a block diagram of information stored in the information storage area 130. FIG. 11 is a flowchart for explaining the outline of the process of S3. FIG. 12 is a flowchart for explaining the details of the compiling process in the first embodiment. FIG. 13 is a flowchart for explaining the details of the compiling process in the first embodiment. FIG. 14 is a flowchart for explaining details of the compiling process in the first embodiment. FIG. 15 is a flowchart for explaining the details of the compiling process in the first embodiment. FIG. 16 is a diagram illustrating a specific example of a loop in which loop replacement is instructed. FIG. 17 is a diagram illustrating a specific example of the loop after the loop division is performed on the loop shown in FIG. FIG. 18 is a diagram illustrating a specific example of a loop after the loop exchange is performed on the loop shown in FIG. FIG. 19 is a diagram illustrating a specific example of the first information 135 generated from the loop illustrated in FIG. FIG. 20 is a diagram illustrating a specific example of the first information 135 generated from the loop illustrated in FIG. FIG. 21 is a diagram illustrating a specific example of a loop for which no loop replacement is instructed. FIG. 22 is a diagram for explaining a specific example of the loop after the loop division is performed on the loop shown in FIG. FIG. 23 is a diagram illustrating a specific example of the second information 136 generated from the loop illustrated in FIG. FIG. 24 is a diagram illustrating a specific example of the second information 136 generated from the loop illustrated in FIG. FIG. 25 is a diagram illustrating a specific example of the second information 136 to which the second recommended information 136c is added. FIG. 26 is a diagram illustrating a specific example of the first information 135 to which the first recommendation information 135c is added.

[Configuration of information processing system]
FIG. 1 is a diagram illustrating an overall configuration of the information processing system 10. An information processing system 10 illustrated in FIG. 1 includes an information processing device 1 (an information processing device on which a compiler operates), a storage device 2, and an operation terminal 3. The operation terminal 3 shown in FIG. 1 includes operation terminals 3a, 3b and 3c.

  When the information processing apparatus 1 (the CPU of the information processing apparatus 1) reaches the timing for starting compilation (hereinafter also referred to as compilation start timing), for example, the source code stored in the storage device 2 (hereinafter referred to as source code 131). Is also obtained, and an object code (hereinafter also referred to as object code 133) is generated by performing processing for compiling the acquired source code 131 (hereinafter also referred to as compilation processing). The compile start timing may be, for example, a timing when an instruction to compile is received from the operation terminal 3.

  In addition, when the timing for executing the object code 133 (hereinafter also referred to as code execution timing) is reached, the information processing apparatus 1 executes processing for executing the object code 133 generated by the compile processing (hereinafter also referred to as code execution processing). )I do. Hereinafter, the compile process and the code execution process performed by the information processing apparatus 1 will be described.

[Compile processing by information processing device]
First, compilation processing performed by the information processing apparatus 1 will be described. FIG. 2 is a flowchart for explaining a compile process performed by the information processing apparatus 1.

  As shown in FIG. 2, the information processing apparatus 1 waits until the compilation start timing (NO in S1). When the compile start timing comes (YES in S1), the information processing apparatus 1 generates an intermediate language (hereinafter also referred to as an intermediate language 132) by performing lexical analysis and syntax analysis of the source code 131 ( S2). Then, the information processing apparatus 1 stores the generated intermediate language 132 in the information storage area 130, for example.

  Thereafter, the information processing apparatus 1 optimizes the intermediate language 132 generated in the process of S2 (S3). Specifically, the information processing apparatus 1 performs loop division, loop exchange, and the like for each of the loops included in the intermediate language 132.

  Then, for example, the information processing apparatus 1 generates the object code 133 from the intermediate language 132 optimized in S2 (S4). Then, the information processing apparatus 1 stores the generated object code 133 in the storage device 2, for example.

  Thereby, the information processing apparatus 1 can optimize the processing performance of the HPC when the object code 133 is executed.

[Code execution processing by information processing device]
Next, a code execution process performed by the information processing apparatus 1 will be described. FIG. 3 is a flowchart for explaining code execution processing performed by the information processing apparatus 1.

  As shown in FIG. 3, the information processing apparatus 1 waits until the code execution timing (NO in S11). When the code execution timing comes (YES in S11), the information processing apparatus 1 executes the object code 133 generated in the process of S4 (S12). Specifically, the information processing apparatus 1 acquires and executes the object code 133 stored in the storage device 2, for example.

[Specific examples of source code]
Subsequently, a specific example of the source code 131 will be described. 4 and 5 are diagrams for explaining a specific example of the source code 131. FIG. Note that the source code 131 is a source code described by Fortran.

  Specifically, in the source code 131 shown in FIG. 4, an instruction consisting of a character string “a (i, j) = b (i, j) + c (i, j)” is included in a double loop. ing. In the source code shown in FIG. 4, an instruction from the character string “x (j) = j” is located in the outer loop of the double loop and outside the innermost loop.

  Then, for example, in the process of S3, the compiler generates the intermediate language 132 shown in FIG. 5 by performing loop division or the like on the double loop described in FIG. Hereinafter, the intermediate language 132 is expressed in the same format as the source code 131.

  Specifically, as illustrated in FIG. 5, the compiler includes an instruction including a character string “x (j) = j” in a loop different from the double loop described in FIG. 4.

  Accordingly, the compiler can reduce the amount of data that needs to be accessed in the processing within one loop when the object code 133 generated from the source code 131 described with reference to FIG. 4 is executed. For this reason, for example, the compiler can suppress the number of times the cache line stored in the main memory is stored in the cache memory, and the rate of occurrence of cache misses when access to the data stored in the cache memory occurs. Can be suppressed.

[Specific examples of memory access]
Next, a specific example of memory access when the object code 133 is executed will be described. FIG. 6 is a diagram for explaining a specific example when stride access is performed. FIG. 7 is a diagram illustrating a specific example when continuous access is performed. Specifically, FIG. 6A illustrates a specific example of a double loop in which stride access is performed, and FIG. 6B illustrates that stride access is performed on data stored in the cache memory. It is a figure explaining the case. FIG. 7A illustrates a specific example of a double loop in which continuous access is performed. FIG. 7B illustrates a case in which continuous access is performed on data stored in the cache memory. FIG.

  In the following description, it is assumed that stride access is memory access that is not sequentially performed on continuous storage areas, and that continuous access is memory access that is sequentially performed on continuous storage areas. Do.

  In the double loop shown in FIG. 6A, the control variable of the innermost loop is j, and the control variable of the outer loop is i. In the double loop shown in FIG. 6A, the number of repetitions of the innermost loop and the outer loop is 10 (times), respectively. The innermost loop of the double loop shown in FIG. 6A includes an instruction consisting of a character string “a (i, j) = b (i, j) * 2 + 1”. Therefore, when the double loop shown in FIG. 6A is executed, (i, j) of the array a and the array b includes “(1, 1), (1, 2), (1, 3)”. ,... (1, 9), (1, 10), (2, 1), (2, 2),.

  On the other hand, in the cache memory shown in FIG. 6B, “array b (1, 1) data, array b (2, 1) data, array b (3, 1) data,. The data is stored in the order of (9,1) data, array b (10,1) data,... Array b (1,2) data, array b (2,2) data,. Has been. Therefore, when memory access is performed during execution of the double loop shown in FIG. 6A, the double loop shown in FIG. 6A has a stride with a stride width of 10 as shown in FIG. 6B. Access is made.

  On the other hand, in the double loop shown in FIG. 7A, the control variable of the innermost loop is i, and the control variable of the outer loop is j. In the double loop shown in FIG. 7A, the number of repetitions of the innermost loop and the outer loop is 10 (times), respectively. The innermost loop of the double loop shown in FIG. 7A includes an instruction made up of a character string “a (i, j) = b (i, j) * 2 + 1”. Therefore, when the double loop shown in FIG. 7A is executed, (i, j) of the array a and the array b includes “(1,1), (2,1), (3,1)”. ,... (9, 1), (10, 1), (1, 2), (2, 2),.

  On the other hand, in the cache memory shown in FIG. 7B, as in the case described in FIG. 6B, “data in array b (1, 1), data in array b (2, 1), array b (3,1) data,... Array b (9,1) data, array b (10,1) data,... Array b (1,2) data, array b (2,2) ) Data,... Therefore, when memory access is performed during execution of the double loop shown in FIG. 7A, continuous access is performed in the double loop shown in FIG. 7A, as shown in FIG. 7B.

  That is, the developer executes the object code 133 by causing the HPC to execute the double loop shown in FIG. 7A, compared with the case where the HPC executes the double loop shown in FIG. It becomes possible to improve the processing performance at the time. Therefore, for example, the developer instructs the compiler in advance to perform loop exchange necessary when compiling the source code 131.

  Here, the loop division and the loop exchange may be automatically performed not only when the specification is made by the developer but also by the judgment of the compiler. Specifically, for example, the compiler automatically performs loop division even for a loop designated by the developer to perform loop exchange. In this case, the compiler performs loop exchange for each of the plurality of loops generated by the loop division.

  Therefore, when loop exchange is performed for each of a plurality of loops generated by loop division automatically performed by the compiler, those loop exchanges are not performed from the viewpoint of improving the processing performance of HPC. May include preferred loop exchanges. Therefore, the developer needs to verify, for example, whether or not each of the loop exchanges as described above was necessary to improve the processing performance of the HPC.

  However, when performing the verification as described above, for example, the developer needs to operate the object code 133 generated by the compiler on the actual machine, and cannot easily obtain necessary information. Therefore, the developer may not be able to easily verify whether or not each of the loop exchanges as described above is necessary for improving the processing performance of the HPC.

  Therefore, when compiling the source code 131, the information processing apparatus 1 according to the present embodiment uses a loop (hereinafter also referred to as a first loop) in which loop replacement is instructed among the loops included in the source code 131. Based on the order of memory access to be performed, information on the first loop when loop exchange is performed (hereinafter also referred to as first information), or the first loop when loop exchange is not performed Information (hereinafter also referred to as second information) is generated. Then, the information processing apparatus 1 outputs the generated first information or second information.

  Further, when the information processing apparatus 1 compiles the source code 131, memory access performed in a loop (hereinafter also referred to as a second loop) in which loop replacement is not instructed among the loops included in the source code 131. Based on the above order, the first information regarding the second loop when the loop exchange is performed or the second information regarding the second loop when the loop exchange is not performed is generated. Then, the information processing apparatus 1 outputs the generated first information or second information.

  That is, for example, when the source code 131 is compiled, the information processing apparatus 1 determines whether the memory access performed in the first loop or the second loop (hereinafter also referred to as a specific loop) is continuous access. It is determined whether the access is stride access. For example, when loop exchange is performed in a specific loop and it is determined that continuous access is performed in the specific loop, the information processing apparatus 1 should not perform loop exchange in the specific loop. Information (first information) indicating this is output. On the other hand, for example, when loop exchange is not performed in a specific loop and it is determined that stride access is performed in the specific loop, the information processing apparatus 1 should perform loop exchange in the specific loop. The information (second information) indicating that is output.

  As a result, the developer refers to the information output by the information processing apparatus 1 so that, for example, each of the loop exchanges performed by the compiler without causing the object code 133 to operate on the actual machine, improves the processing performance of the HPC. It becomes possible to easily verify whether or not it was necessary for improvement.

[Hardware configuration of information processing device]
Next, the hardware configuration of the information processing apparatus 1 will be described. FIG. 8 is a diagram for explaining the hardware configuration of the information processing apparatus 1.

  As illustrated in FIG. 8, the information processing apparatus 1 includes a CPU 101 that is a processor, a main memory 102 (hereinafter also simply referred to as a memory 102), an external interface (I / O unit) 103, and a storage medium (storage) 104. And have. Each unit is connected to each other via a bus 105.

  The storage medium 104 stores a program 110 that performs compilation processing and code execution processing in a program storage area (not shown) in the storage medium 104.

  As shown in FIG. 8, when executing the program 110, the CPU 101 loads the program 110 from the storage medium 104 to the memory 102 and performs a compilation process by cooperating with the program 110.

  The storage medium 104 is, for example, an HDD (Hard Disk Drive), an SSD (Solid State Drive), or the like, and an information storage area 130 (hereinafter also referred to as a storage unit 130) that stores information used when performing compilation processing or the like. Have Note that the storage device 2 described in FIG. 1 may correspond to the storage medium 104, for example.

  The external interface 103 communicates with the operation terminal 3 via a network.

[Software configuration of information processing equipment]
Next, the software configuration of the information processing apparatus 1 will be described. FIG. 9 is a block diagram of functions of the information processing apparatus 1. FIG. 10 is a block diagram of information stored in the information storage area 130.

  As shown in FIG. 9, the CPU 101 cooperates with the program 110 to perform a loop division unit 111, an information generation unit 112, a loop exchange unit 113, an information output unit 114, a code generation unit 115, a code, The execution unit 116 operates. Further, in the information storage area 130, as shown in FIG. 10, the source code 131, the intermediate language 132, the object code 133, the post-loop division information 134, and the first information 135 (hereinafter simply referred to as the first information 135). Loop information 135) and second information 136 (hereinafter also simply referred to as second loop information 136) are stored.

  In the following description, it is assumed that the loop dividing unit 111, the information generating unit 112, the loop exchanging unit 113, and the information output unit 114 perform at least part of the process of S3 described in FIG. Further, the description will be made assuming that the code generation unit 115 performs at least a part of the processing of S4 described in FIG. Further, description will be made assuming that the code execution unit 116 performs at least a part of the processing of S12 described in FIG.

  The loop division unit 111 performs loop division on the loop included in the source code 131. Specifically, the loop division unit 111 performs the loop division among the loops included in the intermediate language 132 generated by performing lexical analysis and syntax analysis on the source code 131, and the object code 133 Loop division is performed on a loop determined to improve the HPC processing performance at the time of execution.

  The information generation unit 112 generates first information 135 related to a specific loop when a loop is exchanged based on the order of memory access performed in the specific loop among the loops included in the source code 131. . The information generation unit 112 also includes second information 136 regarding a specific loop when no loop exchange is performed based on the order of memory access performed in the specific loop among the loops included in the source code 131. Is generated. Specifically, the information generation unit 112 refers to the first information 135 or the second information 136 with reference to post-loop division information 134 that is information regarding a plurality of loops generated by the loop division unit 111 performing the loop division. Is generated.

  The loop exchanging unit 113 performs loop exchanging for a specific loop instructed to exchange loops among the loops included in the source code 131. The instruction for loop exchange may be described in advance in the source code 131 by the developer, for example.

  The information output unit 114 outputs the first information 135 or the second information 136 generated by the information generation unit 112. Specifically, for example, the information output unit 114 outputs the first information 135 or the second information 136 to the operation terminal 3 that can be browsed by the developer.

  For example, the code generation unit 115 generates the object code 133 from the intermediate language 132 in which the loop division by the loop division unit 111, the loop exchange by the loop exchange unit 113, and the like are performed. The code generation unit 115 stores the generated object code 133 in the information storage area 130, for example.

  For example, when the code execution timing comes, the code execution unit 116 executes the object code 133 stored in the information storage area 130.

[Outline of First Embodiment]
Next, an outline of the first embodiment will be described. Specifically, the outline of the process of S3 described in FIG. 2 will be described here. FIG. 11 is a flowchart for explaining the outline of the process of S3.

  The loop division unit 111 acquires the intermediate language generated by the process of S2 (S21). Then, the loop dividing unit 111 generates a plurality of loops by performing loop division on the loop included in the intermediate language 132 generated by the processing of S2 (S22).

  Subsequently, the information generation unit 112 acquires post-loop division information 134 that is information regarding a plurality of loops after the loop division is performed in the process of S22 (S23).

  Thereafter, the information generating unit 112 and the loop exchanging unit 113 refer to the post-loop division information 134 acquired in the process of S23, and perform loop exchange for a specific loop among a plurality of loops generated in the process of S22. In addition, when the loop exchange is performed by the loop exchanging unit 113, the information generation unit 112 performs the first operation on the specific loop when the loop exchange is performed based on the order of the memory access performed in the specific loop. The information 135 or the second information 136 related to a specific loop when the loop exchange is not performed is generated (S24).

  And the information output part 114 outputs the 1st information 135 produced | generated by the process of S24, or the 2nd information 136 (S25).

  That is, for example, when the source code 131 is compiled, the information processing apparatus 1 determines whether the memory access performed in a specific loop is continuous access or stride access. For example, when loop exchange is performed in a specific loop and it is determined that continuous access is performed in the specific loop, the information processing apparatus 1 should not perform loop exchange in the specific loop. Information indicating that (first information 135) is output. On the other hand, for example, when loop exchange is not performed in a specific loop and it is determined that stride access is performed in the specific loop, the information processing apparatus 1 should perform loop exchange in the specific loop. Is output (second information 136) indicating that the

  As a result, the developer refers to the information output by the information processing apparatus 1 so that, for example, each of the loop exchanges performed by the compiler without causing the object code 133 to operate on the actual machine, improves the processing performance of the HPC. It becomes possible to easily verify whether or not it was necessary for improvement. In this case, for example, the developer manually generates a plurality of loops with respect to the loop included in the source code 131, and the information output from the information processing apparatus 1 among the plurality of generated loops is generated. Based on this, it is possible to instruct the loop exchange only for the loop that is determined to be subjected to the loop exchange.

[Details of First Embodiment]
Next, details of the first embodiment will be described. 12 to 15 are flowcharts illustrating details of the compile processing in the first embodiment. Specifically, FIGS. 12 to 15 are flowcharts illustrating details of the processing of S24 described in FIG. FIGS. 16 to 26 are diagrams for explaining the details of the compiling process in the first embodiment. Details of the processing of S24 shown in FIGS. 12 to 15 will be described with reference to FIGS.

  As illustrated in FIG. 12, the information generation unit 112 identifies one loop whose information is included in the post-loop division information 134 acquired in the process of S23 (S31).

  When the loop exchange is instructed for the loop identified in the process of S31 (YES in S32), the loop exchange unit 113 performs the loop exchange for the loop identified in the process of S31 (S34). Thereafter, the information generation unit 112 analyzes the loop in which the loop is exchanged in the process of S34, and generates first information 135 corresponding to the loop in which the loop exchange is performed in S34 (S35).

  That is, in this case, the loop exchanging unit 113 generates information about the loop after the loop exchange is performed as the first information 135. Hereinafter, a specific example when the first information 135 is generated will be described.

[Specific example when first information is generated]
First, specific examples of a loop instructed to exchange loops, a loop after loop division, and a loop after loop division and loop exchange will be described. FIG. 16 is a diagram illustrating a specific example of a loop in which loop replacement is instructed. FIG. 17 is a diagram for explaining a specific example of the loop after the loop division is performed on the loop shown in FIG. Further, FIG. 18 is a diagram for explaining a specific example of the loop after the loop exchange is performed on the loop shown in FIG.

  In the double loop shown in FIG. 16, the control variable of the innermost loop is i, and the control variable of the outer loop is j. In the double loop shown in FIG. 16, the inner loop is repeated 10 times and the outer loop is repeated 10,000 times. The innermost loop of the double loop shown in FIG. 16 includes an instruction consisting of a character string “b (j) = b (j) + a (j, i)” and “c (i) = c (i ) + D (i, j) −e (i, j) ”. Further, before the double loop shown in FIG. 16, a character string “instruction for exchanging! And i”, which is an instruction to perform loop exchange, is described.

  Therefore, in the process of S21, the loop dividing unit 111 converts the loop shown in FIG. 16 into “b (j) = b (j) + a (j, i)” as shown in FIGS. ”And a loop including“ c (i) = c (i) + d (i, j) −e (i, j) ”. Then, the loop exchanging unit 113 responds to the instruction to perform the loop exchanging in the process of S34, as shown in FIGS. 18A and 18B, the subscript i included in the loop shown in FIG. Exchange the subscript j.

  Next, a specific example of the first information 135 generated from the loop shown in FIGS. 18A and 18B will be described. FIG. 19 is a diagram illustrating a specific example of the first information 135 generated from the loop illustrated in FIG. FIG. 20 is a diagram illustrating a specific example of the first information 135 generated from the loop illustrated in FIG. Hereinafter, the first information 135 generated from the loop illustrated in FIG. 18A is also referred to as first information 135a, and the first information 135 generated from the loop illustrated in FIG. 18B is the first information. Also referred to as 135b.

  Specifically, for example, the information generation unit 112 sets the information of the entire loop shown in FIG. 18A in the item “[[loops]]” like the first information 135a shown in FIG. , “Id1” indicating the loop identifier is set as “loop1_interchanged”, “dimension” indicating the number of dimensions of the loop is set as “2”, and “index” indicating the subscript access order is set as “j” , I "". Then, for example, as in the first information 135a illustrated in FIG. 19, the information generation unit 112 includes “[[loops]]” in the item “[[loops]]” as “innermost loop index” indicating “innermost loop index”. j "" is set, "10000 * 10" is set as "iteration_count" indicating the number of iterations of the loop, and "1" is set as "increment" indicating the increment value of the loop.

  Further, for example, the information generation unit 112 sets the first “[[loops] in which information about the array b included in the loop illustrated in FIG. 18A is set like the first information 135a illustrated in FIG. .Arrays]] ”is set to blank as“ operator ”indicating an operator for the array,“ 3 ”is set as“ line ”indicating the line number of the array b in the source code 131, and the array name “B” ”is set as“ name ”indicating“ ”. Then, for example, as in the first information 135a illustrated in FIG. 19, the information generation unit 112 sets “1” as “dimension” indicating the number of dimensions of the array in the item “[[loops.arrays]]”. ”Is set,“ j ”” is set as “index” indicating the access order of subscripts, “def” is set as “def_ref” indicating reference definition information, and “ “10000” is set as “size”.

  Of the first information 135a shown in FIG. 19, the second item “[[loops.arrays]]” in which information about the array b included in the loop shown in FIG. 18A is set is set. The description of the information to be set and the information set in the third “[[loops.arrays]]” item in which the information about the array a included in the loop shown in FIG. To do.

  Further, the content included in the first information 135b illustrated in FIG. 20 is the same as the content included in the first information 135a described in FIG. Therefore, detailed description of the first information 135b illustrated in FIG. 20 is omitted.

  Returning to FIG. 12, when loop replacement is not instructed for the loop specified in the process of S31 (NO in S32), the information generation unit 112 analyzes the loop specified in the process of S31, and performs the process of S31. Second information 136 corresponding to the identified loop is generated (S33).

  That is, in this case, the loop exchanging unit 113 generates, as the second information 136, information regarding the loop when the loop is not exchanged. Hereinafter, a specific example when the second information 136 is generated will be described.

[Specific example when second information is generated]
First, a specific example of a loop for which loop exchange is not instructed and a loop after loop division is described. FIG. 21 is a diagram illustrating a specific example of a loop for which no loop replacement is instructed. FIG. 22 is a diagram illustrating a specific example of the loop after the loop division is performed on the loop shown in FIG.

  In the double loop shown in FIG. 21, the control variable of the innermost loop is i, and the control variable of the outer loop is j. In the double loop shown in FIG. 21, the innermost loop has a loop count of 10 (times) and the outer loop has a loop count of 10,000 (times). The double loop shown in FIG. 21 includes an instruction consisting of a character string “b (j) = b (j) + a (j, i)” and “c (i) = c (i) + d (i , J) -e (i, j) ”. Note that an instruction to perform loop exchange is not described before the double loop shown in FIG.

  Therefore, in the process of S21, the loop dividing unit 111 converts the loop shown in FIG. 21 into “b (j) = b (j) + a (j, i)” as shown in FIGS. 22 (A) and (B). ”And a loop including“ c (i) = c (i) + d (i, j) −e (i, j) ”. In this case, unlike the case described with reference to FIG. 18, the loop exchanging unit 113 does not exchange the subscript i and the subscript j included in the loop shown in FIG.

  FIG. 23 is a diagram illustrating a specific example of the second information 136 generated from the loop illustrated in FIG. FIG. 24 is a diagram illustrating a specific example of the second information 136 generated from the loop illustrated in FIG. Hereinafter, the second information 136 generated from the loop illustrated in FIG. 22A is also referred to as second information 136a, and the second information 136 generated from the loop illustrated in FIG. 22B is the second information. Also referred to as 136b.

  The contents included in the second information 136a illustrated in FIG. 23 and the second information 136b illustrated in FIG. 24 are the same as the contents included in the first information 135a described with reference to FIG. Therefore, detailed description of the second information 136a shown in FIG. 23 and the second information 136b shown in FIG. 24 is omitted.

  Returning to FIG. 12, after the process of S33 or S35, the information generation unit 112 identifies one array included in the loop identified in the process of S31 as shown in FIG. 13 (S41).

  If the array specified in the process of S41 is a multidimensional array (YES in S42), the information generating unit 112 determines that the value of the first dimension of the array specified in the process of S41 is within the innermost loop. In step S43, it is determined whether or not the change is constant.

  As a result, when it is determined that the value of the first dimension subscript of the array identified in the process of S41 is invariant in the innermost loop (YES in S44), the information generating unit 112 identifies in the process of S41. It is determined whether or not the second and subsequent subscripts in the array are control variables of the innermost loop (S45).

  If it is determined that the second and subsequent subscripts of the array identified in the processing of S41 are control variables of the innermost loop (YES in S46), the information generating unit 112 performs S31 as shown in FIG. It is determined whether loop exchange is instructed for the loop identified in the process (S61).

  As a result, when it is determined that loop exchange is not instructed for the loop identified in S31 (NO in S61), the information generation unit 112 recommends loop exchange for the array identified in S41. Information indicating this (hereinafter also referred to as second recommended information 136c) is generated (S62). On the other hand, when it is determined that loop replacement is instructed for the loop specified in the process of S31 (YES in S61), the information generating unit 112 does not perform the process of S62.

  That is, the value of the first dimension subscript of the array specified in the process of S41 is unchanged in the innermost loop, and any one of the subscripts after the second dimension of the array specified in the process of S41 is the innermost. If the control variable is a loop control variable, the information generation unit 112 determines that the memory access performed in the array identified in the process of S41 is a stride access. For this reason, the information generation unit 112 determines that the loop including the array specified in the process of S41 (the loop specified in the process of S31) is a loop that should be replaced. Specifically, in this case, the information generation unit 112 determines that the loop including the array specified in the process of S41 is a subscript that is the control variable of the innermost loop among the subscripts after the second dimension, and the one-dimensional It is determined that the loop should replace the subscript of the eye. Therefore, when loop exchange is not instructed for the loop specified in the process of S31, the information generation unit 112 performs loop exchange for the loop specified in the process of S31 with respect to the array specified in the process of S41. Information that recommends what to do (second recommended information 136c) is generated.

  In addition, when the 2nd recommendation information 136c is produced | generated, the information generation part 112 may add the 2nd recommendation information 136c to the 2nd information 136 produced | generated by the process of S33. Hereinafter, a specific example of the second information 136 to which the second recommended information 136c is added will be described.

[Specific example of second information to which second recommended information is added]
FIG. 25 is a diagram illustrating a specific example of the second information 136a to which the second recommended information 136c is added.

  In the example shown in FIG. 22A, the value of the first dimension subscript j of the array a included in the loop is invariant because the control variable of the innermost loop is i. The subscript i in the second dimension of the array a is a control variable of the innermost loop. Furthermore, the loop shown in FIG. 22A does not describe a loop replacement instruction. Therefore, for example, when the loop shown in FIG. 22A is specified in the process of S31 and the array a is specified in the process of S41, the information generating unit 112 relates to the array a in the process of S62. The second recommendation information 136c indicating that the performance of the HPC can be improved by performing the loop exchange on the loop shown in A) is generated.

  Therefore, for example, as illustrated in FIG. 25, the information generation unit 112 may specify “hint =“ loop exchange ”for information corresponding to the array a in the second information 136 a described with reference to FIG. 23. Execution efficiency can be improved "and the second recommended information 136c with the content" "is added.

  As a result, when the source code 131 is compiled, the information generation unit 112 can provide information for improving the processing performance of the HPC to, for example, the developer who performed the compilation. Therefore, for example, the developer can easily acquire information for improving the processing performance of the HPC without operating the object code 133 generated by the compiler in the actual machine.

  Returning to FIG. 13, when it is determined that the value of the first dimension subscript of the array specified in the process of S41 is not unchanged in the innermost loop (NO in S44), or 2 of the array specified in the process of S41 When it is determined that the subscripts after the dimension are not control variables of the innermost loop (NO in S46), the information generation unit 112, as shown in FIG. 14, the information generation unit 112 uses the array specified in the process of S41. It is determined whether or not the first-dimensional subscript is a control variable of the innermost loop (S51).

  As a result, when it is determined that the first-dimensional subscript of the array specified in the process of S41 is the control variable of the innermost loop (YES in S52), the information generating unit 112 stores the array specified in the process of S41. It is determined whether or not the value of the subscript after the second dimension is unchanged in the innermost loop (S53).

  If it is determined that the subscript values after the second dimension of the array identified in the process of S41 are unchanged in the innermost loop (YES in S54), the information generating unit 112, as shown in FIG. Then, it is determined whether or not a loop exchange is instructed for the loop specified in the process of S31 (S65).

  As a result, when it is determined that loop replacement is instructed for the loop identified in S31 (YES in S65), the information generation unit 112 does not recommend loop replacement for the array identified in S41. Information indicating this (hereinafter also referred to as first recommended information 135c) is generated (S66). On the other hand, when it is determined that loop replacement is not instructed for the loop specified in the process of S31 (NO in S65), the information generating unit 112 does not perform the process of S66.

  That is, if the information generation unit 112 determines that the memory access performed in the array specified in the process of S41 is not a stride access, whether the memory access performed in the array specified in the process of S41 is a continuous access or not. Make a decision. Specifically, the information generation unit 112 determines that the first-dimensional subscript of the array specified in the process of S41 is the control variable of the innermost loop, and the subscripts for the second and subsequent dimensions of the array specified in the process of S41. Is unchanged in the innermost loop, it is determined that the memory access performed in the array specified in the process of S41 is a continuous access. Therefore, in this case, the information generation unit 112 determines that the loop including the array identified in the process of S41 (the loop identified in the process of S31) is a loop that should not be replaced. Therefore, when the loop exchange is instructed for the loop specified in the process of S31, the information generation unit 112 performs the loop exchange for the loop specified in the process of S31 with respect to the array specified in the process of S41. Information that is not recommended to be generated (first recommended information 135c) is generated.

  Note that when the first recommendation information 135c is generated, the information generation unit 112 may add the first recommendation information 135c to the first information 135 generated in the process of S35. Hereinafter, a specific example of the first information 135 to which the first recommendation information 135c is added will be described.

[Specific example of first information to which first recommended information is added]
FIG. 26 is a diagram illustrating a specific example of the first information 135 to which the first recommendation information 135c is added.

  In the example shown in FIG. 18B, the value of the first dimension subscript i of the array d included in the loop is invariant because the control variable of the innermost loop is j. The subscript j in the second dimension of the array d is a control variable of the innermost loop. Further, a loop exchange instruction is described in the loop shown in FIG. Therefore, for example, when the loop shown in FIG. 18B is specified in the process of S31 and the array d is specified in the process of S41, the information generation unit 112 relates to the array d in the process of S66. The first recommendation information 135c is generated to indicate that the HPC processing performance can be improved when the loop is not exchanged for the loop shown in B). Similarly, the information generation unit 112 similarly generates the first recommended information 135c for the array e included in the loop illustrated in FIG.

  Therefore, for example, as illustrated in FIG. 26, the information generation unit 112 should not specify “hint =“ loop exchange ”for information corresponding to the array d in the first information 135 described in FIG. 20. Execution efficiency can be improved, and first recommendation information 135c having the content "" is added. Similarly, the information generation unit 112 also improves the execution efficiency of the information corresponding to the array e in the first information 135 described with reference to FIG. 20 by not specifying “hint =“ loop exchange ”. The first recommendation information 135c having the content “can be planned” is added.

  As a result, when the source code 131 is compiled, the information generation unit 112 can provide information for improving the processing performance of the HPC to, for example, the developer who performed the compilation. Therefore, for example, the developer can easily acquire information for improving the processing performance of the HPC without operating the object code 133 generated by the compiler in the actual machine.

  Returning to FIG. 15, after the process of S62 or the process of S66, the information generating unit 112 determines whether or not all of the arrays have been specified in the process of S41 (S63). If the array specified in the process of S41 is not a multidimensional array (NO in S42), it is determined that the first-dimensional subscript of the array specified in the process of S41 is not a control variable of the innermost loop (in S52) NO) or when it is determined that the values of the subscripts after the second dimension of the array specified in the processing of S41 are not invariant in the innermost loop (NO in S54), the information generating unit 112 also performs S63. Perform the process.

  As a result, when it is determined that the identification of all the arrays has been completed in the process of S41 (YES in S63), the information generating unit 112 determines whether the identification of all the loops has been completed in the process of S31 ( S64). On the other hand, when it is determined that the identification of all the arrays has not been completed in the process of S41 (NO in S63), the information generation unit 112 performs the processes after S41 again.

  And when it determines with the identification of all the loops having been completed by the process of S31 (YES of S64), the information processing apparatus 1 complete | finishes the process of S24. On the other hand, if it is determined that the identification of all the loops has been completed in the process of S31 (NO in S64), the information generating unit 112 performs the processes after S31 again.

  Returning to FIG. 11, the information output unit 114 outputs the first information or the second information generated in the process of S24 (S25). Specifically, the information output unit 114 outputs the first information or the second information generated in the process of S24 for each of the loops included in the intermediate language 132 generated in S2.

  Thus, when the information processing apparatus 1 according to the present embodiment compiles the source code 131, the order of memory access performed in a specific loop instructed to replace the loop among the loops included in the source code 131. The first information 135 related to the specific loop when the loop exchange is performed or the second information 136 related to the specific loop when the loop exchange is not performed is generated. Then, the information processing apparatus 1 outputs the generated first information 135 or second information 136.

  That is, for example, when the source code 131 is compiled, the information processing apparatus 1 determines whether the memory access performed in a specific loop is continuous access or stride access. For example, when loop exchange is performed in a specific loop and it is determined that continuous access is performed in the specific loop, the information processing apparatus 1 should not perform loop exchange in the specific loop. Information indicating that (first information 135) is output. On the other hand, for example, when loop exchange is not performed in a specific loop and it is determined that stride access is performed in the specific loop, the information processing apparatus 1 should perform loop exchange in the specific loop. Is output (second information 136) indicating that the

  As a result, the developer refers to the information output by the information processing apparatus 1 so that, for example, each of the loop exchanges performed by the compiler without causing the object code 133 to operate on the actual machine, improves the processing performance of the HPC. It becomes possible to easily verify whether or not it was necessary for improvement.

  The above embodiment is summarized as follows.

(Appendix 1)
When compiling source code, among the loops included in the source code, the identification when the loop is exchanged based on the order of memory access performed in the specific loop instructed to exchange the loop An information generation unit that generates first information about the loop of the second loop or information about the specific loop when the loop is not exchanged;
An information output unit that outputs the generated first information or the second information;
An information processing apparatus characterized by that.

(Appendix 2)
In Appendix 1,
When the memory access performed in the specific loop is sequentially performed on consecutive storage areas, the information generation unit displays information indicating that it is not recommended to replace the loop with respect to the specific loop. Generate as information,
An information processing apparatus characterized by that.

(Appendix 3)
In Appendix 1,
The information generation unit receives information indicating that a loop replacement for the specific loop is recommended when the memory access performed in the specific loop is not sequentially performed on continuous storage areas. Generate as information
An information processing apparatus characterized by that.

(Appendix 4)
In Appendix 2 or 3,
In the information generation unit, the value of the first dimension subscript in the specific loop is unchanged in the innermost loop of the specific loop, and the second and subsequent subscripts in the specific loop are in the innermost loop. If it is a control variable of a loop, it is determined that the memory access performed in the specific loop is not performed in order for a continuous storage area;
An information processing apparatus characterized by that.

(Appendix 5)
In Appendix 2 or 3,
In the information generation unit, the first-dimensional subscript in the specific loop is a control variable of the innermost loop of the specific loop, and the second-dimensional subscript value in the specific loop is the innermost loop. Determining that the memory access performed in the specific loop is sequentially performed on consecutive storage areas,
An information processing apparatus characterized by that.

(Appendix 6)
In Appendix 1,
The specific loop is a plurality of loops divided from a loop included in the source code,
The information generation unit generates the first information or the second information for each of the plurality of loops.
An information processing apparatus characterized by that.

(Appendix 7)
When the source code is compiled, the loop in the case where the loop is exchanged based on the order of the memory access performed in a specific loop that is not instructed to exchange the loop among the loops included in the source code. An information generation unit that generates first information about a specific loop or second information about the specific loop when no loop is exchanged;
An information output unit that outputs the generated first information or the second information;
An information processing apparatus characterized by that.

(Appendix 8)
When compiling source code, among the loops included in the source code, the identification when the loop is exchanged based on the order of memory access performed in the specific loop instructed to exchange the loop Generating first information regarding a loop of the second loop, or second information regarding the specific loop when no loop is exchanged,
Outputting the generated first information or the second information;
A compiling method characterized by the above.

(Appendix 9)
In Appendix 8,
In the generating step, when the memory access performed in the specific loop is sequentially performed on a continuous storage area, information indicating that the replacement of the loop for the specific loop is not recommended is displayed in the first loop. Generate as information,
A compiling method characterized by the above.

(Appendix 10)
In Appendix 8,
In the generating step, when the memory access performed in the specific loop is not sequentially performed on a continuous storage area, information indicating that a loop replacement for the specific loop is recommended is provided in the second loop. Generate as information
A compiling method characterized by the above.

(Appendix 11)
When the source code is compiled, the loop in the case where the loop is exchanged based on the order of the memory access performed in a specific loop that is not instructed to exchange the loop among the loops included in the source code. Generating first information about a specific loop, or second information about the specific loop in the case where no loop exchange has occurred,
Outputting the generated first information or the second information;
A compiling method characterized by the above.

(Appendix 12)
When compiling source code, among the loops included in the source code, the identification when the loop is exchanged based on the order of memory access performed in the specific loop instructed to exchange the loop Generating first information regarding a loop of the second loop, or second information regarding the specific loop when no loop is exchanged,
Outputting the generated first information or the second information;
A compiling program for causing a computer to execute processing.

(Appendix 13)
In Appendix 12,
In the generating step, when the memory access performed in the specific loop is sequentially performed on a continuous storage area, information indicating that the replacement of the loop for the specific loop is not recommended is displayed in the first loop. Generate as information,
A compiled program characterized by that.

(Appendix 14)
In Appendix 12,
In the generating step, when the memory access performed in the specific loop is not sequentially performed on a continuous storage area, information indicating that a loop replacement for the specific loop is recommended is provided in the second loop. Generate as information
A compiled program characterized by that.

(Appendix 15)
When the source code is compiled, the loop in the case where the loop is exchanged based on the order of the memory access performed in a specific loop that is not instructed to exchange the loop among the loops included in the source code. Generating first information about a specific loop, or second information about the specific loop in the case where no loop exchange has occurred,
Outputting the generated first information or the second information;
A compiling program for causing a computer to execute processing.

1: Information processing device 2: Storage device 3: Operation terminal 101: CPU
102: Memory 103: I / O unit 104: Storage medium 130: Information storage area

Claims (11)

When compiling source code, among the loops included in the source code, the identification when the loop is exchanged based on the order of memory access performed in the specific loop instructed to exchange the loop An information generation unit that generates first information about the loop of the second loop or information about the specific loop when the loop is not exchanged;
An information output unit that outputs the generated first information or the second information;
An information processing apparatus characterized by that. In claim 1,
When the memory access performed in the specific loop is sequentially performed on consecutive storage areas, the information generation unit displays information indicating that it is not recommended to replace the loop with respect to the specific loop. Generate as information,
An information processing apparatus characterized by that. In claim 1,
The information generation unit receives information indicating that a loop replacement for the specific loop is recommended when the memory access performed in the specific loop is not sequentially performed on continuous storage areas. Generate as information
An information processing apparatus characterized by that. In claim 2 or 3,
In the information generation unit, the value of the first dimension subscript in the specific loop is unchanged in the innermost loop of the specific loop, and the second and subsequent subscripts in the specific loop are in the innermost loop. If it is a control variable of a loop, it is determined that the memory access performed in the specific loop is not performed in order for a continuous storage area;
An information processing apparatus characterized by that. In claim 2 or 3,
In the information generation unit, the first-dimensional subscript in the specific loop is a control variable of the innermost loop of the specific loop, and the second-dimensional subscript value in the specific loop is the innermost loop. Determining that the memory access performed in the specific loop is sequentially performed on consecutive storage areas,
An information processing apparatus characterized by that. In claim 1,
The specific loop is a plurality of loops divided from a loop included in the source code,
The information generation unit generates the first information or the second information for each of the plurality of loops.
An information processing apparatus characterized by that. When the source code is compiled, the loop in the case where the loop is exchanged based on the order of the memory access performed in a specific loop that is not instructed to exchange the loop among the loops included in the source code. An information generation unit that generates first information about a specific loop or second information about the specific loop when no loop is exchanged;
An information output unit that outputs the generated first information or the second information;
An information processing apparatus characterized by that. When compiling source code, among the loops included in the source code, the identification when the loop is exchanged based on the order of memory access performed in the specific loop instructed to exchange the loop Generating first information regarding a loop of the second loop, or second information regarding the specific loop when no loop is exchanged,
Outputting the generated first information or the second information;
A compiling method characterized by the above. When the source code is compiled, the loop in the case where the loop is exchanged based on the order of the memory access performed in a specific loop that is not instructed to exchange the loop among the loops included in the source code. Generating first information about a specific loop, or second information about the specific loop in the case where no loop exchange has occurred,
Outputting the generated first information or the second information;
A compiling method characterized by the above. When compiling source code, among the loops included in the source code, the identification when the loop is exchanged based on the order of memory access performed in the specific loop instructed to exchange the loop Generating first information regarding a loop of the second loop, or second information regarding the specific loop when no loop is exchanged,
Outputting the generated first information or the second information;
A compiling program for causing a computer to execute processing. When the source code is compiled, the loop in the case where the loop is exchanged based on the order of the memory access performed in a specific loop that is not instructed to exchange the loop among the loops included in the source code. Generating first information about a specific loop, or second information about the specific loop in the case where no loop exchange has occurred,
Outputting the generated first information or the second information;
A compiling program for causing a computer to execute processing.

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