JP2019021831A - Semiconductor device and submodule for semiconductor device - Google Patents

Abstract

To provide a semiconductor device that can suppress blowout of gas through a crack when the crack is produced at a resin portion adjacent to neighborhood of a semiconductor element by flowing large current through the semiconductor element.SOLUTION: A submodule 20 for a semiconductor device comprises: a semiconductor element that has a first principal surface 23 and a second principal surface 25 spreading in a perpendicular direction to its chip thickness direction; a first metallic conductor 30 that is electrically connected to at least a portion of the first principal surface 23 and that has a first external surface 35; and a second metallic conductor 50 that is connected to at least a portion of the second principal surface 25 and that has a second external surface. Further, the semiconductor device 10 comprises: a resin part 60 that resin-seals the semiconductor element 22, the first metallic conductor 30 and the second metallic conductor 50 such that at least a portion of the first external surface 35 and at least a portion of the second external surface 55 expose respectively to the outside of the submodule 20; and a case 70 that is disposed adjacent to the resin part 60, and that at least partially surrounds the resin part.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a semiconductor device that performs power control using a semiconductor element.

  There is a semiconductor device that performs power control such as power conversion and power switching using a semiconductor element. A so-called power semiconductor element used in such a device is usually configured to handle a high voltage and a large current. Examples of a power device that performs power control using such a semiconductor element include a power converter that performs power conversion using a semiconductor element, such as a thyristor converter or a transistor inverter.

  In order to realize a large-capacity power converter, it is required to increase the current capacity flowing through the semiconductor element. For this reason, some semiconductor devices have a plurality of semiconductor elements arranged therein and electrically connected in parallel. For example, the following patent document proposes a semiconductor device in which a plurality of semiconductor elements are sandwiched between members made of two metals, and these are arranged in an envelope made of ceramics. ing. In addition, as a component of a semiconductor device, a semiconductor element and a conductor bonded to the semiconductor element are sealed (molded) with a synthetic resin.

Japanese Patent No. 3258200 Japanese Patent No. 4385324

  In such a semiconductor device, generally, a plate-like semiconductor element is disposed between plate-like members (so-called electrode plates) made of two metals. For example, in the technique described in Patent Document 1, a plurality of semiconductor elements (semiconductor chips) are arranged at intervals between two metal plate-like portions (electrode plates). In this example, an emitter current flows through one of the two electrode plates, and a collector current flows through the other. The main surface of each semiconductor chip is in contact with the thermal buffer plate, and each semiconductor chip receives a compressive force acting between the two electrode plates via the thermal buffer plate. That is, in each semiconductor chip, stress in the compressive direction is generated in the thickness direction. In such a semiconductor device, it is necessary to generate uniform stress on each semiconductor chip, and high accuracy is required for the dimensions of each component and the assembly of the components.

  Further, as in the semiconductor device described in Patent Document 2, two main surfaces of the semiconductor element are joined to electrodes and the like by solder or the like, so that almost no stress is generated in the semiconductor element. The side surface between the two main surfaces, that is, the outer periphery of the semiconductor element, is surrounded by a synthetic resin as an electrical insulator. In this semiconductor device, bonding failure may occur on the main surface of the semiconductor element in the manufacturing process. When a large current flows through a semiconductor element due to a failure of a semiconductor device, the temperature rises due to Joule heat generation, particularly in a region where there is a poor connection, and the semiconductor element and the metal conductor adjacent to the semiconductor element expand, melt, and vaporize. (Sublimation) or the like may increase the pressure rapidly.

  When a semiconductor element and a conductor bonded to the semiconductor element are resin-sealed with a synthetic resin, when the pressure increase described above occurs in the vicinity of the semiconductor element, a crack is formed in the synthetic resin part adjacent to the semiconductor element. May occur. Such a crack generally occurs from the vicinity of the semiconductor element and often propagates in a direction substantially perpendicular to the thickness direction of the semiconductor element. When the crack reaches the outer surface of the resin portion, the gas in which the metal or the like is vaporized is jetted out of the resin portion through the crack. If such a gas adheres to a component made of an electrically insulating material such as an envelope, for example, the electrical insulating performance of the component may be impaired.

  An embodiment of the present invention has been made in view of the above, and when a large current flows through a semiconductor element and a crack is generated in the resin portion adjacent from the vicinity of the semiconductor element, gas is passed through the crack. An object is to provide a semiconductor device capable of suppressing ejection.

A semiconductor device according to an embodiment of the present invention is a semiconductor device in which a submodule is disposed therein, and the submodule has a first main surface and a second main surface extending in a direction perpendicular to the chip thickness direction. And a semiconductor element having at least a portion of the first main surface and electrically connected to at least a portion of the first metal conductor having a first outer surface and the second main surface. The semiconductor element, the first metal conductor, and the second metal conductor having a second outer surface, and at least a part of the first outer surface and at least a part of the second outer surface exposed to the outside of the submodule, respectively. The second metal conductor includes a resin portion that is resin-sealed, and a case that is disposed adjacent to the resin portion and at least partially surrounds the resin portion.
Further, the semiconductor device submodule of the embodiment of the present invention is a semiconductor device submodule disposed in the semiconductor device,
A semiconductor element having a first main surface and a second main surface extending in a direction perpendicular to the chip thickness direction, and a first element having a first outer surface electrically connected to at least a part of the first main surface. 1 metal conductor and at least a part of the second main surface are electrically connected, a second metal conductor having a second outer surface, at least a part of the first outer surface and at least a part of the second outer surface The semiconductor element, the first metal conductor, and the second metal conductor are respectively disposed adjacent to the resin portion, and the resin portion is exposed so as to be exposed outside the submodule. And a case enclosing at least partially.

  According to the embodiment of the present invention, a large current flows and the pressure in the submodule increases, and a crack extends from the vicinity of the semiconductor element to the adjacent resin portion in a direction perpendicular to the thickness direction of the semiconductor element. The gas can be prevented from being ejected through the crack.

It is sectional drawing of the semiconductor device of 1st Embodiment. It is sectional drawing of the submodule for semiconductor devices of 1st Embodiment. It is sectional drawing by the III-III line of FIG. FIG. 3 is a side view of the semiconductor device according to the first embodiment, and is a view seen from a direction indicated by an arrow S in FIG. 2. It is sectional drawing of the semiconductor device of 2nd Embodiment. It is sectional drawing of the submodule for semiconductor devices of 3rd Embodiment. It is sectional drawing of the submodule for semiconductor devices of 4th Embodiment. It is a side view of the submodule for semiconductor devices of 4th Embodiment. It is sectional drawing of the submodule for semiconductor devices of 5th Embodiment, and is sectional drawing by the IX-IX line of FIG. FIG. 10 is an enlarged side view of a semiconductor device submodule according to a fifth embodiment, and is an enlarged view of FIG. 9. FIG. 10 is a cross-sectional view of a submodule for a semiconductor device according to a fifth embodiment, and is a bottom view seen from the direction indicated by arrow B in FIG. 9. It is sectional drawing of the semiconductor device of 6th Embodiment. It is sectional drawing of the semiconductor device of the modification of 6th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the embodiments described below, and various modifications can be made without departing from the scope of the invention.

[First Embodiment]
The semiconductor device of this embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view of the semiconductor device of this embodiment. FIG. 2 is a cross-sectional view of the semiconductor device submodule of the present embodiment. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is a side view of the semiconductor device of this embodiment, and is a view seen from the direction indicated by the arrow S in FIG.

  As shown in FIGS. 1 and 2, the semiconductor device 10 of the present embodiment is a power device in the field of power electronics, and a semiconductor device submodule (hereinafter simply referred to as “submodule”) 20 is included therein. Is to be placed. In the present embodiment, the semiconductor device 10 has a plurality of submodules 20 arranged therein. Each submodule 20 has a semiconductor element 22 therein. The plurality of submodules 20, that is, the semiconductor elements 22 are electrically connected in parallel, and are configured to withstand a high voltage (several kV). An example of such a semiconductor device 10 is a semiconductor power converter (semiconductor converter) that performs power conversion.

  The semiconductor element 22 of this embodiment is a power semiconductor element to which a high voltage (for example, 8000 V) of a power system (not shown) is applied, a so-called power semiconductor. The semiconductor element 22 of the present embodiment forms a switching element such as an insulated gate bipolar transistor (IGBT) or an oxide film semiconductor field effect transistor (MOSFET).

  As shown in FIG. 2, the semiconductor element 22 is a so-called semiconductor chip having a substantially plate shape, and extends in a direction perpendicular to the thickness direction (hereinafter referred to as the chip thickness direction). 23 and a second main surface 25. The second main surface 25 is a surface on the side opposite to the first main surface 23 in the chip thickness direction, that is, a so-called back surface. The first main surface 23 and the second main surface 25 are parallel to each other. The semiconductor element 22 has a substantially rectangular shape when viewed from the chip thickness direction. The first main surface 23 and the second main surface 25 each include an electrode surface for controlling electric power.

  The direction toward the semiconductor element 22 in the chip thickness direction is referred to as “inside”, and the direction away from the semiconductor element 22 is referred to as “outside”. In the submodule 20, the direction toward the semiconductor element 22 in the direction perpendicular to the chip thickness direction is referred to as “inside”, and the direction away from the semiconductor element 22 is referred to as “outside”.

  In the semiconductor element 22 of the present embodiment, the first main surface 23 is a collector electrode surface and is made of a conductor such as metal. The 1st main surface 23 (namely, collector electrode surface) can be comprised with the material containing aluminum, such as an aluminum alloy, for example. The first main surface 23 may include a surface (so-called guard ring) surrounding the collector electrode surface made of an electrically insulating material.

  On the other hand, the second main surface 25 includes an emitter electrode surface and a gate electrode surface (not shown). The emitter electrode surface and the gate electrode surface are each made of a conductor such as metal, and can be made of a material containing aluminum such as an aluminum alloy, for example. The second main surface 25 preferably has a guard ring that electrically insulates the gate electrode surface from the emitter electrode surface.

  The submodule 20 includes a conductor (hereinafter referred to as a first metal conductor) 30 that is electrically connected to at least a part of the first main surface 23 of the semiconductor element 22 and made of metal. Yes. In the present embodiment, the first metal conductor 30 is electrically connected to the collector electrode surface included in the first main surface 23. A part of the first main surface 23 may be a collector electrode surface. The first metal conductor 30 is disposed on one side of the semiconductor element 22 (indicated by an arrow T1 in the drawing), that is, on the collector side in the chip thickness direction.

  A bonding material 24 is disposed between the inner surface 31 of the first metal conductor 30 and the first main surface 23 of the semiconductor element 22. The first metal conductor 30 and the semiconductor element 22 are bonded to each other by the bonding material 24. Thereby, at least a part of the first main surface 23 of the semiconductor element 22, specifically, the collector electrode surface is electrically connected to the first metal conductor 30 through the bonding material 24.

  The submodule 20 has a conductor 50 (hereinafter referred to as a second metal conductor) 50 that is electrically connected to at least a part of the second main surface 25 of the semiconductor element 22 and made of metal. doing. In the present embodiment, the second metal conductor 50 is electrically connected to the emitter electrode surface of the second main surface 25. A part of the second main surface 25 may be a collector electrode surface. The second metal conductor 50 is the other side of the semiconductor element 22 in the chip thickness direction, that is, the side opposite to the first metal conductor 30 (indicated by an arrow T2 in the drawing), and is disposed on the emitter side.

  A bonding material 26 is disposed between the inner surface 51 of the second metal conductor 50 and the second main surface 25 of the semiconductor element 22. The second metal conductor 50 and the semiconductor element 22 are bonded to each other by the bonding material 26. Thereby, at least a part of the second main surface 25 of the semiconductor element 22, specifically, the emitter electrode surface is electrically connected to the second metal conductor 50 through the bonding material 26.

  The submodule 20 has two outer surfaces 35 and 55 in order to provide an external electrical connection. Specifically, in the submodule 20, the first metal conductor 30 has a first outer surface 35, and the second metal conductor 50 has a second outer surface 55. The first outer surface 35 and the second outer surface 55 are surfaces exposed to the outside of the submodule 20 (so-called exposed surfaces).

  In the present embodiment, the first outer surface 35 is electrically connected to the collector electrode surface, and the second outer surface 55 is electrically connected to the emitter electrode surface. The first outer surface 35 and the second outer surface 55 are surfaces (so-called bonding surfaces) that are bonded to the corresponding metal members 13 and 15, respectively. That is, the first metal conductor 30 is electrically connected to the collector-side metal member 13 through the first outer surface 35, and the second metal conductor 50 is electrically connected to the emitter-side metal member 15 through the second outer surface 55. Is done.

  In the present embodiment, the first outer surface 35 is disposed outside the first metal conductor 30 in the chip thickness direction, specifically, on the collector side indicated by the arrow T1. On the other hand, the second outer surface 55 is disposed on the outer side in the chip thickness direction of the second metal conductor 50, specifically, on the emitter side T2 indicated by the arrow T2. In the first metal conductor 30, the first outer surface 35 and the inner surface 31 extend in a direction perpendicular to the chip thickness direction, and are parallel to each other. Further, in the second metal conductor 50, the second outer surface 55 and the inner surface 51 are spread in a direction perpendicular to the chip thickness direction, and are parallel to each other.

  In the present embodiment, the second metal conductor 50 includes a portion (hereinafter, referred to as an inner portion) 52 that forms the inner side in the thickness direction including the inner surface 51, and a thickness direction including the second outer surface 55. A portion (hereinafter referred to as an outer portion) 54 forming the outside. The inner portion 52 is a portion whose cross-sectional area perpendicular to the thickness direction is smaller than that of the outer portion 54. The outer portion 54 has a surface 53 (hereinafter referred to as an opposing surface) 53 that opposes the semiconductor element 22 and the second main surface 25 in the thickness direction. The inner portion 52 is a portion protruding from the facing surface 53 of the outer portion 54 in the thickness direction, that is, toward the second main surface 25 of the semiconductor element 22.

  In the semiconductor device 10 of the present embodiment, two submodules 20 are arranged inside, and the two submodules 20 are arranged in a predetermined direction (hereinafter referred to as width) in a direction perpendicular to the chip thickness direction. It is described as a direction and indicated by an arrow W in FIG. The second metal conductor 50 of each submodule 20 has one outer portion 54 and two inner portions 52 protruding from the outer portion 54. The two inner portions 52 are arranged at intervals in a direction perpendicular to the chip thickness direction and the width direction (hereinafter referred to as a longitudinal direction and indicated by an arrow L in FIG. 3).

  The first metal conductor 30 and the second metal conductor 50 are preferably composed of a material having both high electrical conductivity and high thermal conductivity. For example, copper or a copper alloy can be used as the material. The thickness of the first metal conductor 30 in the chip thickness direction is preferably 4 mm or more. The thickness of the second metal conductor 50 including the inner portion 52 and the outer portion 54 is preferably 4 mm or more. In addition, the 1st metal conductor 30 and the 2nd metal conductor 50 are good also as what is comprised with the material from which a linear expansion coefficient differs according to the difference in the shape.

  The bonding materials 24 and 26 described above can use filler metals having various melting points such as solder, conductive adhesive, or silver paste. By melting such a filler material by, for example, reflow treatment, the semiconductor element 22 can be joined to the first metal conductor 30 and the second metal conductor 50, respectively.

  The semiconductor element 22, the first and second metal conductors 30 and 50, and the bonding materials 24 and 26 bonded as described above are sealed with resin. That is, the submodule 20 includes a portion (hereinafter referred to as a resin portion) 60 for plastic molding the semiconductor element 22 and the first and second metal conductors 30 and 50 described above. The resin portion 60 is made of a synthetic resin, and a thermosetting resin is used in the present embodiment. As such a thermosetting resin, for example, a melamine resin can be used. The resin-sealing mold is placed in a vacuum state, and a high-temperature thermosetting resin is injected into the mold and solidified, so that the resin is sealed without leaving bubbles in the vicinity of the metal conductors 30 and 50 and the semiconductor element 22. It is possible to stop.

  In the submodule 20, the first metal conductor 30 and the second metal conductor 50 are each a thermosetting resin such that at least a part of the first outer surface 35 and at least a part of the second outer surface 55 are exposed outside the submodule 20. Is sealed with resin. In the present embodiment, the entire first outer surface 35 and the entire second outer surface 55 are exposed outside the submodule 20. Note that at least one of the first outer surface 35 and the second outer surface 55 may be covered with a resin that forms the resin portion 60.

  In addition, the submodule 20 includes a member (hereinafter simply referred to as “case”) 70 that at least partially surrounds the resin portion 60. In the present embodiment, the case 70 is disposed adjacent to the resin portion 60 in a direction perpendicular to the chip thickness direction. The case 70 at least partially covers the surface of the resin portion 60 that is not in contact with the semiconductor element 22, the first metal conductor 30, and the second metal conductor 50.

  In this embodiment, as shown in FIG. 3, the case 70 surrounds the resin part 60 over the whole periphery, and has comprised the substantially cylindrical shape. The case 70 is disposed adjacent to a surface 66 (hereinafter, simply referred to as “outer surface”) 66 of the resin portion 60 in the direction perpendicular to the chip thickness direction, and covers the entire outer surface 66. Yes. Of the resin portion 60, a surface 67 that surrounds the first outer surface 35 adjacent to the first outer surface 35 and a surface 68 that surrounds the second outer surface 55 adjacent to the second outer surface 55 are: It is not covered by the case 70.

  The case 70 of the present embodiment is disposed adjacent to the resin portion 60 outside the semiconductor element 22, the first metal conductor 30, and the second metal conductor 50 in a direction perpendicular to the chip thickness direction, and the chip thickness. It is formed only by a portion (side portion) extending in the vertical direction. The case 70 surrounds the resin part 60 over the entire circumference.

  The case 70 is made of a composite material using glass fiber as a reinforcing material and a thermosetting resin as a base material (matrix), so-called glass fiber reinforced plastic (GFRP). In the present embodiment, a woven fabric using glass fibers (glass yarn), so-called glass cloth, is used as the reinforcing material. An epoxy resin is used as the thermosetting resin as a base material. Various materials can be used for the case 70. In the submodule 20 of the present embodiment, the case 70 may be made of metal.

  In the present embodiment, the second main surface 25 of the semiconductor element 22 includes a gate electrode surface, and the submodule 20 has a gate terminal 29 electrically connected to the gate electrode surface. The gate terminal 29 extends through the case 70 and its end is exposed outside the submodule 20. As shown in FIGS. 2 and 4, the case 70 has a through hole 79 through which the gate terminal 29 passes. The gate terminal 29 passes through the inside of the through hole 79.

  The gate terminal 29 is electrically connected to the gate electrode surface on the second main surface 25 through the bonding wire 85. The gate terminal 29 and the bonding wire 85 may be electrically connected via another metal conductor. In the present embodiment, the gate terminal 29 and the bonding wire 85 are resin-sealed by the resin portion 60 together with the semiconductor element 22, the first metal conductor 30 and the second metal conductor 50.

  As illustrated in FIG. 1, the submodule 20 described above is disposed between two metal members (hereinafter referred to as metal members) 13 and 15 in the semiconductor device 10. In the present embodiment, the plurality of submodules 20 are arranged between the two metal members 13 and 15 and are electrically connected in parallel. Specifically, the semiconductor device 10 is made of metal, and a member (hereinafter referred to as a first metal member) 13 that is electrically connected to the first metal conductor 30 of each submodule 20 and each submodule. It has a member (hereinafter referred to as a second metal member) 15 electrically connected to the second metal conductor 50 of the module 20.

  The second metal member 15 is arranged at a distance from the first metal member 13 in a predetermined direction. In the present embodiment, the second metal member 15 is arranged at an interval in the chip thickness direction. The first metal member 13 and the second metal member 15 are each substantially plate-shaped and spread in a direction perpendicular to the chip thickness direction. The inner surface 13a on the inner side in the chip thickness direction of the first metal member 13 and the inner surface 15a on the inner side in the chip thickness direction of the second metal member 15 are parallel to each other. For example, an aluminum alloy can be used as the material constituting the first metal member 13 and the second metal member 15.

  Note that the thickness direction of the first and second metal members 13 and 15 and the internal space formed between the first and second metal members 13 and 15 of the semiconductor device 10 is hereinafter referred to as “device thickness direction” and indicated by an arrow A. In the present embodiment, the device thickness direction A coincides with the chip thickness direction. That is, the second metal member 15 is arranged with a gap in the apparatus thickness direction A from the first metal member 13, and the plurality of submodules 20 are spaced in a direction perpendicular to the apparatus thickness direction A. Are arranged. In a direction perpendicular to the apparatus thickness direction A, the envelope 17 is disposed outside the plurality of submodules 20 and surrounds the plurality of submodules 20. The case 70 of each submodule 20 faces the envelope 17 in a direction perpendicular to the apparatus thickness direction A.

  As shown in FIGS. 1 and 2, the bonding material 14 is disposed between the inner surface 13 a of the first metal member 13 and the first outer surface 35 of the first metal conductor 30. The first metal member 13 and the first metal conductor 30 are joined to each other by the joining material 14. Similarly, the bonding material 16 is disposed between the inner surface 15 a of the second metal member 15 and the second outer surface 55 of the second metal conductor 50. The second metal member 15 and the second metal conductor 50 are joined to each other by the joining material 16. For these bonding materials 14 and 16, a filler material such as solder, conductive adhesive or silver paste can be used. Note that it is preferable that the bonding materials 14 and 16 have a lower melting point than the bonding materials 24 and 26 used in the submodule 20.

  The first metal member 13 and the second metal member 15 are coupled to each other via an envelope 17 made of an electrically insulating material. That is, the semiconductor device 10 includes an envelope 17 that electrically insulates the second metal member 15 from the first metal member 13 and connects (physically) the first metal member 13 and the second metal member 15. have. The envelope 17 at least partially surrounds the plurality of submodules 20 between the first metal member and the second metal member.

  As shown in FIGS. 1 and 3, the envelope 17 according to the present embodiment is disposed outside the plurality of submodules 20, the first metal member 13, and the second metal member 15 in a direction perpendicular to the chip thickness direction. The sub-module 20 and the first and second metal members 13 and 15 are surrounded over the entire circumference. Each submodule 20 is arranged in a space (hereinafter referred to as an internal space) 18 surrounded by the envelope 17, the first metal member 13, and the second metal member 15. The internal space 18 of this embodiment is sealed.

  Each submodule 20 is arranged such that its case 70 faces the envelope 17 made of an electro-insulating material in a direction perpendicular to the chip thickness direction. The plurality of submodules 20 are arranged so that a predetermined interval (gap) is formed between the case 70 and the envelope 17. That is, in the direction perpendicular to the chip thickness direction, a case 70 having a higher strength than the resin portion 60 is disposed between the semiconductor element 22 and the envelope 17 in addition to the resin portion 60.

  In the semiconductor device 10 of the present embodiment, when a large current flows through the semiconductor element 22 of each sub-module 20, the temperature rises due to Joule heat generation near the semiconductor element 22, and a gas in which metal is vaporized is generated and pressure is increased. As a result of this pressure increase, a crack is generally generated in the resin portion 60 from the vicinity of the semiconductor element 22 in the direction perpendicular to the chip thickness direction. Since a high-strength case 70 is disposed outside the resin portion 60 in the direction perpendicular to the chip thickness direction, that is, in the direction in which the crack propagates, the crack in the resin portion 60 propagates outward from the outer surface 66. Can be suppressed. Further, the gas in which metal or the like is vaporized through the crack is prevented from being ejected toward the envelope 17 facing the case 70 in the direction perpendicular to the chip thickness direction, particularly in the direction perpendicular to the chip thickness direction. It can suppress that the metal etc. which are contained in the said gas adhere to the envelope 17 comprised with the electrical insulation material, and the electrical insulation performance is impaired.

  As described above, in the semiconductor device 10, the submodule 20 includes the semiconductor element having the first main surface 23 and the second main surface 25 extending in the direction perpendicular to the chip thickness direction, and the first main surface 23. The first metal conductor 30 having the first outer surface 35 and at least a part of the second main surface 25 are electrically connected to at least a part of the first outer surface 35, and the second outer surface is connected to the second outer surface. And a second metal conductor 50. The first metal conductor 30 is disposed on one side (collector side) of the semiconductor element 22 in the chip thickness direction, and the second metal conductor 50 is disposed on the opposite side (emitter side).

  The semiconductor device 10 further includes the semiconductor element 22, the first metal conductor 30, and the second metal conductor such that at least a part of the first outer surface 35 and at least a part of the second outer surface 55 are exposed outside the submodule 20. A resin part 60 for resin-sealing 50 and a case 70 disposed adjacent to the resin part 60 and at least partially surrounding the resin part are provided. In the present embodiment, the resin portion 60 resinous the semiconductor element 22, the metal conductors 30 and 50, and the bonding materials 24 and 26 so that the first outer surface 35 and the entire second outer surface 55 are exposed outside the submodule 20. It is sealed. The case 70 entirely covers the outer surface 66 on the outer side in the direction perpendicular to the chip thickness direction among the surfaces not in contact with the semiconductor element 22, the metal conductors 30 and 50, and the bonding materials 24 and 26.

  According to the present embodiment, it is possible to suppress the crack of the resin part 60 from extending outward from the surface on the outer side in the chip thickness direction, that is, the outer surface 66. Moreover, it can suppress that the gas which the metal etc. vaporized through the said crack spouts out of the submodule 20, and it suppresses that the metal etc. which are contained in the said gas adhere to the envelope 17. Can do.

  In the present embodiment, the first metal member 13 and the second metal member 15 are arranged at intervals in the chip thickness direction, and the plurality of submodules 20 are arranged in a direction perpendicular to the chip thickness direction. Although it is assumed that the semiconductor devices are arranged, the semiconductor device according to the present invention is not limited to this mode.

[Second Embodiment]
The semiconductor device of this embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view of the semiconductor device of this embodiment. This embodiment is different from the first embodiment in that the submodules are arranged so that the chip thickness direction is perpendicular to the device thickness direction A. In addition, about the structure substantially common to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  As shown in FIG. 5, the semiconductor device 10 </ b> C of the present embodiment has a plurality of submodules 20 </ b> C arranged therein, and each submodule 20 </ b> C has a chip thickness direction perpendicular to the device thickness direction A. It is arranged to be in the direction. That is, in the internal space 18C surrounded by the first metal member 13, the second metal member 15, and the envelope 17, the plurality of submodules 20C are perpendicular to the device thickness direction A (ie, the chip thickness direction). Are arranged at intervals.

  In the present embodiment, the first outer surface 35 is disposed on the first metal conductor 30 in the direction perpendicular to the chip thickness direction, that is, outside the device thickness direction A, specifically, on the first metal member 13 side. ing. On the other hand, the second outer surface 55C is disposed on the outer side in the chip thickness direction of the second metal conductor 50, specifically, on the second metal member 15 side. In the first metal conductor 30, the first outer surface 35 </ b> C extends in a direction perpendicular to the inner surface 31. Similarly, in the second metal conductor 50, the second outer surface 55 </ b> C extends in a direction perpendicular to the inner surface 51.

  A bonding material 14 c is disposed between the inner surface 13 a of the first metal member 13 and the first outer surface 35 </ b> C of the first metal conductor 30. The first metal member 13 and the first metal conductor 30 are bonded to each other by the bonding material 14c. Similarly, the bonding material 16 c is disposed between the inner surface 15 a of the second metal member 15 and the second outer surface 55 </ b> C of the second metal conductor 50. As the bonding materials 14c and 16c, the same filler material as the bonding materials 14 and 16 described above is used.

  The case 70C of the present embodiment is disposed outside the first metal conductor 30, the second metal conductor 50, and the resin portion 60C in the chip thickness direction, and in addition to the resin portion 60C, the first metal conductor 30 or It is arranged adjacent to the second metal conductor 50. The case 70C surrounds the resin portion 60C, the first metal conductor 30, and the second metal conductor 50, and has a substantially cylindrical shape.

  Specifically, the case 70C covers the surfaces 67C and 68C on the outer side in the chip thickness direction of the resin portion 60C. In addition, in the resin part 60 </ b> C, the surface 66 c facing the first metal member 13 and the surface 66 e facing the second metal member 15 are not covered by the case 70.

  In the semiconductor device 10C of the present embodiment, when a large current flows through the semiconductor element 22 of each submodule 20, the resin portion 60C has a direction perpendicular to the chip thickness direction from the vicinity of the semiconductor element 22, that is, the device thickness. A crack that propagates in direction A occurs. For example, when a gas containing metal is ejected from the surface 66 c facing the first metal member 13 through such a crack, the flow of the gas collides with the inner surface 13 a of the first metal member 13. Further, when the gas is ejected from the surface 66 e facing the second metal member 15, the gas collides with the inner surface 15 a of the second metal member 15. In this way, the possibility that the gas ejected through the crack generated in the resin portion 60C directly collides with the envelope 17 can be reduced.

[Third Embodiment]
The semiconductor device of this embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view of the semiconductor device submodule of the present embodiment. In this embodiment, the shape of the case is particularly different from that of the first embodiment. In addition, about the structure substantially common to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  As shown in FIG. 6, in the submodule 20 </ b> E of the present embodiment, the case 70 </ b> E includes the semiconductor element 22, the first metal conductor 30, the second metal conductor 50, and the bonding material 24 that joins them, 26 is configured to cover all of the surface not in contact with 26. The case 70E is disposed outside the resin portion 60 in a direction perpendicular to the chip thickness direction, and has a portion (hereinafter referred to as a side portion) 71 extending in the chip thickness direction. The side portion 71 covers a surface 66 of the resin portion 60 on the outer side in the direction perpendicular to the chip thickness direction.

  Further, the case 70E extends from one edge of the side portion 71 toward the first outer surface 35, and a portion (hereinafter referred to as a first edge portion) 73 that surrounds the space E1 on the first outer surface 35; , Extending from the other edge of the edge portion 73 toward the second outer surface 55 and having a portion (hereinafter referred to as a second edge portion) 75 surrounding the space E2 on the second outer surface 55. . The first edge portion 73 and the second edge portion 75 are joined via the side portion 71.

  The first edge portion 73 and the second edge portion 75 cover the surfaces 67 and 68 on the outside of the resin portion 60 in the chip thickness direction, respectively. Specifically, the first edge portion 73 covers a surface 67 of the resin portion 60 that is adjacent to the first outer surface 35 and surrounds the first outer surface 35. On the other hand, the second edge portion 75 covers a surface 68 of the resin portion 60 that is adjacent to the second outer surface 55 and surrounds the second outer surface 55. The first edge portion 73 is not in contact with the first outer surface 35, and the second edge portion 75 is not in contact with the second outer surface 55.

  The case 70E is made of, for example, a metal case that completely covers the semiconductor element 22, the first and second metal conductors 30 and 50, and the resin portion 60, and then a portion E1 that is outside the first outer surface 35. The portion E2 outside the second outer surface 55 is removed by cutting or the like, so that the first outer surface 35 and the second outer surface 55 are exposed outside the submodule 20, respectively. Thereafter, the bonding material 14 is disposed on the first outer surface 35 to bond the first metal conductor 30 and the first metal member 13 (see FIG. 1). Similarly, the bonding material 16 is disposed on the second outer surface 55 to bond the second metal conductor 50 and the second metal member 15 together. The case 70E is preferably made of a material that is relatively easy to cut.

  In the present embodiment, in the case 70 </ b> E, the first edge portion 73 does not contact the first outer surface 35, and the second edge portion 75 does not contact the second outer surface 55. For this reason, the first outer surface 35 and the second outer surface 55 are not electrically connected via the case 70E. For this reason, the case 70E can be made of a metal that is relatively easy to cut.

  According to the submodule 20E of the present embodiment, the case 70E covers all surfaces of the resin portion 60 that are not in contact with the semiconductor element 22, the first metal conductor 30, the second metal conductor 50, and the bonding materials 24 and 26. Therefore, it is possible to suppress the gas containing metal from being ejected outside the submodule 20 through the crack generated in the resin portion 60.

  In the present embodiment, the case 70E is made of metal, but the material constituting the case 70E is not limited to this. In addition to the side portion 71, the case 70E has a shape having a first edge portion 73 surrounding the space E1 on the first outer surface 35 and a second edge portion 75 surrounding the space E2 on the second outer surface 55. If possible, it can be composed of various materials. For example, the case 70E can be made of a synthetic resin that is relatively easy to cut.

[Fourth Embodiment]
The semiconductor device of this embodiment will be described with reference to FIGS. FIG. 7 is a cross-sectional view of the semiconductor device submodule of the present embodiment. FIG. 8 is a side view of the semiconductor device submodule of the present embodiment. In addition, about the structure substantially common with 1st and 3rd embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  As shown in FIG. 7, in the submodule 20F of the present embodiment, the case 70F is on the first outer surface 35 and from the edge 35e in addition to the side portion 71 that covers the outer surface 66 of the resin portion 60. It has a first edge portion 74 surrounding the space F1 on the inner side and a second edge portion 76 surrounding the space F2 on the second outer surface 55 and inside the edge portion 55e. The first edge portion 74 and the second edge portion 76 cover the surfaces 67 and 68 on the outside of the resin portion 60 in the chip thickness direction, respectively.

  In addition, the first edge portion 74 is adjacent to the edge portion 35e of the first outer surface 35 in the resin portion 60, and also covers the edge portion 35e. Similarly, the second edge portion 76 is adjacent to the edge portion 55e of the second outer surface 55 of the resin portion 60, and also covers the edge portion 55e. That is, the case 70 </ b> F has an edge portion of the first outer surface 35 in addition to all the surfaces of the resin portion 60 that are not in contact with the semiconductor element 22, the first metal conductor 30, the second metal conductor 50, and the bonding materials 24 and 26. 35e and the edge 55e of the second outer surface 55 are also covered.

  Thus, the case 70F needs to be made of an electrically insulating material because the first edge portion 74 and the second edge portion 76 thereof are in contact with the first outer surface 35 and the second outer surface 55, respectively. In the present embodiment, the case 70F is made of a synthetic resin having electrical insulation.

  The case 70 </ b> F of the present embodiment is, for example, a case made of a synthetic resin that completely covers the semiconductor element 22, the first and second metal conductors 30, 50, and the resin portion 60, and then the edge of the first outer surface 35. A portion excluding the edge portion 35e of the first outer surface 35 by removing the portion F1 inside the portion 35e and the portion F2 outside the edge portion 55e of the second outer surface 55 by cutting or the like; A portion of the second outer surface 55 excluding the edge portion 55e is exposed outside the submodule 20. Further, as shown in FIG. 8, a through hole 79 through which the gate terminal 29 is passed is formed in the side portion 71 of the case 70 </ b> F, and the gate terminal 29 is passed inside the through hole 79. Thereafter, the bonding materials 14 and 16 are disposed on the portion excluding the edge portion 35e and the portion excluding the edge portion 55e, respectively, and the submodule 20F is bonded to the first and second metal members 13 and 15 ( (See FIG. 1).

  According to the submodule 20F of the present embodiment, in the case 70F that covers the resin portion 60, from between the first edge portion 74 and the first outer surface 35 and between the second edge portion 76 and the second outer surface 55. The gas containing metal can be prevented from being ejected out of the submodule 20 through the crack generated in the resin portion 60.

[Fifth Embodiment]
The semiconductor device of this embodiment will be described with reference to FIGS. FIG. 9 is a cross-sectional view of the semiconductor device submodule of the present embodiment, and is a cross-sectional view taken along the line IX-IX of FIG. FIG. 10 is an enlarged side view of the semiconductor device submodule of the present embodiment, and is an enlarged view of FIG. 9. FIG. 11 is a cross-sectional view of the semiconductor device submodule of the present embodiment, and is a bottom view as seen from the direction indicated by the arrow B in FIG. In addition, about the structure substantially common to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The submodule of this embodiment has a substantially rectangular parallelepiped shape. As shown in FIG. 9, the first metal conductor 30 and the second metal conductor 50 are joined to the semiconductor element 22 (hereinafter referred to as an intermediate part). 2) are arranged at intervals in a direction perpendicular to the chip thickness direction, and these two intermediate parts are resin-sealed by one resin portion 60G.

  These two intermediate parts are coupled via a portion 62 (hereinafter referred to as a central portion) 62 in the center in the direction perpendicular to the chip thickness direction of the resin portion 60G. This direction is a direction in which two intermediate components are arranged, and is a direction perpendicular to the chip thickness direction. The direction is referred to as “array direction” and is indicated by an arrow G in the figure. In the resin portion 60G, the two end portions 64 outside the intermediate components in the arrangement direction are coupled to each other via the central portion 62.

  In the present embodiment, the first metal conductor 30 has an electrode 37 protruding from the first outer surface 35 to the outer side (emitter side) in the chip thickness direction on the inner side in the arrangement direction of the first outer surface 35. ing. Similarly, the second metal conductor 50 has an electrode 57 projecting from the second outer surface 55 to the outer side (collector side) in the chip thickness direction on the inner side in the arrangement direction of the second outer surface 55. These electrodes 37 and 57 are joined to the first and second metal members 13 and 15, respectively (see FIG. 1).

  As shown in FIGS. 9 and 11, the submodule of this embodiment has two cases 70 </ b> G corresponding to these two intermediate components. Each case 70G has a box shape having an opening on one of the six surfaces, and has a substantially rectangular parallelepiped shape in the present embodiment. The case 70G is made of an electrically insulating material, and can be made of, for example, a composite material using glass fiber as a reinforcing material and a thermosetting resin as a base material.

  The case 70G has a portion (hereinafter referred to as a side portion) 72 outside the end portion 64 outside in the arrangement direction G of the resin portion 60G, and a portion (hereinafter referred to as the inside) in the arrangement direction from the side portion 72. , Which will be referred to as an inner extension portion). The inner extending portion 77 has a rectangular cross section perpendicular to the arrangement direction, and is a portion surrounding the end portion 64 and the first and second metal conductors 30 and 50 in the resin portion 60G. This is a portion extending from the edge to the electrodes 37 and 57 described above. The opening edge 77e in the arrangement direction of the inner extending portion 77 is in contact with these electrodes 37 and 57.

  The side portion 72 covers the outer surface 66G on the outer side in the arrangement direction of the end portion 64 of the resin portion 60G. The inner extending portion 77 includes side surfaces 67G and 68G extending from the outer surface 66G toward the inner side in the arrangement direction of the end portion 64, a part of the first outer surface 35 extending continuously from the side surfaces 67G and 68G, 2 covers a part of the outer surface 55.

  The side portion 72 covers the outer surface 66G outside the end portion 64 in the arrangement direction. On the other hand, the inner extending portion 77 includes side surfaces 67G and 68G extending from the outer surface 66G toward the inner side in the arrangement direction of the end portion 64, and a part of the first outer surface 35 extending continuously from the side surfaces 67G and 68G, respectively. A portion of the second outer surface 55 is covered.

  As shown in FIG. 11, the submodule of the present embodiment has a member 80 (hereinafter referred to as a connecting member) 80 that connects the two cases 70G. The connecting member 80 extends in the arrangement direction G, and extends from the electrode 37 and from the central portion 62 of the resin portion 60 with a space in the direction perpendicular to the arrangement direction G. Two end portions 82 of the connecting member 80 in the arrangement direction G are respectively coupled to the outer surface 77 c of the inner extending portion 77. That is, the two cases 70G are coupled to each other by the connecting member 80.

  According to the present embodiment, the box-shaped case 70G is attached to the intermediate component in which the first metal conductor 30 and the second metal conductor 50 are joined to the semiconductor element 22 by the resin portion 60G. Modules can be configured. When two intermediate parts are resin-sealed by one resin portion 60G as in the present embodiment, the case 70G is attached to each of the two end portions outside the arrangement direction G of the intermediate parts. Thus, it is possible to realize a submodule in which the outer surface 66G outside the resin portion 60G in the direction perpendicular to the chip thickness direction is covered with the case 70G.

[Sixth Embodiment]
The semiconductor device of this embodiment will be described with reference to FIG. FIG. 12 is a cross-sectional view of the semiconductor device of this embodiment. In addition, about the structure substantially common to 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  As shown in FIG. 12, the semiconductor device 10 </ b> H of this embodiment is provided with members (hereinafter, referred to as heat dissipation members) 90 and 95 for radiating heat from the submodule 20 to the outside. The two heat radiating members 90 and 95 are respectively coupled to the corresponding first metal member 13 and second metal member 15. Specifically, in the semiconductor device 10 </ b> H, the heat radiated from the sub module 20 to the first metal member 13 is dissipated to the outside, and the first heat radiating member 90 is transmitted from the sub module 20 to the second metal member 15. And a second heat radiating member 95 that dissipates heat to the outside.

  In the present embodiment, the first heat radiating member 90 is arranged outside the first metal member 13 in the apparatus thickness direction A, that is, on the emitter side. The first heat radiating member 90 has a substantially plate shape and extends along the outer surface 13 c of the first metal member 13 (hereinafter referred to as a plate-like portion) 92, and the thickness of the device from the plate-like portion 92. And a fin 94 protruding outward in the direction A.

  The second heat radiating member 95 is disposed outside the second metal member 15 in the apparatus thickness direction A, that is, on the collector side. The second heat radiating member 95 has a substantially plate shape and extends along the outer surface 15c of the second metal member 15, and protrudes outward from the plate portion 97 in the apparatus thickness direction A. The fin 99 is provided.

  The semiconductor device 10 </ b> H according to the present embodiment includes the heat radiating members 90 and 95, so that the heat transferred from the submodule 20 to the first and second metal members 13 and 15 can be favorably outside the semiconductor device 10. Can be dissipated. The semiconductor device 10H may further include a jacket that covers the outer surface on which the fins 94 and 99 are formed and forms a passage through which the coolant flows between the outer surface.

  Further, in the semiconductor device 10 </ b> H of the present embodiment, the plurality of submodules 20 are disposed in the sealed internal space 19 surrounded by the envelope 17, the first metal member 13, and the second metal member 15. . The internal space 19 is filled with an electrically insulating substance, and in this embodiment, is filled with silicon gel. The internal space 19 may be filled with a thermosetting resin as an electrically insulating material. Thus, even when a large current flows through the semiconductor element 22 and a gas containing metal is ejected outside the submodule 20, the metal contained in the gas is not contained in the envelope 17, the first metal member 13 or the first metal member 13. Adhesion to the two metal members 15 can be suppressed, and desired electrical insulation performance in the semiconductor device 10 can be ensured. In addition, it is possible to prevent oxidation of components such as the submodule 20 disposed in the internal space 19.

  In the present embodiment, the first heat radiating member 90 and the second heat radiating member 95 are provided corresponding to the first metal member 13 and the second metal member 15, respectively. The semiconductor device provided with the heat radiating member according to the present invention is not limited to this aspect. The heat radiating member may be provided only on one of the first and second metal members 13 and 15.

  In the semiconductor device 10H of the present embodiment, the submodule 20 is arranged so that the chip thickness direction of the semiconductor element 22 coincides with the device thickness direction A. However, the semiconductor device according to the present invention is not limited thereto. Is not limited to this embodiment. For example, as in the semiconductor device 10K of the modification shown in FIG. 13, the submodule 20C is arranged so that the chip thickness direction of the semiconductor element 22 is perpendicular to the device thickness direction A. It is also suitable.

  [Other embodiments]

  In the embodiment described above, the semiconductor element 22 in the submodule 20 forms a switching element such as an IGBT, and the first main surface 23 includes a collector electrode surface (not shown), and the second main surface. The surface 25 includes an emitter electrode surface (not shown), a gate electrode surface (not shown), and a guard ring that electrically insulates the gate electrode surface (not shown) from the emitter electrode surface (not shown). However, the semiconductor element according to the present invention is not limited to this mode. The first main surface and the second main surface of the semiconductor element may be electrically connected to the first metal conductor and the second metal conductor, respectively, and may be made of metal and have an electrode surface.

  For example, the semiconductor element may form a diode such as a fast recovery diode (FRD). In this case, like the present embodiment, the first main surface includes the collector electrode surface, the second main surface includes the emitter electrode surface, and does not include the gate electrode surface. The arranged submodule may not have a gate terminal. One of the first main surface and the second main surface according to the present invention may include an anode electrode surface and a drain electrode surface instead of the collector electrode surface. Further, a cathode electrode surface or a source electrode surface may be included instead of the emitter electrode surface.

  Further, the plurality of semiconductor elements arranged in the semiconductor device according to the present invention need not all be of the same type. In the semiconductor device according to the present invention, a semiconductor element forming a switching element such as an IGBT and a semiconductor element forming a diode such as an FRD may be mixedly arranged.

  Although several embodiments of the present invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 10C, 10H, 10K: semiconductor device, 13: first metal member (metal member), 13a: inner surface, 13c: outer surface, 14, 14c: bonding material, 15: second metal member (metal member), 15a: Inner surface, 15c: outer surface, 16, 16c: bonding material, 17: envelope, 18, 18C: inner space, 19: gel (inner space) 20, 20C, 20E, 20F: submodule, 22, 22C: semiconductor element , 23: first main surface, 24: bonding material, 25: second main surface, 26: bonding material, 29: gate terminal, 30: first metal conductor (metal conductor), 31: inner surface, 35, 35C: first 1 outer surface, 35e: edge, 37: electrode, 50: second metal conductor (metal conductor), 51: inner surface, 52: inner portion, 53: facing surface, 54: outer portion, 55: second outer surface, 55C: Second outer surface, 55e: edge, 57: electrode, 60, 0C, 60G: Resin part, 62: Center part (resin part), 64: End part (resin part), 66, 66G: Outer surface, 66c, 66e: Surface, 67, 67C, 67G: Side surface, 68, 68C, 68G : Side surface, 70, 70C, 70E, 70F, 70G: case, 71, 72: side portion, 73, 74: first edge portion (edge portion), 75, 76: second edge portion (edge portion), 76: Second edge portion, 77: inner extension portion, 77c: outer surface, 77e: opening edge, 79: through hole, 80: connection member, 82: end portion, 85: bonding wire, 90: first heat radiation member (heat radiation Member), 92: plate-like portion, 94: fin, 95: second heat radiating member (heat radiating member), 97: plate-like portion, 99: fin

Claims (15)

A semiconductor device in which a submodule is arranged,
The submodule is
A semiconductor element having a first main surface and a second main surface extending in a direction perpendicular to the chip thickness direction;
A first metal conductor electrically connected to at least a portion of the first main surface and having a first outer surface;
A second metal conductor electrically connected to at least a portion of the second main surface and having a second outer surface;
A resin portion for resin-sealing the semiconductor element, the first metal conductor, and the second metal conductor such that at least a part of the first outer surface and at least a part of the second outer surface are exposed to the outside of the submodule, respectively.
A case that is disposed adjacent to the resin portion and at least partially surrounds the resin portion;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the case covers an outer surface of the resin portion that is outside in a direction perpendicular to the chip thickness direction. The said case covers all the surfaces which are not in contact with the said semiconductor element, the 1st metal conductor, the 2nd metal conductor, and the joining material which joins these among the said resin parts. Alternatively, the semiconductor device according to claim 2. The case is
A side portion disposed outside the resin portion in a direction perpendicular to the chip thickness direction and extending in the chip thickness direction;
A first edge portion extending from one edge of the side portion toward the first outer surface and surrounding a space on the first outer surface;
A second edge portion extending from the other edge of the side portion toward the second outer surface and surrounding a space on the second outer surface;
Have
The first edge portion and the second edge portion are coupled to each other through the side portion, and each of the first edge portion and the second edge portion covers a surface of the resin portion that is outside the chip thickness direction. The semiconductor device according to claim 1. The first edge portion and the second edge portion are not in contact with the first outer surface and the second outer surface, respectively.
The semiconductor device according to claim 4, wherein the case is made of metal or synthetic resin. The first edge portion and the second edge portion cover the edge portion of the first outer surface and the edge portion of the second outer surface, respectively.
The semiconductor device according to claim 4, wherein the case is made of an electrically insulating material. The resin part is made of a thermosetting resin,
7. The semiconductor device according to claim 1, wherein the case is made of a composite material including glass fiber as a reinforcing material and a thermosetting resin as a base material. The second main surface includes a gate electrode surface,
The submodule has a gate terminal that is electrically connected to the gate electrode surface and is exposed outside the submodule through the case.
The semiconductor device according to claim 4, wherein a through hole through which the gate terminal passes is formed in the side portion of the case. The case is
It has a box shape with an opening on one of the six surfaces, and is made of an electrically insulating material.
A side portion covering an outer surface on the outer side in a direction perpendicular to the chip thickness direction of the resin portion;
Of the resin portion, a side surface extending inward in a direction perpendicular to the chip thickness direction from the end surface, a part of the first outer surface and a part of the second outer surface respectively extending continuously to these side surfaces, An inner extension that covers,
The semiconductor device according to claim 1, further comprising: A first metal member joined to the first metal conductor by a joining material and electrically connected to the first metal conductor;
A second metal member that is disposed at a predetermined distance from the first metal member in the device thickness direction and is electrically connected to the second metal conductor by being joined to the second metal conductor by a joining material;
Electrically insulating the second metal member from the first metal member, connecting the first metal member and the second metal member, and at least including a plurality of the submodules between the first metal member and the second metal member; A partially enclosing envelope,
The semiconductor device according to claim 1, further comprising: The submodule is disposed in an internal space surrounded by the envelope, the first metal member, and the second metal member,
11. The semiconductor device according to claim 10, wherein the semiconductor device is arranged at intervals in a direction perpendicular to the device thickness direction in the internal space. The sub-modules are arranged so that the chip thickness direction coincides with the device thickness direction, or the chip thickness direction coincides with a direction perpendicular to the device thickness direction. The semiconductor device according to claim 10, wherein: The sub-module is disposed in an enclosed internal space surrounded by the envelope, the first metal member, and the second metal member,
13. The semiconductor device according to claim 10, wherein the internal space is filled with an electrically insulating material. A plate-like portion that is disposed outside at least one of the first metal member and the second metal member, and extends outward in the apparatus thickness direction from the plate-like portion extending along the metal member. A heat dissipating member capable of dissipating heat transmitted from the submodule,
The semiconductor device according to claim 10, further comprising: A sub-module for a semiconductor device disposed in a semiconductor device,
A semiconductor element having a first main surface and a second main surface extending in a direction perpendicular to the chip thickness direction;
A first metal conductor electrically connected to at least a portion of the first main surface and having a first outer surface;
A second metal conductor electrically connected to at least a portion of the second main surface and having a second outer surface;
A resin portion for resin-sealing the semiconductor element, the first metal conductor, and the second metal conductor such that at least a part of the first outer surface and at least a part of the second outer surface are exposed to the outside of the submodule, respectively.
A case that is disposed adjacent to the resin portion and at least partially surrounds the resin portion;
A sub-module for a semiconductor device, comprising:

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