JP2019016382A - Circuit design method and program - Google Patents

Abstract

To support a layout design work of an electronic circuit.SOLUTION: A circuit design method includes selecting on the basis of circuit design data and analysis data generated on the basis of the circuit design data: an analysis object path including a start point circuit element, first circuit elements, an end point circuit element, and first wiring electrically connecting the start point circuit element via the first circuit elements to the end point circuit element; second circuit elements electrically connected to the first circuit elements included in the path, and excluded from the path; and second wiring electrically connecting the first circuit elements to the second circuit elements. The selection step includes: selecting the designated number of first circuit elements in a decreasing order of a total value of a distance from the start point circuit element and a distance from the end point circuit element; selecting the second circuit elements electrically connected to the designated number of first circuit elements, and excluded from the path; and selecting the second wiring electrically connecting the designated number of first circuit elements to the second circuit elements.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a circuit design method and a program.

  As the circuit design device, for example, an information processing device including a layout CAD (Computer Aided Design) tool is used. The circuit design apparatus supports layout design work of an electronic circuit (for example, an integrated circuit) by an information processing apparatus by a user.

US Pat. No. 6,205,573

  Embodiments provide a circuit design method and a program that effectively support a user's electronic circuit layout design work.

  According to the embodiment, a circuit design method includes: a circuit element at a starting point, a first circuit element, and a circuit element at an end point based on circuit design data and analysis data generated based on the circuit design data by a computer. , And a path to be analyzed including a first wiring that electrically connects the circuit element at the start point to the circuit element at the end point via the first circuit element, and the first circuit element included in the path Selecting a second circuit element that is electrically connected to and not included in the path, and a second wiring that electrically connects the first circuit element and the second circuit element. This selection means that, based on the designation information of the number of first circuit elements, the distance from the circuit element at the start point and the distance from the circuit element at the end point among the plurality of first circuit elements included in the path The first selection for selecting a specified number of first circuit elements in descending order of the total value of the first and the second circuit elements are electrically connected to the specified number of first circuit elements and are not included in the path. A second selection for selecting a second circuit element; a third selection for selecting a second wiring that electrically connects a specified number of first circuit elements and the second circuit element; including.

1 is a block diagram showing an example of a circuit design device according to a first embodiment. 5 is a flowchart illustrating an example of circuit design and timing analysis by the circuit design device according to the first embodiment. 6 is a flowchart showing an example of selection and display by the circuit design device according to the first embodiment. The figure which shows the example of a display of a timing path. The figure which shows the 1st example of a display of the timing path which concerns on this embodiment. The figure which shows the 2nd example of a display of the timing path which concerns on this embodiment. The figure which shows the 3rd example of a display of the timing path which concerns on this embodiment. The figure which shows the 4th example of a display of the timing path which concerns on this embodiment. The figure which shows the 5th example of a display of the timing path which concerns on this embodiment. The figure which shows the 6th example of a display of the timing path which concerns on this embodiment. The figure which shows the 7th example of a display of the timing path which concerns on this embodiment. The block diagram which shows the specific example of the circuit provided with the timing path containing a detour part. FIG. 9 is a diagram illustrating an example of a timing path according to a second embodiment.

  Hereinafter, embodiments of the invention will be described with reference to the drawings. In the following description, substantially the same or substantially the same components and functions are denoted by the same reference numerals, and will be described as necessary.

[First Embodiment]
In the present embodiment, the start point circuit element, the first circuit element, the end point circuit element, and the start point circuit element to the end point circuit element via the first circuit element are electrically connected. Electrically between the path to be analyzed including the first wiring, the second circuit element that is not included in the path but affects the shape of the path, and the first circuit element and the second circuit element A circuit design apparatus for selecting a second wiring to be connected will be described. Circuit elements are sometimes called cells.

  In the present embodiment, the analysis target path includes, for example, a timing path. The timing path is, for example, a path through which a clock signal is transmitted from the starting circuit element to the ending circuit element, and is an object to be analyzed whether or not the timing constraint is satisfied.

  FIG. 1 is a block diagram illustrating an example of a circuit design apparatus according to the present embodiment.

  The circuit design device 1 includes a storage device 2, an input device 3, a display device 4, and a processor 5. As the circuit design device 1, for example, an information processing device (computer) is used.

  The circuit design device 1 can display a timing path including circuit elements and wiring. When executing the timing analysis, the circuit design device 1 generates timing analysis data 8 including, for example, a delay with respect to the timing path from the starting circuit element to the ending circuit element. The user checks the timing path and delay displayed on the display device 4 to optimize the delay of the electronic circuit. The delay represents a delay of the clock signal in the timing path.

  The storage device 2 stores, for example, a circuit design program 6, circuit design data 7, and timing analysis data 8.

  As the input device 3, for example, a pointing device or a keyboard is used. For example, a mouse, a touch panel, a touch pad, or the like is used as the pointing device.

  The display device 4 is an example of an output device. Instead of the display device 4, for example, a printing device, a communication device, a storage device for storing display data, or the like may be used.

  The processor 5 functions as a reception unit 9, a CAD unit 10, a timing analysis unit 11, a reception unit 12, a selection unit 13, and a generation unit 14 by executing the circuit design program 6 stored in the storage device 2.

  The user refers to the screen of the display device 4, operates the input device 3, and gives various instructions to the processor 5.

  The accepting unit 9 accepts an instruction. In the present embodiment, the command accepted by the accepting unit 9 may be, for example, a user command from the input device 3, for example, a command generated by processing by the processor 5.

  The CAD unit 10 generates circuit design data 7 based on the instruction received by the receiving unit 9 and stores the circuit design data 7 in the storage device 2.

  For example, the circuit design data 7 includes circuit element identification data, circuit element type data, circuit element position data, circuit element fan-out, circuit element fan-in, wiring identification data, wiring position data, and net information. Etc.

  As the identification data of the circuit element, for example, a module name, an instance name, or a unique identification number is used. The instance name is information for identifying a circuit element, and for example, the circuit element is specified by hierarchical notation.

  For example, the circuit element type data indicates types of flip-flop circuits, combinational circuits, AND circuits, OR circuits, resistance elements, capacitors, inductors, relay circuits, and the like.

  The position data of the circuit element includes coordinates where the circuit element is arranged.

  The fan-out indicates how many gates the outputs of the gates (AND, OR, NOT) which are basic elements of the logic circuit are connected. In other words, fanout indicates the number of devices that can be input to a circuit element connected to one output pin.

  The wiring position data includes the coordinates of the start point and end point of the wiring.

  The timing analysis unit 11 performs timing analysis based on the circuit design data 7 stored in the storage device 2 and the designation information of the start and end circuit elements, and generates timing analysis data 8. Then, the timing analysis unit 11 stores the timing analysis data 8 in the storage device 2.

  The designation information of the start and end circuit elements may be, for example, designation information based on a user command received from the input device 3 via the receiving unit 9. Further, the designation information of the circuit elements at the start point and the end point may be, for example, designation information based on an instruction generated by processing by the processor 5.

  The timing analysis data 8 includes, for example, identification data of the timing path from the start circuit element to the end circuit element, and the circuit element and wiring identification data included in the timing path. The timing analysis data 8 further includes slack and delay from the starting circuit element to various circuit elements, and slack and delay from the various circuit elements to the terminal circuit element. Slack is the difference between the actual clock signal transmission time from the start circuit element to the end circuit element and the clock signal transmission time to be satisfied by the timing constraint. If the slack is a positive value, the timing path satisfies the timing constraint. If the slack is negative, the timing path does not satisfy the timing constraint.

  In the present embodiment, part or all of the circuit design data 7 may be included in the timing analysis data 8. On the contrary, part or all of the timing analysis data 8 may be included in the circuit design data 7. The circuit design data 7 and the timing analysis data 8 may be managed as one data. In other words, the circuit design data 7 and the timing analysis data 8 can be freely separated or combined.

  The accepting unit 12 accepts the circuit design data 7 and the timing analysis data 8 stored in the storage device 2 in accordance with the command accepted by the accepting unit 9. The receiving unit 12 may receive the generated circuit design data 7 and the timing analysis data 8 each time the circuit design data 7 and the timing analysis data 8 are generated. The circuit design data 7 and the timing analysis data 8 are received by the receiving unit 12, so that the circuit design data 7 and the timing analysis data 8 can be used by the processor 5.

  The selection unit 13 selects a display target based on the read circuit design data 7 and timing analysis data 8 and the instruction received by the reception unit 9.

  The generation unit 14 includes circuit elements and wirings included in the timing path and circuit elements and wirings that are not included in the timing path but affect the shape of the timing path based on the display target selected by the selection unit 13. Display data D including the above is generated, and the display data D is sent to the display device 4.

  The display unit 4 displays the display data D generated by the generation unit 14.

  The selection of the display target by the selection unit 13 and the specific example of the display data D generated by the generation unit 14 will be described with reference to FIGS. 4 to 11.

  FIG. 2 is a flowchart showing an example of circuit design and timing analysis by the circuit design device 1 according to the present embodiment.

  In step S201, the reception unit 9 receives a circuit design command.

  In step S202, the CAD unit 10 generates circuit design data 7 based on the circuit design command.

  In step S <b> 203, the CAD unit 10 stores the circuit design data 7 in the storage device 2.

  In step S204, the reception unit 9 receives a timing analysis command. The timing analysis instruction includes, for example, designation information of circuit elements at the start point and the end point.

  In step S205, the timing analysis unit 11 generates the timing analysis data 8 based on the designation information of the start and end circuit elements.

  In step S <b> 206, the timing analysis unit 11 stores the timing analysis data 8 in the storage device 2.

  FIG. 3 is a flowchart showing an example of selection and display by the circuit design device 1 according to the present embodiment.

  In step S301, the reception unit 9 receives a timing analysis result display command. The display instruction of the timing analysis result includes, for example, designation information for selecting a display target.

  In step S <b> 302, the receiving unit 12 receives the circuit design data 7 and the timing analysis data 8 from the storage device 2 based on the timing analysis result display command.

  In step S303, the selection unit 13 selects a circuit element and a wiring to be displayed based on the circuit design data 7 and the timing analysis data 8, and a timing analysis result display command.

  In step S <b> 304, the generation unit 14 generates display data D including the display target circuit element and wiring selected by the selection unit 13, and sends the display data D to the display device 4. The display device 4 displays the display data D.

  In step S305, the accepting unit 9 accepts a new timing analysis result display command or an end command indicating that the timing analysis result is displayed under a new condition.

  In step S306, when the reception unit 9 receives a display instruction for a new timing analysis result, the process proceeds to step S303, and when the reception unit 9 receives an end command, the process ends.

  Below, the selection of the display target by the selection part 13 and the specific example of the display data D produced | generated by the production | generation part 14 are demonstrated. Note that the following display examples can be freely combined or modified.

  FIG. 4 is a diagram illustrating a display example of a timing path.

  The timing path TP1 includes a start-point circuit element e1, circuit elements e2 to e4, and an end-point circuit element e5.

  Further, the timing path TP1 electrically connects the wiring p1 that electrically connects the circuit element e1 and the circuit element e2 at the starting point, the wiring p2 that electrically connects the circuit elements e2 and e3, and the circuit elements e3 and e4. Wiring p3 to be connected, and wiring p4 to electrically connect circuit elements e4 and e5.

  This timing path TP1 is a detour path in which the path between the circuit element e1 at the start point and the circuit element e5 at the end point is bent. The circuitous path includes, for example, a U-shaped portion. Since the timing path TP1 is a detour path, it is longer than the linear timing path. Further, the total length of the wirings p1 to p4 included in the timing path TP1 is longer than the total length of the wirings included in the linear timing path. When only the timing path TP1 is displayed, it is difficult for the user to understand the cause of the timing path TP1 being a detour path.

  FIG. 5 is a diagram illustrating a first display example of the timing path according to the present embodiment.

  Based on the circuit design data 7 and the timing analysis data 8, the selection unit 13 selects the timing path TP1 from the start circuit element e1 to the end circuit element e5 and the circuit elements e2 to e4 included in the timing path TP1. The circuit element e6 that is electrically connected to any one of the circuit elements e4 and is not included in the timing path TP1, and the wiring p5 that electrically connects the circuit element e4 and the circuit element e6 are selected as display targets. To do.

  For example, based on the display command received by the receiving unit 9, the selection unit 13 determines, for each circuit element e2 to e4 included in the timing path TP1, the distance a from the start circuit element e1 and the end circuit element e5. The total value with the distance b is calculated. The selection unit 13 may select the circuit element e4 having the largest calculated total value, and may select the circuit element e6 electrically connected to the circuit element e4 as a display target.

  For example, the selection unit 13 selects the circuit element e6 and the wiring p5 as display targets when the circuit element e6 that is electrically connected to the circuit element e4 and is not included in the timing path TP1 is a flip-flop circuit or a combinational circuit. You may do that.

  The generation unit 14 generates display data D including the display target circuit element e6 and the display target wiring p5 in addition to the timing path TP1, and sends the display data D to the display device 4.

  For example, the generation unit 14 generates display data D including the circuit element e6 and the wiring p5 based on a display command indicating that the cause of the timing path TP1 becoming a detour path is generated, and based on the non-display command. Thus, display data not including the circuit element e6 and the wiring p5 is generated.

  FIG. 6 is a diagram illustrating a second display example of the timing path according to the present embodiment.

  The selection unit 13 is electrically connected to the circuit element e4 included in the timing path TP1 based on the display command received by the reception unit 9, and is not included in the timing path TP1, but is a flip-flop circuit or a combinational circuit. A certain circuit element e6 is selected. The selection unit 13 selects a circuit element e7 that is electrically connected between the circuit element e4 and the circuit element e6 and is not a flip-flop circuit or a combinational circuit. Then, the selection unit 13 selects the wiring p51 between the circuit element e4 and the circuit element e7 and the wiring p52 between the circuit element e6 and the circuit element e7.

  The generation unit 14 generates display data D including display target circuit elements e6 and e7 and display target wirings p51 and p52 in addition to the timing path TP1, and sends the display data D to the display device 4.

  FIG. 7 is a diagram illustrating a third display example of the timing path according to the present embodiment.

  The receiving unit 9 receives display commands for connection relations for all the circuit elements e2 to e4 that are included in the timing path TP1 and are electrically connected between the circuit element e1 at the start point and the circuit element e5 at the end point. .

  Then, the selection unit 13 is electrically connected to the circuit elements e2 to e4 included in the timing path TP1, and the circuit elements e6, e8, e9 that are not included in the timing path TP1, and the circuit elements e6, e8, e9, The wirings p5, p6, and p7 that electrically connect the circuit elements e4, e3, and e2 are selected.

  The generation unit 14 generates display data D including circuit elements e6, e8, e9 and wirings p5, p6, p7 in addition to the timing path TP1, and sends the display data D to the display device 4.

  FIG. 8 is a diagram illustrating a fourth display example of the timing path according to the present embodiment.

  The accepting unit 9 accepts from the input device 3 an instruction including designation information on the number of circuit elements e2 to e4 included in the timing path TP1 (assuming that 2 is designated as the number in FIG. 8).

  Then, the selection unit 13 calculates the total value of the distance a from the start circuit element e1 and the distance b from the end circuit element e5 for each of the plurality of circuit elements e2 to e4 included in the timing path TP1.

  Next, the selection unit 13 selects the circuit elements e4 and e3 of the specified number of timing paths TP1 in descending order of the calculated total value.

  The selection unit 13 is electrically connected to the designated number of circuit elements e4 and e3 and is not included in the timing path TP1, and the circuit elements e6 and e8 and the circuit elements e4 and e4. The wirings p5 and p6 that electrically connect e3 are selected.

  The generation unit 14 generates display data D including circuit elements e6 and e8 and wirings p5 and p6 in addition to the timing path TP1, and sends the display data D to the display device 4.

  Thereby, the connection relationship between the circuit element e4 farthest from the circuit element e1 at the start point and the circuit element e5 at the end point in the timing path TP1 and the circuit element e6 not included in the timing path TP1 is the second farthest. The user can investigate and understand the connection relationship between the circuit element e3 far away from the circuit element e3 and the circuit element e8 not included in the timing path TP1.

  FIG. 9 is a diagram illustrating a fifth display example of the timing path according to the present embodiment.

  Based on the display command received by the receiving unit 9, the selection unit 13 includes a delay 15 and a slack 16 from the circuit element e1 at the start point to the circuit element e6, a delay 17 from the circuit element e6 to the circuit element e5 at the end point, and The slack 18 is further selected as a display target.

  The generation unit 14 generates display data D in which the selected delays 15 and 17 and slacks 16 and 18 are associated with the circuit element e6, and sends the display data D to the display device 4. For example, the generation unit 14 may generate the display data D by switching the color, thickness, and line type of the wiring p5 according to the values of the slacks 16 and 18.

  FIG. 10 is a diagram illustrating a sixth display example of the timing path according to the present embodiment.

  The accepting unit 9 accepts a command including stage number designation information for displaying circuit elements not included in the timing path TP1 (assuming that the stage number 2 is designated in FIG. 10). Here, the number of stages is the number of circuit elements connected in series.

  The selection unit 13 is electrically connected to the circuit element e4 included in the timing path TP1 based on the stage number designation information, and the circuit elements e6 corresponding to the designated number of stages not included in the timing path TP1. And the circuit element e10 (third circuit element) are selected.

  The selection unit 13 selects the wiring (third wiring) p8 that electrically connects the circuit elements e6 and e10.

  The display unit 14 generates display data D including circuit elements e6 and e10 and wirings p5 and p8 in addition to the timing path TP1, and sends the display data D to the display device 4.

  If there is no stage number designation information, the selection unit 13 may select the display target with the stage number as 1, for example, as shown in FIGS.

  FIG. 11 is a diagram illustrating a seventh display example of the timing path according to the present embodiment.

  Based on the display command received by the receiving unit 9, the selection unit 13 selects a circuit element (referred to as circuit element e4 in FIG. 11) specified by the display command among the circuit elements e1 to e6 selected as the display target. The fan-out 19 and the instance name 20 are further selected.

  The generation unit 14 generates display data D in which the designated circuit element e4 is associated with the fan-out 19 and the instance name 20, and sends the display data D to the display device 4. The display device 4 displays the specified circuit element e4, the fan-out 19 and the instance name 20 in association with each other.

  In the present embodiment described above, the timing path TP1 including the detour portion is electrically connected to any one of the circuit elements e2 to e4 included in the timing path TP1, and is not included in the timing path TP1. The circuit elements e6 to e10 can be displayed.

  In the present embodiment, flip-flop circuits or combinational circuits that are not included in the timing path TP1 can be selected and displayed.

  In the present embodiment, a circuit that is electrically connected to the circuit element e4 included in the timing path TP1 and is not included in the timing path TP1 and is a flip-flop circuit or a combinational circuit in accordance with the display command. The element e6 and the circuit element e7 which is not a flip-flop circuit or a combinational circuit electrically connected between the circuit elements e4 and e6 can be displayed.

  The user can easily investigate and understand the cause of the timing path TP1 being a detour path by referring to the display as described above.

  In the present embodiment, display or non-display of the circuit elements e6 to e10 not included in the timing path TP1 can be switched according to a display command or a non-display command.

  As a result, it is possible to prevent the user from understanding the cause of the timing path TP1 becoming a detour path due to too many circuit elements e6 to e10 being displayed.

  In the present embodiment, a specified number (one or a plurality, here two) of circuit elements e4 and e3 included in the timing path TP1 and separated from the start and end circuit elements e1 and e5 are included. The circuit elements e6 and e8 that are selected and are electrically connected to the selected circuit elements e4 and e3 and are not included in the timing path TP1 can be displayed.

  Accordingly, the user can limit the number of circuit elements e6 and e8 to be displayed outside the timing path TP1 according to the order of the distance from the circuit elements e1 and e5 at the start point and the end point. The user can investigate the cause of the timing path TP1 becoming a detour path by referring to the appropriate number of circuit elements e6 and e8 outside the timing path TP1.

  In the present embodiment, the delay 15 and the slack 16 from the starting circuit element e1 to the circuit element e6 not included in the timing path TP1, and the delay 17 and the slack 18 from the circuit element e6 to the ending circuit element e5 are displayed. can do. In the present embodiment, the color, thickness, and line type of the wiring p5 can be switched according to the values of the slacks 16 and 18.

  As a result, the user can investigate the cause of the slack timing path TP1 becoming a detour path while referring to the delays 15 and 17 and the slacks 16 and 18.

  In the present embodiment, according to the stage number designation information, circuit elements e6 for the designated number of stages that are electrically connected to the circuit element e4 included in the timing path TP1 and are not included in the timing path TP1. e10 can be displayed.

  As a result, the user can check not only the first-stage circuit element e6 but also the second-stage circuit element e10 ahead.

  In the present embodiment, the fan-out 19 and instance name 20 of the designated circuit element e4 can be displayed.

  Thereby, the user can freely confirm the fan-out 19 and the instance name 20 of the displayed circuit element e4.

  In the present embodiment, the user inputs a display command along the menu screen. The circuit design device 1 can freely switch or combine the above display states according to a user display command.

  FIG. 12 is a block diagram illustrating a specific example of a circuit including a timing path including a detour portion.

  The circuit 21 is formed on a rectangular substrate 22. The circuit 21 includes a data bus 23, registers 251, 255, 261, 265, and combinational circuits 252-254, 262-264, 24A, 24B.

  The data bus 23 is disposed at the center of the plane of the substrate 22. The combinational circuits 24 </ b> A and 24 </ b> B are disposed on both short sides of the plane of the substrate 22.

  The register 251, the combinational circuits 252 to 254, and the register 255 are connected in an arcuate shape. The registers 251 and 255 are electrically connected to the data bus 23. The combinational circuit 253 is electrically connected to the combinational circuit 24A.

  The register 261, the combinational circuits 262 to 264, and the register 265 are connected in an arcuate shape. The registers 261 and 265 are electrically connected to the data bus 23. The combinational circuit 263 is electrically connected to the combinational circuit 24B.

  Here, it is assumed that the user inputs an instruction that designates the register 251 as the circuit element of the start point and designates the register 255 as the circuit element of the end point by the input device 3.

  Then, the circuit design device 1 is electrically connected to the timing path TP2 including the registers 251 to 255 and the register 253 included in the timing path TP2 and farthest from the start and end registers 251 and 255. The combinational circuit 24A is displayed.

  Thereby, the user can easily understand that the timing path TP2 is a detour path due to the position of the combinational circuit 24A.

  As described above, the circuit design device 1 according to the present embodiment can effectively support the layout design work of the electronic circuit by the user even when there are many circuit elements of the designed circuit. The work time of the user can be shortened.

  In the present embodiment, the combinational circuits 252 to 254 and 262 to 264 may be buffer circuits.

  In the present embodiment, the fan-in may be displayed together with the fan-out or instead of the fan-out.

[Second Embodiment]
In the present embodiment, a modified example of the first embodiment will be described. The present embodiment is different from the first embodiment in the method of calculating the distance between the circuit elements included in the timing path and the circuit elements at the start and end points.

  FIG. 13 is a diagram illustrating an example of a timing path according to the present embodiment.

  The timing path TP3 includes a start-point circuit element e21, circuit elements e22 to e27, and an end-point circuit element e28. The timing path TP3 also electrically connects the wiring p21 that electrically connects the circuit element e21 and the circuit element e22 at the starting point, the wiring p22 that electrically connects the circuit elements e22 and e23, and the circuit elements e23 and e24. Wiring p23 to be connected, wiring p24 to electrically connect circuit elements e24 and e25, wiring p25 to be electrically connected to circuit elements e25 and e26, wiring p26 to be electrically connected to circuit elements e26 and e27, and circuit element e27 A wiring p27 that electrically connects the terminal circuit element e28 is included.

  In the present embodiment, the selection unit 13 selects, for each circuit element e22 to e27 in the timing path TP3, a circuit element that passes from the starting circuit element e21 to the circuit elements e22 to e27 along the timing path TP3. The sum of the distances between them (first sum) is calculated.

  In addition, the selection unit 13 adds, for each circuit element e22 to e27, the total distance between the circuit elements that pass from each circuit element e22 to e27 until reaching the terminal circuit element e28 along the timing path TP3 (first order). 2) is calculated.

  The selector 13 calculates the absolute value of the difference between the first sum and the second sum for each of the circuit elements e22 to e27.

  Then, the selection unit 13 selects the circuit element having the smallest absolute value of the difference between the first sum and the second sum as the circuit element farthest from the start point and end point circuit elements e21 and e28, and to the timing path TP3. Select a circuit element to display a connection relationship with a circuit element that is not included.

  For example, the first sum of the circuit element e24 is the sum of the distance between the circuit element e21 and the circuit element e22 at the starting point, the distance between the circuit elements e22 and e23, and the distance between the circuit elements e23 and e24. .

  For example, the second sum of the circuit elements e24 is the distance between the circuit elements e24 and e25, the distance between the circuit elements e25 and e26, the distance between the circuit elements e26 and e27, and the distance between the circuit elements e27 and e28. The total distance.

  Similarly, for each of the other circuit elements e22, e23, e25 to e27, the absolute value of the difference between the first and second sums and the first sum and the second sum is calculated.

  The selection unit 13 selects the circuit element having the closest first sum and the second sum as the circuit element farthest from the start and end circuit elements e21 and e28. Then, the selection unit 13 selects a circuit element that is electrically connected to the circuit element farthest from the circuit elements e21 and e28 at the start point and the end point and is not included in the timing path TP3 as a display target.

  In the present embodiment described above, a circuit element that causes the timing path TP3 to be a detour path can be displayed based on a reference different from that of the first embodiment. As a result, the user can investigate and understand the cause of the timing path TP3 becoming a detour path.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Circuit design apparatus, 2 ... Memory | storage device, 3 ... Input device, 4 ... Display apparatus, 5 ... Processor, 6 ... Circuit design program, 7 ... Circuit design data, 8 ... Timing analysis data, 9, 12 ... Reception part, DESCRIPTION OF SYMBOLS 10 ... CAD part, 11 ... Timing analysis part, 13 ... Selection part, 14 ... Generation part, D ... Display data, TP1-TP3 ... Timing path, e1, e21 ... Starting circuit element, e2-e4, e6-e10, e22 to e27 ... circuit elements, e5, e28 ... end point circuit elements, p1 to p8, p51, p52, p21 to p27 ... wiring, 15, 17 ... delay, 16, 18 ... slack, 19 ... fanout, 20 ... instance Name, 21 ... Circuit, 22 ... Board, 23 ... Data bus, 24A, 24B, 252 to 254, 262 to 264 ... Combinational circuit, 251, 255, 261, 265 ... Register.

Claims (19)

Based on the circuit design data by the computer and the analysis data generated based on the circuit design data, the first circuit element, the first circuit element, the end circuit element, and the start circuit element A path to be analyzed including a first wiring that electrically connects the first circuit element to the terminal circuit element, and is electrically connected to the first circuit element included in the path Selecting a second circuit element that is not included in the path, and a second wiring that electrically connects the first circuit element and the second circuit element,
The selection is
Based on the designation information of the number of the first circuit elements, the distance from the circuit element at the start point and the distance from the circuit element at the end point among the plurality of first circuit elements included in the path, A first selection for selecting the number of the first circuit elements in descending order of the total value of
A second selection for selecting the second circuit element that is electrically connected to the number of the first circuit elements and not included in the path;
A third selection for selecting the second wiring for electrically connecting the number of the first circuit elements and the second circuit elements;
A circuit design method comprising: The circuit design data further includes type data,
The selecting selects, as the second circuit element, a flip-flop circuit or a combinational circuit that is electrically connected to the first circuit element and is not included in the path based on the type data. ,
The circuit design method according to claim 1. The selecting includes a first sum having a largest sum of a distance from the circuit element at the start point and a distance from the circuit element at the end point among the plurality of first circuit elements included in the path. A circuit element is selected, the second circuit element electrically connected to the first circuit element having the largest total value is selected, and the first circuit element having the largest total value and the second circuit element are selected. Selecting the second wiring to electrically connect the circuit elements of
The circuit design method according to claim 1 or 2. The selection is
For each of the plurality of first circuit elements, a first sum that is a sum of distances between circuit elements that pass from the starting circuit element to reach each of the first circuit elements along the path. To calculate
For each of the plurality of first circuit elements, a second sum that is the sum of the distances between the circuit elements that pass from each circuit element to reach the terminal circuit element along the path is calculated. ,
Calculating the absolute value of the difference between the first sum and the second sum for each of the plurality of first circuit elements;
Selecting a circuit element having the smallest absolute value of the difference as a circuit element farthest from the circuit element at the start point and the circuit element at the end point;
The circuit design method according to claim 1 or 2. Generating display data including the path and the selected second circuit element and the second wiring;
The circuit design method according to claim 1. The generating generates the display data including the second circuit element and the second wiring based on a display command of the second circuit element, and hides the second circuit element Generating display data not including the second circuit element and the second wiring based on the command;
The circuit design method according to claim 5. The selecting further comprises selecting at least one of a fanout and an instance name for at least one of the first circuit element and the second circuit element;
The generating generates the display data further including at least one of the fan-out and the instance name.
7. The circuit design method according to claim 5 or 6. The selecting further comprises selecting at least one of slack and delay corresponding to the second circuit element;
The generating generates the display data further including at least one of the slack and the delay;
The circuit design method according to claim 5. The selecting includes electrically connecting a third circuit element that is electrically connected to the second circuit element and is not included in the path, and the second circuit element and the third circuit element. And further selecting a third wiring connected to
The generating generates the display data further including the selected third circuit element and the third wiring;
The circuit design method according to claim 5. The circuit design data includes circuit element identification data and position data,
The analysis data is data generated based on the circuit design data, the designation information of the circuit element at the start point, and the designation information of the circuit element at the end point.
The circuit design method according to claim 1. On the computer,
Based on the circuit design data and the analysis data generated based on the circuit design data, the first circuit from the start circuit element, the first circuit element, the end circuit element, and the start circuit element A path to be analyzed including a first wiring that electrically connects the circuit element to the terminal circuit element via the element, and is electrically connected to the first circuit element included in the path. Realizing a selection function of selecting a second circuit element not included in the path, and a second wiring that electrically connects the first circuit element and the second circuit element;
The selection function is:
Based on the designation information of the number of the first circuit elements, the distance from the circuit element at the start point and the distance from the circuit element at the end point among the plurality of first circuit elements included in the path, A first selection function for selecting the number of the first circuit elements in descending order of the total value of
A second selection function for selecting the second circuit element that is electrically connected to the number of the first circuit elements and is not included in the path;
A third selection function for selecting the second wiring that electrically connects the number of the first circuit elements and the second circuit elements;
Comprising
The circuit design data further includes type data,
The selection function selects, as the second circuit element, a flip-flop circuit or a combinational circuit that is electrically connected to the first circuit element and is not included in the path, based on the type data.
program. The selection function includes a first circuit having a largest total value of a distance from the circuit element at the start point and a distance from the circuit element at the end point among the plurality of first circuit elements included in the path. And selecting the second circuit element that is electrically connected to the first circuit element having the largest total value, and selecting the second circuit element having the largest total value and the second circuit element. Selecting the second wiring for electrically connecting the circuit elements;
The program according to claim 11. The selection function is:
For each of the plurality of first circuit elements, a first sum that is a sum of distances between circuit elements that pass from the starting circuit element to reach each of the first circuit elements along the path. To calculate
For each of the plurality of first circuit elements, a second sum that is the sum of the distances between the circuit elements that pass from each circuit element to reach the terminal circuit element along the path is calculated. ,
Calculating the absolute value of the difference between the first sum and the second sum for each of the plurality of first circuit elements;
Selecting a circuit element having the smallest absolute value of the difference as a circuit element farthest from the circuit element at the start point and the circuit element at the end point;
The program according to claim 11. In the computer,
The program according to any one of claims 11 to 13, further realizing a generation function of generating display data including the path, the selected second circuit element, and the second wiring. The generation function generates the display data including the second circuit element and the second wiring based on a display instruction for the second circuit element, and a non-display instruction for the second circuit element. Generating display data not including the second circuit element and the second wiring,
The program according to claim 14. The selection function further selects at least one of a fanout and an instance name for at least one of the first circuit element and the second circuit element,
The generation function generates the display data further including at least one of the fan-out and the instance name.
The program according to claim 14 or 15. The selection function further selects at least one of slack and delay corresponding to the second circuit element,
The generation function generates the display data further including at least one of the slack and the delay.
The program according to any one of claims 14 to 16. The selection function electrically connects the third circuit element that is electrically connected to the second circuit element and is not included in the path, and the second circuit element and the third circuit element. Further select the third wiring to be connected,
The generation function generates the display data further including the selected third circuit element and the third wiring;
The program according to any one of claims 14 to 16. The circuit design data includes circuit element identification data and position data,
The analysis data is data generated based on the circuit design data, the designation information of the circuit element at the start point, and the designation information of the circuit element at the end point.
The program according to any one of claims 11 to 18.

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