JP2019008845A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing power consumption.SOLUTION: A semiconductor device comprises: N pieces of subblocks; a setting register 16 for designating the number of presearch entry data in first to N-th entry data divided in accordance with the subblocks; and a search data change section 18 for changing a data array order of search data inputted on the basis of a value of the setting register. The presearch subblock in N pieces of the subblocks retrieves data matched with presearch data following the data array order changed by the search data change section, outputs a retrieval result of matching or non-matching for respective rows, retrieves data matched with post search data in search data among entry data stored for respective rows of the memory cell array on the basis of the retrieval result of the presearch subblock, and outputs the retrieval result of matching or non-matching for the respective rows.SELECTED DRAWING: Figure 9

Description

  The present disclosure relates to a semiconductor device, for example, an associative memory.

  A storage device called associative memory or CAM (Content Addressable Memory) searches a stored data word that matches a search word and finds a matching data word Outputs the address.

  CAM includes BCAM (Binary CAM) and TCAM (Ternary CAM). Each memory cell of the BCAM stores either “0” or “1” information. On the other hand, in the case of TCAM, each memory cell stores “Don't Care” (in this example, the symbol “*”) in addition to “0” and “1”. Is possible. “*” Indicates that either “0” or “1” may be used.

  TCAM devices are widely used for address search and access control in routers for networks such as the Internet. In order to cope with an increase in capacity, a TCAM device usually has a plurality of arrays, and a search operation is simultaneously performed on each array.

  The TCAM device can compare the input search data (input packet) and the TCAM cell data all at once, and is therefore faster than a RAM (Random Access Memory) in all search applications. However, since a search current is generated during a search, an increase in power consumption is a problem.

  In this regard, when the initial segment search (presearch) is inconsistent (MISS) by time-division search, it is possible to reduce the power consumption of the search by not performing the subsequent segment search (post search). It is possible (Patent Document 1).

Japanese Patent Laid-Open No. 62-293596

  However, it is desirable from the viewpoint of power consumption that the time-division search is inconsistent in pre-search as much as possible. For example, when time-division search is executed for fields constituting a table such as an ACL (Access Control List). Are less likely to become inconsistent, and even in the same table, the power saving effect by time division search varies depending on how to write to the TCAM device.

  The present disclosure has been made to solve the above-described problem, and an object thereof is to provide a semiconductor device capable of reducing power consumption.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes N sub-blocks each including a memory cell array, and pre-search out of 1 to N-th entry data divided corresponding to the N sub-blocks. A setting register for designating the entry data number, and a search data changing unit for changing the data arrangement order of the search data input based on the value of the setting register. Of the N sub-blocks, the pre-search sub-block is pre-search data in accordance with the data arrangement order changed by the search data changing unit among the entry data stored for each row of the memory cell array in accordance with the search instruction. Are searched for, and a search result of match or mismatch is output for each row. The post-search sub-block of the N sub-blocks is based on the search result of the pre-search sub-block, Of the entry data stored for each row of the memory cell array, the search data that matches the post search data other than the presearch data is searched, and a search result that matches or does not match is output for each row.

  According to an embodiment, the semiconductor device of the present disclosure can achieve low power consumption.

It is a figure explaining the structure of the communication apparatus 1 based on Embodiment 1. FIG. It is a figure explaining the structure of the search memory 8 based on Embodiment 1. FIG. It is a figure explaining the structure of the TCAM apparatus 12 based on Embodiment 1. FIG. It is a circuit diagram which shows an example of a structure of a TCAM cell. FIG. 5 is a diagram showing a correspondence relationship between the contents stored in the X cell and the Y cell of FIG. It is a figure explaining the structure of the segment (subblock) 12A based on embodiment. 3 is a circuit diagram showing an example of a configuration of a search line driver 22. FIG. It is a circuit diagram which shows an example of a structure of a match amplifier. It is a figure explaining the search system of the search block 10 based on Embodiment 1. FIG. FIG. 4 is a diagram for explaining a search timing of a search block 10. 5 is a diagram for describing a maintenance operation of a search memory 8. FIG. It is a figure explaining the search method of the search block 10 # based on Embodiment 2. FIG. It is a circuit diagram which shows an example of a structure of the BCAM cell MC # of the BCAM apparatus 12P. It is a figure explaining the search system of 10 A of search blocks based on the modification of Embodiment 2. FIG. It is a figure explaining the search timing of 10 A of search blocks.

  Embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
<Overall configuration of communication device 1>
FIG. 1 is a diagram illustrating a configuration of a communication device 1 based on the first embodiment.

As shown in FIG. 1, the communication device 1 is a communication device such as a switch or a router.
The communication device 1 includes a CPU (Central Processing Unit) 2, a transfer control circuit 4, a general-purpose memory 6, and a search memory 8.

The CPU 2 controls the entire device.
The CPU 2 realizes various functions in cooperation with a program stored in the general-purpose memory 6. For example, the general-purpose memory 6 can be constituted by a DRAM (Dynamic Random Access Memory), and an operating system (OS) is constructed by cooperating with the CPU 2. The CPU 2 exchanges information with adjacent communication devices and maintains and manages information necessary for transfer processing.

  The transfer control circuit 4 executes communication packet transfer processing. The transfer control circuit 4 is provided with dedicated hardware such as an ASIC (Application Specific Integrated Circuit) circuit or an NPU (Network Processing Unit) specialized for transfer processing. The transfer control circuit 4 accesses the search memory 8 and acquires information necessary for transfer processing.

In this example, the search memory 8 will be described using a TCAM device.
<Configuration of Search Memory 8>
FIG. 2 is a diagram illustrating the configuration of the search memory 8 based on the first embodiment.

  As shown in FIG. 2, the search memory 8 includes a search key generation unit 29 that generates a search key from input data, a profile register 26, a plurality of search blocks 10, and a search result generation unit 28.

  The entire search memory 8 is managed in units of search blocks 10 having a certain granularity. In this example, a configuration in which a plurality of search blocks 10-1 to 10-n are provided is shown.

  Although details of the configuration of each search block 10 will be described later, based on the TCAM device 12 having a TCAM cell, the setting register 16 for designating the number of entry data for pre-search, and the value of the setting register 16 And a data changing unit 27 that changes the data arrangement order.

The profile register 26 holds various settings necessary for the search.
Based on the information in the profile register 26, the search key generation unit 29 generates a search key from the input data.

The search blocks 10-1 to 10-n are provided in parallel and have a parallel search function.
The search result generation unit 28 gives priority to the search results from the search blocks 10 and generates a final search result.

  When the search command is issued, the search key generation unit 29 generates a search key based on the received data and various information including the profile register 26.

  The search key generation unit 29 distributes the search key to each search block 10. In each search block 10, the data changing unit 27 changes the data arrangement order of the search keys based on the register value preset in the setting register 16 and outputs it. The search key thus changed becomes a unique value for each search block 10.

<Configuration of TCAM device 12>
FIG. 3 is a diagram illustrating the configuration of the TCAM device 12 based on the first embodiment.

As shown in FIG. 3, the TCAM device 12 has a time division search function.
The TCAM device 12 is divided into a plurality of segments (sub-blocks). In this example, the case where it is divided into four segments (sub-blocks) is shown.

As an example, the case where it is divided into segments 12A to 12D is shown.
The segments 12A to 12D are connected from the front stage to the rear stage.

  Each of the segments 12A to 12D has basically the same configuration, and is provided with a memory cell array and a match amplifier. However, the last segment 12D is provided with a memory cell array, a match amplifier, and a priority encoder. ing.

  A match amplifier exists at least for each segment, and amplifies and outputs a match / mismatch determination result of each match line.

  The priority encoder converts the input from the match amplifier into an address and generates a final output.

  The memory cell array is provided with a plurality of se (Search Enable) terminals, and the search range can be limited by precharging the match line only in the region where the se terminal is asserted.

  In this example, a flip-flop FF1 for holding a signal for activating the match amplifier is provided as an example. Specifically, when a search command is input to the flip-flop FF1, a signal for activating the match amplifier is held and output to the match amplifier of each segment.

  Further, flip-flops FF2 to FF4 are provided in the segments 12B to 12D, and the search key can be held until the search process in the previous segment is completed. In this example, the search key SB is input to the segment 12A, the search key SA is input to the segment 12B, and the search keys SC and SD are input to the segments 12C and 12D. Yes.

  By connecting the match amplifier output of the preceding segment to the se terminal of the succeeding segment, it is possible to search only the entries that match in the preceding segment.

  More specifically, only the first segment 12A is activated and the first search is executed. The second search is executed in the segment 12B only for the areas that are matched in the first search. Similarly, the third and fourth searches are executed. It is possible to suppress the power consumption of the subsequent segment by an amount corresponding to the area that does not match in the search for the previous segment.

<Structure of segment (sub block)>
[Configuration of TCAM cell]
FIG. 4 is a circuit diagram showing an example of the configuration of the TCAM cell.

  Referring to FIG. 4, a TCAM cell (also referred to as a memory cell MC) includes two SRAM cells (Static Random Access Memory Cells) 11 and 12 and a data comparison unit 13. The SRAM cell 11 is also referred to as an X cell, and the SRAM cell 14 is also referred to as a Y cell. The X cell 11 stores 1-bit data that is complementary to the internal storage node pair ND1, ND1_n (one is “1” and the other is “0”). The Y cell 14 stores 1-bit data complementary to each other in the internal storage node pair ND2, ND2_n. The TCAM cell is also referred to as an associative memory cell.

  The TCAM cell is connected to the bit line pair BL, BL_n, the search line pair SL, SL_n, the match line ML, and the word lines WLX, WLY. The bit line pair BL, BL_n extends in the column direction (Y direction) of the TCAM cell array 20 of FIG. 6 and is shared by a plurality of TCAM cells arranged in the column direction. The search line pair SL, SL_n extends in the column direction (Y direction) of the TCAM cell array 20 and is shared by a plurality of TCAM cells arranged in the column direction.

  The match line ML extends in the row direction (X direction) of the TCAM cell array 20 and is shared by a plurality of TCAM cells arranged in the row direction. The word lines WLX and WLY extend in the row direction (X direction) of the TCAM cell array 20 and are shared by a plurality of TCAM cells arranged in the row direction.

  X cell 11 includes inverters INV1 and INV2 and N-channel MOS (Metal Oxide Semiconductor) transistors Q1 and Q2. The inverter INV1 is connected between the storage node ND1 and the storage node ND1_n so that the direction from the storage node ND1_n to the storage node ND1 is the forward direction. Inverter INV2 is connected in parallel and in the opposite direction to INV1. MOS transistor Q1 is connected between storage node ND1 and bit line BL. The MOS transistor Q2 is connected between the storage node ND1_n and the bit line BL_n. MOS transistors Q1, Q2 have their gates connected to word line WLX.

  Y cell 14 includes inverters INV3 and INV4 and MOS (Metal Oxide Semiconductor) transistors Q3 and Q4. The inverter INV3 is connected between the storage node ND2 and the storage node ND2_n so that the direction from the storage node ND2_n to the storage node ND2 is the forward direction. The inverter INV4 is connected in parallel with INV3 in the reverse direction. MOS transistor Q3 is connected between storage node ND2 and bit line BL. The MOS transistor Q4 is connected between the storage node ND2_n and the bit line BL_n. MOS transistors Q3 and Q4 have their gates connected to word line WLY.

  Data comparison unit 13 includes N channel MOS transistors Q6 to Q9. MOS transistors Q6 and Q7 are connected in series between node ND3, which is a connection point with match line ML, and ground node GND. MOS transistors Q8 and Q9 are connected in series between node ND3 and ground node GND, and in parallel with the whole of MOS transistors Q6 and Q7 connected in series. MOS transistors Q6 and Q8 have their gates connected to storage nodes ND1 and ND2, respectively. MOS transistors Q7 and Q9 have their gates connected to search lines SL and SL_n, respectively.

  FIG. 5 is a table showing the correspondence between the stored contents of the X cell and Y cell of FIG. 4 and the TCAM data in a tabular format.

  Referring to FIGS. 4 and 5, the TCAM cell can store three values of “0”, “1”, “*” (don't care) using a 2-bit SRAM cell. it can. Specifically, when “1” is stored in the storage node ND1 of the X cell 11 and “0” is stored in the storage node ND2 of the Y cell 14, “0” is stored in the TCAM cell. To do. It is assumed that “1” is stored in the TCAM cell when “0” is stored in the storage node ND1 of the X cell 11 and “1” is stored in the storage node ND2 of the Y cell 14. It is assumed that “*” (don't care) is stored in the TCAM cell when “0” is stored in the storage node ND1 of the X cell 11 and “0” is stored in the storage node ND2 of the Y cell 14. . When “1” is stored in the storage node ND1 of the X cell 11 and “1” is stored in the storage node ND2 of the Y cell 14, it is not used.

  According to the above TCAM cell configuration, the search data is “1” (that is, the search line SL is “1” and the search line SL_n is “0”), and the TCAM data is “0” (storage node ND1). Is “1” and the storage node ND2 is “0”), the MOS transistors Q6 and Q7 are turned on, so that the potential of the precharged match line ML is pulled out to the ground potential. The search data is “0” (that is, the search line SL is “0” and the search line SL_n is “1”), the TCAM data is “1” (the storage node ND1 is “0”, and the storage node ND2 Is “1”), the MOS transistors Q8 and Q9 are turned on, so that the potential of the precharged match line ML is pulled out to the ground potential. That is, when the search data and the TCAM data do not match, the potential of the match line ML is pulled out to the ground potential.

  Conversely, when the input search data is “1” and the TCAM data is “1” or “*”, or the search data is “0” and the TCAM data is “0” or In the case of “*” (that is, when both match), the potential (power supply potential VDD level) of the precharged match line ML is maintained.

  As described above, in the TCAM, unless the data of all TCAM cells connected to the match line ML corresponding to one entry (row) match the input search data, the charge stored in the match line ML is extracted. . For this reason, although the search by TCAM is high speed, there exists a problem that current consumption is large.

  FIG. 6 is a diagram for explaining the configuration of the segment (sub-block) 12A based on the embodiment.

  As shown in FIG. 6, the segment 12A includes a TCAM cell array 20 (also simply referred to as a cell array), a write driver 21, a search line driver 22, a match amplifier unit 23, a control logic circuit 24, and a read circuit 25. Including.

  Although not shown, the segment 12A includes a word line driver (not shown) for driving the word lines WLX and WLY, and an input / output circuit (not shown) that receives input of a control signal, an address signal, and the like.

  The TCAM cell array 20 includes TCAM cells arranged in a matrix (m rows; k columns). In this example, the cell array 20 shows a case where the number of rows (number of entries) m is N and the number of columns (number of bits) k is 40.

  Corresponding to each column of the cell array 20, k (k = 40) bit line pairs (from BL [0], BL_n [0] to BL [k−1], BL_n [k−1]), k (K = 40) search line pairs (from SL [0], SL_n [0] to SL [k−1], SL_n [k−1]) are provided.

  Corresponding to each row of the cell array 20, m (m = N) match lines (from ML [0] to ML [N]) and m X-cell word lines (not shown) (WLX [0]) WLX [m−1]) and m Y cell word lines (from WLY [0] to WLY [m−1]) (not shown) are provided.

  The write driver 21 supplies write data to each TCAM cell via the bit line pair BL, BL_n at the time of writing. The search line driver 22 supplies search data to each TCAM cell via the search line pair SL, SL_n at the time of search.

  The control logic circuit 24 controls the operation of the entire segment 12A. For example, the control logic circuit 24 receives a search command at the time of search, and outputs a control signal to the search line driver 22 and the match amplifier unit 23, thereby causing the search line driver 22, the match amplifier unit 23, and the precharge circuit to Control the behavior. The control logic circuit 24 receives a read command at the time of reading and outputs a control signal for controlling the reading circuit 25. As a result, the entry data stored in the cell array 20 can be read and output.

  The match amplifier unit 23 includes a plurality of match amplifiers MA respectively corresponding to the rows of the cell array. The match amplifier MA detects whether or not the corresponding TCAM cell data matches the corresponding portion of the input search data based on the potential of the corresponding match line ML during the search. In this embodiment, the match amplifier MA includes a precharge circuit for precharging the corresponding match line ML at the time of search.

FIG. 7 is a circuit diagram showing an example of the configuration of the search line driver 22.
As shown in FIG. 7, when the search line enable signal sena is activated to “H” level, the search line driver 22 receives input search data sky [i] (i = 0, 1,..., K). Is output to the search line SL [i]. Further, a signal obtained by inverting the logic level of the input search data sky [i] is output to the complementary search line SL_n [i].

  In this example, a case where the search key SB is configured as input search data sky [i] (i = 0, 1,..., K) will be described as an example.

  Specifically, the search line driver 22 applies AND gates 60 [0] to 60 [k] and search lines SL_n [0] to SL_n [k] corresponding to the search lines SL [0] to SL [k], respectively. Each includes AND gates 61 [0] to 61 [k] and inverters 62 [0] to 62 [k], respectively.

  The search line enable signal sena is commonly input to the AND gates 60 [0] to 60 [k] and the AND gates 61 [0] to 61 [k]. Further, the corresponding input search data sky [i] is input to the AND gate 60 [i] (i = 0, 1,..., K).

  The output signal of the AND gate 60 [i] (i = 0, 1,..., K) is transmitted to the search line SL [i]. A signal obtained by inverting the corresponding input search data sky [i] is input to the AND gate 61 [i] (i = 0, 1,..., K).

  According to the above configuration, for example, when the search line enable signal sena is activated to the “H” level and the input search data sky [i] is at the “H” level (“1”), the search line The voltage of SL [i] becomes “H” level, and the voltage of the search line SL_n [i] becomes “L” level. When the search line enable signal sena is activated to “H” level and the input search data sky [i] is at “L” level (“0”), the voltage of the search line SL [i] is “ “L” level, and the voltage of the search line SL_n [i] becomes “H” level.

FIG. 8 is a circuit diagram showing an example of the configuration of the match amplifier.
Referring to FIG. 8, match amplifier MA includes a P-channel MOS transistor 70 as a precharge circuit and inverters 71-74.

  Although the MOS transistor 70 as the precharge circuit is illustrated as being inside the match amplifier MA, the MOS transistor 70 may be provided outside the match amplifier MA. The control logic circuit 24 outputs a match amplifier enable signal mae.

  Further, as described above, in this example, the se terminal is used as a precharge signal for precharging the match line. Here, a case where the input from the se terminal is inverted by an inverter and the inverted signal is input to the MOS transistor 70 as a precharge signal is shown.

  Therefore, as described with reference to FIG. 3, in the first stage segment, when the “H” level (“1”) is input to the se terminal as a search command, all match lines are precharged.

  On the other hand, in the second and subsequent segments, since the output from the match amplifier MA in the previous segment is connected to the se terminal, when the output from the previous match amplifier MA is “L” level, Match lines in the same row in the segments are not precharged. On the other hand, when the output from the preceding match amplifier MA is at “H” level, the match line in the same row in the next segment is precharged. Therefore, by connecting the match amplifier output of the preceding segment to the se terminal of the succeeding segment, it is possible to search only the entries that match in the preceding segment. It is possible to suppress the power consumption of the subsequent segment by the amount of the area that does not match in the search for the previous segment.

  Hereinafter, the connection of the above components will be described. MOS transistor 70 is connected between a corresponding match line ML and a power supply node supplying power supply potential VDD. A match line precharge signal that is an inverted signal of the se terminal is input to the gate of the MOS transistor 70. Match line ML is further connected to an input node of inverter 71. The output node of inverter 71 is connected to the input node of inverter 74. The output node of inverter 74 is connected to the input node of inverter 72 through inverter 72.

  The match amplifier enable signal mae and the signal obtained by inverting the logic level thereof by the inverter 73 are connected to the drive power supply nodes of the inverters 71 and 72. When match amplifier enable signal mae is in an inactive state (“L” level), inverter 71 is in an inoperative state and inverter 72 is in an operating state. When match amplifier enable signal mae is in an active state (“H” level), inverter 71 is in an operating state and inverter 72 is in a non-operating state.

  Next, the circuit operation of the match amplifier MA will be described. When the match line precharge signal is activated (becomes “L” level), MOS transistor 70 becomes conductive. As a result, the match line ML is charged (precharged) to the power supply potential VDD.

  After the match line precharge signal is deactivated, the search line enable signal sena is activated (becomes “H” level), whereby search data is input to the search line pair SL, SL_n. As a result, the potential of the match line ML changes depending on the search result (the comparison result between the corresponding portion of the input search data and the TCAM cell data). That is, in the case of a match (hit: hit), the potential of the match line ML is maintained at the power supply potential VDD (“H” level), and in the case of a mismatch (miss: miss), the charge of the match line ML is discharged to the ground node. As a result, the ML potential of the match line changes to the ground potential (“L” level).

  Next, the match amplifier enable signal is activated (becomes “H” level). As a result, the potential of match line ML based on the search result is output as match amplifier output signal mo via inverter 71 and inverter 74. When match amplifier enable signal mae is deactivated (becomes “L” level), the potential of match line ML based on the search result is held by the latch circuit formed of inverter 74 and inverter 72.

<Search Method of Search Block 10>
FIG. 9 is a diagram illustrating a search method of the search block 10 based on the first embodiment.

  As shown in FIG. 9, the search block 10 includes a setting register 16, a rearrangement control signal generation unit 15, rearrangement circuits 17 and 18, and a TCAM device 12.

  The rearrangement control signal generation unit 15 and the rearrangement circuits 17 and 18 constitute a data change unit 27.

The TCAM device 12 has a time division search function.
The rearrangement circuits 17 and 18 are crossbar switches.

  The rearrangement control signal generation unit 15 outputs a control signal for instructing rearrangement to the rearrangement circuits 17 and 18 based on the register value of the setting register 16.

  In this example, crossbar switches are used as the rearrangement circuits 17 and 18. However, any circuit may be used as long as it can rearrange an area effective for time division search at a specific location. For example, a configuration in which the upper and lower bits of data are exchanged, or a rotation circuit may be used.

  In this example, a TCAM device will be described as an example of the configuration of the search block 10. However, the present invention is not limited to this, and any data structure capable of time-division search can be used.

  The search block 10 has a data bus and a control system pin used for writing and searching as input pins. The search block 10 has a search result output pin and a read result output data bus as output pins.

  The rearrangement circuits 17 and 18 perform rearrangement on the signals of these input and output data buses. Specifically, the data arrangement order is changed.

  The rearrangement circuits 17 and 18 change the data arrangement order according to the control signal generated by the rearrangement control signal generation unit 15.

  In this example, the case where the TCAM device 12 divides into four segments (sub-blocks) as described above will be described. Of the four segments (sub-blocks), the first segment (sub-block) is a pre-search target, and the second to fourth segments (sub-blocks) are post-search targets.

  In this example, the setting register 16 specifies the number of entry data for pre-search among the first to fourth entry data divided corresponding to four segments (sub-blocks). As an example, 2-bit data is stored in the setting register 16.

  The rearrangement control signal generation unit 15 generates control signals S1 to S4 based on the data in the setting register 16.

  For example, when “00” is stored in the setting register 16, the rearrangement control signal generation unit 15 outputs the control signal S <b> 1 to the rearrangement circuits 17 and 18.

  When the control signal S1 is input, the rearrangement circuits 17 and 18 do not change the data arrangement order and output the data as it is.

  When “01” is stored in the setting register 16, the rearrangement control signal generation unit 15 outputs the control signal S <b> 2 to the rearrangement circuits 17 and 18.

  When the control signal S2 is input, the rearrangement circuits 17 and 18 change the data arrangement order and output it. Since the TCAM device 12 is divided into four segments (sub-blocks), the write data or search key is also divided into four fields in order to correspond to each segment. The rearrangement circuit 17 changes the data arrangement order to replace the second field and the first field of the write data or the search key according to the input of the control signal S2.

  The rearrangement circuit 18 changes the data arrangement order to switch the second field and the first field of the read data in accordance with the input of the control signal S2.

  When “10” is stored in the setting register 16, the rearrangement control signal generation unit 15 outputs the control signal S <b> 3 to the rearrangement circuits 17 and 18.

  When the control signal S3 is input, the rearrangement circuits 17 and 18 change the data arrangement order and output it. The write data or search key is divided into four fields. The rearrangement circuit 17 changes the data arrangement order to replace the third field and the first field of the write data or search key in accordance with the input of the control signal S3.

  The rearrangement circuit 18 changes the data arrangement order to switch the third field and the first field of the read data in accordance with the input of the control signal S3.

  When “11” is stored in the setting register 16, the rearrangement control signal generation unit 15 outputs the control signal S 4 to the rearrangement circuits 17 and 18.

  When the control signal S4 is input, the rearrangement circuits 17 and 18 change the data arrangement order and output it. The write data or search key is divided into four fields. The rearrangement circuit 17 changes the data arrangement order to replace the fourth field and the first field of the write data or the search key in accordance with the input of the control signal S4.

  The rearrangement circuit 18 changes the data arrangement order to switch the fourth field and the first field of the read data in accordance with the input of the control signal S4.

(About initialization (setting) of search memory 8)
The communication device 1 described with reference to FIG. 1 has a rule set necessary for performing transfer processing such as ACL and FIB (Forwarding Information Base).

  These may be set manually by the user or may be automatically generated by a specific communication protocol.

  Each rule set is composed of a field group including information necessary for packet transfer processing such as an IP address and a port number.

  In each rule set, there is a rule in which information is completely set in all fields, but there is also a rule in which information is only partially set in the field.

  As an example, for example, an IPv4 address is 32-bit data, but there is a concept of a network part / host part. Often, only the upper N bits of the network part are searched, and the lower (32-N) bits are not included in the search target. The operation is made.

  In the portion not included in the search target, “Don't Care” data is written in the search memory 8.

  When a field containing a large amount of “Don't Care” bits is assigned to the first segment (sub-block) of time-division search, it does not function as an entry narrower. Is difficult to obtain.

  Further, a specific range such as 1024 to 65335 may be collectively handled for port numbers. In this way, with respect to a rule set including range information, a method of expressing one rule with a plurality of entries using a range expansion algorithm is used.

  At this time, the same data is copied to all fields other than the port number.

  Therefore, when a rule set is stored in the search memory 8, there are locally field areas where entry narrowing does not work effectively.

  In the embodiment, in the time division search, a field region that is highly likely to be effective for narrowing down the entry is assigned to the first segment (subblock).

  When initializing (setting) the search memory 8, the CPU 2 executes an analysis process for each rule set stored in the search memory 8.

  Normally, each rule set is held in a table format, but each rule table is expressed in a format that is easy for humans to manage. Therefore, it is necessary to convert each rule table into a format suitable for search hardware.

  Each converted table is allocated to each block of the search memory 8, and the data width and mask setting of the setting register 16 and the setting of the profile register 26 are performed.

  The CPU 2 performs data analysis on the sub-table obtained by dividing each rule table into units of the search block 10.

  The CPU 2 specifies a field that is effective for time-division search in each search block 10 by data analysis on the sub-table.

  In this example, a case where the TCAM device 12 included in the search block 10 has four sub-blocks will be described.

  As an example, when the length of the entry data of the sub-table is 160 bits, it is divided into four fields of 40 bits each.

  The CPU 2 specifies which of the four fields corresponding to the four sub-blocks among the sub-tables stored in each search block 10 is an effective field for the time-division search.

  In this respect, a field having no or few “Don't Care” bits is specified as a valid field.

  As an example, it is assumed that the second field of the first to fourth fields is specified as a valid field.

  In this case, the CPU 2 sets “01” in the setting register 16 of the search block 10 based on the analysis result.

  Thereby, when “01” is stored in the setting register 16, the rearrangement control signal generation unit 15 outputs the control signal S <b> 2 to the rearrangement circuits 17 and 18.

  The rearrangement circuits 17 and 18 change the data arrangement order when the control signal S2 is input.

  In this case, the rearrangement circuit 17 changes the data arrangement order so that the second field and the first field of the entry data in the sub-table are switched.

  Then, the sub-tables according to the changed data arrangement order are stored in the four sub-blocks, respectively. That is, when the data arrangement order is not changed, the data of the first field of the subtable is stored in the first subblock, and the second field of the subtable is stored in the second subblock. However, by changing the data arrangement order, the second field of the sub-table is stored in the first sub-block, and the first field of the sub-table is stored in the second sub-block.

The above setting is performed for each search block 10.
Therefore, in the search blocks 10-1 to 10-n shown in FIG. 2, the values stored in the setting register 16 may be different based on the analysis results of the stored subtables.

  Thereby, initialization (setting) of the search memory 8 is completed, and actual transfer processing, that is, data writing processing is started.

(Searching the search memory 8)
At the time of search, the search key generation unit 29 generates a search key.

The search key is output to each search block 10.
In each search block 10, a control signal is generated based on the value of the setting register 16 as described above.

  As an example, when the value of the setting register 16 is “01”, the rearrangement control signal generation unit 15 outputs the control signal S2 to the rearrangement circuits 17 and 18.

  When the control signal S2 is input, the rearrangement circuits 17 and 18 change the data arrangement order and output a search key.

  In this case, the rearrangement circuit 17 divides the input search key into four search keys SA to SD, and changes the data arrangement order of the second search key SB and the first search key SA.

  Then, the rearrangement circuit 17 outputs the search key whose data arrangement order has been changed to each of the segments 12A to 12D. That is, the second search key SB is output to the segment 12A, and the first search key SA is output to the segment 12B.

  As a result, the comparison process between the second field of the sub-table, which is originally executed as the second search, and the search key SB is executed as the first search. The second field of the sub-table is specified as an effective field having no or few “Don't Care” bits, and is likely to be inconsistent.

  Accordingly, when there is a mismatch, the entry of the mismatch in the subsequent segment is not a search target, so that the power consumption of the subsequent segment can be suppressed.

  In this example, the case where the second field of the sub-table is identified as a valid field has been described. However, the present invention is not limited to this, and the third and fourth fields are identified as valid fields. The same applies to.

FIG. 10 is a diagram for explaining the search timing of the search block 10.
As shown in FIG. 10, the search block 10 operates in synchronization with the clock CLK.

  In synchronization with the clock CLK, the rearrangement circuit 18 acquires a search key (keyA) at time T1. At time T 2, the search key (keyB) according to the data arrangement order changed based on the control signal output from the setting register 16 is output to the TCAM device 12. At time T3, the TCAM device 12 receives the input of the search key (keyB) output from the rearrangement circuit 18 and executes the search operation.

  A case is shown in which the result is output from the first-stage segment 12A at time T4 at the synchronization timing of the next clock CLK.

  Further, the case where the result is output from the next segment 12B at time T5 at the synchronization timing of the next clock CLK is shown.

The process is repeated and the search result from the last segment 12D is output.
(Reading the search memory 8)
The reading of entry data stored in the search memory 8 will be described.

  When the value of the setting register 16 is “01”, the rearrangement control signal generation unit 15 outputs the control signal S2 to the rearrangement circuit 18.

  When the control signal S2 is input, the rearrangement circuit 18 changes the data arrangement order and outputs it.

  In this case, the rearrangement circuit 18 changes the data arrangement order of the entry data read from each of the segments 12A to 12D.

  Specifically, the data arrangement order of the data read from the segment 12A and the data read from the segment 12B is changed. The data read from the segment 12B is output as the first, the data read from the segment 12B is the second, and the data read from the segments 12C and 12D is output as the third and fourth.

  By this method, it is possible to easily restore the data before changing the data arrangement order before storing in the search block 10.

  Therefore, in the embodiment, it is possible to maximize the effect of such a time division search by setting the setting register 16 so that a field that is likely to be inconsistent is written in the first-stage segment. .

(Maintenance of search memory 8)
The maintenance operation of the search memory 8 will be described.

  The rule table is updated during actual operation for various reasons, such as automatic update by a network control protocol and policy change by a network administrator. Specifically, the entry is overwritten or newly added.

  Since the setting register 16 cannot be rewritten during operation, there is a difference between the analysis content of the first rule table and the analysis content of the latest rule table information due to the update of the rule table. May be reduced.

  In the embodiment, the case where the CPU 2 executes the maintenance process of the search memory 8 will be described. However, the transfer control circuit 4 such as an NPU may be executed by the CPU 2 and the search memory 8 may be maintained. It is good also as a structure which incorporates the chip | tip which performs a process.

FIG. 11 is a diagram for explaining the maintenance operation of the search memory 8.
As shown in FIG. 11, the maintenance process is executed with a predetermined time elapse or the number of write commands issued to the search memory 8 as a trigger. Here, a case where a trigger is generated as an interrupt after a predetermined time elapses by a timer or the like is shown.

  Next, the CPU 2 reads the latest rule table stored in the search block 10 that is the target of the search memory 8, for example, the search block 10-1 (read all entries) (1). As described above, when data is read from the search block 10-1, the rearrangement circuit 18 changes the data arrangement order based on the register value of the setting register 16. As a result, the data is restored to the initial data array, and can be used as it is as write data to an empty search block 10, which will be described later, for example, the search block 10-n.

  Next, the CPU 2 executes a process of analyzing the latest rule table read from the target search block 10-1, and generates information related to the register value stored in the setting register 16 based on the analysis result (2).

  Next, the CPU 2 checks whether or not the current setting register 16, that is, the register value stored in the setting register 16 of the search block 10-1, is the same as the information related to the generated register value.

  That is, it is determined whether or not the register value of the setting register 16 of the search block 10-1 specifies a field area that can effectively narrow down entries. Determine whether the field is valid for time-division search.

  When the CPU 2 determines that the information about the generated register value is different from the register value stored in the setting register 16 of the search block 10-1, the CPU 2 uses the information about the generated register value as an empty search block 10, That is, it is stored in the setting register 16 of the search block 10-n (3).

  Then, the latest rule table information acquired from the original search block 10-1 is copied to the TCAM device 12 of the empty search block 10-n (4).

  At this time, the rearrangement circuits 17 and 18 of the search block 10-n change the data arrangement order based on the stored register value of the setting register 16. As described above, the field data effective for the search is stored in the first segment of the empty search block 10-n.

  When the copying is completed, the CPU 2 resets the profile register 26 and replaces the search block 10-1 as the original target to be searched with the search block 10-n as the copy destination (5).

  Since the new search block 10 maximizes the low power consumption effect of the time division search, it contributes to low power consumption of the entire system.

  With this maintenance method, it is possible to reduce power consumption without stopping the operation of the entire system.

  Further, various rule tables having different properties such as NetFlow / FIB / QoS / ACL are written in the search memory, and processing such as a range expansion algorithm is performed as described above. Therefore, the data actually written in the search block is likely to be biased. If a time division search is performed uniformly on such a data structure, a situation occurs in which the time division search is extremely effective for a certain block and not effective at all for another block.

  In particular, in a table using IPv6 addresses, a large don't care lump is likely to occur, and this portion is inappropriate for narrowing down the entries to be searched. Therefore, when assigned to the first segment of the time division search, the time division search is not performed. No effect at all.

  By adopting the system based on the embodiment, it is possible to eliminate such a bias for each block, and as a result, it is possible to maximize the power saving effect by the time division search.

  Further, the method according to the first embodiment makes it possible to generate a search key optimal for time-division search for each search block from one search key, so that a plurality of search commands can be collected at one time. Thus, the throughput can be improved.

  Further, in a device with high power consumption such as a TCAM device, a search operation may be divided into multiple times by limiting search blocks to be searched from the viewpoint of system thermal design and power supply design. In such a case, reducing the power consumption leads to elimination or reduction of the division operation, and contributes to the improvement of the throughput of the search operation.

(Embodiment 2)
Also in the second embodiment, the rule set created by the end user is converted into a table format suitable for the search memory 8, and the rule set is further divided into smaller areas for analysis and setting the setting register 16.

  In the first embodiment described above, the case where the field information effective for the search is stored in the first segment of the TCAM device 12 has been described.

  In the second embodiment, an area that does not include a don't care bit is stored in a BCAM (Binary Content Addressable Memory) device as information on a field effective for search. The remaining area is stored in the TCAM device. In this example, a case where a BCAM device is used will be described, but an ASE (Algorithmic Search Engine) is implemented by combining a storage element such as SRAM or FF and a logic circuit that implements a search algorithm such as a tree hash. May be used.

FIG. 12 is a diagram for explaining a search method of the search block 10 # based on the second embodiment.
As shown in FIG. 12, the search block 10 # differs from the search block 10 in that a BCAM device 12P and a TCAM device 12Q are provided instead of the TCAM device 12. Other configurations are the same as those described with reference to FIG. 9, and thus detailed description thereof will not be repeated.

  FIG. 13 is a circuit diagram showing an example of the configuration of the BCAM cell MC # of the BCAM device 12P.

  Referring to FIG. 13, BCAM cell MC # includes one SRAM cell 11 and a data comparison unit 13 #. The SRAM cell 11 stores 1-bit data that is complementary to the internal storage node pair ND1, ND1_n (one is “1” and the other is “0”).

  The BCAM cell is connected to the bit line pair BL, BL_n, the search line pair SL, SL_n, the match line ML, and the word line WLX. The bit line pair BL, BL_n extends in the column direction (Y direction) and is shared by a plurality of BCAM cells arranged in the column direction. The search line pair SL, SL_n extends in the column direction (Y direction) and is shared by a plurality of BCAM cells arranged in the column direction.

  The match line ML extends in the row direction (X direction) and is shared by a plurality of BCAM cells arranged in the row direction. The word line WLX extends in the row direction (X direction) and is shared by a plurality of BCAM cells arranged in the row direction.

  Data comparison unit 13 # differs from data comparison unit 13 in that MOS transistors Q8 and Q9 are deleted. Since other configurations are the same as those of the data comparison unit 13, detailed description thereof will not be repeated.

  In the search block 10 # of the second embodiment, the first search is performed by the BCAM device, and the second and subsequent searches are performed by the TCAM device. And the time division operation | movement which produces | generates a search result is performed. The BCAM device stores a field that does not include don't care in the rule set.

  The value of the setting register 16 is set so that the Binary segment is assigned to the first segment by the BCAM device for time division search.

The rearrangement control signal generation unit 15 generates a control signal based on the value of the setting register 16.
The rearrangement circuits 17 and 18 change the data arrangement order of the search keys based on the control signal generated by the rearrangement control signal generation unit 15.

  The value of the setting register 16 may be any value as long as it leads to the determination of whether to allocate each segment to a BCAM device or a TCAM device. Note that when using an ASE for tree search, LPM (Longest Prefix Match) can also be used as effective information, or a specific search order may be described.

  In this case, there is no need to be aware of the internal structure of the search memory 8 when viewed from the ASIC circuit or NPU, and the search table is automatically divided and rearranged by appropriately setting the register value of the setting register of each search block. Can be performed.

(Searching the search memory 8)
At the time of search, the search key generation unit 29 generates a search key.

The search key is output to each search block 10 #.
For the search keys distributed to each search block 10 #, the data arrangement order of the search keys is changed by the rearrangement circuit 17 based on the value of the setting register 16.

  Then, after being rearranged by the rearrangement circuit 17, it is divided into a BCAM device 12P and a TCAM device 12Q, and outputted.

  Then, in the BCAM device 12P, a comparison operation between the received search key and each entry data stored in the BCAM device 12P is executed. Then, all the comparison results are output from the BCAM device 12P as the control signal MLOUT.

  The TCAM device 12Q controls the comparison operation between the received search key and each entry data by the control signal MLOUT. Specifically, as described in the first embodiment, the control signal MLOUT is connected to the se terminal. With this configuration, only the entry data corresponding to the entry data hit by the BCAM device 12P is compared with the search key, thereby reducing the power consumption of the TCAM device 12Q.

  In the TCAM device 12Q, the search result is passed to the priority encoder, and a final search result address is generated.

  With this configuration, by storing a part of the rule table in the BCAM device 12P, the area can be reduced as compared with the case where all the rule tables are stored in the TCAM device.

  In the first embodiment, it is necessary to analyze a rule table when setting a setting register and specify a field that is considered to be effective for narrowing down entries in a time division search. For this purpose, it is necessary to analyze the number of don't care bits and the variation of data included in a certain range. However, in the second embodiment, analysis can be performed only by binary or tertiary determination. Processing can also be reduced.

(Modification)
In the second embodiment, the case where a plurality of different search modules are connected to perform time division search has been described.

  On the other hand, it is necessary to delay the signal input for the second search in accordance with the delay until the first search is output.

  FIG. 14 is a diagram illustrating a search method of the search block 10A based on the modification of the second embodiment.

  As shown in FIG. 14, the search block 10A is provided with a timing adjustment circuit 19 as compared with the search block 10 #.

  The timing adjustment circuit 19 includes a rearrangement circuit 18, data flip-flop circuits DFF1 to DFF4 used for data retention, and selectors SEL1 to SEL4.

  The data flip-flop circuits DFF1 to DFF4 hold the signal output from the rearrangement circuit 18.

  The selectors SEL1 to SEL4 switch which of the signal output from the rearrangement circuit 18 and the data flip-flop circuits DFF1 to DFF4 is selected and output.

  A switching signal for switching selection of the selectors SEL1 to SEL4 is output from the rearrangement control signal generation unit 15 #.

  For example, in this example, the selectors SEL1 to SEL3 output data from the data flip-flop circuits DFF1 to DFF3 because the selectors SEL1 to SEL3 are configured to output search keys to the TCAM device 12Q.

  On the other hand, since the selector SEL4 is configured to output a search key to the BCAM device 12P, it outputs the data from the rearrangement circuit 18 as it is, not the data from the data flip-flop circuit DFF4.

FIG. 15 is a diagram for explaining the search timing of the search block 10A.
As shown in FIG. 15, the search block 10A operates in synchronization with the clock CLK.

  In synchronization with the clock CLK, the rearrangement circuit 18 acquires a search key (keyA) at time T10. At time T11, the search key (keyB) according to the data arrangement order changed based on the control signal output from the setting register 16 is output to the BCAM device 12P. Here, as an example, a case will be described in which a 160-bit search key is input, a 40-bit search key is output to the BCAM device 12P, and the remaining 120-bit search key is divided and output to the TCAM device 12Q. .

  At time T12, the BCAM device 12P receives the input of the search key (keyB) output from the rearrangement circuit 18 and executes the search operation.

  A case is shown in which the result is output from the BCAM device 12P at time T13 at the synchronization timing of the next clock CLK.

  Then, at time T13 at the same timing, the search key (keyC) held in the data flip-flop circuits DFF1 to DFF3 is output to the TCAM device 12Q.

  In this example, the remaining 120-bit search key used in the TCAM device 12Q, which is the subsequent segment, is once taken into the data flip-flop circuit DFF, and is therefore input to the TCAM device 12Q with a delay of one cycle. Therefore, the TCAM device 12Q can receive the input of the search key and the output of the search result of the BCAM device 12P at substantially the same timing.

  At time T14, the search operation of the TCAM device 12Q with the search key (keyC) is executed based on the result from the BCAM device 12P.

  A case is shown in which the result is output from the TCAM device 12Q at time T15 at the synchronization timing of the next clock CLK.

  As mentioned above, although this indication was concretely demonstrated based on embodiment, it cannot be overemphasized that this indication is not limited to embodiment, and can be variously changed in the range which does not deviate from the summary.

  DESCRIPTION OF SYMBOLS 1 Communication apparatus, 4 Transfer control circuit, 6 General-purpose memory, 8 Search memory, 10, 10A search block, 12 TCAM apparatus, 13 Data comparison part, 15 Relocation control signal generation part, 16 Setting register, 17, 18 Relocation circuit , 19 Timing adjustment circuit, 20 TCAM cell array, 21 Write driver, 22 Search line driver, 23 Match amplifier unit, 24 Control logic circuit, 25 Read circuit, 26 Profile register, 27 Data change unit, 28 Search result generation unit, 29 Search key generation unit.

Claims (9)

N sub-blocks each including a memory cell array;
A setting register for designating the number of entry data for pre-search among the 1st to Nth entry data divided in correspondence with the N sub-blocks;
A search data changing unit that changes the data arrangement order of the search data input based on the value of the setting register,
Of the N sub-blocks, the pre-search sub-block is pre-registered according to the data arrangement order of the entry data stored for each row of the memory cell array according to the search instruction. Search for data that matches the search data, and output a search result that matches or does not match for each row.
Of the N sub-blocks, a post-search sub-block is based on a search result of the pre-search sub-block, and among the entry data stored for each row of the memory cell array, A semiconductor device that searches for data that matches post search data other than the pre-search data, and outputs a search result that matches or does not match for each row.   The semiconductor device according to claim 1, further comprising a read entry data changing unit that changes an arrangement order of 1st to Nth entry data read from each of the N sub-blocks based on a value of the setting register.   The read entry data changing unit obtains all the 1st to Nth entry data stored for each row stored in the N sub-blocks, and based on the data analysis, The semiconductor device according to claim 2, further comprising an analysis unit that re-specifies the number. A write entry data changing unit for changing the data arrangement order of the first to Nth write entry data based on the value of the setting register;
2. The semiconductor device according to claim 1, wherein each of the N sub-blocks further includes a write circuit that writes entry data in the changed order into the memory array.   The search data changing unit includes a holding circuit that outputs presearch data out of the input search data to the presearch subblock and holds post search data other than the presearch data. The semiconductor device according to claim 1.   The memory cell array of the pre-search sub-block has memory cells that hold binary values and can be compared with the pre-search data for matching or non-matching, and for the post-search sub-block 2. The semiconductor device according to claim 1, wherein the memory cell array includes memory cells that hold three values and can be compared with the post-search data for matching or mismatching. With multiple search blocks,
Each said search block
N sub-blocks each including a memory cell array;
A setting register for designating the number of entry data for pre-search among the 1st to Nth entry data divided in correspondence with the N sub-blocks;
A search data changing unit that changes the data arrangement order of search data input in common to the plurality of search blocks based on the value of the setting register,
Of the N sub-blocks, the pre-search sub-block is pre-registered according to the data arrangement order of the entry data stored for each row of the memory cell array according to the search instruction. Search for data that matches the search data, and output a search result that matches or does not match for each row.
Of the N sub-blocks, a post-search sub-block is based on a search result of the pre-search sub-block, and among the entry data stored for each row of the memory cell array, A semiconductor device that searches for data that matches post search data other than the pre-search data, and outputs a search result that matches or does not match for each row. First and second sub-blocks each including an associative memory cell arranged in a matrix;
A setting register specifying a correspondence relationship with the first and second sub-blocks in which the first and second write data constituting the write data are stored,
The first and second sub-blocks corresponding to the first and second search keys constituting the search data by changing the data arrangement order of the input search data based on the value of the setting register A data array order changing unit for outputting to
The first sub-block performs a search operation using one of the first and second search keys input to the first sub-block,
The second sub-block performs a search operation using the other of the first and second search keys based on a result of the search operation of the first sub-block.   Read data arrangement order for changing the arrangement order of the first and second write data stored in the first and second sub-blocks and outputting them as read data in accordance with the value of the setting register The semiconductor device according to claim 8, further comprising a changing unit.

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