JP2019004097A - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Abstract

To provide a multilayer ceramic capacitor in which freedom of design and improvement of heat dissipation can be compatible, and to provide a manufacturing method thereof.SOLUTION: In a counter electrode part 22a where a first internal electrode 18a and a second internal electrode 18b, in the central part of the lamination direction x connecting the first and second principal surfaces 14a, 14b of a laminate 14, are facing, portions where the first and second internal electrodes 18a, 18b are thick exist. As approaching the center of the central part of the lamination direction x connecting the first and second principal surfaces 14a, 14b of the laminate 14, the thick portions of the first and second internal electrodes 18a, 18b become thick. Furthermore, in the plan view of the first and second internal electrodes 18a, 18b, the thick portions of the first and second internal electrodes 18a, 18b become thick as approaching the center of the counter electrode part 22a.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

In general, when an alternating current is applied to a multilayer ceramic capacitor, heat generation ΔT (ΔT) proportional to an equivalent series resistance ESR (ESR = electrode resistance r + resistance tan δ / ωC due to dielectric loss).
∝ ESR × I ² ) occurs. Due to this heat generation, the temperature of the multilayer ceramic capacitor rises, and in particular, the temperature rises at the center, which causes a reduction in high temperature load reliability.

  In addition, since heat is transferred from the multilayer ceramic capacitor to other electronic components and adversely affects other electronic components, a means for reducing the heat generation of the multilayer ceramic capacitor is desired.

  As shown in FIG. 13, generally, the multilayer ceramic capacitor 100 includes a multilayer body 114, a first external electrode 124a, and a second external electrode 124b. The stacked body 114 includes a plurality of stacked dielectric layers 116 and a plurality of internal electrodes 118. The plurality of internal electrodes 118 include a plurality of first internal electrodes 118a and a plurality of second internal electrodes 118a. The plurality of dielectric layers 116 include an outer layer portion 116a and an inner layer portion 116b.

  The multilayer body 114 is an inner layer in which the first internal electrode 118a is disposed on the dielectric layer 116 and the second internal electrode 118b is disposed on the dielectric layer 116 alternately. It has a structure comprising a part 116b and an outer layer part 116a in which a plurality of dielectric layers 116a having no internal electrode are respectively laminated on both upper and lower sides.

  In the conventional multilayer ceramic capacitor 100, the thickness of the plurality of internal electrodes 118 is generally substantially uniform over the entire surface.

  In the multilayer ceramic capacitor 100 having such a structure, when an alternating current is applied, most of the heat generated inside the multilayer ceramic capacitor 100 is dissipated to the outer layer portion 116 a via the internal electrode 118. Therefore, the surface temperature of the outer layer portion 116 a depends on the heat dissipation characteristics of the internal electrode 118.

  In particular, in recent years, the dielectric layer 116 and the internal electrode 118 have been made thinner due to the demand for smaller and larger capacity multilayer ceramic capacitors, and improvement of the heat dissipation characteristics of the internal electrode 118 has become a problem. .

  Therefore, for example, as disclosed in Patent Document 1, a dielectric ceramic composition is devised by paying attention to dielectric loss, and heat dissipation is reduced by combining a plurality of internal electrodes as disclosed in Patent Document 2 or a technique for reducing heat generation. Techniques for improving the quality have been proposed.

JP 2006-321670 A JP-A-7-297072

  However, the multilayer ceramic capacitor of Patent Document 1 has a problem that the degree of freedom in design is low because the application is limited by the dielectric ceramic composition.

  In addition, although the multilayer ceramic capacitor of Patent Document 2 has improved heat dissipation, the thickness of the internal electrode is increased, so that the number of stacked layers is limited and the degree of freedom in designing the capacitance is reduced. was there. Furthermore, there is a problem that the manufacturing cost increases due to an increase in the amount of the material used for the internal electrode.

  Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor and a method for manufacturing the same that can achieve both a degree of freedom in design and an improvement in heat dissipation.

The multilayer ceramic capacitor according to the present invention includes a plurality of stacked dielectric layers, and a first main surface and a second main surface facing the stacking direction, and a first facing the width direction orthogonal to the stacking direction. A stacked body including a side surface and a second side surface of the first side surface, a first end surface and a second end surface facing in the length direction orthogonal to the stacking direction and the width direction, and disposed on the plurality of dielectric layers, A first internal electrode in which the first lead electrode portion is exposed on the first end face, and a second internal electrode that is disposed on the plurality of dielectric layers and in which the second lead electrode portion is exposed on the second end face A first external electrode connected to the first internal electrode and disposed on the first end face; and a second external electrode connected to the second internal electrode and disposed on the second end face A multilayer ceramic capacitor having a product connecting the first main surface and the second main surface of the multilayer body In the counter electrode portion where the first internal electrode and the second internal electrode face each other in the central portion in the direction, there are portions where the first internal electrode and the second internal electrode are thick. A multilayer ceramic capacitor.
In addition, the multilayer ceramic capacitor according to the present invention has the first internal electrode and the second internal electrode as they approach the center of the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. It is preferable that the thick part is thick.
Moreover, the multilayer ceramic capacitor according to the present invention is a counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In the portion, when the first internal electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode may become thicker as they approach the center of the counter electrode portion. preferable.
Moreover, the multilayer ceramic capacitor according to the present invention is a counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In the portion, when the first internal electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode gradually become thicker as they approach the center of the counter electrode portion. It is preferable to have a smooth dome shape in which the thickness is increased.
Alternatively, the multilayer ceramic capacitor according to the present invention is a counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In the portion, when the first internal electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode are stepped as they approach the center of the counter electrode portion. It is preferable to have a stepped dome shape with an increased thickness.
A method for manufacturing a multilayer ceramic capacitor according to the present invention is a method for manufacturing a multilayer ceramic capacitor according to any one of the foregoing, wherein the first internal electrode and the second internal electrode are printed by an ink jet printing method and have a thickness. A method for producing a multilayer ceramic capacitor, characterized in that the thickness of a thick portion is controlled.
In the method for manufacturing a multilayer ceramic capacitor according to the present invention, the thickness of the thick portion is preferably controlled by a single coating.

According to the multilayer ceramic capacitor of the present invention, the counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In this part, since the first internal electrode and the second internal electrode have thick portions, the resistance of the internal electrode can be reduced, and the volume of the internal electrode having higher thermal conductivity than ceramic can be reduced. Since it can be increased, the heat dissipation characteristics can be improved. Therefore, the heat generation of the multilayer ceramic capacitor can be reduced.
In addition, the multilayer ceramic capacitor according to the present invention has the first internal electrode and the second internal electrode as they approach the center of the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. When the thick part is thick, heat generation can be reduced with as little temperature gradient as possible. As a result, the calorific value of the multilayer ceramic capacitor can be reduced while maintaining the material composition, and the degree of freedom in design can be ensured. In addition, since the thickness of the internal electrode can be increased only in a necessary portion, the amount of material used for the internal electrode is optimized, and an increase in manufacturing cost can be suppressed.
Furthermore, the multilayer ceramic capacitor according to the present invention is a counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In the portion, when the first internal electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode become thicker as they approach the center of the counter electrode portion. In the central part where the heat generation is most likely to occur in the ceramic capacitor, it becomes easy to realize the reduction of the heat generation with the least possible temperature gradient, and the heat generation can be further reduced.
Moreover, the multilayer ceramic capacitor according to the present invention is a counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In the portion, when the first internal electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode gradually become thicker as they approach the center of the counter electrode portion. When the smooth dome shape is made thicker, the degree of freedom in design can be expanded, and the heat generation can be further reduced in the central portion where the heat generation is most likely to occur in the multilayer ceramic capacitor.
Furthermore, the multilayer ceramic capacitor according to the present invention is a counter electrode in which the first internal electrode and the second internal electrode are opposed to each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body. In the portion, when the first internal electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode are stepped as they approach the center of the counter electrode portion. When the thickness of the stepped dome is increased, the thickest portion at the center becomes flat, and the effect of alleviating electric field concentration can be obtained.
According to the method for manufacturing a multilayer ceramic capacitor according to the present invention, when the multilayer ceramic capacitor according to the present invention is manufactured, the internal electrode patterns having different thicknesses are printed by the ink jet printing method so that the present invention is applied. A multilayer ceramic capacitor can be manufactured efficiently.
Further, according to the method for manufacturing a multilayer ceramic capacitor according to the present invention, when the thickness is controlled by applying the thick internal electrode pattern once, the multilayer ceramic capacitor can be more efficiently manufactured. .

  According to the present invention, it is possible to obtain a multilayer ceramic capacitor and a method for manufacturing the same, which can achieve both a degree of freedom in design and an improvement in heat dissipation.

  The above-described object, other objects, features, and advantages of the present invention will become more apparent from the following description of embodiments for carrying out the invention with reference to the drawings.

1 is an external perspective view showing an embodiment of a multilayer ceramic capacitor according to the present invention. It is sectional drawing in the II-II line of FIG. It is sectional drawing in the III-III line of FIG. It is sectional drawing in the IV-IV line of FIG. It is a schematic block diagram which shows the internal electrode of the 3 layer structure shown in FIG. It is sectional drawing in the VI-VI line of FIG. It is a schematic block diagram which shows the internal electrode of the 2 layer structure shown in FIG. It is sectional drawing in the VIII-VIII line of FIG. It is a schematic block diagram which shows the internal electrode of the 1 layer structure shown in FIG. It is a schematic sectional drawing which shows the effect | action of the internal electrode which consists of a staircase dome shape which thickened the step shape. It is a schematic sectional drawing which shows the effect | action of the internal electrode which consists of a smooth curved-surface dome shape which thickened gradually. It is a see-through | perspective perspective view of the laminated body which shows the range which thickens an internal electrode. It is sectional drawing which shows the conventional multilayer ceramic capacitor.

1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to an embodiment of the present invention will be described. FIG. 1 is an external perspective view showing an embodiment of a multilayer ceramic capacitor according to the present invention. 2 is a cross-sectional view taken along line II-II in FIG. 3 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a schematic configuration diagram showing the internal electrode having the three-layer structure shown in FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. FIG. 7 is a schematic configuration diagram showing the internal electrode of the two-layer structure shown in FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. FIG. 9 is a schematic configuration diagram showing the internal electrode having the single-layer structure shown in FIG.

  As shown in FIGS. 1 and 2, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 14 and an external electrode 24.

The stacked body 14 includes a plurality of stacked dielectric layers 16 and a plurality of internal electrodes 18. Furthermore, the laminate 14 includes a first main surface 14a and a second main surface 14b that are opposed to the lamination direction x, and a first side surface 14c and a second side surface that are opposed to the width direction y orthogonal to the lamination direction x. 14d, and a first end face 14e and a second end face 14f that face the length direction z orthogonal to the stacking direction x and the width direction y. The laminated body 14 is preferably rounded at corners and ridge lines. In addition, a corner | angular part is a part where three adjacent surfaces of a laminated body cross, and a ridgeline part is a part where two adjacent surfaces of a laminated body intersect.
In addition, the first main surface 14a and the second main surface 14b, the first side surface 14c and the second side surface 14d, and the first end surface 14e and the second end surface 14f are partially or entirely uneven. Etc. may be formed.

  The dielectric layer 16 includes an outer layer portion 16a and an inner layer portion 16b. The outer layer portion 16a is located on the first main surface 14a side and the second main surface 14b side of the laminate 14, and is between the first main surface 14a and the inner electrode 18 closest to the first main surface 14a. And the dielectric layer 16 positioned between the second main surface 14b and the internal electrode 18 closest to the second main surface 14b. A region sandwiched between the outer layer portions 16a is the inner layer portion 16b.

As a material of the dielectric layer 16, for example, a dielectric ceramic containing a component such as BaTiO ₃ , CaTiO ₃ , SrTiO ₃ CaZrO ₃ can be used. When the above dielectric material is included as a main component, the content is less than that of a main component such as a Mn compound, Fe compound, Cr compound, Co compound, Ni compound, etc., depending on the desired characteristics of the multilayer ceramic capacitor 10. You may use what added the component.

  The thickness of the dielectric layer 16 after firing is preferably not less than 0.5 μm and not more than 20 μm.

  As illustrated in FIG. 2, the multilayer body 14 includes, as the plurality of internal electrodes 18, for example, a plurality of first internal electrodes 18 a and a plurality of second internal electrodes 18 b having a substantially rectangular shape. The plurality of first internal electrodes 18 a and the plurality of second internal electrodes 18 b are embedded so as to be alternately arranged at equal intervals along the stacking direction x of the stacked body 14.

One end side of the first internal electrode 18 a has a first extraction electrode portion 20 a that is extracted to the first end surface 14 e of the multilayer body 14. On the one end side of the second internal electrode 18b, a second extraction electrode portion 20b drawn to the second end face 14f of the multilayer body 14 is provided. Specifically, the first extraction electrode portion 20 a on one end side of the first internal electrode 18 a is exposed on the first end face 14 e of the multilayer body 14. Further, the second extraction electrode portion 20 b on one end side of the second internal electrode 18 b is exposed on the second end face 14 f of the multilayer body 14.
The internal electrode 18 may be disposed so as to be parallel to the mounting surface or may be disposed so as to be vertical.

  The laminated body 14 includes a counter electrode portion 22a in which the first internal electrode 18a and the second internal electrode 18b face each other in the inner layer portion 16b of the dielectric layer 16. The stacked body 14 is formed between one end in the width direction y of the counter electrode portion 22a and the first side surface 14c and between the other end in the width direction y of the counter electrode portion 22a and the second side surface 14d. Side part (hereinafter referred to as “W gap”) 22b of the laminate 14. Further, the multilayer body 14 includes a second extraction electrode of the second internal electrode 18b between the end portion of the first internal electrode 18a opposite to the first extraction electrode portion 20a and the second end surface 14f. It includes an end portion (hereinafter referred to as “L gap”) 22c of the stacked body 14 formed between the end portion on the opposite side to the portion 20b and the first end face 14e.

  The internal electrode 18 contains, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy such as an Ag—Pd alloy containing one of these metals. In particular, the main component of the internal electrode 18 is preferably Ni. The internal electrode 18 may further include dielectric particles having the same composition system as the ceramic contained in the dielectric layer 16.

  The first internal electrode 18a and the second internal electrode 18b in the central part (hot spot where the degree of heat generation is large) in the stacking direction x connecting the first main surface 14a and the second main surface 14b of the stacked body 14 Are opposed to each other, a portion where the thickness of the first internal electrode 18a is locally thick and a portion where the thickness of the second internal electrode 18b is locally thick are disposed.

Specifically, the stacking direction x in which the plurality of first internal electrodes 18a3 and the plurality of second internal electrodes 18b3 having a three-stage structure connect the first main surface 14a and the second main surface 14b of the stacked body 14 is described. It is formed in the central part. As shown in FIGS. 4 and 5, the first internal electrode 18a3 having a three-stage structure includes a first layer 40, a second layer 42, and a third layer 44. In the counter electrode portion 22a, There is a portion where the thickness of the internal electrode 18a3 is locally thick (a portion where the second layer 42 and the third layer 44 are disposed).
The second internal electrode 18b3 having a three-stage structure includes a first layer 40, a second layer 42, and a third layer 44, and the thickness of the second internal electrode 18b3 is locally thick in the counter electrode portion 22a. A portion (a portion where the second layer 42 and the third layer 44 are disposed) exists.

The second layer 42 and the third layer 44 stacked on the first layer 40 as the base are within a range in which the total thickness of the first layer 40 to the third layer 44 does not exceed three times the thickness of the first layer 40. Any number of layers may be stacked as long as they are present, but it is preferable to form about 2-3 layers with the same thickness as the first layer 40.
For example, the first internal electrode 18a3 and the second internal electrode 18b3 having a three-stage structure have locally thick portions (portions where the second layer 42 and the third layer 44 are disposed) other than The thickness is preferably about 1.2 to 3 times thicker than the portion (the portion where only the first layer 40 is disposed). Specifically, the locally thick portion (the portion where the second layer 42 and the third layer 44 are disposed) is preferably 0.4 μm or more and 3 μm or less, and the other portion (first portion). The portion where only the layer 40 is disposed is preferably 0.3 μm or more and 1 μm or less.

The plurality of first internal electrodes 18a2 and the plurality of second internal electrodes 18b2 having a two-stage structure are composed of two groups, and are formed in the central portion of the stacked body 14 in the stacking direction x. The internal electrode 18a3 and the second internal electrode 18b3 are disposed on both sides. As shown in FIGS. 6 and 7, the first internal electrode 18a2 having a two-stage structure includes a first layer 50 and a second layer 52, and the thickness of the first internal electrode 18a2 in the counter electrode portion 22a. There are locally thick portions (portions where the second layer 52 is disposed).
The second internal electrode 18b2 having a two-stage structure includes a first layer 50 and a second layer 52. In the counter electrode portion 22a, a portion where the thickness of the second internal electrode 18b2 is locally thick (second layer) There is a portion where 52 is arranged).

  In the first internal electrode 18a2 and the second internal electrode 18b2 having a two-stage structure, a locally thick portion (a portion where the second layer 52 is disposed) is provided in the other portion (only the first layer 50 is provided). It is preferable that the thickness is 1.2 to 3 times thicker than the (arranged portion). Specifically, the locally thick portion (the portion where the second layer 52 is disposed) is preferably 0.4 μm or more and 3 μm or less, and the other portion (only the first layer 50 is disposed). Is preferably 0.3 μm or more and 1 μm or less.

The plurality of first inner electrodes 18a1 and the plurality of second inner electrodes 18b1 having a one-stage structure are composed of two groups, one group of which is the first of the two-stage structure closest to the first main surface 14a. Are disposed in a region sandwiched between the internal electrode 18a2 and the exterior portion 16a of the dielectric layer 16. The other group is disposed in a region sandwiched between the second internal electrode 18b2 having a two-stage structure closest to the second main surface 14b and the exterior portion 16a of the dielectric layer 16. As shown in FIGS. 8 and 9, the first internal electrode 18a1 having a one-stage structure is composed of the first layer 60. In the counter electrode portion 22a, the thickness of the first internal electrode 18a1 is substantially uniform over the entire surface. It is a thickness, and there is no portion where the thickness is locally thick.
The second internal electrode 18b1 having a one-stage structure includes the first layer 60. In the counter electrode portion 22a, the entire thickness of the second internal electrode 18b1 is substantially uniform, and the thickness is locally increased. There is no thick part.

  The first internal electrode 18a1 and the second internal electrode 18b1 having a one-stage structure have a substantially uniform thickness over the entire surface, and specifically, it is preferably 0.3 μm or more and 1 μm or less.

  Thereby, in addition to being able to reduce the resistance of the internal electrode 18 in the central portion where the multilayer ceramic capacitor 10 is likely to generate heat, the volume of the internal electrode 18 having higher thermal conductivity than ceramic can be increased. The heat dissipation characteristics can be improved. Therefore, the heat generation of the multilayer ceramic capacitor 10 can be reduced.

  In the present embodiment, by reducing the thickness of the internal electrode 18 only in the central portion where the heat generation of the multilayer ceramic capacitor 10 is likely to occur, the heat generation can be reduced with as little temperature gradient as possible. As a result, the calorific value of the multilayer ceramic capacitor 10 can be reduced while maintaining the material composition, and the degree of freedom in design can be ensured. Moreover, since the thickness of the internal electrode 18 can be increased only in a necessary portion, the amount of material used for the internal electrode 18 is optimized, and the manufacturing cost can be suppressed.

  Further, in the present embodiment, as shown in FIG. 2, as the center approaches the center of the stacking direction x connecting the first main surface 14 a and the second main surface 14 b of the stacked body 14, The thicknesses of the first internal electrode 18a3 and the second internal electrode 18b3 are locally higher than the portion where the thickness of the electrode 18a2 and the second internal electrode 18b is locally thick (the portion where the second layer 52 is disposed). The thicker portion (the portion where the second layer 42 and the third layer 44 are disposed) is designed to be thicker.

  In other words, in the present embodiment, the multilayer ceramic capacitor 10 is designed such that the portion where the thickness of the internal electrode 18 is locally thicker increases as it approaches the center of the central portion where heat generation is likely to occur. Can be achieved with as little temperature gradient as possible. As a result, the calorific value of the multilayer ceramic capacitor 10 can be reduced while maintaining the material composition, and the degree of freedom in design can be ensured. Moreover, since the thickness of the internal electrode 18 can be increased only in a necessary portion, the amount of material used for the internal electrode 18 is optimized, and the manufacturing cost can be suppressed.

  Moreover, in this Embodiment, as shown in FIG.2, FIG4 and FIG.6, in the center part of the lamination direction x which ties the 1st main surface 14a and the 2nd main surface 14b of the laminated body 14, it is 1st. In the counter electrode portion 22a where the internal electrode 18a and the second internal electrode 18b face each other, the first internal electrode 18a2, the first internal electrode 18a3, the second internal electrode 18b2, and the second internal electrode 18b3 are planar. When viewed, a portion where the thickness of the first internal electrode 18a2 and the second internal electrode 18b2 is locally thicker as it approaches the center of the counter electrode portion 22a (a portion where the second layer 52 is disposed), The first internal electrode 18a3 and the second internal electrode 18b3 are designed so that the locally thick portions (portions where the second layer 42 and the third layer 44 are disposed) are thickened.

  As a result, in the central part where the heat generation is most likely to occur in the multilayer ceramic capacitor 10, it is easy to reduce the heat generation with the least possible temperature gradient, and the heat generation can be further reduced.

  The first internal electrode 18a2 and the second internal electrode 18b2 are locally thick (the portion where the second layer 52 is disposed), the first internal electrode 18a3 and the second internal electrode 18b3. The portion where the thickness of the electrode is locally thick (the portion where the second layer 42 and the third layer 44 are disposed) is designed so that the shape has a dome shape when the internal electrode 18 is viewed in plan. Is preferred. With this design, the degree of freedom in design can be expanded, and heat generation can be further reduced in the central portion of the multilayer ceramic capacitor 10 where heat generation is most likely to occur. In addition, regarding the dome shape, the shape is not particularly limited, but is preferably raised in a rectangular shape or a circular shape.

  For example, in the case of the dome shape of the present embodiment, the first internal electrode 18a and the second internal portion in the central portion in the stacking direction x connecting the first main surface 14a and the second main surface 14b of the stacked body 14 are used. When the first internal electrode 18a2, the first internal electrode 18a3, the second internal electrode 18b2, and the second internal electrode 18b3 are viewed in plan in the counter electrode portion 22a facing the electrode 18b, the counter electrode portion 22a , The first internal electrode 18a2 and the second internal electrode 18b2 are locally thick (the portion where the second layer 52 is disposed), the first internal electrode 18a3 and the second internal electrode 18b2. The portion where the thickness of the internal electrode 18b3 is locally thick (the portion where the second layer 42 and the third layer 44 are disposed) is designed to have a stepped dome shape having a thick stepped shape. See Figure 10).

  Alternatively, the dome shape shown in FIG. 11 includes the first internal electrode 18a and the second internal electrode 18b in the central portion in the stacking direction x connecting the first main surface 14a and the second main surface 14b of the stacked body 14. When the first internal electrode 18a2, the first internal electrode 18a3, the second internal electrode 18b2, and the second internal electrode 18b3 are viewed in plan, the counter electrode portion 22a faces the center of the counter electrode portion 22a. As approaching, the first internal electrode 18a2 and the second internal electrode 18b2 are locally thick (the portion where the second layer 52 is disposed), the first internal electrode 18a3 and the second internal electrode The portion where the thickness of 18b3 is locally thick (the portion where the second layer 42 and the third layer 44 are disposed) is designed to have a smooth dome shape in which the thickness is gradually increased.

  Then, the staircase dome shape in which the thickness is increased stepwise is more preferable than the smooth dome shape in which the thickness is gradually increased. In the case of a smooth dome shape in which the thickness is gradually increased, as shown in FIG. 11, the thickest portion at the center becomes steep, the concentration of the electric field E2 tends to increase, and there is a problem of causing deterioration due to the electric field E2. Easy to do. On the other hand, in the case of a staircase dome shape that is thicker in a staircase shape, the thickest part at the center is flat, and the effect of relaxing the concentration of the electric field E1 can be obtained. In addition, although the staircase shape is not particularly limited, it is preferable that the step is formed in a rectangular shape or a circular shape.

  A region in which the first internal electrode 18a and the second internal electrode 18b are locally thick in the multilayer body 14 is designed as shown in FIG. That is, in the first end surface 14e and the second end surface 14f facing each other of the stacked body 14, four corners on the first end surface 14e side and four corners on the second end surface 14f side are connected. The intersection point of the (longest) diagonal is defined as a center point C.

  Specifically, a diagonal line (indicated by a two-dot chain line in FIG. 12) connecting the corner portion 80a of the first end face 14e and the corner portion 82c of the second end face 14f is L1, and The diagonal connecting the corner 80b of the first end face 14e and the corner 82d of the second end face 14f is L2, and the diagonal connecting the corner 80c of the first end face 14e and the corner 82a of the second end face 14f. Is L3, and the diagonal line connecting the corner part 80d of the first end face 14e and the corner part 82b of the second end face 14f is L4, the center point is the intersection of the diagonal line L1, the diagonal line L2, the diagonal line L3, and the diagonal line L4. C.

A point at a position of 20% or more and 80% or less of the distance from the center point C toward the corner 80a is defined as a vertex 92a, and 20% or more and 80% or less of the distance from the center point C toward the corner 80b. A point at a position is a vertex 92b, a point at a position that is 20% to 80% of the distance from the center point C to the corner 80c is a vertex 92c, and a distance 20 from the center point C to the corner 80d is 20%. A point at a position not less than 80% and not more than 80% is a vertex 92d, and a point at a position not less than 20% and not more than 80% of the distance from the center point C toward the corner 82a is a vertex 94a. A point at a position 20% or more and 80% or less of the distance to 82b is a vertex 94b, and a point at a position 20% or more and 80% or less of the distance from the center point C to the corner 82c is a vertex 94c. Corner point 82 from center point C The apex 94d toward to a distance of 20% to 80% of the points of location of the.
The first internal electrode 18a and the second internal electrode 18a and the second internal electrode 18a are formed in a rectangular parallelepiped 90 formed by connecting the eight vertices 92a, 92b, 92c, 92d, 94a, 94b, 94c, and 92d. A portion where the thickness of the internal electrode 18b is locally thick is provided. If the distance from the center point C to each of the corners 80a to 82d is set to less than 20%, the size of the rectangular parallelepiped 90 becomes too small, and the increase in the volume of the internal electrode 18 is reduced, and the heat dissipation characteristics are reduced. The improvement effect is not recognized. On the other hand, if the distance from the center point C toward each of the corners 80a to 82d is set to be more than 80%, the amount of the material used for the internal electrode 18 increases and the manufacturing cost increases. The ends of the internal electrodes 18 are preferably rounded.

External electrodes 24 are disposed on the first end face 14 e side and the second end face 14 f side of the multilayer body 14. The external electrode 24 includes a first external electrode 24a and a second external electrode 24b.
The first external electrode 24a is disposed on the surface of the first end surface 14e of the multilayer body 14, and extends from the first end surface 14e to form the first main surface 14a, the second main surface 14b, and the first side surface. 14c and second side surface 14d are formed so as to cover each part. In this case, the first external electrode 24a is electrically connected to the first extraction electrode 20a of the first internal electrode 18a.
The second external electrode 24b is disposed on the surface of the second end face 14f of the stacked body 14, and extends from the second end face 14f to the first main face 14a, the second main face 14b, and the first side face. 14c and second side surface 14d are formed so as to cover each part. In this case, the second external electrode 24b is electrically connected to the second extraction electrode 20b of the second internal electrode 18b.

  In the stacked body 14, the first internal electrode 18 a and the second internal electrode 18 b are opposed to each other through the dielectric layer 16 in each counter electrode portion 22 a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 24a to which the first internal electrode 18a is connected and the second external electrode 24b to which the second internal electrode 18b is connected.

  As shown in FIG. 2, the first external electrode 24a includes a first base electrode layer 28a and a first plating layer 30a disposed on the surface of the first base electrode layer 28a in this order from the stacked body 14 side. Have Similarly, the second external electrode 24b includes a second base electrode layer 28b and a second plating layer 30b disposed on the surface of the second base electrode layer 28b in this order from the stacked body 14 side.

The first base electrode layer 28a is disposed on the surface of the first end face 14e of the multilayer body 14, and extends from the first end face 14e to form the first main surface 14a, the second main surface 14b, and the first main surface 14e. It is formed so as to cover a part of each of the side surface 14c and the second side surface 14d. However, the first base electrode layer 28 a may be disposed only on the surface of the first end surface 14 e of the multilayer body 14.
Further, the second base electrode layer 28b is disposed on the surface of the second end face 14f of the multilayer body 14, and extends from the second end face 14f so as to extend from the first main face 14a, the second main face 14b, and the second main face 14b. The first side surface 14c and the second side surface 14d are formed so as to cover a part thereof. However, the second base electrode layer 28 b may be disposed only on the surface of the second end face 14 f of the multilayer body 14.

Each of the first base electrode layer 28a and the second base electrode layer 28b includes at least one selected from a baking layer, a resin layer, a thin film layer, and the like. Here, the first base electrode formed of the baking layer is used. The electrode layer 28a and the second base electrode layer 28b will be described.
The baking layer includes glass and metal. Examples of the metal of the baking layer include at least one selected from Cu, Ni, Ag, Pb, an Ag—Pb alloy, Au, and the like. Moreover, as a glass of a baking layer, at least 1 chosen from B, Si, Ba, Mg, Al, Li etc. is included. The baking layer may be a plurality of layers. The baking layer is obtained by applying a conductive paste containing glass and metal to the laminated body 14 and baking it. The baking layer may be fired at the same time as the dielectric layer 16 and the internal electrode 18, and the dielectric layer 16 and the internal electrode 18. It may be baked after firing. The thickness of the thickest part in the baking layer is preferably 10 μm or more and 50 μm or less.

A resin layer containing conductive particles and a thermosetting resin may be formed on the surface of the baking layer. The resin layer may be directly formed on the laminate 14 without forming a baking layer. The resin layer may be a plurality of layers. The thickness of the thickest portion of the resin layer is preferably 10 μm or more and 150 μm or less.
Further, the thin film layer is a layer of 1 μm or less formed by a thin film forming method such as a sputtering method or a vapor deposition method and deposited with metal particles.

The first plating layer 30a is disposed so as to cover the first base electrode layer 28a. Specifically, the first plating layer 30a is disposed on the first end surface 14e on the surface of the first base electrode layer 28a, and the first main surface 14a and the first main surface 14a on the surface of the first base electrode layer 28a. It is preferable that the second main surface 14b and the first side surface 14c and the second side surface 14d are provided. When the first base electrode layer 28a is disposed only on the surface of the first end face 14e of the multilayer body 14, the first plating layer 30a is only the surface of the first base electrode layer 28a. As long as it is provided so as to cover.
Similarly, the second plating layer 30b is disposed so as to cover the second base electrode layer 28b. Specifically, the second plating layer 30b is disposed on the second end face 14f of the surface of the second base electrode layer 28b, and the first main surface 14a and the first main surface 14a of the surface of the second base electrode layer 28b. It is preferable that the second main surface 14b and the first side surface 14c and the second side surface 14d are provided. When the second base electrode layer 28b is disposed only on the surface of the second end face 14f of the stacked body 14, the second plating layer 30b is formed only on the surface of the second base electrode layer 28b. As long as it is provided so as to cover.

Further, as the first plating layer 30a and the second plating layer 30b (hereinafter also simply referred to as a plating layer), for example, at least selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like. One kind of metal or an alloy containing the metal is used.
The plating layer may be formed of a plurality of layers. In this case, the plating layer preferably has a two-layer structure of a Ni plating layer and a Sn plating layer. By providing the Ni plating layer so as to cover the surface of the base electrode layer, the base electrode layer can be prevented from being eroded by the solder when the multilayer ceramic capacitor 10 is mounted on the circuit board. Further, by providing the Sn plating layer on the surface of the Ni plating layer, when mounting the multilayer ceramic capacitor, the wettability of the solder used for mounting can be improved and mounting can be easily performed.

  The thickness per plating layer is preferably 1 μm or more and 15 μm or less. Moreover, it is preferable that a plating layer does not contain glass. Further, the plating layer preferably has a metal ratio per unit volume of 99% by volume or more.

Next, a case where the first base electrode layer 28a and the second base electrode layer 28b are made of plating electrodes will be described. The first base electrode layer 28a is composed of a plating layer that is directly connected to the internal electrode 18, and is disposed directly on the surface of the first end face 14e of the multilayer body 14, and extends from the first end face 14e and extends to the first end face 14e. The first main surface 14a, the second main surface 14b, the first side surface 14c, and the second side surface 14d are formed so as to cover a part thereof.
The second base electrode layer 28b is composed of a plating layer that is directly connected to the internal electrode 18, and is disposed directly on the surface of the second end face 14f of the multilayer body 14 and extends from the second end face 14f. The first main surface 14a, the second main surface 14b, the first side surface 14c, and the second side surface 14d are formed so as to cover a part thereof.
However, in order for the first base electrode layer 28a and the second base electrode layer 28b to be composed of plating layers, a catalyst is provided on the laminate 14 as a pretreatment.

  The first base electrode layer 28a made of a plating layer is preferably covered with the first plating layer 30a. Similarly, the second base electrode layer 28b made of a plating layer is preferably covered with the second plating layer 30b.

The first base electrode layer 28a, the second base electrode layer 28b, the first plating layer 30a, and the second plating layer are, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc. It is preferable to include plating of at least one metal selected from or an alloy containing the metal.
For example, when Ni is used as the internal electrode 18, it is preferable to use Cu having good bonding properties with Ni as the first base electrode layer 28a and the second base electrode layer 28b.
Moreover, it is preferable to use Sn or Au with good solder wettability as the first plating layer 30a and the second plating layer 30b. As the first base electrode layer 28a and the second base electrode layer 28b, Ni having solder barrier performance is preferably used.

  The first plating layer 30a and the second plating layer 30b are formed as needed, and the first external electrode 24a is composed of only the first base electrode layer 28a, and the second external electrode 24b. May be composed of only the second base electrode layer 28b. The first plating layer 30a and the second plating layer 30b may be provided as the outermost layers of the first external electrode 24a and the second external electrode 24b, and the first plating layer 30a or the second plating layer may be provided. Another plating layer may be provided on the layer 30b.

  The thickness per plating layer is preferably 1 μm or more and 15 μm or less. Moreover, it is preferable that a plating layer does not contain glass. Further, the plating layer preferably has a metal ratio per unit volume of 99% by volume or more.

The multilayer ceramic capacitor 10 including the multilayer body 14, the first external electrode 24a, and the second external electrode 24b has a dimension L in the length direction z, and the multilayer body 14, the first external electrode 24a, and the second external electrode. The dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the electrode 24b is T, and the dimension in the width direction y of the multilayer ceramic capacitor 10 including the multilayer body 14, the first external electrode 24a and the second external electrode 24b is W. Dimension.
The dimension of the multilayer ceramic capacitor 10 is not particularly limited, but the L dimension in the length direction z is 3.2 mm or more and 5.7 mm or less, the W dimension in the width direction y is 1.6 mm or more and 5.0 mm or less, and T dimension is 0.8 mm or more and 3.0 mm or less. Note that the L dimension in the length direction z is not necessarily longer than the W dimension in the width direction y. The dimensions of the multilayer ceramic capacitor 10 can be measured with a microscope.

  In the multilayer ceramic capacitor 10 having the above structure, the thickness of the internal electrode is adjusted to be thick in the central portion where the heat generation of the multilayer body 14 is likely to occur, and the first internal electrode 18a and the second internal electrode in the central portion of the multilayer body 14 are adjusted. In the counter electrode portion 22a of 18b, a portion where the first internal electrode 18a and the second internal electrode 18b are thick is provided. Thereby, in addition to being able to reduce the resistance of the first internal electrode 18a and the second internal electrode 18b, the volume of the first internal electrode 18a and the second internal electrode 18b having higher thermal conductivity than ceramic. Therefore, the heat dissipation characteristics can be improved. Therefore, the heat generation of the multilayer ceramic capacitor 10 can be reduced.

  Further, in the present invention, by increasing the thickness of the internal electrode 18 only in the central portion where the multilayer ceramic capacitor 10 is likely to generate heat, the temperature rise in the central portion is reduced, and the temperature gradient from the central portion toward the edge is reduced. The amount of heat generation can be reduced as much as possible, and a reduction in heat generation can be realized with a small temperature gradient. As a result, the calorific value of the multilayer ceramic capacitor 10 can be reduced while maintaining the material composition, and the degree of freedom in design can be ensured. In addition, since the thickness of the internal electrode 18 can be increased only in a necessary portion, the amount of use of the internal electrode 18 is optimized, and the problem of cost increase can be avoided.

2. Next, an embodiment of a method for manufacturing a multilayer ceramic capacitor 10 having the above configuration will be described.

  First, a dielectric green sheet, an internal electrode conductive paste for forming the internal electrode 18 and an external electrode conductive paste for forming the external electrode 24 are prepared. The dielectric green sheet, the internal electrode conductive paste, and the external electrode conductive paste include an organic binder and a solvent, and a known organic binder or organic solvent can be used.

  Then, the internal electrode conductive paste is printed in a predetermined pattern on the dielectric green sheet by an ink jet printing method, and the pattern of the internal electrode 18 is formed on the dielectric green sheet. In addition, about the thick part of the pattern of the internal electrode 18, it forms by multiple times of inkjet printing. Alternatively, it is formed by a single application of ink jet printing while controlling the amount of ink. In the present embodiment, the thick part of the pattern of the internal electrode 18 is formed by multiple coating.

  Specifically, as shown in FIGS. 4 and 5, the pattern of the first internal electrode 18a3 and the pattern of the second internal electrode 18b3 having a three-layer structure are formed by three times of ink jet printing. The coating thickness of each first layer 40 of the pattern of the first internal electrode 18a3 and the pattern of the second internal electrode 18b3 is preferably 0.3 μm or more and 1.0 μm or less. The coating thickness of each second layer 42 of the pattern of the first internal electrode 18a3 and the pattern of the second internal electrode 18b3 is preferably 0.3 μm or more and 1.0 μm or less. The coating thickness of each third layer 44 of the pattern of the first internal electrode 18a3 and the pattern of the second internal electrode 18b3 is preferably 0.3 μm or more and 1.0 μm or less.

  Also, as shown in FIGS. 6 and 7, the pattern of the first internal electrode 18a2 and the pattern of the second internal electrode 18b2 having a two-layer structure are formed by two-time application of ink jet printing. The coating thickness of each first layer 50 of the pattern of the first internal electrode 18a2 and the pattern of the second internal electrode 18b2 is preferably 0.5 μm or more and 1.0 μm or less. The coating thickness of each second layer 52 in the pattern of the first internal electrode 18a2 and the pattern of the second internal electrode 18b2 is preferably 0.5 μm or more and 1.0 μm or less.

  Further, as shown in FIGS. 8 and 9, the pattern of the first internal electrode 18a1 and the pattern of the second internal electrode 18b1 having a single-layer structure are formed by a single application of ink jet printing. The coating thickness of each first layer 60 of the pattern of the first internal electrode 18a1 and the pattern of the second internal electrode 18b1 is preferably 0.5 μm or more and 1.0 μm or less.

  Next, a predetermined number of dielectric green sheets for outer layers on which no internal electrode patterns are printed are laminated, and dielectric green sheets on which internal electrode patterns are printed are sequentially laminated on the dielectric green sheets for outer layers. A predetermined number of green body sheets are laminated to produce a laminated sheet.

Specifically, first, a predetermined number of outer-layer dielectric green sheets on which no internal electrode pattern is printed are stacked. Next, the dielectric green sheet on which the pattern of the first internal electrode 18a1 having the single-layer structure shown in FIGS. 8 and 9 is formed and the dielectric green sheet on which the pattern of the second internal electrode 18b1 is formed are alternately arranged. A predetermined number of sheets are stacked.
Next, the dielectric green sheet on which the pattern of the first internal electrode 18a2 having the two-layer structure shown in FIGS. 6 and 7 is formed and the dielectric green sheet on which the pattern of the second internal electrode 18b2 is formed are alternately arranged. A predetermined number of sheets are stacked.
Next, the dielectric green sheet on which the pattern of the first internal electrode 18a3 having the three-layer structure shown in FIGS. 4 and 5 is formed and the dielectric green sheet on which the pattern of the second internal electrode 18b3 is formed are alternately arranged. A predetermined number of sheets are stacked.
Next, again, the dielectric green sheet on which the pattern of the first internal electrode 18a2 having the two-layer structure shown in FIGS. 6 and 7 is formed and the dielectric green sheet on which the pattern of the second internal electrode 18b2 is formed are shown. A predetermined number of sheets are alternately stacked.
Next, again, the dielectric green sheet on which the pattern of the first internal electrode 18a3 having the three-layer structure shown in FIGS. 8 and 9 is formed and the dielectric green sheet on which the pattern of the second internal electrode 18b3 is formed are shown. A predetermined number of sheets are alternately stacked.
Finally, a predetermined number of outer-layer dielectric green sheets on which no internal electrode pattern is printed are laminated to produce a dielectric sheet.

  Subsequently, the laminate sheet is pressed in the lamination direction x by means such as an isostatic press to produce a laminate block.

  Thereafter, the laminated body block is cut into a predetermined shape and a raw laminated body chip is cut out. At this time, the corners and ridges of the raw laminate may be rounded by barrel polishing or the like. Subsequently, the cut raw laminate chip is fired to produce a laminate 14. The firing temperature of the raw laminate chip depends on the ceramic material and the material of the internal electrode conductive paste, but is preferably 900 ° C. or higher and 1300 ° C. or lower.

  Next, in order to form the baking layer of the external electrode 24a, for example, an exposed portion of the first extraction electrode portion 20a of the first internal electrode 18a exposed on the surface of the multilayer body 14 from the first end surface 14e. The external electrode conductive paste is applied and baked on the second electrode. Similarly, in order to form a baked layer of the outer electrode 24b, for example, the second electrode 14b exposed from the second end face 14f of the stacked body 14 is exposed. An external electrode conductive paste is applied to the exposed portion of the second extraction electrode portion 20b of the internal electrode 18b and baked to form a baking layer. At this time, the baking temperature is preferably 700 ° C. or higher and 900 ° C. or lower. In addition, if necessary, one or more plating layers are formed on the surface of the baking layer, the external electrode 24 is formed, and the multilayer ceramic capacitor 10 is manufactured.

  In addition, instead of forming a baking layer as the external electrode 24, the first internal electrode exposed from the first end surface 14e is subjected to plating on the first end surface 14e side portion of the surface of the multilayer body 14 A base plating film is formed on the exposed portion of the first extraction electrode portion 20a of 18a, and similarly, a plating treatment is applied to the portion on the second end face 14f side of the surface of the multilayer body 14, and the second end face 14f. A base plating film may be formed on the exposed portion of the second extraction electrode portion 20b of the second internal electrode 18b exposed from the substrate.

  The plating process may be either electrolytic plating or electroless plating. However, electroless plating requires a pretreatment with a catalyst or the like in order to improve the plating deposition rate, and has the disadvantage that the process becomes complicated. is there. Therefore, it is usually preferable to employ electrolytic plating. As the plating method, barrel plating is preferably used.

In addition, when forming a part of conductor of the external electrode 24 on the surface of the first main surface 14a and the second main surface 14b of the laminate 14, a surface conductor pattern is previously formed on the outermost dielectric green sheet. It may be printed and fired at the same time as the laminated body 14, or may be baked after printing the surface conductors on the first main surface 14 a and the second main surface 14 b of the laminated body 14 after baking. Furthermore, if necessary, an upper plating layer is formed on the surface of the base plating film.
In this way, the plating electrode is formed directly on the first end surface 14e and the second end surface 14f of the laminate 14.

  As described above, the multilayer ceramic capacitor 10 shown in FIG. 1 is manufactured.

  According to the method for manufacturing a multilayer ceramic capacitor according to the present invention, when the multilayer ceramic capacitor 10 according to the present invention is manufactured, printing is performed by an inkjet printing method in order to form internal electrode patterns having different thicknesses. 10 can be efficiently manufactured.

  In addition, according to the method for manufacturing a multilayer ceramic capacitor according to the present invention, the multilayer ceramic capacitor 10 can be efficiently manufactured more efficiently by applying the thick internal electrode pattern by a single coating.

3. Experimental Example Next, a multilayer ceramic capacitor was produced and the surface heat generation distribution was evaluated.
The design of the example and the comparative example is as follows.

(A) Example In the example, the multilayer ceramic capacitor 10 of the present embodiment shown in FIGS. 1 to 9 was produced and evaluated.
-Length x width x height size (design value): 5.7 mm x 5.0 mm x 2.0 mm
-Dielectric (ceramic) material: BaTiO ₃
・ Capacitance: 180 nF
・ Rated voltage: 630V
Structure of external electrode 24 Underlying electrode layer: baked electrode containing conductive metal (Cu) and glass Plating layer: Two-layer structure of Ni plating layer and Sn plating layer Structure of internal electrode 18 Metal: Ni
The number of laminated dielectric sheets on which the first internal electrode 18a3 or the second internal electrode 18b3 having the three-layer structure is formed: 5 The first internal electrode 18a2 or the second internal electrode 18b2 having the two-layer structure is formed. The number of dielectric sheets stacked: 5 on the first main surface 14a side and 5 on the second main surface 14b side The first internal electrode 18a1 or the second internal electrode 18b1 having a one-layer structure was formed. Number of laminated dielectric sheets: 5 on the first main surface 14a side, 5 on the second main surface 14b side ・ Thickness of internal electrode 18 Internal electrode of three-layer structure: first layer 40 is 0.9 μm, The second layer 42 is 0.9 μm, and the third layer 44 is 0.9 μm
Two-layer internal electrode: the first layer 50 is 0.9 μm, the second layer 52 is 0.9 μm
Single-layer internal electrode: the first layer 60 is 0.9 μm

(B) Comparative Example In the comparative example, the conventional multilayer ceramic capacitor 100 shown in FIG. 13 was produced and evaluated.
-Length x width x height size (design value): 5.7 mm x 5.0 mm x 2.0 mm
-Dielectric (ceramic) material: BaTiO ₃
・ Capacitance: 180 nF
・ Rated voltage: 630V
Structure of external electrode 124 Base electrode layer: baked electrode containing conductive metal (Cu) and glass Plating layer: Two-layer structure of Ni plating layer and Sn plating layer Structure of internal electrode 118 Metal: Ni
The number of laminated dielectric sheets on which the first internal electrode 118a or the second internal electrode 118b having a single-layer structure is formed: 25. The thickness of the internal electrode 118: 0.9 μm

(C) Test method and results The heat dissipation test was performed as follows.
The substrate on which the produced multilayer ceramic capacitor is mounted is connected to a high frequency power source with a lead wire, a sine wave current is applied at 6 kHz at 300 kHz in a 25 ° C. no wind state, and the surface temperature distribution in a stable temperature state is obtained with a thermo viewer. It was measured.

  As a result, the multilayer ceramic capacitor 100 of the comparative example had a large difference of 3.5 ° C. between the outer peripheral portion having a low temperature and the central portion having a high temperature.

  On the other hand, in the multilayer ceramic capacitor 10 of the example, the thickness of the internal electrode is designed to be locally thick so that the heat generation at the high temperature center is low, so that the temperature difference between the outer periphery and the center is only 0. It was possible to make it as very small as 5 ° C.

  From the above results, in the multilayer ceramic capacitor according to the present invention, the thickness of the internal electrode in each part is adjusted to be thick in the central portion where heat generation is likely to occur, and the first internal electrode and the second internal electrode in the central portion of the multilayer body are adjusted. In addition to being able to reduce the resistance of the internal electrode by providing a thick part in the electrode, it is possible to increase the volume of the internal electrode, which has a higher thermal conductivity than ceramic, and to improve heat dissipation characteristics Was confirmed. Therefore, it was confirmed that the heat generation of the multilayer ceramic capacitor can be reduced.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is carried out within the range of the summary. Further, the thickness, the number of layers, the counter electrode area, and the external dimensions of the dielectric layers of the electronic component main body are not limited thereto.

DESCRIPTION OF SYMBOLS 10 Multilayer ceramic capacitor 14 Laminated body 14a 1st main surface 14b 2nd main surface 14c 1st side surface 14d 2nd side surface 14e 1st end surface 14f 2nd end surface 16 Dielectric layer 16a Outer layer part 16b Inner layer part 18 Internal electrode layer 18a, 18a3, 18a2, 18a1 First internal electrode 18b, 18b3, 18b2, 18b1 Second internal electrode 20a First extraction electrode portion 20b Second extraction electrode portion 22a Counter electrode portion 22b Side portion (W gap)
22c End (L gap)
24 external electrode 24a first external electrode 24b second external electrode 28a, 28b ground electrode layer 30a, 30b plating layer 40, 50, 60 first layer 42, 52 second layer 44 third layer 80a, 80b, 80c, 80d Corner portion 82a, 82b, 82c, 82d Corner portion L1 Diagonal line connecting corner portion 80a and corner portion 82c L2 Diagonal line connecting corner portion 80b and corner portion 82d L3 Diagonal line connecting corner portion 80c and corner portion 82a L4 Corner portion 80d and Diagonal line connecting corner portion 82b 90 cuboid 92a vertex (point at a position 20% to 80% of the distance from center point C to corner portion 80a)
92b vertex (point at a position 20% to 80% of the distance from the center point C to the corner 80b)
92c vertex (point of 20% to 80% of the distance from the center point C to the corner 80c)
92d vertex (point at a position 20% to 80% of the distance from the center point C to the corner 80d)
94a vertex (point of 20% to 80% of the distance from the center point C to the corner 82a)
94b vertex (a point at a position 20% to 80% of the distance from the center point C to the corner 82b)
94c vertex (point of 20% to 80% of the distance from the center point C to the corner 82c)
94d vertex (point of 20% to 80% of the distance from the center point C to the corner 82d)
C Center point (intersection of diagonal line L1, diagonal line L2, diagonal line L3, and diagonal line L4)
x Stacking direction y Width direction z Length direction

Claims (7)

A plurality of dielectric layers stacked, the first main surface and the second main surface facing the stacking direction, the first side surface and the second side surface facing the width direction orthogonal to the stacking direction; A laminated body including a first end face and a second end face opposed to each other in a length direction orthogonal to the lamination direction and the width direction;
A first internal electrode disposed on the plurality of dielectric layers and exposing a first extraction electrode portion on the first end face;
A second internal electrode disposed on the plurality of dielectric layers and exposing a second lead electrode portion on the second end face;
A first external electrode connected to the first internal electrode and disposed on the first end face; and a second external electrode connected to the second internal electrode and disposed on the second end face. A multilayer ceramic capacitor having an external electrode,
In the counter electrode portion where the first internal electrode and the second internal electrode face each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body, the first internal The electrode and the second internal electrode have a thick portion;
A multilayer ceramic capacitor characterized by   The thicker portions of the first internal electrode and the second internal electrode become thicker as they approach the center of the central portion in the stacking direction connecting the first main surface and the second main surface of the stacked body. The multilayer ceramic capacitor according to claim 1, wherein:   In the counter electrode portion where the first internal electrode and the second internal electrode face each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body, the first internal When the electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode become thicker as they approach the center of the counter electrode portion. The multilayer ceramic capacitor according to claim 1 or 2.   In the counter electrode portion where the first internal electrode and the second internal electrode face each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body, the first internal When the electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode gradually increase in thickness as they approach the center of the counter electrode portion. The multilayer ceramic capacitor according to claim 3, wherein the multilayer ceramic capacitor has a smooth dome shape.   In the counter electrode portion where the first internal electrode and the second internal electrode face each other in the central portion in the stacking direction connecting the first main surface and the second main surface of the multilayer body, the first internal When the electrode and the second internal electrode are viewed in plan, the thicker portions of the first internal electrode and the second internal electrode become thicker in a stepped manner as they approach the center of the counter electrode portion. The multilayer ceramic capacitor according to claim 3, wherein the multilayer ceramic capacitor is formed in a stepped dome shape. A method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 5,
The method of manufacturing a multilayer ceramic capacitor, wherein the first internal electrode and the second internal electrode are printed by an ink jet printing method, and the thickness of the thick part is controlled.   The method for manufacturing a multilayer ceramic capacitor according to claim 6, wherein the thickness of the thick portion is controlled by a single coating.

Images