JP2019003313A - Fail-safe circuit - Google Patents

Abstract

To achieve a fail-safe circuit capable of withstanding against vibration and shock, and of being downsized.SOLUTION: A fail-safe circuit 1 includes: a pulse monitoring circuit 4 which includes a semiconductor integrated circuit and which monitors an input of a pulse signal that is output by a programmable controller 100; a pulse normality detecting relay 5 that changes to an OFF state when an abnormality occurs in the input of the pulse signal; a contact 7 for the pulse normality detecting relay which becomes an OFF state when the pulse normality detecting relay 5 is in the OFF state; a normality detecting relay 6 that becomes an OFF state when the contact 7 is in the OFF state; and a contact 9 for the normality detecting relay which is connected in series to an external load 8 connected to the programmable controller 100, becomes an OFF state when the normality detecting relay 6 is in the OFF state, and cuts off a power supply from an external power source to the external load 8.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a fail safe circuit, and more particularly to a fail safe circuit of a programmable controller.

  When an abnormality occurs in the programmable controller, it is necessary to perform control such as stopping or opening / closing the apparatus in order to switch the external load to a safe operation direction so as not to adversely affect the system.

  As a conventional abnormality detection method for a programmable controller, a method for determining normality / abnormality of a programmable controller by outputting a pulse signal having a constant period from a CPU and monitoring the pulse signal has been proposed. This pulse is output at a fixed period when normal, and is stopped when abnormal, so the pulse on or off time is monitored by the off-delay timer and on-delay timer, respectively. When it does not change for a certain period of time, it is determined that the programmable controller is abnormal (see, for example, Patent Document 1).

Japanese Patent No. 3435274

  As described above, the conventional fail-safe circuit described in Patent Document 1 uses an on-delay timer and an off-delay timer, which are important components for switching an external load in a safe operating direction. However, since the signal output section of the on-delay timer and off-delay timer is composed of mechanical contacts, it has the characteristic of being vulnerable to vibration and impact, and is affected by vibration and impact during transportation and earthquakes. There is also a possibility of causing a malfunction. In addition, the structure with built-in mechanical contacts has a short mechanical and electrical life, and because the parts themselves are large, it is difficult to reduce the size of the device that houses the circuit. There were various issues above.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a fail-safe circuit that is resistant to vibration and impact and can be downsized.

  The present invention is a fail-safe circuit that is connected to a programmable controller that outputs a pulse signal at a constant cycle and monitors normality / abnormality of the programmable controller, and is constituted by a semiconductor integrated circuit, and the pulse signal output by the programmable controller Is connected to the pulse monitoring circuit and the pulse monitoring circuit detects that an abnormality has occurred in the input of the pulse signal. A pulse normal detection relay that switches from an on state to an off state, and the pulse normal detection relay that is on when the pulse normal detection relay is on and is off when the pulse normal detection relay is off Connected in series with the contact of the pulse normal detection relay Connected to the programmable controller, which is in the on state when the contact of the pulse normal detection relay is on, and is in the off state when the contact of the pulse normal detection relay is off. Is connected in series to the external load, is turned on when the normal detection relay is on, and is connected to the external power source, and is off when the normal detection relay is off. It is a fail safe circuit provided with the contact of the said normal detection relay which interrupts | blocks the power supply from the said external power supply with respect to the said external load.

  In the fail-safe circuit according to the present invention, since the pulse monitoring circuit is constituted by a semiconductor integrated circuit, it is more resistant to vibrations and shocks and can be reduced in size than the case where it is constituted by a conventional mechanical contact. is there.

It is a block diagram which shows the structure of the fail safe circuit which concerns on Embodiment 1 of this invention. It is a timing chart which shows operation | movement of the fail safe circuit which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the fail safe circuit which concerns on Embodiment 2 of this invention. It is a timing chart which shows operation | movement of the fail safe circuit which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the fail safe circuit which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the fail safe circuit which concerns on Embodiment 4 of this invention.

Embodiment 1 FIG.
Hereinafter, a fail-safe circuit according to Embodiment 1 of the present invention will be described with reference to FIG. 1 and FIG. FIG. 1 is a block diagram showing a configuration of a fail-safe circuit according to the first embodiment.

  As shown in FIG. 1, the fail safe circuit 1 is connected to a programmable controller 100. The fail-safe circuit 1 performs a fail-safe operation for cutting off the power supply from the external power supply apparatus 10B to the external load 8 connected to the programmable controller 100 when an abnormality occurs in the programmable controller 100.

  As shown in FIG. 1, the programmable controller 100 includes a CPU 2 and output units 3A and 3B.

  The fail safe circuit 1 is connected to the output unit 3A via the Y00 terminal. Further, an external load 8 is connected to the output unit 3B via a Y10 terminal.

  In the fail safe circuit 1, a pulse monitoring circuit 4, a pulse normal detection relay 5, a normal detection relay 6, a contact 7 of the pulse normal detection relay 5, and a contact 9 of the normal detection relay 6 are provided. .

  The fail safe circuit 1 is connected to an external power supply device 10A, and the fail safe circuit 1 is driven by power from the external power supply device 10A. An external power supply device 10B is connected to the external load 8, and the external load 8 is driven by electric power from the external power supply device 10B.

  As shown in FIG. 1, the pulse monitoring circuit 4 is connected to the Y00 terminal of the output unit 3A. The pulse monitoring circuit 4 is composed of a semiconductor integrated circuit. The pulse monitoring circuit 4 receives the pulse signal output from the programmable controller 100 and outputs a response pulse signal after a predetermined time (t) has elapsed since the pulse signal was input. A pulse normality detection relay 5 is connected in series downstream of the pulse monitoring circuit 4. The pulse normality detection relay 5 switches from the on state to the off state when the response pulse output from the pulse monitoring circuit 4 is not input even if it exceeds a certain time (t).

  Further, a normal detection relay 6 is connected in parallel to the pulse normal detection relay 5. The contact point 7 of the pulse normality detection relay 5 is connected in series before the normality detection relay 6. The contact 7 of the pulse normality detection relay 5 is connected to 0V of the output unit 3A.

  The external load 8 is connected to the Y10 terminal of the output unit 3B. Further, the contact 9 of the normal detection relay 6 is connected in series downstream of the external load 8.

  Next, the operation of the fail safe circuit according to the first embodiment will be described.

  When the programmable controller 100 is operating normally, a pulse signal is output from the programmable controller 100 at a constant cycle via the Y00 terminal of the output unit 3A under the control of the CPU 2 and input to the pulse monitoring circuit 4. On the other hand, the pulse signal stops when the programmable controller 100 is abnormal. The pulse monitoring circuit 4 monitors the input state of the pulse signal to determine whether the programmable controller 100 is normal or abnormal.

  This will be described with reference to the time chart of FIG.

  In FIG. 2, (1) shows the state of the pulse signal from the CPU 2, (2) shows the operation of the pulse normal detection relay 5, (3) shows the operation of the normal detection relay 6, and (4) shows the state of the external load 8. .

  In FIG. 2, when the pulse signal is normally output under the control of the CPU 2 ((1) -a in FIG. 2), the pulse normality detection relay 5 is turned on ((2) -a in FIG. 2). On the other hand, if any abnormality occurs in the programmable controller 100 and the pulse signal is stopped ((1) -b in FIG. 2), the pulse is normal after a predetermined time (t) has elapsed from the rising timing of the last output pulse signal. The detection relay 5 is turned off ((2) -b in FIG. 2). That is, the pulse normality detection relay 5 is turned off when the next pulse signal is not input from the pulse monitoring circuit 4 even after a predetermined time (t) has elapsed.

  Here, the pulse monitoring circuit 4 incorporates a one-shot IC (reference numeral 4a) as shown in FIG. The one-shot IC is composed of an IC (Integrated Circuit) that outputs one response pulse signal after a predetermined time (t) has elapsed when one pulse signal is input. Therefore, when the next pulse signal is input within a certain time (t) from the input of one pulse signal to the output of one response pulse signal, a further fixed time (t) from the time when the next pulse signal is input. It operates to output another response pulse signal after the passage. For this reason, when a continuous pulse signal is input, it is not output while the pulse signal is input. When the input of the pulse signal is stopped, a continuous response pulse signal is output after a certain time (t) has elapsed from that point. Will be. Therefore, the pulse normal detection relay 5 is switched to the OFF state when no response pulse signal is output even after a predetermined time (t) has elapsed from the pulse monitoring circuit 4, so that the input of the pulse signal can be performed. Monitoring is possible. Also, since the one-shot IC determines that there is a pulse input by looking at the rising operation of the pulse signal, it recognizes that the pulse signal has stopped, regardless of whether the pulse signal is on or off. After a predetermined time (t) has elapsed, the pulse normality detection relay 5 is switched to the off state.

  Further, the fixed time (t) from when the pulse signal is stopped until the pulse normality detection relay 5 is turned off is determined by the time constants of the resistor R (reference numeral 4b) and the capacitor C (reference numeral 4c) in the pulse monitoring circuit 4. Is done. Therefore, a predetermined time (t) is set in advance to a value that meets the circuit specifications. When the pulse normal detection relay 5 is turned off, the contact 7 of the pulse normal detection relay 5 is turned off, and the normal detection relay 6 is turned off ((3) in FIG. 2). In response to this, the contact 9 of the normal detection relay 6 connected to the external load 8 is opened, and the external load 8 can be forcibly turned off ((4) in FIG. 2).

  As described above, according to the first embodiment, the mechanical contact has a function equivalent to that of the on-delay timer / off-delay timer having a large outer dimension provided with the mechanical contact used in the conventional fail-safe circuit. It can be realized by a one-shot IC of a semiconductor integrated circuit having a small external dimension. Thereby, compared with the case where it comprises with the conventional mechanical contact, it is strong to a vibration and an impact, and size reduction is possible.

  Furthermore, by changing the pulse normal detection relay 5 and the normal detection relay 6 from a mechanical relay to a semiconductor relay, all the components can be made semiconductor, and a fail-safe circuit completely free of mechanical contacts is realized. Therefore, it is possible to obtain a fail-safe circuit that is strong against vibration and shock and can be further reduced in size.

  Although it has been described that the one-shot IC is used for the pulse monitoring circuit 4 that monitors the pulse signal, the present invention is not limited to this, and a circuit having the same function as the one-shot IC, such as an FPGA, may be used.

Embodiment 2. FIG.
In the first embodiment, a one-shot IC is used for the pulse monitoring circuit 4 and a certain time (t) from the pulse stop to the abnormality detection is set by the time constant of the resistor R and the capacitor C. Then, it is set as the structure which uses counter IC for the pulse monitoring circuit 4. FIG. Hereinafter, a fail-safe circuit according to Embodiment 2 of the present invention will be described with reference to FIGS. 3 and 4. FIG.

  FIG. 3 is a block diagram showing a configuration of a fail-safe circuit according to the second embodiment. As shown in FIG. 3, in the second embodiment, a counter IC (reference numeral 21) and a clock oscillator 22 are provided in the pulse monitoring circuit 4. The pulse monitoring circuit 4 is connected to a counter upper limit value setting DIP switch 11. Since other configurations are the same as those in the first embodiment, description thereof is omitted here.

  The clock oscillator 22 always outputs a clock signal. The counter IC counts the clock signal output from the clock oscillator 22. Similarly to the first embodiment, the CPU 2 outputs a pulse signal at a constant cycle via Y00 of the output unit 3A. When the counter IC receives a pulse signal from the CPU 2 while counting the clock signal from the clock oscillator 22, the counter IC uses the pulse signal as a count value reset signal. That is, when the programmable controller 100 is in a normal state and a pulse signal is output at a constant cycle, the count value is reset to 0 at the fixed cycle, and the clock signal count is restarted again.

  At this time, if an abnormality occurs in the CPU 2 and the pulse signal is stopped, the count value of the counter IC is not reset and thus continues to increase. When the count value reaches the counter upper limit value (threshold value) set by the counter upper limit value setting DIP switch 11, the pulse monitoring circuit 4 determines that the programmable controller 100 is abnormal, The normal detection relay 5 is switched from the on state to the off state.

  As described above, in the second embodiment, whether the programmable controller 100 is normal or abnormal is determined based on whether or not the count value of the counter IC built in the pulse monitoring circuit 4 reaches the counter upper limit value.

  This will be described with reference to the time chart of FIG.

  4, (1) is the clock signal from the clock oscillator 22, (2) is the count value of the counter IC 21, (3) is the state of the pulse signal from the CPU 2, (4) is the operation of the pulse normal detection relay 5, (5) shows the operation of the normal detection relay 6, and (6) shows the state of the external load 8.

  In FIG. 4, as shown in (1) and (2), the counter IC 21 counts the clock signal of the clock oscillator 22, but uses the rising operation of the pulse signal from the CPU 2 as the reset signal of the counter IC 21. Therefore, while the pulse signal is normally output ((3) -a in FIG. 4), the count value of the counter IC 21 is always reset at a constant period. It is reset to 0 ((2) -a in FIG. 4). At this time, the pulse normality detection relay 5 is always on ((4) -a in FIG. 4). Next, when the pulse signal is stopped due to an abnormality of the programmable controller 100 and the counter IC 21 is not reset by the rising edge of the pulse signal ((3) -b in FIG. 4), the counter IC 21 continues counting, and the counter upper limit value When the count value reaches the counter upper limit value set by the setting DIP switch 11 ((2) -b in FIG. 4), the count is increased, and the pulse normality detection relay 5 is turned off ((4)-in FIG. 4). b).

  At this time, since the count value of the counter IC 21 is reset by the rising operation of the pulse signal, the counter IC is not reset to the count value even if the pulse signal is stopped in either the on state or the off state. become.

  Further, the time (t) from the last reset to the count value of the counter IC 21 by the rising operation of the pulse signal until the pulse normality detection relay 5 is turned off can be arbitrarily set by the counter upper limit value setting dip switch 11. is there.

  For example, when the clock signal of the clock oscillator 22 is set to 50 ms cycle (20 Hz) and the pulse signal from the CPU 2 is set to 500 ms cycle (2 Hz), the count value of the counter IC 21 is reset at 10 counts. That is, the normal count value of the programmable controller 100 does not exceed 10 counts. Here, the counter upper limit value setting DIP switch 11 is set to “20”, for example. When the pulse signal from the CPU 2 stops, that is, when an abnormality occurs in the programmable controller 100, the counter IC 21 does not reset and continues counting, and when the count value reaches 20 counts, it is programmable. It is determined that the controller 100 is abnormal.

  The abnormality detection time at this time is 1 s (50 ms × 20 counts) from the last reset to the counter IC 21 by the pulse rising operation. The abnormality detection time can be changed by changing the set value of the counter upper limit value setting DIP switch 11. If the value is larger than 20, it can be longer than 1 s, and if it is smaller than 20, it can be shorter than 1 s.

  When the pulse normal detection relay 5 is turned off, the contact 7 of the pulse normal detection relay 5 is turned off, and the normal detection relay 6 is turned off ((5) in FIG. 4). In response to this, the contact 9 of the normal detection relay 6 connected to the external load 8 is opened, and the external load 8 can be forcibly turned off ((6) in FIG. 4).

  As described above, also in the second embodiment, the same effect as in the first embodiment can be obtained. Furthermore, in the second embodiment, the failure detection time can be changed by appropriately setting the count upper limit value of the counter upper limit value setting DIP switch 11 according to the programmable controller 100 to which the fail safe circuit is applied. A safe circuit can be configured.

  In the second embodiment, the counter IC is used as the pulse monitoring circuit 4 for monitoring the pulse. However, the present invention is not limited to this, and a circuit having the same function as the counter IC such as an FPGA is used. May be used. Further, as an example of a device for setting the counter upper limit value, the case where the counter upper limit value setting DIP switch 11 is used has been described as an example. However, as long as the counter upper limit value can be set, other configurations and The method may be used.

Embodiment 3 FIG.
In the first and second embodiments described above, a fail-safe circuit that is resistant to vibration and impact, can be reduced in size, and can change the abnormality detection time according to the system is realized by configuring the component parts with semiconductors. Described how to do. In the third embodiment, not only the normal monitoring function of the programmable controller but also the normal monitoring function of peripheral devices such as an external power supply device is mounted on the fail safe circuit, and a fail safe that can construct a more reliable system. The circuit will be described.

  FIG. 5 is a block diagram illustrating a configuration of a fail-safe circuit according to the third embodiment. As shown in FIG. 5, in the third embodiment, the contacts of the external power supply monitoring relay 12 and the external power supply monitoring relay 12 are different from the configuration of the fail safe circuit 1 of the first embodiment shown in FIG. 13, an external contact relay 14 and a contact 15 of the external contact relay 14 are added. In FIG. 5, an external power supply device 10 </ b> C and an external contact 16 are connected to the fail safe circuit 1. Since other configurations are the same as those of the first embodiment shown in FIG. 1, the description thereof is omitted here.

  The external power supply monitoring relay 12 is connected to the external power supply 10C used in the system. When the external power supply device 10C is normal, the external power supply device monitoring relay 12 operates to turn on the contact 13 of the external power supply device monitoring relay 12. On the other hand, when the external power supply device 10C is abnormal, the external power supply device monitoring relay 12 does not operate, so the contact 13 of the external power supply device monitoring relay 12 is turned off.

  In addition, an external contact relay 14 is mounted so that a signal can be input by a non-voltage external contact 16 indicating normality / abnormality of an external connection device such as a sensor. The external contact relay 14 is connected to the external contact 16 in series. When an external connection device such as a sensor is operating normally, when the external contact 16 is turned on, the external contact relay 14 is operated, and the contact 15 of the external contact relay 14 is turned on. On the other hand, when an external connection device such as a sensor is abnormal, the external contact 16 is turned off and the external contact relay 14 does not operate, so the contact 15 of the external contact relay 14 is turned off.

  As shown in FIG. 5, the contact 13 of the external power supply monitoring relay 12, the contact 15 of the external contact relay 14, and the contact 7 of the pulse normal detection relay 5 are connected in series to the normal detection relay 6. ing. Therefore, the contact 13 of the external power supply monitoring relay 12, the contact 15 of the external contact relay 14, and the contact 7 of the pulse normal detection relay 5 operate the normal detection relay 6 under AND conditions. Either the stop of the pulse signal due to an abnormality of the controller 100, the occurrence of an abnormality of the external power supply 10C, or the input of the external contact 16 is turned off, the normal detection relay 6 is turned off, and the normal detection relay 6 connected to the external load 8 is turned off. The contact 9 is turned off.

  As described above, also in the third embodiment, the same effect as in the first and second embodiments can be obtained. Furthermore, in the third embodiment, the external power supply monitoring relay 12 and the external power supply monitoring relay contact 12 for detecting the occurrence of an abnormality in the external power supply 10C are provided. Even when an abnormality occurs, adverse effects on the process can be minimized. Furthermore, in the third embodiment, the external contact relay 14 for detecting the occurrence of an abnormality in the input to the external contact 16 and the contact 15 of the external contact relay 14 are provided. Even when an abnormality occurs, adverse effects on the process can be minimized.

  The abnormality detection function of the conventional fail-safe circuit described in Patent Literature 1 and the like is only monitoring the pulse signal output from the programmable controller, and the abnormality detection function of the peripheral device is not mounted, so the programmable controller is used. In order to detect abnormalities in the entire system, it is necessary to add a detection circuit corresponding to each.

  On the other hand, according to the fail-safe circuit according to the third embodiment, not only normal monitoring of the programmable controller 100 but also normal monitoring of peripheral devices such as external power supply devices and external connection devices can be performed. A high system can be constructed.

  In order to simplify the description, in the above description, the connection of the external power supply device and the connection of the external contact input are each described as only one circuit, but a plurality of circuits may be used as necessary. In FIG. 5, the pulse monitoring circuit 4 is described as the circuit configuration of the one-shot IC described in the first embodiment, but the circuit configuration of the counter IC described in the second embodiment is also possible. Any other circuit may be used as long as it has a function similar to that of these ICs, such as an FPGA.

Embodiment 4 FIG.
In the third embodiment described above, it is described that the normal monitoring function of peripheral devices is mounted in addition to the configurations of the first and second embodiments. However, in the fourth embodiment, enable / disable of each monitoring function is set. A fail-safe circuit that can be applied to any system is described.

  FIG. 6 is a block diagram illustrating a configuration of a fail-safe circuit according to the fourth embodiment. As shown in FIG. 6, the fourth embodiment is different from the configuration of the fail safe circuit 1 of the third embodiment shown in FIG. The valid / invalid setting switch 18, the valid / invalid setting switch 19 for the external contact monitoring function, and the valid / invalid setting switch 20 for all the monitoring functions are added.

  The pulse monitoring function valid / invalid setting switch 17 is connected in parallel to the contact 7 of the pulse normality detection relay 5. When the pulse monitoring function valid / invalid setting switch 17 is on, the pulse monitoring function is invalid. On the other hand, when the pulse monitoring function valid / invalid setting switch 17 is off, the pulse monitoring function is valid. Explaining the principle, when the pulse monitoring function valid / invalid setting switch 17 is on, the contact 7 of the pulse normality detection relay 5 is forcibly short-circuited, regardless of whether the programmable controller 100 is normal or abnormal. The contact 7 is always on, and the pulse monitoring function is disabled.

  The external power supply monitoring function valid / invalid setting switch 18 is connected in parallel to the contact 13 of the external power supply monitoring relay 12. When the external power supply monitoring function valid / invalid setting switch 18 is on, the monitoring function of the external power supply 10C is invalid, while when the external power supply monitoring function valid / invalid setting switch 18 is off, the external power supply monitoring function valid / invalid setting switch 18 The monitoring function of the power supply device 10C becomes effective. Since the principle is the same as the above principle, the description is omitted.

  The external contact monitoring function valid / invalid setting switch 19 is connected in parallel to the contact 15 of the external contact relay 14. When the external contact monitoring function valid / invalid setting switch 19 is on, the external contact 16 monitoring function is invalid. On the other hand, when the external contact monitoring function valid / invalid setting switch 19 is off, the external contact 16 The monitoring function is enabled. Since the principle is the same as the above principle, the description is omitted.

  The all monitoring function valid / invalid setting switch 20 includes a pulse monitoring function valid / invalid setting switch 17, an external power supply monitoring function valid / invalid setting switch 18, and an external contact monitoring function valid / invalid setting switch 19. On the other hand, they are connected in parallel. When the all monitoring function valid / invalid setting switch 20 is on, the pulse monitoring function, the monitoring function of the external power supply apparatus 10C, and the monitoring function of the external contact 16 are all disabled. On the other hand, when the valid / invalid setting switch 20 for all monitoring functions is off, the pulse monitoring function, the monitoring function of the external power supply device 10C, and the monitoring function of the external contact 16 are all enabled. Explaining the principle, since the contacts 20, 13, and 15 are short-circuited at once when the valid / invalid setting switch 20 for all monitoring functions is turned on, the normal detection relay 6 , It is always on and disables all the monitoring functions of the fail-safe circuit 1.

  Hereinafter, the operation of the fail-safe circuit 1 according to the fourth embodiment will be described.

  As described in the third embodiment, the normal detection relay 6 is an AND condition of the contact 7 of the pulse normal detection relay 5, the contact 13 of the external power supply device monitoring relay 12, and the contact 15 of the external contact relay 14. The normal detection relay 6 operates only when all of the contacts 7, 13, 15 are on, that is, when all the monitoring results are normal. In other words, when any one of the contacts 7, 13, 15 is off, that is, when any one of the monitoring results is abnormal, the normal detection relay 6 does not operate and is connected to the external load 8. The contact 9 is turned off and serves to minimize adverse effects on the plant. However, depending on the system, for example, even if an abnormality occurs in the external power supply 10C, the contact 9 is turned off when it is not desired to turn off the contact 9 or when an external device such as a sensor is removed for inspection or replacement. You may not want to In order to cope with these, in the fourth embodiment, switches 17 to 20 for setting each monitoring function to valid / invalid are provided.

  In FIG. 6, for example, a case where the contact 9 of the normal detection relay 6 is not desired to be turned off even if an abnormality occurs in the external power supply device 10C described above will be described. When an abnormality occurs in the external power supply apparatus 10C, in the normal operation, the external power supply apparatus monitoring relay 12 does not operate and the contact 13 of the external power supply apparatus monitoring relay 12 is turned off. At this time, regardless of whether the external power supply 10C is normal or abnormal, if the contact 13 of the external power supply monitoring relay 12 is kept on, the external power supply 10C is normal even if an abnormality occurs. The contact 9 of the detection relay 6 does not turn off. In order to realize this, the external power supply monitoring function valid / invalid setting switch 18 is connected in parallel to the contact 13 of the external power supply monitoring relay 12. When the monitoring function of the external power supply apparatus 10C is enabled, the external power supply monitoring function enable / disable setting switch 18 is turned off. When the monitoring function is disabled, the external power supply monitoring function is enabled. -Turn the invalid setting switch 18 on. When the external power supply monitoring function valid / invalid setting switch 18 is on, the contact 13 of the external power supply monitoring relay 12 is forcibly short-circuited. 13 is always on, and the external power supply monitoring function is disabled.

  The valid / invalid setting switch 17 of the pulse monitoring function and the valid / invalid setting switch 19 of the external contact monitoring function have the same configuration. By turning on these switches 17, 19, the contacts 7, 15 are forcibly set. Since it is short-circuited and always turned on, each monitoring function is disabled. In addition, since the valid / invalid setting switch 20 for all monitoring functions is turned on, the contacts 7, 13 and 15 are short-circuited together, so that the normal detection relay 6 is always turned on regardless of the monitoring results. All the monitoring functions of this fail-safe circuit can be disabled.

  The monitoring function valid / invalid setting switches 17 to 20 can be changed even during system operation by being installed at a position where the user can operate from the outside of the fail safe circuit 1.

  As described above, also in the fourth embodiment, the same effects as in the first, second, and third embodiments can be obtained. Further, in the fourth embodiment, the monitoring function valid / invalid setting switches 17 to 20 can be set to enable / disable each monitoring function, so that the application range is expanded, and inspection, replacement, etc. are temporarily performed. It is possible to configure a fail-safe circuit that can cope with a general monitoring function stoppage.

  In the above description, the setting of whether the monitoring function is valid / invalid is described as being performed by a switch operation. However, a method using an output of an external relay contact or a controller may be used.

  In FIG. 6, the pulse monitoring circuit 4 is described as the circuit configuration of the one-shot IC described in the first embodiment. However, the circuit configuration of the counter IC described in the second embodiment is also possible. Any other circuit may be used as long as it has a function similar to that of these ICs, such as an FPGA.

The external power supply device A, the external power supply device B, and the external power supply device C indicated by reference numerals 10A, 10B, and 10C are a fail-safe circuit drive power supply device, an external load drive power supply device, and devices used in the system, respectively. The power supply device for driving is shown. Since these are generally used with individual power supply devices, they are described as using individual power supply devices in the figure. However, it is possible to use the same power supply device depending on the specifications of the system to be applied, and even in this case, there is no problem in the operation of the fail-safe circuit.
Further, if the relay in the fail-safe circuit is used for both DC and AC, the power supply device can be used for either a DC power supply device or an AC power supply device, and the application range of the fail-safe circuit is expanded.

  1 Fail-safe circuit, 2 CPU, 3A Output unit A, 3B Output unit B, 4 Pulse monitoring circuit, 5 Pulse normal detection relay, 6 Normal detection relay, 7 contacts, 8 External load, 9 contacts, 10A External power supply device A, 10B External power supply device B, 10C External power supply device C, 11 Dip switch for counter upper limit value setting, 12 External power supply device monitoring relay, 13 contacts, 14 External contact relay, 15 contacts, 16 External contacts, 17 Pulse monitoring function Valid / invalid setting switch, 18 External power supply monitoring function valid / invalid setting switch, 19 External contact monitoring function valid / invalid setting switch, 20 All monitoring function valid / invalid setting switch, 21 Counter IC, 22 Clock oscillator.

Claims (10)

A fail-safe circuit that is connected to a programmable controller that outputs a pulse signal at a constant cycle and monitors the normality / abnormality of the programmable controller,
A pulse monitoring circuit configured by a semiconductor integrated circuit, to which the pulse signal output from the programmable controller is input, and to monitor normality / abnormality of the input of the pulse signal;
A pulse normal detection relay that is connected to the pulse monitoring circuit and switches from an on state to an off state when the pulse monitoring circuit detects that an abnormality has occurred in the input of the pulse signal;
A contact of the pulse normal detection relay that is in an on state when the pulse normal detection relay is in an on state and is in an off state when the pulse normal detection relay is in an off state;
It is connected in series with the contact of the pulse normal detection relay, is turned on when the contact of the pulse normal detection relay is on, and is turned off when the contact of the pulse normal detection relay is off. Normal detection relay,
When connected in series to an external load connected to the programmable controller, and when the normal detection relay is in an on state, it is in an on state to connect the external load to an external power source, and when the normal detection relay is in an off state And a contact point of the normality detection relay that shuts off the power supply from the external power source to the external load. The pulse monitoring circuit is composed of a circuit that receives the pulse signal output from the programmable controller and outputs a response pulse signal after a lapse of a certain time from the time when the pulse signal is input,
The pulse normality detection relay is switched from an on state to an off state when the response pulse signal output from the pulse monitoring circuit is not input after the lapse of the predetermined time.
The fail-safe circuit according to claim 1. The pulse monitoring circuit includes:
A clock oscillator for oscillating a clock signal;
The clock signal oscillated from the clock oscillator is counted, and when the pulse signal output from the programmable controller is input, the count value of the clock signal is reset, and the count value is not reset in advance. The fail-safe circuit according to claim 1, further comprising: a counter circuit that switches the normal pulse detection relay from an on state to an off state when a set threshold value is reached. The fail safe circuit according to claim 3, further comprising a threshold setting unit connected to the pulse monitoring circuit and configured to set the threshold. An external power supply monitoring relay that is connected to an external power supply, is turned on when the external power supply is normal, and is turned off when an abnormality occurs in the external power supply;
The external power supply monitoring connected in series to the normality detection relay, turned on when the external power supply monitoring relay is turned on, and turned off when the external power supply monitoring relay is turned off Relay contacts,
The failsafe circuit according to any one of claims 1 to 4, further comprising: An external contact relay that is connected to an external contact, and is turned on when the external contact is normal, and turned off when an abnormality occurs in the external contact;
A contact of the external contact relay, which is connected in series to the normality detection relay and is turned on when the external contact relay is turned on, and turned off when the external contact relay is turned off. The failsafe circuit according to any one of claims 1 to 5, further comprising: The pulse monitoring function valid / invalid setting switch further connected to the contact of the pulse normality detection relay in parallel, and short-circuits the contact of the pulse normality detection relay when turned on. The fail-safe circuit according to any one of the above. An external power supply monitoring function valid / invalid setting switch that is connected in parallel to the contact of the external power supply monitoring relay and that short-circuits the contact of the external power supply monitoring relay when in an on state. The fail-safe circuit according to claim 5. The external contact monitoring function valid / invalid setting switch, further connected to the contact of the external contact relay in parallel and short-circuiting the contact of the external contact relay when turned on. The fail-safe circuit described. An external power supply monitoring relay that is connected to an external power supply, is turned on when the external power supply is normal, and is turned off when an abnormality occurs in the external power supply;
The external power supply monitoring connected in series to the normality detection relay, turned on when the external power supply monitoring relay is turned on, and turned off when the external power supply monitoring relay is turned off Relay contacts,
An external contact relay that is connected to an external contact, and is turned on when the external contact is normal, and turned off when an abnormality occurs in the external contact;
A contact of the external contact relay, which is connected in series to the normality detection relay, is turned on when the external contact relay is on, and is turned off when the external contact relay is off;
The pulse normal detection relay is connected in parallel to the contact of the pulse normality detection relay, the contact of the external power supply device monitoring relay, and the contact of the external contact relay, and in the ON state. Further comprising a valid / invalid setting switch for all monitoring functions for short-circuiting all of the contacts, the contacts of the external power supply device monitoring relay, and the contacts of the external contact relay. The fail-safe circuit according to any one of the above.

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