JP2019003141A - Liquid crystal display device - Google Patents

Abstract

To drive a liquid crystal display device using LTPS (low temperature polycrystalline silicone) by using a driver IC having a function of resetting a pixel charge under an abnormal power-off condition.SOLUTION: A gate signal generation circuit for driving a gate signal line includes a shift register part comprising cascaded unit register circuits 52 in a plurality of stages. The unit register circuit 52 has an output circuit for controlling conduction/non-conduction between an input terminal CK for a clock signal and an output terminal OUT for an output pulse depending on the potential of a reference point P1 in the unit register circuit, a reference point set circuit for controlling conduction/non-conduction between a power source VGL and the reference point P1, and a reference point reset circuit for controlling conduction/non-conduction between the power source VGL and the reference point P1. The reference point reset circuit in all stages includes a switch SW7 that is turned into conductive by a reset pulse output by the driver IC before starting and after finishing a shift operation of the shift register part, so as to set the reference point P1 to the potential of the power source VGL.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a liquid crystal display device. In particular, the present invention relates to a liquid crystal display device using polysilicon as a semiconductor layer of a thin film transistor (TFT) formed on a substrate of a display panel.

  The liquid crystal display device is configured to include a liquid crystal panel including a TFT substrate and a counter substrate which are disposed to face each other, and a liquid crystal material sealed in a gap provided therebetween. In the TFT substrate, pixel circuits arranged in a matrix in the image display area are formed, and a drive circuit for driving the pixel circuits is provided in the outer area. The drive circuit may include a portion formed on the surface of the TFT substrate in the same manner as the pixel circuit, and an integrated circuit (IC) formed separately from the TFT substrate and mounted on or connected to the TFT substrate. For example, a gate signal generation circuit is formed using a TFT on the surface of a TFT substrate, and power and various control signals are supplied to the gate signal generation circuit from a driver IC. The semiconductor layer of the TFT is formed of amorphous silicon (a-Si) or polysilicon (polycrystalline silicon: p-Si). In particular, low-temperature polysilicon (LTPS) formed at a low temperature is used for p-Si laminated on the substrate of the display panel.

  The gate signal generation circuit includes a shift register in which a plurality of unit register circuits corresponding to gate signal lines are connected in cascade, and the plurality of unit register circuits operate in synchronization with a clock signal and output a pulse based on a pulse. A gate signal is sequentially supplied to the signal line to control writing of the video signal to the pixel circuit.

  FIG. 14 is a circuit diagram of the unit register circuit. When a high potential (H level) is applied to the set terminals IN1 and IN2, the reference point P1 is set to the H level. When a clock signal pulse is input to the clock terminal CK in this state, a pulse is output to the output terminal OUT. Is done. On the other hand, when an H level is applied to the reset terminals RST1 and RST2, the reference point P1 is reset to a low potential (L level). In this state, even if a clock signal pulse is input to the clock terminal CK, a pulse is applied to the output terminal OUT. Is not output. FIG. 14 shows a unit register circuit of a bidirectional shift register, which is provided with a set terminal and a reset terminal for each of the forward shift operation and the reverse shift operation. The other-stage output pulses input to IN1 and RST1 of the register circuit are used in the forward operation, while the other-stage output pulses input to IN2 and RST2 are used in the backward operation.

The driver IC supplies a power source used in the gate signal generation circuit from the system power source, specifically, a power source VGH having a predetermined high potential φ _H (for example, φ _H > 0) corresponding to the H level, and a predetermined level corresponding to the L level. A power supply VGL having a low potential φ _L (for example, φ _L <0) is generated.

  Here, when the system power supply is abnormally lowered (hereinafter referred to as power supply abnormally off), the driver IC sets all the voltage of the gate signal lines to a high potential (here, H level for convenience of explanation). Some have a function of turning on a pixel transistor of a pixel circuit and resetting a pixel charge written in a pixel electrode (a pixel charge reset function). With this function, it is possible to prevent an abnormal display from being made when the operation is resumed after the power is abnormally turned off. Specifically, the driver IC detects that the voltage of the system power supply has dropped to, for example, a certain threshold value, and supplies all the H level to the power supply line and the control signal line to the gate signal generation circuit. In this operation, the potential of the power supply VGL is also set to the H level. As a result, the entire unit register circuit becomes a high potential corresponding to the H level, and the potential of the terminal OUT also becomes the H level. As a result, an H level is output from the gate signal generation circuit to all the gate signal lines, the pixel transistors of all the pixels are turned on, the pixel electrode and the video signal line are in a conductive state, and the pixel charge is discharged from the pixel electrode. Is done.

JP 2001-159877 A

  The above-described pixel charge reset function is employed in a driver IC that controls a gate signal generation circuit of a display panel using a-Si. When a driver IC having this function is used in a display panel using LTPS, when the operation of the gate signal generation circuit is resumed from the operation stop state due to abnormal power off, the output switches of a relatively large number of stages of the unit register circuit There is a problem that SW5 is turned on at the same time, and an overcurrent is induced in the driver IC that supplies the clock signal of the clock terminal CK.

  The present invention has been made to solve the above-described problems. For example, a driver IC provided with a function such as pixel charge reset corresponding to a liquid crystal display panel using a-Si is used to provide a p- A liquid crystal display panel using Si can be preferably operated.

  A liquid crystal display device according to the present invention includes a shift register unit including a plurality of pixel circuits, a plurality of gate signal lines for supplying gate signals to the pixel circuits, and a plurality of unit register circuits connected in cascade. A gate signal generation circuit that sequentially outputs gate signals to the plurality of gate signal lines based on output pulses that are sequentially driven and output in synchronization with a signal, a power source for the gate signal generation circuit, and the clock signal Each of the unit register circuits between the input terminal of the clock signal and the output terminal of the output pulse according to the potential of the reference point in the unit register circuit. An output circuit for controlling conduction / non-conduction, a reference point set circuit for controlling conduction / non-conduction between a first power source having a predetermined high potential and the reference point, and a predetermined low A reference point reset circuit for controlling conduction / non-conduction between the second power source and the reference point, and the reference point reset circuit is reset before and after the start of the operation of the shift register unit. It includes a common reset circuit for all stages that conducts by a pulse and sets the reference point to the predetermined low potential.

1 is a schematic overall perspective view of a display panel in a liquid crystal display device according to an embodiment of the present invention. 1 is a block diagram illustrating a schematic configuration of a liquid crystal display device according to an embodiment of the present invention. It is a schematic diagram which shows the structure of the outline of the circuit mainly formed in a TFT substrate in the display panel of embodiment of this invention. It is a schematic diagram which shows the structure of the gate signal generation circuit in embodiment of this invention. FIG. 3 is a schematic circuit diagram of a unit register circuit in an embodiment of the present invention. It is a circuit diagram which shows the example of the other circuit structure of the unit register circuit in embodiment of this invention. It is a circuit diagram which shows the example of the other circuit structure of the unit register circuit in embodiment of this invention. It is a typical top view which shows the vicinity part of a pixel transistor among pixels. FIG. 9 is a schematic vertical sectional view of the display panel taken along line IX-IX in FIG. 8. FIG. 4 is a schematic plan view showing a vicinity of a pixel transistor in a pixel circuit in which an additional capacitor is provided between a gate and a pixel electrode. FIG. 11 is a schematic vertical sectional view of the display panel taken along line XI-XI in FIG. 10. FIG. 4 is a schematic plan view showing a vicinity of a pixel transistor in a pixel circuit in which an additional capacitor is provided between a gate and a pixel electrode. FIG. 13 is a schematic vertical sectional view of the display panel taken along line XIII-XIII in FIG. 12. It is a circuit diagram of a unit register circuit of a comparative example.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In addition, the drawings shown below are merely examples of the embodiment, and the size of the drawings and the scales described in this example do not necessarily match.

  FIG. 1 is a schematic overall perspective view of a display panel 2 in the liquid crystal display device 1. FIG. 1 shows a three-dimensional space defined by a first direction X, a second direction Y perpendicular to the first direction, and a third direction Z perpendicular to the first direction X and the second direction Y. In the illustrated example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees.

  As shown in FIG. 1, the display panel 2 includes a counter substrate 3, a TFT substrate 4, and a backlight 5. In the present embodiment, an IPS (In-Plane Switching) method is described as an example of the liquid crystal driving method of the display panel 2, but the present invention is not limited to the liquid crystal driving method.

  The counter substrate 3 and the TFT substrate 4 are disposed facing each other, and a liquid crystal material is sealed in a region sandwiched between the substrates 3 and 4. A color filter or the like is formed on the counter substrate 3. In the display area of the TFT substrate 4, a plurality of pixel circuits provided for each pixel and controlling the orientation of the liquid crystal are formed, and a circuit for driving the pixel circuits is formed in an outer area of the display area. The counter substrate 3 is formed shorter than the TFT substrate 4 in the second direction Y. In other words, the display panel 2 has a portion of only the TFT substrate 4 of the two substrates 3 and 4 facing each other, and a driver IC 12 and the like are mounted and connected thereto.

  FIG. 2 is a block diagram illustrating a schematic configuration of the liquid crystal display device 1. A display unit 10, a driver IC 12, an RGB switch circuit 14, and a gate signal generation circuit 16 shown in FIG. 2 are provided on the TFT substrate 4 of the liquid crystal display device 1.

  The driver IC 12 is formed separately from the TFT substrate 4 and is mounted on the TFT substrate 4 as described above, for example. The driver IC 12 may be connected to the TFT substrate 4 via a flexible printed circuit (FPC) or the like. The driver IC 12 includes, for example, a gate signal line control circuit 20, a video signal line drive circuit 22, and a reference voltage line drive circuit 24. Here, although the gate signal line control circuit 20, the video signal line drive circuit 22, and the reference voltage line drive circuit 24 are configured as an integrated driver IC 12, they are provided separately or a part of one driver. It may be provided in the IC.

  The plurality of pixel circuits, the RGB switch circuit 14, and the gate signal generation circuit 16 formed in the display unit 10 are formed using thin films stacked on the surface of the TFT substrate 4, and in particular, the transistors constituting these circuits are TFTs. It becomes. The TFT of the liquid crystal display device 1 is formed using, for example, p-Si such as LTPS as a semiconductor layer. The RGB switch circuit 14 may not be provided.

  The gate signal line control circuit 20 supplies power supplies VGH and VGL and control signals to the gate signal generation circuits 16 disposed on both sides of the display unit 10. The gate signal generation circuit 16 includes a shift register unit including a plurality of cascaded unit register circuits, and is an n-phase clock signal (n is an integer of 2 or more) applied in accordance with the cascade connection order. Synchronously, each stage of the unit register circuit is driven in sequence to output a pulse, and a gate signal is output to a plurality of gate signal lines in sequence based on the output pulse.

  In this embodiment, the left and right gate signal generation circuits 16 are each driven by a four-phase clock signal. For example, the gate signal generation circuit 16 disposed on the left side of the display unit supplies gate signals to the odd-numbered gate signal lines 40, and the right-side gate signal generation circuit 16 supplies gate signals to the even-numbered gate signal lines 40. Incidentally, in the present embodiment, the gate signal line control circuit 20 and the gate signal generation circuit 16 constitute a gate signal line drive circuit. In the present embodiment, the gate signal generation circuit 16 is disposed on each of both sides of the display unit 10, but may be formed on only one of them.

  The video signal line driving circuit 22 supplies a video signal having a voltage corresponding to the display data of the pixel circuit to each of the plurality of video signal lines via the RGB switch circuit 14. The reference voltage line drive circuit 24 supplies a reference voltage to each pixel circuit via a plurality of reference voltage lines.

  FIG. 3 is a schematic diagram showing a schematic configuration of a circuit mainly formed on the TFT substrate 4. The pixel circuits 30 are arranged in a matrix on the display unit 10 corresponding to the pixels. The pixel circuit 30 includes a pixel transistor 32 that is a TFT, a pixel electrode 34, and a common electrode 36. In the pixel arrangement, the first direction X and the second direction Y are the row direction and the column direction, respectively, a pixel group aligned in the row direction is a pixel row, and a pixel group aligned in the column direction is a pixel column.

  A pixel row corresponds to a scanning line in raster scan, and a gate signal line 40 extends along each pixel row. Further, the common signal line 42 is also extended along each pixel row. On the other hand, a video signal line 44 extends along each pixel column.

  The pixel transistor 32 of each pixel circuit 30 has a gate electrode connected to the gate signal line 40 of the pixel row corresponding to the pixel circuit 30. For example, the video signal line 44 of the pixel column corresponding to the pixel circuit 30 has a source electrode. The drain electrode is connected to the pixel electrode 34 of the pixel circuit 30. Further, the common electrode 36 of the plurality of pixel circuits 30 in each pixel row is connected to the common signal line 42 in the pixel row. Although FIG. 3 shows the common electrode 36 for each pixel and the common signal line 42 for each pixel row, these can be formed by one conductive film in the display portion 10.

  The plurality of gate signal lines 40 are connected to the gate signal generation circuit 16, and the gate signal generation circuit 16 sequentially outputs gate signals to the gate signal lines 40 as described above, and the pixel circuit connected to the gate signal line 40. At 30, the pixel transistor 32 is turned on, and display data can be written to the pixel circuit 30.

  The plurality of video signal lines 44 are connected to the video signal line drive circuit 22 via the RGB switch circuit 14. The video signal line drive circuit 22 outputs a video signal for one scanning line to the video signal line 44. Specifically, a voltage corresponding to the display data of each pixel constituting the pixel row corresponding to the scanning line is output to the video signal line 44 of the column corresponding to the pixel. The display data output to the video signal line 44 is written to the pixel circuit 30 that can be written by a gate signal. Specifically, the pixel electrode 34 is connected to the video signal line 44 via the pixel transistor 32 and is set to a potential corresponding to display data.

  The common signal line 42 is supplied with a reference voltage as a common signal from the reference voltage line driving circuit 24. The common signal is common to each pixel, and the common electrode 36 of each pixel is set to a common potential by the common signal. Each pixel circuit 30 controls the orientation of liquid crystal molecules by an electric field generated by a pixel electrode 34 set to a potential corresponding to display data and a common electrode 36 set to a common potential. The transmission amount of light incident from the backlight 5 is controlled.

  FIG. 4 is a schematic diagram showing the configuration of the gate signal generation circuit 16. The gate signal generation circuit 16 includes a shift register unit 50 that can perform a bidirectional shift operation. FIG. 4 shows a gate signal generation circuit 16 provided on the left side of the display unit 10 as an example. For example, the gate signal generation circuit 16 on the left side sequentially drives the odd-numbered rows, that is, the gate signal lines 40 every two rows at a timing shifted by 2H (H is a horizontal scanning period of one row). On the other hand, the right gate signal generation circuit 16 sequentially drives the even-numbered gate signal lines 40 at a timing shifted by 1H from the odd-numbered rows.

The shift register unit 50 of the gate signal generation circuit 16 on one side is driven by a four-phase clock. However, as described above, the gate signal line control circuit 20 has an eight-phase drive in order to drive each side with a shift of 1H phase. Phase clock signals Ψ _{CK1 to} Ψ _CK8 are generated. The gate signal line control circuit 20 generates clock pulses in order in the forward direction, that is, in the order of Ψ _CK1 , Ψ _CK2 ,..., Ψ _CK8 , Ψ _{CK1 ,.} On the other hand, in the reverse shift operation, the _signals are generated in the reverse direction, that is, in the order of Ψ _CK8 , Ψ _CK7 ,..., Ψ _CK1 , Ψ _CK8,.

The gate signal line control circuit 20 includes a first set of Ψ _CK1 , Ψ _CK3 , Ψ _CK5 , and Ψ _CK7 that are pairs of signals that are shifted in phase by 2H, and Ψ _CK2 , Ψ _CK4 , Ψ _CK6 , and Ψ _CK8. The first set is supplied to the left gate signal generation circuit 16, and the second set is supplied to the right gate signal generation circuit 16. The unit register circuit 52 of each stage is associated with one clock signal (output control clock signal) having a phase that determines the timing of the output pulse of the stage among the plurality of phase clock signals. For example, in the left gate signal generation circuit 16, the phase is changed by one stage in the order of Ψ _CK1 , Ψ _CK3 , Ψ _CK5 , Ψ _CK7 , Ψ _CK1 ,... From the first stage (upper side) to the rear stage (lower side). The clock signal is supplied as an output control clock signal. On the other hand, in the right gate signal generation circuit 16, the order is Ψ _CK2 , Ψ _CK4 , Ψ _CK6 , Ψ _CK8 , Ψ _{CK2 ,.}

Further, the gate signal line control circuit 20 generates trigger signals ψ _ST1 , ψ _ST2 and reset signals ψ _RS1 , ψ _RS2 regarding the start and stop of the shift operation of the shift register unit 50. Each of these signals, for example, generates a pulse that rises to H level at a trigger or reset timing, and is set to L level at other timings. Specifically, the gate signal line control circuit 20 inputs a pulse of the reset signal Ψ _RS2 to the unit register circuit 52 at the first stage before the start of the forward shift operation, and then outputs a pulse of the trigger signal Ψ _{ST1 to} the first stage. Input to start shift operation. Also, at the end of the forward shift operation, after the output pulse of the tail stage is inputted to the terminal END1, inputs the pulse of the reset signal [psi _RS1 to the end stage. On the other hand, in the reverse shift operation, the pulse of the reset signal Ψ _RS1 is input to the rear stage unit register circuit 52 before the start thereof, and then the trigger signal Ψ _ST2 is input to the rear stage of the shift operation to start and end. In some cases, after the output pulse of the first stage is input to the terminal END2, the pulse of the reset signal Ψ _RS2 is input to the first stage.

  The shift register unit 50 has a configuration in which a plurality of unit register circuits 52 are connected in cascade as described above. Each unit register circuit 52 outputs a pulse from its output terminal OUT. The shift register unit 50 outputs pulses from each stage of the unit register circuit 52 in order from the first stage in the forward shift operation, and sequentially from the last stage in the reverse shift operation.

The output terminal OUT of the k-th unit register circuit 52 includes a set terminal IN1 for the (k + 1) -th forward shift operation, a reset terminal RST2 for the (k + 2) -th reverse shift operation, and a (k-1) th-stage reset terminal RST2. It is connected to the set terminal IN2 for the reverse shift operation and the reset terminal RST1 for the (k-2) th forward shift operation. The clock terminal CK of each stage is connected to the clock signal line that supplies Ψ _CK1 to Ψ _CK8 from the gate signal line control circuit 20 and that corresponds to the clock associated with the stage as the output control clock signal. The

  Further, each unit register circuit 52 has a terminal RSTC used for the all-stage common reset operation described later.

  FIG. 5 is a schematic circuit diagram of the unit register circuit 52. The unit register circuit 52 includes switches SW1 to SW9 and inverters INV1 to INV7. Each of these switches and inverters is constituted by a TFT using LTPS formed on the TFT substrate 4. 5 is different from the unit register circuit shown in FIG. 14 in that it includes switches SW7 to SW9, inverters INV6 and INV7, and a reset terminal RSTC.

Here, each unit register circuit 52 includes a pair of terminals RST0 and xRST0 as a reset terminal RSTC, corresponding to the fact that the switch SW8 is a complementary switch (transfer gate circuit) that operates with inverted control signals. . The signal Ψ _RST input to the terminal RST0 is basically a logical OR signal of the reset signals Ψ _RS1 and Ψ _RS2 output from the gate signal line control circuit 20, that is, Ψ _RS1 and Ψ _RS2 . On the other hand, the signal [psi _XRST input to the terminal xRST0 is an inverted signal of the [psi _RST.

The gate signal generation circuit 16 includes a circuit 54 (FIG. 4) that generates a reset pulse that is input from the reset signals ψ _RS1 and ψ _RS2 to the terminals RSTC (that is, RST0 and xRST0) of each stage. The circuit 54 includes, for example, a NOR gate 60 and inverters 61 to 63 as shown in FIG. The inputs of the NOR gate 60 are reset signals Ψ _RS1 and Ψ _RS2 , and the inverters 61 to 63 are connected in series to the output terminal of the NOR gate 60. Note that the inverters 61 to 63 function as a buffer circuit, and sequentially increase the driving capability to enable simultaneous driving of all stages. The output of the inverter 63 is input as a all-stage common reset signal Ψ _RST to the terminals RST0 of all stages via the signal line 64, and the output of the inverter 62 is input as the all-stage common reset signal Ψ _XRST via the signal line 65 to all stages. Input to the terminal xRST0. As described above, the reset signals ψ _RS1 and ψ _RS2 generate a pulse rising to the H level before and after the start of the shift operation, and correspondingly, the signal ψ _RST is at the H level before and after the start of the shift operation. The signal Ψ _XRST generates a reset pulse that falls to L level.

  The unit register circuit 52 includes an output circuit that establishes a conductive state between the clock terminal CK and the output terminal OUT when the reference point P1 in the circuit is at the H level, a power supply VGH (first power supply), and the reference point P1. And a reference point reset circuit for controlling the intermittent connection between the power supply VGL (second power supply) and the reference point P1. Further, the unit register circuit 52 is common to all unit register circuits 52 as a reference point reset circuit, in addition to an individual reset circuit that can be controlled independently of the reference point reset circuits of the unit register circuits 52 of other stages. And a common reset circuit for all stages.

  Specifically, the output circuit includes SW5 and SW8 connected in series between the clock terminal CK and the output terminal OUT. INV3 to INV5 are also included in the output circuit. SW5 and SW8 are transfer gates each combining a p-channel TFT (p-TFT) and an n-channel TFT (n-TFT). For example, SW8, SW5 from the clock terminal CK side to the output terminal OUT side. Are connected in series. INV3 has an input terminal connected to the reference point P1, and an output terminal connected to the gate of the p-TFT of SW5. INV4 has an input terminal connected to the output terminal of INV3, and an output terminal connected to the gate of the n-TFT of SW5. Thus, when the reference point P1 is at the H level, SW5 is turned on.

The gate of the p-TFT of SW8 is applied to [psi _RST from a terminal RST0, the gate of the n-TFT of SW8 is applied to [psi _XRST from terminal XRST0, while the shift register unit 50 is performing the shift operation in the on state There, on the other hand, when the gate signal line control circuit 20 before the start of the shift operation and after completion outputs a pulse to the reset signal [psi _RS1 or [psi _RS2 signal in response thereto [psi _RST, the reset pulse occurring [psi _XRST SW8 is the oFF state Become.

  Therefore, when the reference point P1 is set to H level during the shift operation, the clock terminal CK and the output terminal OUT are in a conductive state, and the clock signal applied to the clock terminal CK is output to the output terminal OUT. The That is, when a clock pulse is input to the clock terminal CK, a pulse is output from the output terminal OUT in synchronization therewith. On the other hand, during the shift operation, while the reference point P1 is reset to the L level, the SW5 is in an off state. Therefore, even if a clock pulse is input to the clock terminal CK, no pulse is output from the output terminal OUT. .

  Note that INV5 has an input terminal connected to the output terminal of INV3, and an output terminal connected to the reference point P1.

Here, in addition to the output circuit described above, SW6 and SW9 are connected to the output terminal OUT as an output reset circuit, which are also involved in the potential of the output terminal OUT. Specifically, SW6 and SW9 are each composed of an n-TFT having a drain connected to the output terminal OUT and a source connected to the power supply VGL. SW6 has a gate connected to the output terminal of INV3 and is turned on in a complementary manner to SW5 of the output circuit. The SW9 is connected to the gate to the reset terminal RST0, the ON state when all the stages common reset signal [psi _RST becomes the H level at the reset pulse.

  That is, since the reference point P1 is set to the H level by the shift operation, SW6 is in the off state and SW9 is also in the off state, so that the output terminal OUT is synchronized with the clock pulse as described above. A pulse is output. On the other hand, during the period in which the reference point P1 is reset to L level by the shift operation, SW6 is in the on state, and the output terminal OUT is maintained at L level.

  Each unit register circuit 52 includes INV6 and INV7 configured to increase the driving capability in order as a buffer circuit at the output terminal OUT, and is cascade-connected to other unit register circuits 52 via the buffer circuit. . Incidentally, the two inverter circuits INV6 and INV7 are basically provided for use as a buffer circuit, and the potential relationship between the input to INV6 and the output from INV7 is not reversed by connecting two stages in series. ing. That is, the H level or L level set by the output circuit and output reset circuit described above is input to another stage without being inverted.

  The reference point set circuit provided in the unit register circuit 52 is a circuit that controls the intermittent connection between the power supply VGH and the reference point P1 and sets the reference point P1 to the H level, and includes SW3 and SW4. INV1 and INV2 are also included in the reference point set circuit. SW3 and SW4 are p-TFTs each having a drain connected to the reference point P1 and a source connected to the power supply VGH. The gate of SW3 is connected to the set terminal IN1 via INV1, and the gate of SW4 is connected to INV2. To the set terminal IN2. When a pulse is input to the set terminal IN1 or IN2 and an H level is input to INV1 or INV2, SW3 or SW4 is turned on, and the reference point P1 is set to the H level. As a result, the output circuit described above can output a pulse in synchronization with the clock signal.

  Specifically, in the forward shift operation, the output pulse of the (k−1) th unit register circuit 52 is input to the kth IN1 and the kth reference point P1 is set to the H level. As a result, the output circuit becomes conductive. In the forward shift operation, the phase of the clock signal is controlled so that the pulse is input to the k-th stage after the (k-1) -th stage, so that when the (k-1) -th stage generates an output pulse, In response to this, the k-th stage generates an output pulse, and a forward shift operation is realized by repeating this.

  The reverse shift operation is the reverse of the forward shift operation. That is, the (k + 1) th stage output pulse is input to the kth stage IN2, and the kth stage reference point P1 is set to the H level. Since the phase of the clock signal is controlled so that the pulse is input to the k-th stage after the (k + 1) -th stage, when the (k + 1) -th stage generates an output pulse, the k-th stage outputs in response to the output pulse. A reverse shift operation is realized by generating a pulse and repeating this.

Incidentally, as described above, in the forward shift operation, the first stage IN1 is input with the pulse of the trigger signal Ψ _ST1 from the gate signal line control circuit 20, and in the reverse shift operation, the rear stage IN2 is the gate signal line. A pulse of the trigger signal Ψ _ST2 is input from the control circuit 20, and the shift operation is started.

  The reference point reset circuit provided in the unit register circuit 52 is a circuit that controls the intermittent connection between the power supply VGL and the reference point P1 and sets the reference point P1 to the L level, and includes SW1, SW2, and SW7.

  Among these, SW1 and SW2 are the individual reset circuits described above, and can be controlled independently of the reference point reset circuit of the unit register circuit 52 at the other stage. SW1 and SW2 are n-TFTs each having a drain connected to the reference point P1 and a source connected to the power supply VGL. The gate of SW1 is connected to the reset terminal RST1, and the gate of SW2 is connected to the reset terminal RST2. . When a pulse is input to the reset terminal RST1 or RST2, SW1 or SW2 is turned on to reset the reference point P1 to L level. Accordingly, the unit register circuit 52 that has generated the output pulse returns the potential of the reference point P1 from the H level to the L level and turns off the output circuit. Therefore, even if the clock pulse is input to the clock terminal CK again, the output terminal OUT Does not output pulses.

  Specifically, in the forward shift operation, the output pulse of the (k + 2) -th unit register circuit 52 is input to the k-th stage RST1, the k-th stage reference point P1 is reset to the L level, In the reverse shift operation, the (k−2) -th stage output pulse is input to the k-th stage RST2, and the k-th stage reference point P1 is reset to the L level.

Incidentally, as already mentioned, at the end of the forward shift operation, tail stages generate output pulses from the gate signal line control circuit 20 to the RST1 inputted pulse of the reset signal [psi _RS1, the reverse shift operation At the end, the top stage that generated the output pulse is input to the pulse of the reset signal [psi _RS2 from the gate signal line control circuit 20 to RST2, are reset respectively the reference points P1 to L level.

SW1 and SW2 constitute an individual reset circuit, whereas SW7 constitutes an all-stage common reset circuit controlled in common by all unit register circuits 52. SW7 is an n-TFT whose drain is connected to the reference point P1, and whose source is connected to the power supply VGL, and the gate of SW7 is connected to the reset terminal RST0. As described above, the all-stage common reset signal Ψ _RST is input to the terminal RST0 of the unit register circuit 52 of all stages via the signal line 64 in common. When the reset pulse of the signal Ψ _RST is input to the reset terminal RST0, SW7 is turned on and the reference point P1 is reset to L level. As a result, the potentials of the reference points P1 in all stages are set to the L level.

  As described above, the feature of the unit register circuit 52 in FIG. 5 compared to the unit register circuit shown in FIG. 14 is that it has switches SW7 to SW9, inverters INV6 and INV7, and a reset terminal RSTC. Due to this feature, the liquid crystal display device 1 causes the abnormal operation of the gate signal generation circuit 16 when the gate signal line control circuit 20 executes the pixel charge reset function and resumes the operation after the operation is stopped when the power supply abnormality is off. prevent.

  The abnormal operation is performed when the driver IC supplies all the H level to the power supply line and the control signal line to the gate signal generation circuit when the power supply abnormality is turned off, stops the operation, and then restarts the operation of the unit register circuit. The output switches SW5 of many stages are simultaneously turned on, and an overcurrent is induced in the driver IC that supplies the clock signal of the clock terminal CK.

  As a result of analyzing this phenomenon, after the entire unit register circuit is set to the H level by the pixel charge reset function, the power supply VGH and VGL of the unit register circuit and the voltage supply to each input terminal are stopped and the operation is stopped. At this time, it has been found that the potential of the reference point P1 is not uniformly determined, and there are many unit register circuits in which the potential is maintained at the H level, and thus an overcurrent is generated. The reason why the potential of the reference point P1 is not uniformly determined when the operation is stopped is considered to be because the method of decreasing the potential of each input terminal of the unit register circuit 52 is not necessarily uniform when the operation is stopped. . For example, considering only SW1, if the timing at which the potential of RST1 decreases from the H level and the SW1 is turned off is earlier than the potential decrease from the H level of VGL, the reference point P1 is in a floating state with a relatively high potential. On the other hand, if the timing is reversed, the reference point P1 can be lowered to a relatively low potential to be in a floating state.

  The phenomenon that the potential of the reference point P1 at the time of stopping the operation becomes H level can also occur in the unit register circuit using the TFT in which the semiconductor layer is formed of a-Si. However, in the unit register circuit using a TFT formed of a-Si, the off-leakage current of the TFT is relatively large, so that the state where the reference point P1 is at the H level is not maintained until the operation restarts. It is presumed that the same problem as in the unit register circuit using the formed TFT did not occur.

The unit register circuit 52 addresses this problem by the above-described features. One of the features of the unit register circuit 52 in this regard is that, in addition to SW1 and SW2, SW7 that is a common reset circuit for all stages is included as a reference point reset circuit that controls the intermittent connection between the power supply VGL and the reference point P1. It is in. SW7 is turned on by a signal [psi _RST generated from the reset signal [psi _RS1, [psi _RS2 after before and the start of the shift operation, and sets the reference point P1 to L level. Thereby, the reference point P1 of the unit register circuits 52 in all stages is set to the L level when the operation is stopped after the power supply is abnormally turned off. That is, since the reference point P1 is also set to the L level even in the unit register circuit 52 in which the reference point P1 is maintained at the H level when the operation is stopped after the power supply is turned off, a plurality of stages are simultaneously output when the shift operation is resumed. A phenomenon of generating a pulse is prevented, and an overcurrent of the driver IC can be avoided.

  Further, even if the clock pulse is input to the clock terminal CK before the operation of turning on the SW7 and resetting the reference point P1 to the L level is completed, the unit register circuit 52 turns off the SW8 of the output circuit. Thus, the current supply from the gate signal line control circuit 20 to the gate signal line 40 via the output terminal OUT is blocked, and the occurrence of the overcurrent can be prevented.

  Further, the unit register circuit 52 transmits the H level of the clock terminal CK to the output terminal OUT due to, for example, a deviation in the off timing of SW8 until the operation of turning on SW7 and resetting the reference point P1 to L level is completed. However, by turning on SW9 of the output reset circuit, it is possible to prevent the potential of the output terminal OUT from rising to the H level, and to prevent the propagation to other stages. That is, when the output terminal OUT of the unit register circuit 52 of a certain stage becomes H level, the reference point P1 of the other stage where the terminals IN1 and IN2 are connected to the output terminal OUT is set to H level, and the output terminal OUT becomes H level. The level may become a level, and there is a possibility that the shift register unit 50 may be abnormally transferred, and the SW 9 prevents this.

  By these SW7 to SW9, it is possible to converge the abnormal state in which the unit register circuits 52 of a plurality of stages simultaneously output pulses. However, for example, when a delay occurs in the recovery of the clock signal line drive capability of the gate signal line control circuit 20 that has occurred in the abnormal state, the output pulse from the unit register circuit 52 that has operated normally The amplitude becomes insufficient, the SW1 or SW2 of the reference point reset circuit is not turned on at the other stage where the output pulse is input to the terminal RST1 or RST2, and the H level of the reference point P1 set by the shift operation is reset. As a result, an abnormal state in which output pulses are generated from a plurality of stages may occur. In this regard, by providing a buffer circuit composed of INV6 and INV7, output pulses capable of driving the other SW1 and SW2 can be obtained even if the driving capability of the gate signal line control circuit 20 is reduced, and the shift is performed. The reference point P1 set to H level by the operation can be surely reset, and the above abnormal state can be avoided.

  An example of another circuit configuration of the unit register circuit 52 having the above-described characteristics corresponding to the driver IC 12 that executes the pixel charge reset function when the power supply is abnormally turned off will be described. 6 and 7 are circuit diagrams showing examples of other circuit configurations of the unit register circuit 52. FIG. In the circuits of FIGS. 6 and 7, the same components as those in the circuit of FIG. In the circuits of FIGS. 6 and 7, the reference point set circuit and the reference point reset circuit (individual reset circuit and all-stage common reset circuit) are configured by RS flip-flop circuits. Note that this circuit is configured using a TFT whose semiconductor layer is made of LTPS.

  Specifically, the unit register circuit 52a of FIG. 6 includes NOR gates 70a and 72a and SW5, SW6, SW8, SW9, INV6, and INV7. The input terminal of the NOR gate 70a is connected to the terminals IN1 and IN2 and the output terminal of the NOR gate 72a. The output terminal of the NOR gate 70a is the gate of the p-TFT that constitutes SW5, the gate of the n-TFT that constitutes SW6, And connected to the input terminal of the NOR gate 72a. On the other hand, the input terminal of the NOR gate 72a is connected to the terminals RST1, RST2, RST0 and the output terminal of the NOR gate 70a, and the output terminal of the NOR gate 72a is the gate of the n-TFT constituting the SW5 and the input terminal of the NOR gate 70a. Connected to.

  7 has NOR gates 70b and 72b, NAND gates 74 and 76, and SW5, SW6, SW8, SW9, INV6, and INV7. The input terminal of the NOR gate 70b is connected to the terminals IN1 and IN2, and the output terminal of the NOR gate 70b is connected to the input terminal of the NAND gate 74. The input terminal of the NOR gate 72b is connected to the terminals RST1, RST2 and RST0, and the output terminal of the NOR gate 72b is connected to the input terminal of the NAND gate 76. The input terminal of the NAND gate 74 is connected to the output terminal of the NOR gate 70b and the output terminal of the NAND gate 76, and the output terminal of the NAND gate 74 is connected to the gate of the n-TFT constituting the SW5 and the input terminal of the NAND gate 76. Is done. On the other hand, the input terminal of the NAND gate 76 is connected to the output terminal of the NOR gate 72b and the output terminal of the NAND gate 74, and the output terminal of the NAND gate 76 is the gate of the p-TFT that constitutes SW5 and the n-TFT that constitutes SW6. And the input terminal of the NAND gate 74.

  With the configuration described above, the shift register unit 50 can be operated using the driver IC 12 that performs the pixel charge reset function when the power supply is abnormally off. That is, the shift register unit 50 can be operated by using a driver IC 12 that is used for driving a TFT substrate having a semiconductor layer formed of a-Si. On the other hand, in this case, the output voltage of the reference voltage line driving circuit 24 provided in the driver IC 12 is set to a range corresponding to a pixel circuit having a pixel transistor whose semiconductor layer is a-Si, and the voltage range is the semiconductor layer. It may happen that the pixel circuit 30 having the pixel transistor 32 using LTPS is not suitable for driving.

Reference voltage line drive circuit 24 is the voltage of the common signal supplied to the common electrode of each pixel is set in consideration of the variation occurring in the potential V _P of the pixel electrode (feed-through voltage [Delta] V _P) by the feed-through phenomenon. The feedthrough phenomenon is caused by a parasitic capacitance _CGD between the gate and the pixel electrode of the pixel transistor. Specifically, when the gate pulse of the pixel transistor is turned on, the charges charged in the liquid crystal capacitor C _LC , the storage capacitor C _S , and the parasitic capacitor C _GD are regenerated to the respective capacitors at the moment when the gate pulse is turned off. by being dispensed, potential V _P of the pixel electrodes is a phenomenon that varies from the video signal voltage applied from the video signal line. Incidentally, the voltage of the gate pulse in response to decreases from phi _H to phi _L during off, the potential V _P of the pixel electrode lowers by [Delta] V _P.

The feedthrough voltage ΔV _P is expressed by the following equation. Here, V _G is the amplitude of the gate pulse. In this embodiment, V _G is the potential difference between the power supplies VGH and VGL, and V _G = φ _H −φ _L.
ΔV _P = V _G C _GD / (C _GD + C _LC + C _S )

The gate-drain parasitic capacitance that becomes the parasitic capacitance _{CGD in the} TFT using a-Si is generally not as small as the TFT using LTPS, and the feedthrough in the pixel circuit in which the semiconductor layer is made of a-Si. voltage [Delta] V _P, the semiconductor layer is larger than a pixel circuit consisting of LTPS.

Here, in order to prevent a flicker in AC drive of the pixel, the common potential is shifted in response to the feed-through voltage [Delta] V _P. For this purpose, the reference voltage line drive circuit 24 that supplies the common potential has its output voltage adjustable range set according to the assumed feedthrough potential ΔV _P.

However, the difference in the above-mentioned feed-through voltage [Delta] V _P, adjustable range of the output voltage of the reference voltage line drive circuit 24 in the driver IC12 made to drive the TFT substrate using a-Si was used LTPS The common potential used in the TFT substrate is not necessarily included.

Here, the feedthrough voltage assumed by the reference voltage line driving circuit 24 of the driver IC 12 is expressed as a temporary setting value ΔV _PA of the feedthrough voltage. That is, the reference voltage line drive circuit 24 supplies a common signal corresponding to [Delta] V _PA. ΔV _PA corresponds to a TFT substrate using a-Si, which is basically excessive for a TFT substrate using LTPS. Accordingly, in the display panel 2 of the present embodiment, to adapt the actual feed-through voltage [Delta] V _P in the pixel circuit 30 to the provisional setting value [Delta] V _PA, in parallel between the gate electrode and the pixel electrode 34 of the pixel transistor 32 Provide additional capacity. In other words, the parasitic capacitance C _GD is increased by providing the additional capacitance, and the field through voltage ΔV _P is increased to the provisional setting value ΔV _PA to which the adjustment range of the output voltage of the reference voltage line driving circuit 24 can correspond.

  FIG. 8 is a schematic plan view showing a pixel, and FIG. 9 is a schematic vertical sectional view taken along line IX-IX in FIG. The plan view of FIG. 8 relates to the pixel circuit 30 formed on the TFT substrate 4, in addition to the pixel transistor 32, the pixel electrode 34, the gate signal line 40 wired in the row direction, and the video signal line wired in the column direction. 44 is represented. Although omitted in FIG. 8, the common electrode 36 is also formed on the TFT substrate 4. The pixel electrode 34 has a plurality of comb portions 34v extending in the column direction from a portion 34h extending in the row direction. The common electrode 36 is formed on the TFT substrate 4 side with respect to the pixel electrode 34 in a vertical cross-sectional structure, and is disposed to face the pixel electrode 34 with an insulating film 114 (shown in FIG. 9) interposed therebetween. The common electrode 36 is formed in a planar shape except for a portion overlapping with a contact hole 116 (shown in FIG. 9) where the pixel electrode 34 and the drain electrode 84 are connected. As a result, a horizontal electric field is generated between the pixel electrode 34 and the common electrode 36.

  The pixel transistor 32 includes a semiconductor layer 80, a gate electrode 82, and a drain electrode 84. The semiconductor layer 80 is made of LTPS, and is laminated on the surface of a substrate 100 made of glass or the like via an insulating film 102 or the like, as shown in FIG. A gate electrode 82 is stacked via the gate insulating film 104 in correspondence with the channel region of the transistor in the semiconductor layer 80. The gate electrode 82 is made of a conductive film in the same layer as the gate signal line 40 and is formed integrally with the gate signal line 40. An insulating film 106 is laminated on the gate electrode 82, and the video signal line 44 and the drain electrode 84 are formed by patterning the conductive film laminated thereon. Note that a light shielding metal film 107 for blocking light from the backlight to the region is disposed below the channel region.

  Both sides of the channel region of the semiconductor layer 80 are a source region and a drain region of the transistor, and the drain electrode 84 is connected to the drain region through the contact hole 108. On the other hand, a video signal line 44 is connected to the source region via a contact hole (not shown) as a source electrode.

  A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) laminated on the insulating film 112 on the drain electrode 84 and the video signal line 44. Thus, the common electrode 36 is formed. Further, an insulating film 114 is laminated thereon, and a pixel electrode 34 is formed by patterning a transparent conductive material such as ITO or IZO laminated thereon. The pixel electrode 34 is connected to the drain electrode 84 through the contact hole 116. The formation positions of the pixel electrode 34 and the common electrode 36 may be reversed. In this case, the pixel electrode 34 is formed in a planar shape, and the common electrode 36 is formed to have a plurality of comb portions.

  An alignment film 118 is formed on the surface of the TFT substrate 4 on which the pixel electrode 34 is formed. Further, a layer 122 on which a color filter, a black matrix, or the like is formed is formed on the surface of the substrate 120 made of glass or the like of the counter substrate 3 on the liquid crystal side, and an overcoat layer that flattens the surface is formed on the surface, for example. After 124 is formed, an alignment film 126 is formed. A liquid crystal layer 128 is provided in a gap between the alignment film 118 of the TFT substrate 4 and the alignment film 126 of the counter substrate 3. A gap between the TFT substrate 4 and the counter substrate 3 is held by a spacer (not shown).

8 and 9 show a structure in which the above-described additional capacitor is not particularly provided. On the other hand, a structure in which an additional capacitor is provided is shown below. FIG. 10 is a schematic plan view showing a pixel as in FIG. 8, and FIG. 11 is a schematic vertical sectional view taken along line XI-XI in FIG. 10 and 11, an overlapping region is provided in the gate signal line 40 and the semiconductor layer 80 to form an additional capacitor serving as a parasitic capacitance _CGD between the gate and the pixel electrode. Specifically, in FIGS. 10 and 11, the gate signal line 40 and the semiconductor layer 80 are provided with extended portions 40 a and 80 a that are expanded compared to FIGS. 8 and 9, respectively, and a region 130 that overlaps them is provided. Additional capacitance is formed.

12 is a schematic plan view showing a pixel, as in FIGS. 8 and 10, and FIG. 13 is a schematic vertical sectional view taken along line XIII-XIII in FIG. In FIG. 12 and FIG. 13, an overlap region is provided in the gate signal line 40 and the drain electrode 84, and an additional capacitor serving as a parasitic capacitance _CGD between the gate and the pixel electrode is formed. Specifically, in FIG. 12 and FIG. 13, the gate signal line 40 and the drain electrode 84 are respectively provided with expanded portions 40b and 84b that are expanded as compared with FIG. 8 and FIG. Additional capacitance is formed.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the configuration described in the embodiment can be replaced with substantially the same configuration, a configuration that exhibits the same operational effects, or a configuration that can achieve the same purpose.

  DESCRIPTION OF SYMBOLS 1 Liquid crystal display device, 2 Display panel, 3 Opposite substrate, 4 TFT substrate, 5 Backlight, 10 Display part, 12 Driver IC, 14 RGB switch circuit, 16 Gate signal generation circuit, 20 Gate signal line control circuit, 22 Video signal Line drive circuit, 24 reference voltage line drive circuit, 30 pixel circuit, 32 pixel transistor, 34 pixel electrode, 36 common electrode, 40 gate signal line, 42 common signal line, 44 video signal line, 50 shift register unit, 52 unit register Circuit, 80 semiconductor layer, 82 gate electrode, 84 drain electrode, 100, 120 substrate, 102, 106, 112, 114 insulating film, 104 gate insulating film, 108, 116 contact hole, 118, 126 alignment film, 128 liquid crystal layer.

Claims (5)

A plurality of pixel circuits;
A plurality of gate signal lines for supplying a gate signal to the pixel circuit;
A shift register unit including a plurality of unit register circuits connected in cascade is included, and gate signals are sequentially output to the plurality of gate signal lines based on output pulses that are sequentially driven and output in synchronization with a clock signal. A gate signal generation circuit;
A driver IC for supplying a control signal including a power source and the clock signal to the gate signal generation circuit;
Have
Each of the unit register circuits includes an output circuit that controls conduction / non-conduction between the input terminal of the clock signal and the output terminal of the output pulse according to a potential of a reference point in the unit register circuit, and a predetermined high level A reference point set circuit for controlling conduction / non-conduction between a first power source of potential and the reference point, and a reference for controlling conduction / non-conduction between a second power source having a predetermined low potential and the reference point A point reset circuit,
The reference point reset circuit includes an all-stage common reset circuit that is turned on by a reset pulse before and after the start of the operation of the shift register unit and sets the reference point to the predetermined low potential.
A liquid crystal display device. The liquid crystal display device according to claim 1.
The output circuit includes a plurality of switches connected in series between an input terminal of the clock signal and an output terminal of the output pulse, and controlled to be turned on / off by the reset pulse. Display device. The liquid crystal display device according to claim 1 or 2,
Each of the unit register circuits includes an output reset circuit that controls conduction / non-conduction between the second power supply and the output terminal of the output pulse by the reset pulse. In the liquid crystal display device according to any one of claims 1 to 3,
Each of the unit register circuits includes a buffer circuit at the output terminal, and is cascade-connected to the other unit register circuits via the buffer circuit. In the liquid crystal display device according to any one of claims 1 to 4,
A video signal line extending in a direction intersecting with the plurality of gate signal lines;
A pixel electrode located in a region surrounded by the gate signal line and the video signal line,
The pixel circuit includes a pixel transistor having a semiconductor layer made of polysilicon, a gate electrode, a drain electrode, and a source electrode,
The gate signal line has an extended portion overlapping at least part of the pixel electrode,
The extension portion overlaps the semiconductor layer;
A liquid crystal display device.

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