JP2018537765A - ストレージ書き込みキャッシュ管理用のハードウェア・アクセラレータの実装のためのデータ・ストレージ・システム、方法、および設計構造 - Google Patents
ストレージ書き込みキャッシュ管理用のハードウェア・アクセラレータの実装のためのデータ・ストレージ・システム、方法、および設計構造 Download PDFInfo
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Abstract
Description
7=割り当て済みCL。割り当てエンジンによって設定される。
6=局所性ビット(Locality bit)
5=PIP(パージ進行中)。CLにパージのマークが付けられたときにオンになり、カウンタをインクリメントする(割り当て解除時にカウンタをデクリメントする)。
4=MIP(ミラー進行中)。HASH内、LRU内。
3=HASHリンク有効(LRU内であってもなくてもよい)
2=RIP(読み取り進行中)。LRU内であってもなくてもよい。
1=DIP(デステージ進行中)。LRU内ではない。
0=OIP(ミラー後のオーバーレイ削除、マスク・マージの結合進行中(Combine Mask Merge in progress))。LRU内ではない。
アレイID(7:0)2006
開始アレイ・オフセット(44:0)(4KBでアライメントされなければならないため、ビット(2:0)=0)2008
終了アレイ・オフセット・サイズ(44:0)(4KBの倍数でなければならないため、ビット(2:0)=0)2010
ページ・テーブル・リスト・ポインタ(31:0)2012
ページ・テーブル・サイズ(11:0)(最大、4K−1個のエントリ)2014
ページ・テーブルの現在のサイズ(11:0)2016
現在のCLインデックス(24:0)2018(開始時にゼロに設定され、一時停止後に保持されてよい)
最大CLインデックス(24:0)2020
アクティブ・ビット、ページ・テーブル中断ビット2022、および
現在のパージ・カウンタ(24:0)2024(割り当て解除によって、PIPビットが設定されたすべてのCLに関してデクリメントされる)
現在のカウンタ値(CL)2302
現在のカウンタ値(局所性ビット)2304
HWM(CL)2306
HWM(局所性ビット)2308
LWM(CL)2310
LWM(局所性ビット)2312
LRU UP、LRU上の最も古いCLエントリ、ゼロ=null2314
LRU DOWN、新しいCLが配置される次の位置、ゼロ=null2316
現在のカウンタ値(WCインストールの合計)2318
現在のカウンタ値(オーバーレイを伴うWCインストール)2320
現在のカウンタ値(WC読み取りの合計)2322
現在のカウンタ値(完全なキャッシュ読み取りヒットを伴うWC読み取り)2324
CLカウント(アレイIDごと)、
CL局所性カウント(アレイIDごと)、
NV 4Kフリー・インデックス(free indexes)(ヘッド・ポインタ/テール・ポインタを介する)、および
NV 528フリー・インデックス(ヘッド・ポインタ/テール・ポインタを介する)を含んでいるレジスタ2504からの、HWからの入力2502を含んでいる。イベント2506からの、HWからの入力2502は、次を含んでいる。
HWMの上のNV 4K、LWMの下のNV 4K、HWMの上のNV 528
LWMの下のNV 528
HWMの上のアレイCLカウント
LWMの下のアレイCLカウント
HWMの上のアレイCL局所性カウント
LWMの下のアレイCL局所性カウント
Claims (20)
- データ・ストレージ・システムであって、
ストレージ書き込みキャッシュのためのストレージ・アダプタ拡張書き込みキャッシュ管理を実装するコントローラを備え、前記コントローラが、
ストレージ書き込みキャッシュのハードウェア・アクセラレーションを実装する書き込みキャッシュ・ハードウェア・エンジンを備え、
前記書き込みキャッシュ・ハードウェア・エンジンが、ファームウェアを実質的に使用せずに書き込みキャッシュのデータおよびメタデータを管理する、データ・ストレージ・システム。 - 前記書き込みキャッシュ・ハードウェア・エンジンが、書き込みキャッシュのデータおよびメタデータを管理することが、新磁気ディスク制御機構(RAID)スタック内の前記ストレージ書き込みキャッシュを提供することを含み、書き込みキャッシュがアレイID/アレイLBA(論理ブロック・アドレス)ごとに実行される、請求項1に記載のデータ・ストレージ・システム。
- 前記書き込みキャッシュ・ハードウェア・エンジンがCL(キャッシュ・ライン)のハードウェア操作を提供する、請求項2に記載のデータ・ストレージ・システム。
- 前記書き込みキャッシュ・ハードウェア・エンジンが、書き込み処理、読み取り処理、およびデステージ処理中にCLの状態を追跡するためにCL(キャッシュ・ライン)定義を使用する、請求項2に記載のデータ・ストレージ・システム。
- 前記書き込みキャッシュ・ハードウェア・エンジンが書き込みキャッシュのコントロール・ストア(CS)から書き込みキャッシュのデータ・ストア(DS)へミラーリングすることを含めて、前記書き込みキャッシュ・ハードウェア・エンジンが前記ストレージ書き込みキャッシュへの書き込みを実行する、請求項1に記載のデータ・ストレージ・システム。
- 前記書き込みキャッシュ・ハードウェア・エンジンが書き込みキャッシュのコントロール・ストア(CS)から書き込みキャッシュのデータ・ストア(DS)へミラーリングすることが、前記コントローラにおけるローカル・ミラーリングおよび二重のコントローラへのリモート・ミラーリングを含む、請求項5に記載のデータ・ストレージ・システム。
- 前記書き込みキャッシュ・ハードウェア・エンジンが、前記ストレージ書き込みキャッシュからの完全または部分的な読み取りヒットを含めて、前記ストレージ書き込みキャッシュからの読み取りを実行する、請求項1に記載のデータ・ストレージ・システム。
- 前記書き込みキャッシュ・ハードウェア・エンジンがハッシュ・テーブルおよびLRU(least recently used)キューのうちの1つを使用して前記ストレージ書き込みキャッシュから検索してデステージ処理を生成することを含めて、前記書き込みキャッシュ・ハードウェア・エンジンが前記ストレージ書き込みキャッシュからのデステージを実行する、請求項6に記載のデータ・ストレージ・システム。
- データ・ストレージ・システムにおけるストレージ・アダプタの書き込みキャッシュ管理を実装するための方法であって、
書き込みキャッシュ・ハードウェア・エンジンを備えるコントローラを提供することと、ストレージ書き込みキャッシュのハードウェア・アクセラレーションを実装するための前記書き込みキャッシュ・ハードウェア・エンジンを提供することと、
ファームウェアを実質的に使用せずに書き込みキャッシュのデータおよびメタデータを管理するための前記書き込みキャッシュ・ハードウェア・エンジンを提供することと
を含む、方法。 - 新磁気ディスク制御機構(RAID)スタック内の前記ストレージ書き込みキャッシュを提供することを含み、書き込みキャッシュがアレイID/アレイLBA(論理ブロック・アドレス)ごとに実行される、請求項9に記載の方法。
- 前記書き込みキャッシュ・ハードウェア・エンジンがCL(キャッシュ・ライン)のハードウェア操作を提供することを含む、請求項9に記載の方法。
- 前記書き込みキャッシュ・ハードウェア・エンジンが、CL(キャッシュ・ライン)定義を使用し、書き込み処理、読み取り処理、およびデステージ処理中にCLの状態を追跡することを含む、請求項9に記載の方法。
- 前記コントローラ内で前記書き込みキャッシュ・ハードウェア・エンジンが書き込みキャッシュのコントロール・ストア(CS)から書き込みキャッシュのデータ・ストア(DS)へミラーリングすること、および二重のコントローラへリモートでミラーリングすることを含めて、前記書き込みキャッシュ・ハードウェア・エンジンが前記ストレージ書き込みキャッシュへの書き込みを実行することを含む、請求項9に記載の方法。
- 前記書き込みキャッシュ・ハードウェア・エンジンが、前記ストレージ書き込みキャッシュからの完全または部分的な読み取りヒットを含めて、前記ストレージ書き込みキャッシュからの読み取りを実行することを含む、請求項9に記載の方法。
- 前記書き込みキャッシュ・ハードウェア・エンジンが、ハッシュ・テーブルおよびLRU(least recently used)キューのうちの1つを使用して前記ストレージ書き込みキャッシュから検索してデステージ処理を生成することを含めて、前記書き込みキャッシュ・ハードウェア・エンジンが前記ストレージ書き込みキャッシュからのデステージを実行することを含む、請求項9に記載の方法。
- 設計工程において使用される機械可読媒体内で具現化される設計構造であって、前記設計構造が、
前記設計工程において使用される前記機械可読媒体内で有形に具現化されるコントローラ回路を備え、前記コントローラ回路がデータ・ストレージ・システムにおいてストレージ・アダプタ拡張書き込みキャッシュ管理を実装するためにあり、前記コントローラ回路が、ストレージ書き込みキャッシュのハードウェア・アクセラレーションを実装する書き込みキャッシュ・ハードウェア・エンジンを備え、
前記書き込みキャッシュ・ハードウェア・エンジンが、ファームウェアを実質的に使用せずに書き込みキャッシュのデータおよびメタデータを管理し、前記設計構造が、半導体チップの製造において読み取られて使用された場合に、前記コントローラ回路を備えるチップを製造する、設計構造。 - 前記設計構造が、集積回路のレイアウト・データの交換に使用されるデータ形式としてストレージ媒体上に存在する、請求項16に記載の設計構造。
- 前記設計構造が、テスト・データ・ファイル、特性評価データ、検証データ、または設計仕様のうちの少なくとも1つを含んでいる、請求項16に記載の設計構造。
- 前記設計構造が、前記コントローラ回路を記述するネットリストを含む、請求項16に記載の設計構造。
- 前記キャッシュ・ハードウェア・エンジンが、書き込みキャッシュのデータおよびメタデータを管理することが、前記キャッシュ・ハードウェア・エンジンが、ストレージ書き込みキャッシュに書き込み、前記ストレージ書き込みキャッシュから読み込むことを含む、請求項16に記載の設計構造。
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