JP2018530187A - Full-duplex transmission through a reduced pair of twinax cables - Google Patents

Abstract

  Cable systems and assemblies integrate a reduced number of twin coaxial copper pairs to send and receive full-duplex transmission signals at transmission rates of 100 gigabytes or more per second. The reduced number of twin coaxial copper pairs has no more than four twin coaxial copper pairs, where each pair forms a single twin coaxial full duplex cable for passive or active communication of signals. .

Description

  The present disclosure relates generally to full-duplex transmission.

  Cables are often used as a physical medium for connecting devices to form a network. For example, the signal can be transmitted through the physical layer of the cable, where signal coding can be used to enhance transmission. The cable includes a data link layer for messages sent between the controller and slave devices. The message has a set of normal bits for bit synchronization, for example followed by a frame synchronization pattern. For example, a frame sync pattern is followed by a data bit frame, where each frame includes a set of start bits, bit data fields, parity bits and / or zero fill bits.

  For applications that require high data rates with low latency performance, such as storage area networks and high performance computing, the selected interconnect medium is a twin coaxial cable to support unmodulated baseband signals. Must have such a very high bandwidth capacity. Baseband digital communications are typically used in place of complex modulation schemes that require sophisticated coding techniques to obtain low latency as well as low power dispersion. The drawback is the analog bandwidth of the medium. For example, to support 10 Gbps (Gigabit / second) data communication, the media supports a frequency Hz with an analog bandwidth. In order to achieve these bandwidths, cable design and coding is refined to address performance parameters in this frequency range.

  Various embodiments for twin coaxial transmission through a reduced number of twinax pairs integrated at each end are disclosed herein. The illustrated system has a set of full duplex twinax pairs configured to communicate a set of signals in different directions. The plug assembly is a plug assembly configured to integrate at least one end of a set of full-duplex twinax pairs with the set of interconnects and connect at least one end to an interface port. The plug assembly includes a transceiver component configured to communicate a set of signals in different directions to and from the interface through a set of full-duplex twinax pairs and a processor operatively connected to the transceiver component. Have. The processor is configured to digitally process a set of signals for transmission over a set of full-duplex twinax pairs.

  In other embodiments, the method includes integrating a reduced set of twinax pairs with the processor and transceiver of the plug assembly. One or more signals can be received via the plug assembly. At least one port of the one or more signals is encoded by the processor with a first communication protocol. The transceiver transmits one or more signals through a reduced set of twinax pairs from the processor.

  In other embodiments, the device has a memory for storing computer-executable instructions, and a first processor coupled to the memory to facilitate computer-executable instruction execution for performing operations. The operation includes transmitting a first set of signals through a twin coaxial copper cable assembly composed of no more than four twinax copper pairs to a second device with a first communication protocol at a communication rate of 100 gigabytes per second or more. . The second set of signals is received simultaneously in full-duplex transmission mode from the second device via no more than four copper twinax pairs of twin coaxial copper cable assemblies.

FIG. 1 is a block diagram illustrating an embodiment of a cable assembly system. FIG. 2 is a block diagram illustrating an embodiment of a cable assembly system. FIG. 3 is a block diagram illustrating an embodiment of a cable assembly system. FIG. 4 is a block diagram illustrating an embodiment of a cable assembly system. FIG. 5 is a block diagram illustrating an embodiment of a transceiver system. FIG. 6 is a block diagram illustrating an embodiment of a transceiver system. FIG. 7 is a flowchart of an embodiment of a method for a cable assembly system. FIG. 8 is a flowchart of an embodiment of a method for a cable assembly system. FIG. 9 is a block diagram of an example electronic computer environment. FIG. 10 is a block diagram of an example of a data communication network.

  In view of the above-mentioned trends or in particular the deficiencies, various embodiments are provided for transmission rates of 100 Gbps and higher for full duplex transmission through a reduced number of twin coaxial pairs. For example, the cable assembly may include a set of twin coaxial cables, each consisting of a full-duplex twinax pair of conductors or a half-duplex twinax pair of conductors. The cable assembly is configured to communicate one or more signals in two directions simultaneously at a transmission rate of 100 gigabytes per second or higher, such as processing or transmitting at a communication rate of 150 gigabytes per second or greater than 200 gigabytes per second. Can do. For example, one twin coaxial cable may be composed of a twin coaxial conductor pair, in other words, two inner conductors. For example, the cable assembly is comprised of four twin coaxial cables having four twin-pair full duplex twin coaxial conductors, so that each twin coaxial cable is a high speed communication, component or processing between workstation and device. Having twin coaxial pairs (conductor pairs) integrated together to form a single cable assembly that allows full duplex communication of data signals for further networking.

  Twin coaxial cables can communicate signals, for example, according to full-duplex data transmission. That means that data can be transmitted in both directions on a single carrier at the same time, or in half-duplex mode where data is communicated in one direction at a time. For example, on a local area network with technology having full-duplex transmission, a workstation (eg, a device) sends data through a cable assembly through at least one conductor of a twinax pair of twinax cables. At the same time, other workstations receive data through the same or different twinax pairs, in other words, through a set of twinax pairs integrated within the cable assembly. As used herein, the term “set” means one or more. Full-duplex transmission implies a bidirectional communication path or line (one that can move data in both directions). Each twinax pair has or constitutes a full-duplex twin coaxial (Twinax) cable. For example, a twin coaxial cable has two twisted balanced conductor wires that have the same or different impedance and a shield braid that surrounds the two wires or two conductors. Unlike simple coaxial wires, twinax wire pairs have two inner conductors instead of one.

  In one embodiment, the cable assembly is configured as a passive cable device or an active cable device, such that within a cable assembly such that no more than four twinax cable pairs are integrated within a single cable assembly. With a reduced number of twinax cables, it can operate at a speed of at least 100 gigabytes per second. The communication process may be executed at a speed of 150 Gbps or more and 200 Gbps or more. The cable assembly may be configured as a passive interconnect cable assembly that does not draw power from within the cable assembly, or may be configured as an active assembly that draws power from one or more ends of the twinax pair to the cable assembly. Passive interconnect cable assemblies operate without consuming power, and active cable assemblies draw or consume power at the end of the cable assembly. A twinax cable pair constitutes a pair of copper cables, wires or conductors that provide high performance options for interconnections between short and long range devices at increased speeds. Although copper conductors, wires, etc. are discussed in various embodiments, cables or twinax pairs with metal conductors other than copper (eg, alloys not limited to gold, silver, platinum, etc.) are also possible.

  Figure 1 shows a signal in 100 Gbps full-duplex transmission mode via 4 or fewer conductor pairs, 8 or fewer conductors in total, 4 or fewer twinax pairs, in other words, 4 or fewer twinax cables. 1 illustrates one embodiment of a cable assembly 100 configured as a passive cable device for transmission. The cable assembly 100 is an end housing that combines and integrates interconnects and components to facilitate full-duplex transmission between devices or device components along a reduced set of full-duplex twinax wire pairs 106. As plug assembly 102 and plug assembly 104, respectively.

  Plug assemblies 102 and 104 are located at each end of the cable assembly 100 and connect one or more receiving ports or plugs (not shown) of a user device (not shown) for signal communication via the twinax pair 106. Each end of the set of full duplex twinax wire pairs 106 is configured to be integrated. Each twinax pair constitutes a pair of conductors or a single twinax cable within the cable assembly 100.

  Plug assemblies 102 and 104 each have a transceiver 108 and transceiver 110 for transmitting and receiving signals, which may each be integrated with the processor as a transceiver microprocessor or controller. Transceivers 108 and 110 are located on the circuit board of the user device and are operatively connected to connectors 112 and 114 at each of the twinax cable ends, and transceivers 108 and 110 are external to plug assemblies 108 and 110. The transceivers 108 and 110 have, for example, traces on a circuit board (not shown) or interconnected to the twinax pair 106 and the transceivers 108, 110 via plug assemblies 102 and 104 (eg, copper interconnects). ) Have other conductor interfaces or paths.

  In one example, the transceivers 108 and 110 may be located on receive ports, jacks or sleeves on respective user devices, such as processor devices and other component devices connected via the cable assembly 100. The transceivers 108, 110 are implemented in, for example, a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a ring network, a storage area network, etc., and these networks for various transmission media Supports various communication protocols such as Ethernet, Sonet / SDH, Fiber Channel applications across various switching and routing architectures for communication between devices connectable via Alternatively or additionally, the transceivers 108, 110 can operate as receivers that receive and process communication transmissions, or as transmitters that transmit and process only communication data for transmission. The transceivers 108, 110 can include a plurality of transceivers for transmitting or receiving communications.

  In one embodiment, transceivers 108 and 110 constitute a transceiver at each end of cable assembly 110 that is operatively connected to connector 112 and connector 114, respectively. For example, a transmission / reception line from the transceiver 108 to the connector 112 allows a communication signal to be transmitted / received to / from the connector 112 via the twinax cable 106 having a conductor twinax cable pair. The illustrated receive path 116 and transmit path 118 are route traces or are interconnects (eg, copper interconnects) that are operable to receive and / or transmit through the same interconnect. is there.

  The twinax cable 106 is encoded, partitioned, and reformatted for transmission through the connectors 112, 114, for example, at a transmission rate of 100 Gbps or higher. Connectors 112 and 114 are different from or the same as each other, and further function to automatically short the twin coaxial cable or twin coaxial pair, integrate transmission between different impedances, or be balanced or unbalanced. Having an interface that functions to convert between signals. Connectors 112 and 114, for example, have interfaces that integrate twinax pairs to allow transmitted or received signals to conform to many standards and to share a common connector for connecting to electronic devices. In one example, multiple different standards can be transmitted over the same cable and / or different twinax pairs with various pin connections or trace connections in each connector 112 or 114. For example, each connector has a clock (not shown) for retiming or reclocking different signals. Connectors 112 and 114 may include balun connectors for twinax pairs and / or other interfaces (eg, media dependent interfaces (MDI), PMDA, SERDES, etc.).

  FIG. 2 illustrates a first end section 206 and a second end section 222 for interconnection of one or more devices (not shown), such as computer devices, mobile processing devices, display devices, personal digital assistants, and the like. 1 illustrates an embodiment of a cable assembly 200 having Cable assembly 200 can operate as a device processor with an active twinax cable device for high speed, full duplex transmission within the device, or a reduced set of twinax conductor pairs. Additionally, the cable assembly 200 can be operated to simultaneously transmit and receive at different transmission protocols at a transmission rate of 100 Gbps or higher. Additionally or alternatively, a cable assembly 200 having no more than four twinax pairs can simultaneously transmit and receive data at a transmission rate of 800 Gbps or more for one or more different communication protocols.

  For example, the cable assembly 200 is an interconnect 204 that interfaces with a plug or receiving port, such as QSFP (quad small form factor pluggable), SFP (small form factor pluggable), or other removable connectors. , 220 with an interface 210 and an interface 226 at each end including a set (eg, copper interconnect or path). Interfaces 210 and 226 are operatively connected to circuit boards 216 and 230, or a processor package mount (eg, a ball grid array, etc.) having surface mounts or processors 208 and 224. Interfaces 210 and 226 have a plug portion of cable assembly 200 that acts as a processing device for communicating between one or more other devices, or a mate for connecting to a device plug or port. . The cable assembly 200 operates as an active cable device that draws or consumes power at one or more ends of the assembly 200, and handles, encodes, and transmits one or more communication protocols with low bit error rate and high efficiency. Decrypt.

  The cable assembly 200 has plug assemblies 202 and 218 at the end of the cable assembly 200 that includes an interface 210 or plug portion that acts as a mate for connecting to a port or plug of the device. Plug assemblies 202 and 218 have a processor 208 or 224 operatively connected to a circuit board 216 or 230, or surface mount, respectively. The processor 208 or 224 may perform error correction, such as a forward error correction code (FEC), according to one or more algorithms that enable high-speed, full-duplex data transmission at a speed of 100 Gbps or higher via the twinax pair 214. Operates with transceivers 212, 228 to encode, decode or process a code (ECC).

  In one embodiment, the processor 208 or 224 operates to draw or consume power from an independent power source (not shown) disposed therein. It may be connected to a circuit board or processor package 216,230. In addition, the transmitted signal may be used to energize the cable. For example, power signal transmission is used to power the processor for transmission, such as by electromagnetic coupling or other remote power signals. Power from the device connected to the cable assembly can also be used to power the processors 208, 224, such as an external power source located on the device.

  Processors 208 and 224 can be integrated as a transceiver that operates to send and receive signals for full-duplex transmission along a twinax pair. In addition, the processors 208 and 224 can be connected to transmitters, receivers or transceivers 212, 228 located within the plug assemblies 202, 218. For example, the transceiver 212 or 228 may be routed through a route trace or processor package having interconnects, connect pads, ball grids mounted on a circuit board 216, 230 (eg, a printed circuit board) of the cable assembly 220, or the circuit board 216 or 230 can be connected to the processor.

  The cable assembly 200 is similar to the cable assembly 100 described above, except that it has a microprocessor on the device board and has connectors to a plurality of twin coaxial cables 214. The microprocessors 208, 224 can be integrated on the head of the twinax cable 214, in which case the connections on the microprocessor head through the circuit board are, for example, plugs or interfaces 210, 226 and / or receive ports. It is. The kale-side operation can operate to drive the cable assembly 200 with power drawn or consumed by integrated mounts and packages on the substrate (eg, semiconductor substrate).

  In other embodiments, the cable assembly 200 has a mate that includes a service connection via a board connected to the interconnects 204, 220. One transceiver end (e.g., plug assembly 202) is connected to a twinax pair (e.g., four twinax copper pairs or eight conductors) of twinax cable 214, where each pair is to receive one communication protocol. A two-way or full-duplex communication system, while the other end is used by multiple different ports or jacks in the device for other communications to standardize a variety of different communication signals into one signal Convert communication protocol to protocol. At the other end of cable assembly 200 (eg, plug assembly 218), operable to decode and reconvert to a first communication protocol based on the type of connected device or connected interface 210, 226 It is. Plug assemblies 202, 218 are operable to conform to a plurality of different standards for communication. One end of the cable assembly may handle one communication protocol and the other end may handle a different communication protocol. Alternatively, both ends of the processor, the device to which the plug assembly is interfaced or connected, the specifications provided by the device connected to the cable assembly 200, and / or one or more twinax cable pairs of the communication twinack pair Depending on the selection, the same communication protocol may be processed depending on the selected mode of operation. For example, the plug assemblies 202, 218 can operate in a first mode for a first communication protocol or a second mode for a different communication protocol, where one or more communication data or signals within the communication protocol are 100 Gbps. It is transmitted through 8 or less conductors of 4 or less pairs of the twinax cable at the above transmission rate.

  FIG. 3 shows an embodiment of a cable assembly 300 connected to plug 302 and plug 304. It constitutes a receiving port which is a receiving port such as a QSFP, SFP port, SFF (small form factor) casing, for example. Cable assembly 300 is a cable assembly similar to that described above with similar components for operation.

  Cable assembly 300 operates with surface mount components together with interconnects 204, 220 to plugs 302, 304 as cages and mates, respectively. Plugs 302, 304 have QSFP and / or SFP protocols, which are form factors designed to reduce cost and power consumption, improve reliability and reduce thermal footprint. SFP Plus is a small form factor pluggable plus (identified by SFF-8431) and QSFP is a quad small factor pluggable (identified by SFF-8436). Originally intended for optical form factors, these interfaces have a copper interconnect solution. The SFP and QSFP form factors are lower power consumption modules, where lower power (smaller amount of heat) improves reliability.

  The board 216 has a chip or processor 208 mounted to the head of the cable assembly 202 where the chip or processor 208 is energized through the QSFP connection of the plug and plug assembly 210. The chip operates as a transceiver chip connected to a plurality of twinax cables 214. In one embodiment, multiple twinax pairs 214 have different cable assembly configurations that communicate at different transmission rates within a single cable assembly 220 having multiple communication transmission rates. The plurality of twinax pairs 214 includes a first twinax pair, a second twinack pair, a third twinax pair, and a fourth twinax pair, where each twinax pair has various transmissions. It has a pair of conductors that can each communicate at a speed (eg, 100 Gbps, 40 Gbps, and / or 10 Gbps).

  FIG. 4 shows an example of a cable assembly operating at a high transmission rate for transmitting and receiving input / output data from one or more devices. The cable assembly 400 has components similar to those described above, and further includes an encoding component and a decoding component mounted on a circuit board or surface mount in the plug assemblies 202, 218.

  The cable assembly 400 is operatively connected to the first device 402 and the second device 404 via a reduced set of twinax pairs 214 at a rate of 100 Gbps or higher. The first device 402 or the second device 404 has processors 406 and 410 and one or more data stores 408 and 412 respectively. First device 402 or second device 404 is a personal computer device, mobile device, input / output device, display, personal digital assistant, or other similar device capable of communicating via plugs 302, 304. Having such a processing device.

  At the opposite end of the twinax pair 214, the surface mount or electronic board 216, 230 of the plug assembly 202, 218 is operably connected to the processor and / or transceiver architecture on the circuit board 216, 230 or mount assembly. 418 and decoders 416 and 420. For example, the encoder 414 operates to convert at least one pair of information from one format, code or communication protocol to another via one or more algorithms based on the selection of the communication protocol. For example, the selection is predetermined or dynamically determined based on the type of device connected to the cable assembly 400. For example, communication protocols (eg, universal serial bus standard, peripheral component interconnect express standard, display port standard, high definition multimedia interface, S-video, RCA, etc.) One or more signals, a communication protocol for one or more signals, a device communication protocol for a first device or a second device connected to one or more ends of a reduced set of twinax pairs 214, and / or a cable assembly Based on identification or determination by selection of a twinax pair of a reduced set of twinax pairs identified by 400 processors (eg, 208, 224 described above).

  Decoders 416 and 420 reverse the operation of the encoder to convert information from one format or protocol to the initial format or protocol. For example, the decoders 416, 420 are operable to convert binary information from many lines to a specific output line. For example, if one or more encoders encode data from the first device 402 into one format for high speed transmission, the plug assembly 218 is a second device that is a different device operating with a different communication protocol. Operate to decode and / or re-encode the data based on 404.

  In one embodiment, the twinax pair 214 has no more than four pairs of conductors for communicating over a twinax cable at a transmission rate of 100 Gbps or higher. In one example, cable assembly 400 includes a plurality of twinax cables 214 that operate at multiple transmission rates. The plurality of twinax pairs each have a first twinax pair and a second twinax pair that operate at a plurality of transmission rates or different transmission rates. For example, a first twinax pair can operate in a cable assembly at 40 Gbps and a second twinax pair can operate at 10 Gbps. The cable assembly operates as an active assembly that draws or consumes power, similar to that described above.

  The plurality of twinax pairs having a first twinax pair and a second twinax pair are made of active copper, for example, where both twinax pairs (first and second) of the four pairs are both Two twinax cables that can operate as full-duplex transmission lines with transmission speeds of 40 Gbps and 10 Gbps. Thus, the cable assembly has a twinax pair that includes two pairs of conductors of a cable assembly operating at 40 Gbps and two 10 Gbps and / or one 100 Gbps.

  5 and 6 illustrate aspects of a transceiver architecture for the cable assembly 400 disclosed herein. FIG. 5 shows a plug assembly 202 having a transceiver architecture for transmitting data encoded at high transmission rates (eg, 80 Gbps or 100 Gbps and higher). FIG. 6 shows a plug assembly 202 having a transceiver architecture for receiving encoded data at high transmission rates (eg, 80 Gbps, 100 Gbps and higher). These are merely illustrative examples, and the described architecture is comprised of both plug assemblies 202, 218, or an opposing plug assembly 218 for communication encoding and decoding in the opposite direction. , 202.

  FIG. 5 shows components similar to the transceiver component 212 described above, including a forward error correction (FCC) encoder 502, a signal processing pipeline 506, and a digital to analog converter (DAC) 508. FEC encoder 502 operates to encode the received data and transmit the most significant bits (msbs) to a single processing pipeline 506, which has one or more processing components for simultaneously processing the signal. . Signal processing pipeline 506, for example, receives signals over a set of bitstream paths (eg, three connections) and outputs a set of symbols for transmission over a channel (eg, twinax pair 214). Has a mapper that assimilate the data. The DAC 508 converts a digital signal into an analog signal for transmission.

  FIG. 6 shows components similar to the transceiver component 228 described above, having a programmable gain amplifier (PGA) 602, an analog to digital converter (ADC) 604, an equalizer component 606, and an FEC decoder 608. The twinax pair 214 communicates (transmits / receives) with the transceiver component 228 in full duplex transmission mode. The signal is amplified by PGA 602, converted from analog to digital by ADC 604, equalized by equalizer 606, and decoded by FEC decoder 608 for transmission rates of 80 Gbps or 100 Gbps and higher.

  FIG. 7 is a flowchart of a method 700 for a cable assembly for transmitting and receiving communication data at a high transmission rate along a reduced set of twinax pairs. In step 702, the method 700 integrates the reduced set of twinax pairs with the processor and transceiver of the plug assembly. A twinax pair is a twin coaxial conductor reduced to four or fewer pairs, such as a twin coaxial conductor that allows full duplex communication between different end devices via a twinax pair. The cable assembly is capable of operating at a speed of 80 Gbps or higher to transmit signals at a transmission speed of 100 Gbps in full-duplex communication mode. In step 704, at least a portion of the one or more signals is encoded by a processor with a first communication programmable gain amplifier. Encoding includes encoding at least a portion of the one or more signals with a second communication protocol to transmit the one or more signals from the first device to the second device. The method 700 selects any protocol from the first communication protocol and the second communication protocol to encode at least a portion of the one or more signals. For example, the step of selecting includes at least one specification of one or more signals, a communication protocol of one or more signals, a first device or a second device connected to one or more ends of a reduced set of twinax pairs. Based on the device communication protocol or the choice of a twinax pair in a reduced set of twinax pairs. In step 708, the transceiver transmits one or more signals via the reduced set of twinax pairs from the processor via the reduced set of twinax pairs.

  In one embodiment, the step of integrating the reduced set of twinax pairs with the transceiver and processor of the plug assembly includes no more than four twin coaxial cables, each including a pair of twinax conductors, for mounting to a circuit board. Integrating with a microprocessor package assembly having: The step of receiving and transmitting the one or more signals comprises communicating one or more signals in a full-duplex communication mode simultaneously in different directions between the first device and the second device.

  FIG. 8 illustrates a method 800 for a cable assembly operable to communicate data at a transmission rate of 100 Gbps or higher through a reduced pair of twinax pairs. For example, each of up to four cables has a twinax pair or twin coaxial conductor pair, which means that a copper conductor or other alloy conductor can signal in full-duplex communication mode at an increased rate of 100 Gbps or more. Is operable to send and receive.

  In step 802, the data is transmitted through eight or fewer conductors (eg, copper conductors) that form no more than four twinax pairs in a full duplex communication mode in a twin coaxial cable assembly at a transmission rate of 100 Gbps or less. Communicated from the first device.

  In step 804, the data integrates no more than 8 conductors, forming no more than 4 twinax pairs in full-duplex communication mode, through a plug assembly that integrates no more than 8 conductors with the processor and transceiver. Received by the second device through the plug assembly.

  As described above, the techniques described herein are applicable to any device and / or network where power management is desired within a microprocessor system. Portable, portable, and other communication devices and all types of computer objects, i.e. all devices where it is desired to perform power management on a microprocessor system, are available in connection with various embodiments. is there. Accordingly, FIG. 9 shows an example, and the items disclosed herein can be performed with any client having network / bus interoperability and interaction. The disclosed matter is performed in a network host service environment, where very little or minimal client resources are involved. For example, a network environment in which a client device functions only as an interface to a network / bus such as an object located in a facility.

  FIG. 9 illustrates an example computer system environment 1300 in which some aspects of the disclosed subject matter are implemented, and as described above, the computer system environment 1300 is an example of a communication environment for devices. .

  FIG. 9 is an exemplary device for performing the disclosed matters in the form of a computer 910, including a general purpose computing device. The components of the computer 910 may have a processing unit 920, a system memory 930, and a system bus 921 that connects various system components including the system memory to the processing unit 920. The system bus 921 may be any number of types of bus structures having a memory bus or memory controller, peripheral memory, and a local bus using any of a variety of bus architectures.

  Computer 910 has a variety of computer readable media. Computer readable media can be any useful media that can be accessed by computer 910. The system memory 930 may include computer storage media in the form of non-volatile memory such as read only memory (ROM) and / or volatile memory such as random access memory (RAM).

  The computer 910 may have other erasable / non-erasable, volatile / nonvolatile computer storage media. For example, the computer 910 may be erasable, such as a non-erasable, hard disk drive that reads and writes non-volatile magnetic media, an erasable, a magnetic disk drive that can read and write non-volatile magnetic disks, and / or a CD-ROM or other optical media And an optical disk drive capable of reading and writing a nonvolatile optical disk.

  Computer 910 can operate in a network or distributed environment using logical connections to one or more other remote computers, such as remote computer 970. In this case, it may have different media capabilities than device 910. The logical connections shown in FIG. 9 have a network 917 such as a local area network (LAN) or a wide area network (WAN), but may include other wired / wireless networks / buses.

  FIG. 10 is a schematic diagram of an exemplary network or distributed computing environment. A distributed computing environment includes computer objects 1010, 1012, etc., and computer objects or devices 1020, 1022, 1024, 1026, 1028, etc., which are represented by applications 1030, 1032, 1034, 1036, 1038 and data store 1040. It may have programs, methods, data stores, programmable logic, etc. as represented. Each computer object 1010, 1012, etc. and computer object or device 1020, 1022, 1024, 1026, 1028 etc. is one or more other computer objects 1010, 1012 etc. and computer object or device 1020, 1022, 1024 1026, 1028, etc. can be communicated directly or indirectly by the communication network 1042. Although shown as a single element in FIG. 10, communication network 1042 may include other computer objects and computing devices that provide services to the system of FIG. 10 and / or multiple interconnects not shown. It may represent a network.

  In a client / server architecture, a client is typically a computer that accesses shared network resources provided by other computers that are servers, for example. In FIG. 10, by way of example, computer objects or devices 1010, 1012, etc. may be servers, and computer objects or devices 1020, 1022, 1024, 1026, 1028, etc. may be clients. In that case, the server computer objects or devices 1010, 1012, etc. receive data from the client computer objects or devices 1020, 1022, 1024, 1026, 1028, etc., store the data, process the data, To the client computer object or device 1020, 1022, 1024, 1026, 1028, etc. Any computer is considered a client, server, or both, depending on the environment.

  Additionally, the disclosed items may be used to control methods, apparatus, or typical manufacturing methods for manufacturing hardware, manufactured articles using programming or engineering techniques, and electrical devices that implement the disclosed items. It can be implemented as firmware, software, or any suitable combination thereof. The computer readable medium includes a hardware medium or a software medium. Additionally, the medium has a persistent medium or a transport medium.

Claims (10)

A set of full duplex twinax pairs having a set of no more than four twin coaxial cables configured to communicate a set of signals simultaneously in opposite directions at a rate of at least 100 gigabytes per second;
A plug assembly configured to integrate at least one end of the set of full-duplex twinax pairs with a set of interconnects, and connecting the at least one end with an interface port;
The plug assembly is
A transceiver component configured to communicate a set of signals in a different direction to or from the interface port through the set of full-duplex twinax pairs;
And a processor operatively connected to the transceiver component and configured to digitally process the set of signals through a set of full-duplex twinax pairs. The processor is further configured to facilitate communication of a set of signals through at least one end of the set of full duplex twinax pairs via a surface mount assembly that is dynamically connected to the transceiver component. And
The set of full-duplex twinax pairs has two conductor twinax pairs configured to communicate a set of signals simultaneously in opposite directions;
The system according to claim 1.   The set of full duplex twinax pairs is transmitted at a rate of at least 100 Gbps by encoding at least a portion of the set of signals with a communication protocol to transmit the set of signals from the first device to the second device. The system of claim 1, wherein the system is configured to communicate. The plug assembly is dynamically connected to the set of full-duplex twinax pairs via a set of interconnects so that power is consumed from at least one end of the set of full-duplex twinax pairs. Further configured,
The plug assembly further includes an interface including at least one of a quad small form factor pluggable interface or a small form factor pluggable interface;
The system according to claim 1. Integrating a reduced set of twinax pairs containing no more than four full-duplex twin coaxial cables with the transceiver of the processor and plug assembly;
Receiving one or more signals through the plug assembly;
Encoding at least a portion of one or more signals with a first communication protocol by the processor;
Transmitting one or more signals by the transceiver via a reduced set of twinax pairs from the processor at a rate of at least 100 gigabytes per second;
A method comprising:   6. The method of claim 5, wherein transmitting one or more signals through the reduced set of twinax pairs comprises communicating one or more signals at a rate of at least 100 gigabytes per second. Method. The step of integrating a reduced set of full-duplex twinax pairs with the transceiver of the processor and the plug assembly includes mounting no more than four twin coaxial cables having twinax conductor pairs to a circuit board. Integrating into a microprocessor package assembly having
Receiving one or more signals and transmitting the one or more signals comprises communicating one or more signals in full-duplex communication simultaneously in different directions between the first device and the second device; The method according to claim 5, wherein: Encoding at least a portion of the one or more signals with a second communication protocol to transmit one or more signals from the first device to the second device;
Selecting a protocol for encoding at least a portion of the one or more signals from the first communication protocol and the second communication protocol;
Power through at least one end of the reduced set of twinax pairs from an independent power source, one or more signals received from the first device and the second device, or from at least one power source of the first device or the second device The method of claim 5, further comprising: Memory for storing computer readable instructions;
A first processor coupled to the memory for facilitating execution of the computer readable instructions to perform operations;
With
The operation is
Transmitting a first set of signals to a second device through a twin coaxial copper cable assembly having no more than four twinax copper pairs with a first communication protocol at a transmission rate of at least 100 gigabytes per second;
Receiving simultaneously a second set of signals in a full-duplex transmission mode from a second device through no more than four copper twinax pairs of a twin coaxial copper cable assembly. Transmitting comprises encoding at least a portion of the first set of signals through a second processor according to a first communication protocol having a transmission rate of 80 gigabytes per second or 100 gigabytes per second;
The second processor is integrated within a plug assembly configured to integrate no more than four twinax copper pairs into the second processor on a package mount assembly having copper interconnects; Drawing power from at least one of an independent power source connected to the package mount assembly, a first set of signals or a second set of signals, or a power source external to a twin coaxial copper cable assembly having the plug assembly. The device according to claim 9.

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